An efficient FPGA-based DDR access automatic control method and system
By employing an efficient DDR access automatic control method based on FPGA, the resource allocation and cache management of DDR are optimized, solving the problem of low efficiency in parallel DDR access by FPGA in video image processing and achieving higher bandwidth and throughput.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- THE 44TH INST OF CHINA ELECTRONICS TECH GROUP CORP
- Filing Date
- 2023-11-17
- Publication Date
- 2026-08-04
AI Technical Summary
The presence of RL (Redirect Array) causes inefficiency and insufficient throughput when FPGA accesses DDR, especially when multiple interfaces and large areas are accessed simultaneously for reading and writing, thus limiting video image processing functions.
An efficient DDR access automatic control method based on FPGA is adopted. Through the collaborative work of image input, processing and output modules, combined with the resource allocation and prediction mechanism of the DDR control module, the resource allocation and cache management of read and write requests are optimized, thereby improving the bandwidth and throughput of DDR.
This enables more image processing modules to access DDR in parallel, improving DDR bandwidth and throughput, and solving the bottleneck problem of parallel access in FPGA video image processing.
Smart Images
Figure CN117573581B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of FPGA video and relates to an efficient DDR access automatic control method and system based on FPGA. Background Technology
[0002] DDR is a commonly used memory device in FPGAs. A key timing parameter for FPGA access to DDR is RL (Read Latency), which is calculated as RL = AL (Additive Latency) + CL (CAS Latency), representing the column address strobe latency. Due to the existence of RL, after a read command is sent, the system must wait for the RL clock cycle before a specified amount of data can be read. In multi-interface and large-area simultaneous read / write access scenarios, ordinary read / write methods result in low efficiency and throughput, limiting the implementation of video image processing functions.
[0003] To achieve efficient access in FPGAs, methods typically include increasing the master clock speed and read / write burst length, establishing a virtual FIFO to merge data before reading and writing, and establishing a unified allocation read / write control for merged read / write. These methods can improve access performance. However, in video image processing, when multiple modules simultaneously and continuously access different address spaces in a large area, bandwidth bottlenecks will be encountered. Due to the presence of RL, simultaneous read and write will limit the throughput of parallel access to DDR in the FPGA. Summary of the Invention
[0004] In view of this, the purpose of this invention is to provide an efficient access mechanism to improve the bandwidth of FPGA accessing DDR, increase DDR throughput, and enable more image processing modules to access DDR simultaneously in parallel.
[0005] To achieve the above objectives, the present invention provides the following technical solution:
[0006] On the one hand, this invention provides an efficient DDR access automatic control method based on FPGA, comprising the following steps:
[0007] S1: The image input module inputs the video image data collected by the sensor into the image processing module for image processing;
[0008] S2: The image processing module issues large-scale read and write access requests to the DDR memory in parallel according to the needs of image processing;
[0009] S3: The DDR control module receives parallel read and write access requests from all image processing modules, allocates resources for the access read and write requests, and predicts the current read and write cache space.
[0010] S4: The DDR driver module receives read and write requests and converts them into DDR hardware access instructions and related operation timings;
[0011] S5: The image output module outputs a series of video images after image processing.
[0012] Furthermore, step S1 specifically includes: using an FPGA to convert the serial data acquired by the sensor into parallel image data to obtain image frame sequence data.
[0013] Furthermore, in step S2, there are multiple image processing modules, which implement image caching or real-time reading of parameters in parallel.
[0014] Furthermore, in step S3, the DDR control module receives parallel read / write access requests from all image processing modules and allocates resources for these requests, specifically including the following steps:
[0015] S311: The DDR control module receives the parallel write request REQ_W_CMD, write length REQ_W_LEN, and write start address REQ_W_ADDR from the image processing module;
[0016] S312: The DDR control module receives continuously written data REQ_W_DATA from the image processing module through the DDR write cache in the cache module;
[0017] S313: The DDR control module judges the DDR write cache and write request. When the write request and write cache reach the threshold at the same time, it obtains the current write address W_ADDR and the write burst length BURST_W_LEN corresponding to the threshold under the request, initiates data writing, and obtains the data W_DATA of the corresponding length in the write cache according to the current DDR write burst length BURST_W_LEN. It then passes the data W_DATA to the DDR driver module and writes the data into the W_ADDR address of the DDR hardware.
[0018] S314: The DDR control module receives a parallel read request REQ_R_CMD, a read length REQ_R_LEN, and a read start address REQ_R_ADDR from the image processing module;
[0019] S315: The DDR control module judges the DDR read request and the corresponding read cache. When both the read request and the read cache reach the threshold, it obtains the current read address R_ADDR and the read burst length BURST_R_LEN corresponding to the threshold, initiates data reading, and passes the continuous read instruction to the DDR driver module according to the current DDR read burst length BURST_R_LEN to read the data at address R_ADDR in the DDR hardware.
[0020] S316: The DDR control module receives continuous data R_DATA read from the DDR driver through the DDR read cache in the cache module, and finally provides continuous data to the image processing module.
[0021] Furthermore, the DDR controller in step S3 predicts the current read / write cache space, specifically including the following steps:
[0022] S321: The DDR control module receives the remaining parameters of the DDR read / write cache;
[0023] S322: When the DDR control module determines that the read cache balance has reached the high threshold R_HTH, it triggers the read request corresponding to the current read cache and sets the current read burst length BURST_R_LEN(1);
[0024] S323: When the DDR control module determines that the write cache remaining amount has reached the high threshold W_HTH, it triggers the write request corresponding to the current read cache and sets the current write burst length BURST_W_LEN(1);
[0025] S324: When the DDR control module determines that the read cache balance has reached the middle threshold R_MTH, it triggers the read request corresponding to the current read cache and sets the current read burst length BURST_R_LEN(2);
[0026] S325: When the DDR control module determines that the write cache remaining amount has reached the middle threshold W_MTH, it triggers the write request corresponding to the current read cache and sets the current write burst length BURST_W_LEN(2);
[0027] S326: When the DDR control module determines that the read cache balance has reached the low threshold R_LTH, it triggers the read request corresponding to the current read cache and sets the current read burst length BURST_R_LEN(3);
[0028] S327: When the DDR control module determines that the write cache balance has reached the low threshold W_LTH, it triggers the write request corresponding to the current read cache and sets the current write burst length BURST_W_LEN(3);
[0029] In the threshold, R_HTH <R_MTH<R_LTH,W_HTH> W_MTH>W_LTH, BURST_R_LEN(1)>=BURST_R_LEN(2)>=BURST_R_LEN(3), BURST_W_LEN(1)>=BURST_W_LEN(2)>=BURST_W_LEN(3).
[0030] On the other hand, the present invention provides a high-efficiency DDR access automatic control system based on FPGA, including a sensor, an FPGA processing board and a PC. The sensor is used to convert external light images into electrical signals for serial output; the FPGA processing board is used to receive video image data collected by the sensor, process it and output it to the PC for display.
[0031] The FPGA processing board includes:
[0032] Image acquisition module: used to decode serial data into parallel image data, providing a data source for subsequent processing;
[0033] Image processing module: used to process the parallel image data according to requirements;
[0034] DDR control module: Used to implement all control logic and drivers for multi-channel parallel read and write access to DDR, and to meet the storage requirements of image algorithms for large-scale image processing;
[0035] Image output module: Used to output the processed image data in various formats.
[0036] The beneficial effects of this invention are as follows: This invention proposes an efficient DDR access automatic control technology based on FPGA, which improves the bandwidth of FPGA accessing DDR and increases DDR throughput through an efficient DDR access control and prediction mechanism, enabling more image processing modules to access DDR in parallel at the same time.
[0037] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description
[0038] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:
[0039] Figure 1 This is a flowchart of the DDR access automatic control system according to an embodiment of the present invention;
[0040] Figure 2 This is a logic diagram of automatic DDR access control according to an embodiment of the present invention;
[0041] Figure 3 This is a flowchart of the DDR read / write control priority according to an embodiment of the present invention;
[0042] Figure 4This is a diagram of the DDR access automatic control system according to an embodiment of the present invention.
[0043] Reference numerals: Sensor 401, FPGA processing board 402, PC terminal 403, image acquisition module 404, image processing module 405, DDR control module 406, image output module 407. Detailed Implementation
[0044] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.
[0045] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.
[0046] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.
[0047] Please see Figures 1-4 This embodiment provides a flowchart of a high-efficiency DDR access automatic control system based on FPGA, as shown below. Figure 1As shown, the system's processing flow includes: the camera video stream originates from the image input module; the FPGA decodes the serial data output by the sensor into parallel image data; the image processing module contains multiple image processing sub-modules, which issue large-scale read and write access requests to the DDR memory in parallel; the DDR control module completes resource allocation and request prediction for the access read and write requests; the DDR driver module completes all commands and operation timing logic for the upper layer's DDR hardware operations; and the image output module outputs the processed video image.
[0048] This embodiment provides an efficient automatic control method for DDR access running on the aforementioned system. Figure 2 This is a logic diagram of the automatic control of DDR access according to the present invention. The logic flow includes:
[0049] Step 1: The DDR control module receives the parallel write request REQ_W_CMD, write length REQ_W_LEN, and write start address REQ_W_ADDR from the image processing module;
[0050] Step 2: The DDR write cache in the cache module receives the continuously written data REQ_W_DATA from the image processing module;
[0051] Step 3: The DDR control module judges the above DDR write cache and write request. When both the write request and the write cache reach the threshold, it obtains the current write address W_ADDR and the write burst length BURST_W_LEN corresponding to the threshold under the request. It initiates data writing and, based on the current DDR write burst length BURST_W_LEN, obtains the data W_DATA of the corresponding length in the write cache and passes it to the DDR driver module to write the data into the W_ADDR address of the DDR hardware.
[0052] Step 4: The DDR control module receives the parallel read request REQ_R_CMD, read length REQ_R_LEN, and read start address REQ_R_ADDR from the image processing module;
[0053] Step 5: The DDR control module judges the above DDR read request and the corresponding read cache. When both the read request and the read cache reach the threshold, it obtains the current read address R_ADDR and the read burst length BURST_R_LEN corresponding to the threshold, initiates data reading, and passes the continuous read instruction to the DDR driver module according to the current DDR read burst length BURST_R_LEN to read the data at address R_ADDR in the DDR hardware.
[0054] Step 6: The DDR read cache in the cache module receives continuous data R_DATA read from the DDR driver and finally provides continuous data to the image processing module.
[0055] Figure 3 This is a flowchart of the DDR read / write control priority in an embodiment of the present invention, which predicts the current read / write cache space, such as... Figure 3 As shown, the process includes:
[0056] Step S301: The DDR control module receives the remaining parameters of the DDR read / write cache;
[0057] In step S302, when the DDR control module determines that the read cache remaining amount has reached the high threshold R_HTH, it triggers the read request corresponding to the current read cache and sets the current read burst length BURST_R_LEN(1);
[0058] Step S303: When the DDR control module determines that the write cache remaining amount has reached the high threshold W_HTH, it triggers the write request corresponding to the current read cache and sets the current write burst length BURST_W_LEN(1);
[0059] Step S304: When the DDR control module determines that the read cache remaining amount has reached the middle threshold R_MTH, it triggers the read request corresponding to the current read cache and sets the current read burst length BURST_R_LEN(2);
[0060] Step S305: When the DDR control module determines that the write cache remaining amount has reached the middle threshold W_MTH, it triggers the write request corresponding to the current read cache and sets the current write burst length BURST_W_LEN(2).
[0061] Step S306: When the DDR control module determines that the read cache balance has reached the low threshold R_LTH, it triggers the read request corresponding to the current read cache and sets the current read burst length BURST_R_LEN(3);
[0062] Step S307: When the DDR control module determines that the write cache remaining amount has reached the low threshold W_LTH, it triggers the write request corresponding to the current read cache and sets the current write burst length BURST_W_LEN(3);
[0063] In the aforementioned embodiment threshold, R_HTH <R_MTH<R_LTH,W_HTH> W_MTH>W_LTH, BURST_R_LEN(1)>=BURST_R_LEN(2)>=BURST_R_LEN(3), BURST_W_LEN(1)>=BURST_W_LEN(2)>=BURST_W_LEN(3).
[0064] According to another embodiment of the present invention, a high-efficiency DDR access automatic control system based on FPGA is also provided, such as Figure 4As shown, the system is a module block diagram according to an embodiment of the present invention, which includes:
[0065] Sensor 401: Converts external light images into electrical signals for serial output;
[0066] FPGA processing board 402: Outputs the image from sensor 401 to PC terminal 403 for display;
[0067] PC 403: Display the output image;
[0068] Image acquisition module 404: This module belongs to FPGA processing board 402. The FPGA decodes serial data into parallel image data to provide a data source for subsequent processing.
[0069] Image processing module 405: This module belongs to FPGA processing board 402. The FPGA performs image processing on the parallel image data according to requirements.
[0070] DDR Control Module 406: This module belongs to FPGA processing board 402. The FPGA implements all control logic and drivers for multi-channel parallel read and write access to DDR, realizing the storage requirements of image algorithms for large-scale image processing.
[0071] Image output module 407: This module belongs to the FPGA processing board 402. The FPGA outputs the processed image data in various formats.
[0072] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium. When the program is executed, it includes the following steps: (steps of the method). The storage medium is, for example, ROM / RAM, magnetic disk, optical disk, etc.
[0073] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.
Claims
1. A high-efficiency DDR access automatic control method based on FPGA, characterized in that: Includes the following steps: S1: The image input module inputs the video image data collected by the sensor into the image processing module for image processing; S2: The image processing module issues large-scale read and write access requests to the DDR memory in parallel according to the needs of image processing; S3: The DDR control module receives parallel read and write access requests from all image processing modules, allocates resources for the access read and write requests, and predicts the current read and write cache space. S4: The DDR driver module receives read and write requests and converts them into DDR hardware access instructions and related operation timings; S5: The image output module outputs a series of video images after image processing; In step S3, the DDR control module receives parallel read / write access requests from all image processing modules and allocates resources for these requests. Specifically, this includes the following steps: S311: The DDR control module receives the parallel write request REQ_W_CMD, write length REQ_W_LEN, and write start address REQ_W_ADDR from the image processing module; S312: The DDR control module receives continuously written data REQ_W_DATA from the image processing module through the DDR write cache in the cache module; S313: The DDR control module judges the DDR write cache and write request. When the write request and write cache reach the threshold at the same time, it obtains the current write address W_ADDR and the write burst length BURST_W_LEN corresponding to the threshold under the request, initiates data writing, and obtains the data W_DATA of the corresponding length in the write cache according to the current DDR write burst length BURST_W_LEN. It then passes the data W_DATA to the DDR driver module and writes the data into the W_ADDR address of the DDR hardware. S314: The DDR control module receives a parallel read request REQ_R_CMD, a read length REQ_R_LEN, and a read start address REQ_R_ADDR from the image processing module; S315: The DDR control module judges the DDR read request and the corresponding read cache. When both the read request and the read cache reach the threshold, it obtains the current read address R_ADDR and the read burst length BURST_R_LEN corresponding to the threshold, initiates data reading, and passes the continuous read instruction to the DDR driver module according to the current DDR read burst length BURST_R_LEN to read the data at address R_ADDR in the DDR hardware. S316: The DDR control module receives continuous data R_DATA read from the DDR driver through the DDR read cache in the cache module, and finally provides continuous data to the image processing module.
2. The FPGA-based high-efficiency DDR access automatic control method according to claim 1, characterized in that: Step S1 specifically includes: using an FPGA to convert the serial data collected by the sensor into parallel image data to obtain image frame sequence data.
3. The FPGA-based high-efficiency DDR access automatic control method according to claim 1, characterized in that: In step S2, there are multiple image processing modules, which implement image caching or real-time reading of parameters in parallel.
4. The FPGA-based high-efficiency DDR access automatic control method according to claim 1, characterized in that: The DDR control module in step S3 predicts the current read / write cache space, specifically including the following steps: S321: The DDR control module receives the remaining parameters of the DDR read / write cache; S322: When the DDR control module determines that the read cache balance has reached the high threshold R_HTH, it triggers the read request corresponding to the current read cache and sets the current read burst length BURST_R_LEN(1); S323: When the DDR control module determines that the write cache remaining amount has reached the high threshold W_HTH, it triggers the write request corresponding to the current read cache and sets the current write burst length BURST_W_LEN(1); S324: When the DDR control module determines that the read cache balance has reached the middle threshold R_MTH, it triggers the read request corresponding to the current read cache and sets the current read burst length BURST_R_LEN(2); S325: When the DDR control module determines that the write cache remaining amount has reached the middle threshold W_MTH, it triggers the write request corresponding to the current read cache and sets the current write burst length BURST_W_LEN(2); S326: When the DDR control module determines that the read cache balance has reached the low threshold R_LTH, it triggers the read request corresponding to the current read cache and sets the current read burst length BURST_R_LEN(3); S327: When the DDR control module determines that the write cache balance has reached the low threshold W_LTH, it triggers the write request corresponding to the current read cache and sets the current write burst length BURST_W_LEN(3); In the threshold, R_HTH <R_MTH<R_LTH,W_HTH> W_MTH>W_LTH, BURST_R_LEN(1)>=BURST_R_LEN(2)>=BURST_R_LEN(3), BURST_W_LEN(1)>=BURST_W_LEN(2)>=BURST_W_LEN(3).
5. A high-efficiency DDR access automatic control system based on FPGA, characterized in that: The system is applicable to the FPGA-based high-efficiency DDR access automatic control method as described in any one of claims 1-4. The system includes a sensor, an FPGA processing board, and a PC. The sensor is used to convert external light images into electrical signals for serial output. The FPGA processing board is used to receive video image data collected by the sensor, process it, and output it to the PC for display. The FPGA processing board includes: Image acquisition module: used to decode serial data into parallel image data, providing a data source for subsequent processing; Image processing module: used to process the parallel image data according to requirements; DDR control module: Used to implement all control logic and drivers for multi-channel parallel read and write access to DDR, and to meet the storage requirements of image algorithms for large-scale image processing; Image output module: Used to output the processed image data in various formats.