An AXI-based universal bit width conversion method

Abstract

The application provides a general bit width conversion method based on AXI, and belongs to the field of data bit width conversion.The method comprises the following steps: buffering data transmitted by an AXI bus in a FIFO, taking a prog_full signal as flow control of a previous stage;setting eight temporary storage units for data, with a depth of 16 and a data bit width of 32 bits, as a transfer station for data bit width conversion; and dividing the address space of the eight temporary storage units into two groups, buffer0 and buffer1, for ping-pong reading and writing.The general bit width conversion method based on AXI can significantly improve the utilization rate of system bandwidth, the transmission efficiency of data and the reusability of data in application scenarios such as high-definition video data transmission / storage, inference and training of AI algorithm models, collection / storage of various mass data and transmission and generation of mass vector data of ATE test equipment, and saves manpower and material resources.

Description

Technical Field

[0001] This invention relates to the field of data bit width conversion, and in particular to a general bit width conversion method based on AXI. Background Technology

[0002] AXI (Advanced eXtensible Interface) is a bus protocol, a key component of ARM's AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol. It's a high-performance, high-bandwidth, low-latency on-chip bus. Its address / control and data phases are separated, supporting unaligned data transfers. In burst transfers, only the starting address is needed. It also features separate read / write data channels, supports significant transfer access and out-of-order access, and facilitates timing closure. AXI is a new high-performance protocol within AMBA. AXI technology enriches the existing AMBA standard, meeting the needs of ultra-high-performance and complex System-on-Chip (SoC) designs.

[0003] AXI features include: a unidirectional channel architecture where information flows in only one direction, simplifying bridging between clock domains and reducing gate count; reduced latency when signals pass through complex on-chip systems; support for multiple data exchanges; and significantly improved data throughput through parallel burst operations, enabling tasks to be completed in shorter times while meeting high-performance requirements and reducing power consumption.

[0004] Independent address and data channels. Separate address and data channels allow for individual optimization of each channel. Timing channels can be controlled as needed, maximizing clock frequency and minimizing latency. Depending on different usage requirements, AXI 3.0 can be further divided into AXI, AXI-Lite, and AXI-Stream.

[0005] Considering the flexibility and versatility of the AXI 3.0 bus, almost all IP cores provided in Xilinx Vivado now use the AXI 3.0 bus as their data interface. However, the standard AXI bus data width is a multiple of 2^N, such as 32 / 64 / 128 / 256 / 512 / 1024, etc. In practical applications, data widths are rarely such. For example, raw data such as video, audio, multi-channel ADC sampling, RF, and radar data requires conversion between data widths. This is especially true in high-density multi-channel digital semiconductor test equipment, where data rate and bandwidth utilization requirements are very high. Therefore, data must be converted to the locally required width before it can be used.

[0006] Existing technical solutions vary from person to person, depending on the use case and requirements. There is no unified format. Different architectures need to be designed for different scenarios. Moreover, the data bandwidth utilization of AXI is not high, the reusability is not high, and it is time-consuming and labor-intensive.

[0007] Therefore, there is an urgent need in this field for a data bit width conversion scheme that can improve the utilization of system bandwidth, data transmission efficiency, and reusability. Summary of the Invention

[0008] The purpose of this invention is to provide a data bit width conversion scheme that can improve system bandwidth utilization, data transmission efficiency, and reusability.

[0009] To achieve the above objectives, the present invention provides the following solution:

[0010] A general bit-width conversion method based on AXI, characterized by comprising:

[0011] S1: The data transmitted on the AXI bus is buffered in the FIFO, and the FIFO uses the prog_full signal as the flow control of the preceding stage;

[0012] S2: Set up 8 temporary cache data storage units with a depth of 16 and a data width of 32 bits, as a data width conversion relay station;

[0013] S3: Divide the address space of the 8 temporary storage units into two groups: buffer0 and buffer1, for use as ping-pong read and write.

[0014] Optionally, the storage unit for setting up 8 temporary cache data is specifically as follows:

[0015] The bit width of AXI-data is 256 bits, and the bit width of User-Data is 160 bits. The least common multiple of 256 and 160 is 1280. Therefore, every 5 frames of AXI-data can carry 8 frames of User-Data. Hence, 8 temporary buffer storage units are set up.

[0016] Optionally, S3 specifically includes:

[0017] When writing to temporary buffer units, AXI-Data is allocated into 8 groups, each with a width of 32 bits. AXI-Data[31:0] is written to temporary buffer unit 0, AXI-Data[63:32] is written to temporary buffer unit 1, AXI-Data[95:64] is written to temporary buffer unit 2, AXI-Data[127:96] is written to temporary buffer unit 3, AXI-Data[159:128] is written to temporary buffer unit 4, AXI-Data[191:160] is written to temporary buffer unit 5, AXI-Data[223:192] is written to temporary buffer unit 6, and AXI-Data[255:224] is written to temporary buffer unit 7. After buffer0 is full, buffer1 is written next, then buffer0 is written again, and so on.

[0018] Optionally, the AXI bus continuously writes 5 sets of data to the temporary storage unit, writing to 8 cache units at the same time each time. It takes 8 writes to read all the data from the cache unit, and 5 cache units are read at the same time each time, thus completing the data bit width conversion.

[0019] Optionally, the reading and writing of the eight temporary cache units are performed using ping-pong operations to achieve the continuity of reading and writing data and improve data throughput and read / write speed.

[0020] Optionally, to ensure consistent read and write throughput, the clock rate of the read port should be higher than that of the write port.

[0021] Optionally, to ensure the stability of cross-clock domain signals, a synchronization mechanism needs to be added, and the four signals need to be processed across clock domains.

[0022] Compared with the prior art, the present invention has the following advantages:

[0023] The universal bit-width conversion method based on AXI provided by this invention can significantly improve the utilization of system bandwidth, data transmission efficiency and reusability, and save manpower and material costs in application scenarios such as high-definition video data transmission / storage, AI algorithm model inference and training, acquisition / storage of various massive data, and transmission and generation of massive vector data in ATE test equipment. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1This is a schematic diagram of the User-Data storage method provided in an embodiment of the present invention.

[0026] Figure 2 This is a schematic diagram of the data bit width conversion architecture and scheduling provided in an embodiment of the present invention.

[0027] Figure 3 This is a schematic diagram illustrating the data bit width conversion principle provided in an embodiment of the present invention.

[0028] Figure 4 This is a schematic diagram illustrating the ping-pong operation principle in bit-width conversion provided in an embodiment of the present invention.

[0029] Figure 5 This is a schematic diagram of signal synchronization provided in an embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] The purpose of this invention is to provide a data bit width conversion scheme that can improve system bandwidth utilization, data transmission efficiency, and reusability. To make the above-mentioned objectives, features, and advantages of this invention more apparent and understandable, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0032] Example 1:

[0033] This embodiment provides a general bit-width conversion method based on AXI. Taking the application scenario of a high-density multi-channel digital board as an example, the technical solution of the present invention is described in detail.

[0034] The digital board uses a 160-bit width for each user-data entry. Each generated symbol contains N user-data entries, which are cached in the board's DDR3 memory. The storage method is as follows: Figure 1 As shown, there are no gaps between data (addresses) when storing raw data.

[0035] The AXI bus has a 256-bit width. To meet high throughput requirements (up to 200M*User-Data rate or higher), the AXI-CLK clock must be at least 150MHz. Since a single User-Data entry is 160 bits, an efficient scheduling and data conversion mechanism is needed to achieve the conversion from 256-bit to 160-bit data width and high-speed data transmission. Figure 2 As shown.

[0036] Data scheduling and bit-width conversion are achieved through the following steps:

[0037] 1. Data transmitted from the AXI bus is buffered in a FIFO, and the FIFO's prog_full signal is used as the flow control of the preceding stage;

[0038] 2. Set up 8 temporary buffer storage units (named width_covt_ram, or ram for short), with a depth of 16 and a data width of 32 bits, as data width conversion relay stations. The bit width of AXI-data is 256 bits, and the bit width of User-Data is 160 bits. The least common multiple of 256 and 160 is 1280. Therefore, every 5 frames of AXI-data can carry 8 frames of User-Data, hence the setting of 8 temporary buffer units;

[0039] 3. Divide the address space of the 8 temporary storage units into two groups: 0-4 and 8-12 (buffer0 and Buffer1), for ping-pong read / write. When writing to the temporary buffer units, AXI-Data is allocated into 8 groups, each with a width of 32 bits. AXI-Data[31:0] is written to width_covt_ram 0 (temporary buffer unit 0), ..., AXI-data[255:224] is written to width_covt_ram 7 (temporary buffer unit 7). After buffer0 is full, buffer1 is written next, then buffer0 is written again, and so on.

[0040] A schematic diagram of read / write scheduling for 4.8 temporary storage units is shown below. Figure 3 As shown, each circle represents a 32-bit cache unit. The red text indicates that the AXI bus continuously writes 5 sets of data to the temporary storage unit, that is, 5 consecutive addresses 0-4 or 8-12, writing 8 cache units (256 bits) at a time; the 5 vertical bars indicate that the 5 sets of data written require 8 reads from the cache unit, reading 5 cache units (160 bits) of data at a time, thus completing the data bit width conversion.

[0041] The reading and writing of the 5.8 temporary cache units are performed using ping-pong operations to ensure the continuity of data reading and writing, thereby improving data throughput and read / write speed. The implementation principle is as follows: Figure 4 As shown.

[0042] When writing data, the write clock domain is AXI-clk, and data is written to 8 temporary buffer units simultaneously. The buffer unit buffer0 / buffer1 is selected according to ram_wr_sel = 0 / 1 (ram_wr_sel = 0 corresponds to buffer0). ram_wr_sel is 0 by default. The write counter ram_wr_cnt is responsible for measuring the data written.

[0043] When the write counter ram_wr_cnt == 4 && ram_wr_en == 1 (write enabled), ram_wr_sel toggles once. Simultaneously, based on the current value of ram_wr_sel, ram_full0 / ram_full1 are marked. If ram_wr_sel = 0, ram_full0 is set, and data is written to addresses 0-4 of the temporary buffer. If ram_wr_sel = 1, ram_full1 is set, and data is written to addresses 8-12 of the temporary buffer. When both ram_full0 and ram_full1 are 1, it indicates that the ping-pong buffers buffer0 and buffer1 are full, requiring flow control at the preceding AXI-data write end to prevent data overflow or overwriting.

[0044] When the backend receives a value of ram_full0 or ram_full1 set to 1, it selects between buffer0 and buffer1 by setting ram_rd_sel = 0 / 1, initially selecting ram_full0. When the read counter ram_rd_cnt == 4 && ram_rd_en == 1 (read enabled), ram_rd_sel toggles once. If ram_rd_sel = 0 at this time, the ram_full0 flag is cleared; if ram_rd_sel = 1, the ram_full1 flag is cleared.

[0045] 6. In reality, reading and writing temporary storage units belong to different clock domains. To ensure consistent read and write throughput, the clock rate of the read port must be higher than that of the write port. To ensure the stability of cross-clock domain signals, a synchronization mechanism must be added. Four signals need to be processed across clock domains: ram_full0 / ram_full1 and ram_full0_clr / ram_full1_clr, such as... Figure 5 As shown.

[0046] When using low-end FPGAs from the Xilinx 7 and 6 series, the DDR controller's read / write clock rate will not exceed 1333MHz. To ensure bandwidth utilization and improve data read / write efficiency, this solution avoids wasting bus bandwidth, utilizing all AXI-DATA. Furthermore, this solution improves versatility, saves labor and component costs, and facilitates later maintenance.

[0047] Existing technologies lack a unified format, leading to different implementations for each developer and project, resulting in inconvenience in use and maintenance, and low bandwidth utilization of AXI. This embodiment implements data conversion between different bit widths in a universal manner, effectively utilizing data transmission bandwidth, saving storage space, facilitating maintenance and reuse, reducing labor costs, and achieving higher data throughput on low-end devices, thus saving material costs.

[0048] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant parts can be referred to the method section.

[0049] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A general bit-width conversion method based on AXI, characterized in that, include: S1: The data transmitted on the AXI bus is buffered in the FIFO, and the FIFO uses the prog_full signal as the flow control of the preceding stage; S2: Set up 8 temporary cache data storage units with a depth of 16 and a data width of 32 bits, as a data width conversion relay station; S3: Divide the address space of the storage units of the 8 temporary cache data into two groups: buffer0 and buffer1, for use as ping-pong read and write; The storage unit for setting up 8 temporary cache data is specifically as follows: The bit width of AXI-data is 256 bits, and the bit width of User-Data is 160 bits. The least common multiple of 256 and 160 is 1280. Therefore, every 5 frames of AXI-data can carry 8 frames of User-Data. Hence, 8 temporary buffer storage units are set up. Specifically, S3 is: When writing temporary buffer data, AXI-Data allocates 8 groups, each with a width of 32 bits. AXI-Data[31:0] is written to the storage unit of temporary buffer data 0, AXI-Data[63:32] is written to the storage unit of temporary buffer data 1, AXI-Data[95:64] is written to the storage unit of temporary buffer data 2, AXI-Data[127:96] is written to the storage unit of temporary buffer data 3, AXI-Data[159:128] is written to the storage unit of temporary buffer data 4, AXI-Data[191:160] is written to the storage unit of temporary buffer data 5, AXI-Data[223:192] is written to the storage unit of temporary buffer data 6, and AXI-Data[255:224] is written to the storage unit of temporary buffer data 7. After buffer0 is full, buffer1 is written next, then buffer0 is written again, and so on. The AXI bus continuously writes 5 sets of data to the temporary buffer storage unit, writing to 8 temporary buffer storage units at a time. It takes 8 writes to read all the data from the temporary buffer storage unit at a time, and then reading the data from 5 temporary buffer storage units at a time to complete the data bit width conversion.

2. The universal bit-width conversion method based on AXI according to claim 1, characterized in that, The reading and writing of the eight temporary cache data storage units are performed using ping-pong operations to achieve the continuity of reading and writing data, thereby improving data throughput and read / write speed.

3. The universal bit-width conversion method based on AXI according to claim 1, characterized in that, To ensure consistent read and write throughput, the clock rate of the read port must be higher than that of the write port.

4. The universal bit-width conversion method based on AXI according to claim 1, characterized in that, To ensure the stability of signals across clock domains, a synchronization mechanism needs to be added, and the four signals need to be processed across clock domains.

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