A method for selecting a simulation step size of a power electronic system

Abstract

The application discloses a kind of power electronic system simulation step length optimization selection methods, comprising the following steps: building power electronic system circuit model, obtains all state space matrix of circuit under different switching states;According to the simulation allowed error range given by user, the simulation step length upper limit t1 and t2 corresponding to simulation error constraint in each switching state and switching transient are obtained by implicit Euler local truncation error step length estimation formula, when there is no switching action, the simulation error constraint t1 is obtained using formula estimation;When switching action occurs, the simulation error constraint t2 is obtained using formula estimation;The maximum simulation step length t of the circuit system allowed is obtained by taking the smaller value of the comprehensive simulation error constraint t1 and t2.The method solves the problem that existing fixed-step simulation software does not provide the best estimation value of simulation step length for users.

Description

Technical Field

[0001] This invention relates to the field of power electronic system simulation technology, specifically to a method for optimizing the selection of simulation step size for power electronic systems. Background Technology

[0002] Power electronics simulation software is an indispensable numerical experimental platform for related scientific research, product development, and engineering applications. However, existing fixed-step simulation software does not provide users with optimal estimates of the simulation step size. These initial values ​​are often set by users based on experience. Traditional simulation step size selection is based on the power frequency, and users mostly rely on empirical methods to choose the simulation step size. Inappropriate step size settings can lead to problems such as low simulation efficiency or large simulation errors. Selecting a reasonable simulation step size is key to obtaining optimal simulation efficiency and accuracy. In addition, fixed-step simulation methods are often used in engineering applications and real-time simulations. Once the simulation step size is determined before the system simulation begins, it is used throughout the entire simulation process. Therefore, the selection of the initial simulation step size is particularly important. Thus, it is necessary to study a reasonable method for optimizing the selection of simulation step size for power electronic systems.

[0003] Circuit simulation uses numerical integration methods to discretize the circuit's differential equations. However, when energy storage components such as inductors and capacitors in a circuit system are discretized into a discrete system divided by a step size, different truncation errors will occur due to different integration methods and simulation step size selections. The selection of the simulation step size is also affected by the numerical integration method. In some cases, an inappropriate integration method and simulation step size can significantly affect simulation accuracy and even cause unstable oscillations.

[0004] Implicit Euler's method is commonly used in engineering applications and real-time simulations for numerical integration of circuit models. Implicit Euler's method has favorable properties; it is a single-step integration method and, compared to explicit Euler's method, exhibits better stability and convergence, maintaining convergence even with large simulation step sizes.

[0005] In summary, existing research largely relies on empirical methods for step size selection, depending on the simulation cycle size, and fails to provide users with optimal estimates of the time step size for simulations, lacking a comprehensive theoretical method for step size selection. Therefore, there is an urgent need for a method to optimize the selection of step size in power electronic system simulations to address these issues. Summary of the Invention

[0006] This invention addresses the shortcomings of existing technologies by proposing a method for optimizing the selection of simulation step size in power electronic systems. This method solves the problem that existing fixed-step-size simulation software does not provide users with the optimal estimate of the simulation step size.

[0007] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows:

[0008] This invention provides a method for optimizing the selection of simulation step size for power electronic systems, comprising the following steps:

[0009] Step 1: Build a circuit simulation model and obtain the state space matrix of the circuit under different switching conditions. The state space matrix includes the state matrix and the input matrix.

[0010] Before obtaining the state-space matrix of the circuit simulation model under different switching conditions, the method further includes:

[0011] Define the names, variable types, and parameter values ​​of circuit components;

[0012] In the circuit simulation model, each switch can be customized to be closed or closed to ensure that the obtained circuit state matches the real situation.

[0013] Alternatively, the closing and closing of switches can be freely arranged and combined, and the algorithm can be used to retrieve circuit states that do not meet the actual conditions and delete them.

[0014] The obtained state space matrix is ​​manually calculated and analyzed to verify its correctness.

[0015] Step 2, which involves calculating the simulation step size range under the allowable error based on the implicit Euler local truncation error step size estimation formula, and comprehensively selecting the optimal simulation step size for the circuit, includes:

[0016] The implicit Euler local truncation error step size estimation formula is used to estimate the allowable simulation step size for each switching state and at each switching instant of the circuit, and these simulation step size sets are denoted as t1 and t2. The derivation process of the implicit Euler local truncation error step size estimation formula is as follows:

[0017] Consider the state equations of an n-dimensional linear time-invariant system.

[0018]

[0019] Its exact solution has the following discrete form:

[0020]

[0021] Where, x n+1 x represents the state quantity of the inductor current or capacitor voltage at the (n+1)th time step. n This represents the state quantity of the inductor current or capacitor voltage at the nth time step. Let A and B represent the matrix index, where A and B represent the system state matrix and input matrix, respectively. -1 Let Δt be the inverse matrix of state matrix A. n Indicates the simulation step size, u n Indicates the system input quantity; Δu n Indicates the change in system input;

[0022] Will Performing a Taylor expansion, we get:

[0023] I represents the identity matrix, which has the same order as the system order;

[0024] Various approximations of the exact solution can be obtained by Taylor series expansion of the matrix exponent, and the higher the order of the Taylor series expansion, the closer it is to the exact solution.

[0025] For the implicit Euler method, the error mainly comes from the quadratic terms, and the solution obtained by expanding the Taylor series to the quadratic terms is close enough to the exact solution.

[0026] Therefore, The approximate exact solution formula is obtained as follows:

[0027]

[0028] make Then, we obtain the implicit Euler formula:

[0029]

[0030] Simplifying, we get:

[0031]

[0032] Subtracting the two yields:

[0033]

[0034] The simplified formula for the implicit Euler local truncation error is obtained as follows:

[0035]

[0036] When the circuit has no switching action, the system input does not change, and at this time Δu n =0, the implicit Euler local truncation error formula can be regarded as The local truncation error mainly comes from the influence of system state variables;

[0037] When the circuit switches, the system input changes, and at this time Δu n ≠0. During the switching process, the circuit state also changes, and the final value of the state variable of the previous circuit state is equal to the initial value of the state variable of the next circuit state. Therefore, x n =x n+1 At this point, the implicit Euler local truncation error formula is considered as The local truncation error mainly comes from the influence of the system input.

[0038] The implicit Euler formula Substitution In the middle, we get At this point, the local truncation error changes from its original relationship with two state variables to its relationship with a single state variable.

[0039] To describe the relationship between the maximum local truncation error and the system simulation step size, the discrete state derivatives can be used. Using the derivative of continuous state quantities Replace, and seek The maximum value is denoted as At this time Given the quantities, the original expression becomes

[0040] In summary, when the system has no switching action, When the system switches on or off...

[0041] Right now:

[0042] This is expressed as the relationship between step size and error, considering the space matrix under different switching states, i.e., the implicit Euler local truncation error step size estimation formula:

[0043] Let it be Δt n (A i B i Error);

[0044] Calculate x(t) under each switching state, and obtain the first and second derivatives of x(t) respectively. and

[0045] If it exists Will Substitute the corresponding time t value get

[0046] If it does not exist Substitute the on-time or off-time t corresponding to t=0 into the equation. get

[0047] Δu n Let u be the change in system input excitation before and after the system switch. Let the input voltage before the change be u1, and the input voltage after the change be u2. Then Δu n =|u1-u2|;

[0048] The above results and Δu nSubstituting the implicit Euler local truncation error estimation formula, we obtain the relationship between the error and the step size.

[0049] via Δt n (A i B i Once the user has built the circuit model and specified the error range, the set of simulation error constraints t1 and t2 that meet the error requirements can be estimated using this formula.

[0050] Step 3: Combine t1 and t2 to select the optimal simulation step size for the circuit.

[0051] Preferably, the "no-switch action" refers to the simulation circuit model maintaining a closed and closed state.

[0052] Preferably, the switching action refers to the time point when the simulation circuit model performs the closing and closing operations.

[0053] This invention has the following characteristics and beneficial effects:

[0054] Using the above technical solution, the present invention provides a method for optimizing the selection of simulation step size for power electronic systems. Based on the implicit Euler local truncation error formula, it has good stability and convergence. Furthermore, based on the actual power electronic circuit, it establishes a relatively reasonable and complete method for selecting the initial simulation step size of power electronic systems for existing simulation software, thereby providing users with the best estimate of the simulation step size. Attached Figure Description

[0055] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a flowchart illustrating a method for optimizing the selection of simulation step size in a power electronic system, as provided in this invention example.

[0057] Figure 2 A schematic diagram illustrating the derivation process of the implicit Euler local truncation error step size estimation formula provided for an example of the present invention.

[0058] Figure 3 A schematic diagram of a Buck power converter simulation test platform provided as an example of the present invention.

[0059] Figure 4-6The diagram shows the circuit structure and corresponding state space matrix of the Buck circuit under different switching states provided in this invention example.

[0060] Figure 7 This is a graph showing the inductor current variation of a Buck power converter in discontinuous conduction (DCM) mode.

[0061] Figure 8 and Figure 9 The error curves of inductor current and capacitor voltage are plotted using the step size estimated by the method provided in this invention example. Detailed Implementation

[0062] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0063] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0064] Circuit simulation has become a crucial technology and tool supporting the analysis, design, and reliable operation of power electronic systems. However, due to the large number of components, complex system structure, and diverse operating scenarios, physical testing of real-world systems is extremely costly in terms of both economics and time, and its safety is difficult to guarantee. For such systems, relying solely on physical experiments for system analysis and design is very challenging. Therefore, conducting virtual numerical experiments based on simulation technology and software is an indispensable part of the analysis and design of complex power electronic systems. In fixed-step simulation, the simulation step size is a crucial parameter that must be set. However, existing fixed-step simulation software does not provide users with optimal estimates of the step size; these initial values ​​are often set by the user based on experience. Inappropriate step size settings can lead to low simulation efficiency or large simulation errors. Traditionally, simulation step size selection is based on the power frequency, using empirical methods, and generally does not exceed a certain proportion of the corresponding power frequency cycle.

[0065] To address the issues that existing fixed-step simulation software does not provide users with the optimal estimate of the simulation step size, and the initial value of the simulation step size is often set by the user based on experience, this invention proposes a fixed-step size optimization method for power electronic systems based on the implicit Euler local truncation error formula.

[0066] This embodiment provides a method for optimizing the selection of simulation step size for power electronic systems, such as... Figure 1 As shown, it includes:

[0067] Step 1: Build a circuit simulation model and define and set the names, variable types, and parameter values ​​of the circuit components used;

[0068] Obtain the state space matrix of the circuit simulation model under all switching states to obtain all dynamic characteristics of the circuit system and achieve a comprehensive description of the system behavior;

[0069] The correctness of the obtained state space matrix is ​​verified by manual calculation analysis and node method analysis.

[0070] Specifically, the circuit simulation model built in this embodiment is as follows: Figure 3 The image shows the simulation test platform for the Buck power converter.

[0071] The main circuit parameters of the simulation experimental platform are shown in Table 1 below:

[0072]

[0073]

[0074] Step 2: Based on the implicit Euler local truncation error step size estimation formula, estimate the simulation error constraints t1 and t2 that meet the error requirements by using the user-given simulation error allowable range and circuit state space matrix.

[0075] Specifically, such as Figure 2 As shown, the implicit Euler local truncation error formula is derived by subtracting the approximate exact solution formula from the back Euler method formula, resulting in:

[0076]

[0077] When there is no switch action, by formula Estimate the simulation step size;

[0078] When there is a switch action, by formula Estimate the simulation step size;

[0079] For the implicit Euler local truncation error formula when there is no switching action, the implicit Euler method formula will be used. Substitution In the middle, we get

[0080] Derivatives of actual discrete state quantities With continuous state derivatives The difference is very small. To simplify the analysis and calculation, we will... Replace the original expression And seek maximum value get

[0081] In summary, the implicit Euler local truncation error estimation formula is as follows:

[0082]

[0083] Through derivation and transformation, and considering the cases under different matrices, the implicit Euler local truncation error step size estimation formula Δt is obtained. n (A i B i Error):

[0084]

[0085] Δt n (A i B i Error describes the relationship between the system simulation step size and the system matrices A and B, as well as the user-given error.

[0086] Furthermore, Δu n Typically, Δu represents the change in system input excitation before and after a switching action. Let the input voltage before the change be u1, and the input voltage after the change be u2. Then, Δu n =|u1-u2|.

[0087] Furthermore, when there is no switching action in the implicit Euler local truncation error step size estimation formula... The calculation methods include:

[0088] Considering a single switching cycle, we can obtain the analytical solution x(t) for all switching states;

[0089] Taking the first and second derivatives of x(t) respectively, we get and

[0090] If it exists available The corresponding time t value, substitute the t value into get

[0091] If it does not exist but If it is a monotonic function, then the corresponding time t needs to be substituted according to the system state, including:

[0092] For the switch closed state, substitute t=0 and t=conduction time into the equation. Compare the two and take the larger value.

[0093] For the switch open state, substitute t=0 and t=off time into... Compare the two and take the larger value.

[0094] Furthermore, the state-space equations under different switching conditions are obtained, that is, the relationship between the system state variables, inputs and outputs is expressed in matrix form, as shown in equation (1):

[0095]

[0096] Where A is the state matrix, B is the input matrix, C is the output matrix, and D is the direct transfer matrix. Table i below indicates that the system is in the i-th switching state.

[0097] When there is no switch action, according to matrix A i and B i Calculate the allowable step size for each switching state and denote the set of these step sizes as t1;

[0098] When a switching action occurs, according to matrix B i Calculate the allowable step size at each instant of switching, and B i Let t2 be the matrix before the switch is switched, and denote the set of these step sizes as t2.

[0099] Δt n (A i B i The error (Error) describes the relationship between the system simulation step size and the system matrices A and B, as well as the user-given error.

[0100] The system does not require prior simulation; it only needs to know the system state space matrix and the user-defined simulation error range to perform the simulation using the formula Δt. n (A i B i Error) Estimate the initial simulation step size for user input;

[0101] Considering the possibility of DC bus voltage fluctuations within a certain step during power electronic system simulation, where the switching state remains unchanged but the input excitation changes, the formula is still used. To estimate the simulation step size;

[0102] The dimension of the state matrix can be of any order, depending on the order of the actual circuit model being built.

[0103] The Buck power converter simulation test platform built according to this embodiment provides three different switching states.

[0104] Specifically, in discontinuous conduction mode (DCM), the circuit structure and corresponding state space matrix of the Buck circuit under different switching states are as follows: Figure 4 — Figure 6 As shown;

[0105] The inductor current variation curve of the Buck power converter in discontinuous conduction mode during one switching cycle is shown in the figure below. Figure 7 As shown;

[0106] In engineering applications, power electronic system simulation mainly analyzes the changes in state variables when the system is in a stable state. Therefore, this invention applies the step size estimation method described in this invention when the system reaches a stable state, and only needs to analyze one switching cycle, including:

[0107] In one switching cycle, the analytical solutions il(t) and vc(t) of the state variables of the Buck circuit in DCM mode can be obtained by using the Laplace transform method. Let the three states of the Buck circuit in DCM mode be state one, state two and state three respectively.

[0108] The switching transistor is turned on, i.e., state one:

[0109] The resulting spatial matrix is:

[0110]

[0111] The analytical solution obtained is:

[0112]

[0113]

[0114] The switch is off, i.e., state two:

[0115] The resulting spatial matrix is:

[0116]

[0117] The analytical solution obtained is:

[0118]

[0119]

[0120] When the switching transistor is turned on, the inductor current drops to 0, i.e., state three:

[0121] The resulting spatial matrix is:

[0122]

[0123] The analytical solution obtained is:

[0124] il(t) = 0;

[0125]

[0126] After analysis The time t values ​​corresponding to the maximum values ​​in the three states are shown in Table 2 below:

[0127]

[0128] Substitute the time t obtained from Table 2 into... In the middle, we get As shown in Table 3 below:

[0129]

[0130] The implicit Euler local truncation error step size estimation formula Δt according to the present invention n (A i B i Substituting the results obtained above into the step size set, as shown in Table 4 below:

[0131]

[0132] Take the minimum value from all step size sets in Table 4. This value is the maximum allowable step size that satisfies the error requirement. It is easy to see that the maximum allowable step size is 2.5 × 10⁻⁶. -8 .

[0133] The error curve plotted based on the step size estimation obtained from the power electronic system simulation step size optimization selection method provided in this embodiment is shown in the figure. Figure 8 As shown,

[0134] The estimated step size is used in circuit simulation software, and the circuit simulation results are compared with the actual values.

[0135] Write a program algorithm to plot the error curve between the analytical solution and the numerical solution at this step size;

[0136] Depend on Figure 8 and Figure 9 It can be seen that the error curves plotted by the step size estimated by the method are all within the error range set by the user.

[0137] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be various simulation tools and circuit simulation software, including several instructions to cause a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments.

[0138] It should be noted that the Buck power converter simulation test platform provided in this embodiment is used as a circuit simulation model of this application and is only used to illustrate this application. The power electronic system simulation step size optimization selection method provided in this application is applicable to any circuit and circuit simulation model.

[0139] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions, and variations can be made to these embodiments, including components, without departing from the principles and spirit of the present invention, and these variations still fall within the protection scope of the present invention.

Claims

1. A method for optimizing the selection of simulation step size for power electronic systems, characterized in that, The steps include the following: Step 1: Build a circuit simulation model and obtain the spatial matrix of the circuit simulation model under different switching states. The spatial matrix includes a state matrix and an input matrix. Step 2: Based on the user-defined simulation error range, obtain the simulation error constraints t1 and t2 for each switching state using the implicit Euler local truncation error step size estimation formula. The formula for estimating the step size of the implicit Euler local truncation error is as follows: When there is no switch action, use type The simulation error constraint set t1 is estimated to be obtained; When a switch action occurs, use the following method: The simulation error constraint set t2 is estimated to be obtained; Recorded as ,in This indicates the fixed step size for system simulation; Error indicates the user-defined error range. Represents the state matrix of the system. Represents the system's input matrix. This represents the maximum value of the derivative of the system state variable, and the subscript i indicates that the system is in the i-th switching state. This indicates the change in system input; Maximum value of the derivative of the system state variables The method for obtaining it is as follows: In one switching cycle, the analytical solutions for all switching states are obtained. ; right Finding the first and second derivatives yields... and ; If it exists ,available The corresponding time t value, substitute the t value into ,get ; If it does not exist ,but It is a monotonic function. Substituting the corresponding time t according to the switching state, including: For the switch closed state, and Substitution Compare the two and take the larger value. ; For the switch in the open state, and Substitution Compare the two and take the larger value. ; Step 3: Combine the simulation error constraint sets t1 and t2, and take the minimum value of the two sets to obtain the maximum simulation step size t allowed for the circuit system.

2. The method for optimizing the selection of simulation step size for a power electronic system according to claim 1, characterized in that, The method for obtaining the space matrix is ​​as follows: Based on the state-space equations under different switching conditions, the space matrix is ​​calculated, and its expression is as follows: ； Where A is the state matrix, B is the input matrix, C is the output matrix, D is the direct transfer matrix, and the subscript i indicates that the system is in the i-th switching state.

3. The method for optimizing the selection of simulation step size for a power electronic system according to claim 1, characterized in that, The term "no-switch action" refers to the simulation circuit model maintaining a closed and closed state.

4. The method for optimizing the selection of simulation step size for a power electronic system according to claim 1, characterized in that, The switching action refers to the time points when the simulation circuit model performs closing and closing operations.

5. The method for optimizing the selection of simulation step size for a power electronic system according to claim 1, characterized in that, In step 1, before obtaining the state space matrix of the circuit under different switching conditions, it is necessary to define the names, variable types, and parameter values ​​of the circuit components.

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