A chip system design verification method based on behavior modeling

Abstract

The application relates to a chip system design verification method based on behavior modeling, which comprises the following steps: establishing a behavior model according to a chip system design, wherein the behavior model is used for expressing the chip system at different abstraction levels; building a verification environment based on the behavior model, and performing function verification on the chip system. The application can provide real performance evaluation for chip system design.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to a chip system design verification method based on behavioral modeling. Background Technology

[0002] The success rate of first-time design for complex chips depends on 80% of the time spent in the early stages of the project, namely system architecture design and planning. With the extensive use of IP in chip design, the performance and reliability of individual IPs have gradually improved. System failures are more often due to performance losses caused by implicit constraints between IPs, rather than functional defects in individual components. To avoid such system failures, the traditional industry approach relies on the experience of system design engineers. Even so, it is still common for chip performance to fall short of the system design expectations. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a chip system design verification method based on behavior modeling, which can provide a realistic performance evaluation for chip system design.

[0004] The technical solution adopted by this invention to solve its technical problem is: to provide a chip system design verification method based on behavioral modeling, comprising the following steps:

[0005] A behavioral model is established based on the chip system design, and the behavioral model is used to express the chip system at different levels of abstraction.

[0006] A verification environment was built based on the behavioral model, and the chip system was functionally verified.

[0007] The abstraction hierarchy of the behavioral model includes:

[0008] The algorithm layer describes the functionality of the chip system.

[0009] The structural layer describes the components of the chip system and the relationships between them.

[0010] The implementation layer describes the specific implementation of the chip system, including the connections and parameters of the circuit elements.

[0011] The verification environment built based on the behavioral model includes:

[0012] A high-level model is built on top of the algorithm layer, and the high-level model is a simple program or algorithm description;

[0013] Map the high-level model to a low-level model;

[0014] The low-level model is then converted into executable code to ensure the correctness of the system in both hardware and software.

[0015] The verification environment includes a random engine, a SOC model, a DDR model, and a platform. The random engine is used to randomly simulate memory read and write instructions. The SOC model includes the structure diagram of the chip system design to form corresponding components. The DDR model is used to implement the hierarchical structure of Channel-Rank-Bank-Row-Column, maintain the state machine of each node in the hierarchical structure, and provide access latency to each node according to address mapping. The platform is used to provide configuration.

[0016] Beneficial effects

[0017] By adopting the above-mentioned technical solution, this invention has the following advantages and positive effects compared with the prior art: This invention establishes a behavioral model based on the chip system design and builds a verification environment based on the behavioral model to perform functional verification on the chip system. The verification results provide a realistic performance evaluation for the system design, thereby improving the accuracy of the system design and reducing the need for corrections and adjustments in the later implementation stage. The behavioral model established in this embodiment can be saved and reused. Based on the reusable behavioral model, the system design can quickly converge to the correct path in the early stages of chip design through a closed-loop operation of modeling -> verification -> model modification, reducing development costs and improving design / verification efficiency. Attached Figure Description

[0018] Figure 1 This is a flowchart of the chip system design verification method based on behavior modeling according to an embodiment of the present invention;

[0019] Figure 2 This is a structural diagram of an 8-core SOC processor in an embodiment of the present invention;

[0020] Figure 3 This is a cache distribution structure diagram in an embodiment of the present invention;

[0021] Figure 4 This is a diagram of the model structure and verification environment in an embodiment of the present invention;

[0022] Figure 5 This is a simulation result diagram of L3 hit rate in an embodiment of the present invention. Detailed Implementation

[0023] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0024] Embodiments of the present invention relate to a chip system design verification method based on behavioral modeling, such as... Figure 1 As shown, it includes the following steps:

[0025] Step 1: Establish a behavioral model based on the chip system design. The behavioral model is used to express the chip system at different levels of abstraction.

[0026] The verification method in this embodiment does not target RTL (Real-Time Level) for verification, but rather a behavioral model derived from a chip system design description. The core of this behavioral model is the use of high-level descriptions to express chip system behavior. These descriptions can represent the chip system at different levels of abstraction. These levels of abstraction include:

[0027] Algorithm layer: This is the highest level of abstraction, used to describe the functionality of the chip system, but it does not consider the specific implementation details.

[0028] Structure Layer: This abstract layer describes the components of the system and the relationships between them. In this implementation, the structure layer is derived from the algorithm layer.

[0029] Implementation layer: This abstraction level describes the specific implementation of the system, including the connection and parameters of circuit elements.

[0030] Step 2: Build a verification environment based on the behavioral model and perform functional verification on the chip system. Building the verification environment based on the behavioral model includes:

[0031] A high-level model is built on top of the algorithm layer, and the high-level model is a simple program or algorithm description;

[0032] Mapping the high-level model to a low-level model can be achieved using pre-defined tools and methods;

[0033] The low-level model is then converted into executable code to ensure the correctness of the system in both hardware and software.

[0034] The present invention will be further illustrated by a specific embodiment below.

[0035] This embodiment demonstrates the implementation of a behavior-based chip system design verification method in a DDR-CACHE application scenario. For example... Figure 2 As shown, the CPU model is 1 Process–2 Cluster–8 Core, with each Cluster containing 4 Cores and operating at a frequency of 800MHz.

[0036] The verification environment consists of RANDOM-ENGINE, SOC_MODEL, DDR_MODEL, and PLATFORM to simulate the implementation of Core / Hac memory read / write access instructions in the cache and / or DDR. The components and their functions are as follows:

[0037] RANDOM_ENGINE: Random engine used to randomly simulate memory read and write instructions.

[0038] SOC_MODEL: The SOC model, which can be referenced. Figure 2 CPU model structure diagram and Figure 3 The cache distribution structure consists of a single CPU, dual clusters, dual L2 caches, eight cores, eight L1 caches, a single HAC, a single L3 cache, and a single DDR controller. The cache provides cache-line lookup functionality based on address and records hit / miss results, maintains the cache-line state machine, and provides latency control for local cache access. The cores / Hacs provide routing between instruction and cache nodes.

[0039] DDR_MODEL: The DDR model is used to implement the Channel-Rank-Bank-Row-Column hierarchical structure, maintain the state machine of each node in the hierarchical structure, and provide access latency to each node based on address mapping.

[0040] PLATFORM: A platform that provides configuration and statistics functions.

[0041] The detailed composition of each component is as follows: Figure 4 As shown. The system behavior description provided by this chip system design includes:

[0042] DDR3: 2Gb x8, speed 1600K or DDR4: 2Gb x8, speed 2400R;

[0043] L1-cache / L2-cache / L3-cache size: configurable;

[0044] L1 cache / L2-cache / L3-cache latency: configurable;

[0045] Cluster number: configurable;

[0046] Number of cores per cluster: configurable;

[0047] Ratio of cache operating frequency to DDR operating frequency: configurable.

[0048] System simulation results are as follows Figure 5 As shown, it can be concluded that L3 cache configurations of 2MB and 4MB are the optimal solutions for scenarios where area / power consumption is prioritized and performance is prioritized, respectively.

[0049] It is easy to see that this invention establishes a behavioral model based on the chip system design and builds a verification environment based on the behavioral model to perform functional verification on the chip system. The verification results provide a realistic performance evaluation for the system design, thereby improving the accuracy of the system design and reducing the need for corrections and adjustments in the later implementation stage. The behavioral model established in this embodiment can be saved and reused. Based on the reusable behavioral model, the system design can quickly converge to the correct path in the early stages of chip design through a closed-loop operation of modeling -> verification -> model modification, reducing development costs and improving design / verification efficiency. In summary, the verification method provided by this invention is an advanced chip design verification method that can significantly improve design efficiency, reduce development costs, and improve the correctness of system design.

Claims

1. A chip system design verification method based on behavioral modeling, characterized in that, Includes the following steps: A behavioral model is established based on the chip system design, and the behavioral model is used to express the chip system at different levels of abstraction. The abstraction hierarchy of the behavioral model includes: The algorithm layer describes the functionality of the chip system. The structural layer describes the components of the chip system and the relationships between them. The implementation layer describes the specific implementation of the chip system, including the connections and parameters of circuit elements; A verification environment was built based on the behavioral model, and the chip system was functionally verified.

2. The chip system design verification method based on behavioral modeling according to claim 1, characterized in that, The verification environment built based on the behavioral model includes: A high-level model is built on top of the algorithm layer, and the high-level model is a simple program or algorithm description; Map the high-level model to a low-level model; The low-level model is then converted into executable code to ensure the correctness of the system in both hardware and software.

3. The chip system design verification method based on behavioral modeling according to claim 1, characterized in that, The verification environment includes a random engine, a SOC model, a DDR model, and a platform. The random engine is used to randomly simulate memory read and write instructions. The SOC model includes the structure diagram of the chip system design to form corresponding components. The DDR model is used to implement the hierarchical structure of Channel-Rank-Bank-Row-Column, maintain the state machine of each node in the hierarchical structure, and provide access latency to each node according to address mapping. The platform is used to provide configuration.

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