Display control method, apparatus, display device, and medium

Abstract

This application relates to a display control method, apparatus, display device, and storage medium. The method includes: controlling the display screen of the display device to turn off upon triggering a screen-off control command; after controlling the display screen to turn off, triggering the generation of multiple level control commands and corresponding level control timing sequences; based on the multiple level control commands and the level control timing sequences, controlling the reset circuit signal and / or the analog reference voltage signal to be in a high-level state, and controlling the digital power supply signal to be in a high-level state. This method can reduce the standby power consumption of the display device.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display control method, apparatus, display device, and storage medium. Background Technology

[0002] With the development of display devices, there are generally two types of chips in display devices: TPIC (Touch Panel driver Integrated Circuit) and DDIC (Display Driver Integrated Circuit). Since TPIC and DDIC have the same voltage requirement for power supply, display device manufacturers usually set TPIC and DDIC to share a single power supply in order to reduce production costs.

[0003] However, this configuration increases the standby power consumption of the display device. Summary of the Invention

[0004] Therefore, it is necessary to provide a display control method, apparatus, display device, computer-readable storage medium, and computer program product that can reduce the standby power consumption of display devices in order to address the above-mentioned technical problems.

[0005] In a first aspect, this application provides a display control method. Applied to a display device, the display device includes a display driver circuit chip, the display driver circuit chip includes a reset circuit, the reset circuit includes an input terminal for a reset circuit signal, a switching module, and a first signal amplification module, the first signal amplification module includes a first inverter, the first inverter includes an input terminal for a digital power signal, and the switching module includes an input terminal for an analog reference voltage signal, used to control the switching state by the level state of the analog reference voltage signal; the method includes:

[0006] When a screen-off control command is triggered, the display screen of the display device is turned off;

[0007] After the display screen is turned off, multiple level control commands and their corresponding level control timing sequences are triggered.

[0008] Based on multiple level control commands and the level control timing, the reset circuit signal and / or the analog reference voltage signal are controlled to be in a high-level state, and the digital power supply signal is controlled to be in a high-level state.

[0009] In one embodiment, controlling the display screen of the display device to turn off upon triggering a screen-off control command includes:

[0010] The screen-off control command is triggered based on a preset command triggering method; the command triggering method includes either a button triggering method or a brightness duration triggering method.

[0011] When a screen-off control command is triggered, the display screen of the display device is turned off by receiving the screen-off control command through the display driver circuit chip.

[0012] In one embodiment, the plurality of level control instructions include a first type of control instructions, the reset circuit includes a second signal amplification module, the second signal amplification module includes an input terminal for a data power signal; controlling the reset circuit signal and / or the analog reference voltage signal to be in a high-level state based on the plurality of level control instructions and the level control timing includes:

[0013] When multiple level control instructions are of the first type, the reset circuit signal is controlled to be in a high-level state;

[0014] When the reset circuit signal is at a high level, the analog reference voltage signal is controlled to be at a high level.

[0015] While controlling the analog reference voltage signal to be at a high level, the data power supply signal is controlled to be at a low level.

[0016] In one embodiment, the plurality of level control instructions includes a second type of control instructions. The step of controlling the reset circuit signal and / or the analog reference voltage signal to be in a high-level state based on the plurality of level control instructions and the level control timing further includes:

[0017] When multiple level control commands are type II control commands, the reset circuit signal is controlled to be in a low-level state;

[0018] When the reset circuit signal is in a low-level state, the analog reference voltage signal is controlled to be in a high-level state;

[0019] While controlling the analog reference voltage signal to be at a high level, the data power supply signal is controlled to be at a low level.

[0020] In one embodiment, the plurality of level control instructions includes a third type of control instruction. The step of controlling the reset circuit signal and / or the analog reference voltage signal to be in a high-level state based on the plurality of level control instructions and the level control timing further includes:

[0021] When multiple level control commands are third-type control commands, the reset circuit signal is controlled to be in a high-level state;

[0022] When the reset circuit signal is at a high level, the analog reference voltage signal is controlled to be at a low level.

[0023] When the analog reference voltage signal is at a low level, the data power supply signal is controlled to be at a low level.

[0024] In one embodiment, controlling the digital power signal to be in a high-level state includes:

[0025] When the data power signal is at a low level, the digital power signal is controlled to be at a high level.

[0026] In one embodiment, the method further includes:

[0027] Upon receiving a screen-on command, the data power signal in the control display driver circuit chip is set to a high level.

[0028] When the data power signal is at a high level, the analog reference voltage signal is controlled to be at a high level.

[0029] When the analog reference voltage signal is at a high level, the reset circuit signal is controlled to be at a high level.

[0030] In one embodiment, the voltage value corresponding to the high-level state of the reset circuit signal is equal to the voltage value corresponding to the high-level state of the digital power signal.

[0031] Secondly, this application also provides a display control device. Applied to a display device, the display device includes a display driver circuit chip, the display driver circuit chip includes a reset circuit, the reset circuit includes a switching module and a first signal amplification module, the first signal amplification module includes a first inverter, the first inverter includes an input terminal for a digital power signal, the switching module includes an input terminal for an analog reference voltage signal, used to control the switching state by the level state of the analog reference voltage signal; the device includes:

[0032] The display screen off control module is used to control the display screen of the display device to turn off when an off control command is triggered.

[0033] The level control instruction generation module is used to trigger the generation of multiple level control instructions and the corresponding level control timing sequence after the display screen is turned off.

[0034] The level state control module is used to control the reset circuit signal and / or the analog reference voltage signal to be in a high level state, and to control the digital power supply signal to be in a high level state, based on multiple level control commands and the level control timing.

[0035] Thirdly, this application also provides a display device. The display device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the steps of the method described above.

[0036] Fourthly, this application also provides a computer-readable storage medium. The computer-readable storage medium stores a computer program thereon, which, when executed by a processor, implements the steps of the above-described method.

[0037] Fifthly, this application also provides a computer program product. The computer program product includes a computer program that, when executed by a processor, implements the steps of the above-described method.

[0038] The aforementioned display control method, apparatus, display device, storage medium, and computer program product, upon triggering a screen-off control command, control the display screen of the display device to turn off; after controlling the display screen to turn off, triggers the generation of multiple level control commands and corresponding level control timing sequences; based on the multiple level control commands and level control timing sequences, controls the reset circuit signal and / or analog reference voltage signal to be in a high-level state, and controls the digital power supply signal to be in a high-level state, thereby avoiding leakage current in the reset circuit of the display driver circuit chip and reducing the standby power consumption of the display device. Attached Figure Description

[0039] Figure 1 This is a schematic diagram showing that the TPIC and DDIC share a single power supply in one embodiment of the display device;

[0040] Figure 2 This is a flowchart illustrating the control method in one embodiment;

[0041] Figure 3 This is a schematic diagram of a reset circuit in one embodiment;

[0042] Figure 4 This is a structural diagram of inverter INV1 in one embodiment;

[0043] Figure 5 This is a timing diagram of the first type of control instruction in one embodiment;

[0044] Figure 6 This is a timing diagram of the second type of control command in one embodiment;

[0045] Figure 7 This is a timing diagram of the third type of control instruction in one embodiment;

[0046] Figure 8 A flowchart illustrating the control method in another embodiment is shown;

[0047] Figure 9 This is a structural block diagram of the control device shown in one embodiment;

[0048] Figure 10 This is a diagram showing the internal structure of a display device in one embodiment. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0050] With the development of display devices, these devices generally contain two types of chips: TPIC and DDIC. Since TPIC and DDIC require the same voltage, display device manufacturers typically share a single power supply for both to reduce production costs. Taking a mobile phone terminal as an example, refer to... Figure 1 This diagram illustrates a display device in which the TPIC and DDIC share a single power supply.

[0051] Specifically, the battery of a mobile terminal is generally 3.85V, which is input to the power chip of the display device. The LDO (low dropout regulator) in the power chip controls the amount of power supplied to the TPIC and DDIC.

[0052] However, in the process of realizing this invention, the inventors discovered the following problem in the related technology: Taking a mobile phone terminal as an example, when the display device is off, the DDIC does not need to use a power supply. Since the TPIC needs to continue to supply power when the display device is off, the DDIC also needs to continue to be powered. By detecting two current values ​​when the display device is off, with and without cutting off the power supply to the DDIC, it was found that the current supplying the DDIC with the power supply on is 3mA, and the current when the power supply is cut off is 0.1mA. This indicates that there is leakage current in the DDIC at this time, which increases the standby power consumption of the display device.

[0053] To solve this problem, such as Figure 2As shown, a display control method is provided, illustrated in the example of a display device. The display device includes a display driver circuit chip (DDIC), which includes a reset circuit. The reset circuit includes an input terminal for a reset circuit signal, a switching module, and a first signal amplification module. The first signal amplification module includes a first inverter, which includes an input terminal for a digital power signal. The switching module includes an input terminal for an analog reference voltage signal, used to control the switching state by the level state of the analog reference voltage signal. The method includes the following steps:

[0054] Step 202: When the screen-off control command is triggered, control the display screen of the display device to turn off.

[0055] The display device can be, but is not limited to, various personal computers, laptops, smartphones, tablets, IoT devices, and portable wearable devices, such as smartwatches, smart bracelets, and head-mounted devices.

[0056] The display device may include a display driver circuit chip (DDIC), a touch driver circuit chip (TPIC), a low-dropout linear regulator (LDO), a power supply chip, and a controller. The display driver circuit chip (DDIC) includes a reset circuit and internal chip circuitry. The reset circuit may include an anti-static module, a switching module, and a signal amplification module. The signal amplification module includes a first signal amplification module, which in turn includes a first inverter. Specifically, the input terminal of the reset circuit is the input terminal of the anti-static module, the output terminal of the anti-static module is the input terminal of the switching module, the output terminal of the switching module is the input terminal of the signal amplification module, and the output terminal of the signal amplification module is the input terminal of the internal chip circuitry.

[0057] The anti-static module prevents abnormal voltage values ​​from occurring at the reset circuit signal (RESX). The switching module controls the switching state by adjusting the level of the analog reference voltage signal (VCI). The reset circuit signal powers the reset circuit in the DDIC, and the signal amplification module receives and amplifies the reset circuit signal to control the voltage values ​​within the DDIC's internal circuitry.

[0058] In practice, the anti-static module can be constructed using diodes. The switching module can include a first switching module and a second switching module. The switching modules can be transistors, specifically P-MOS (P-type transistors), and their conduction state is controlled by the level of an analog reference voltage signal (VCI), thereby controlling the opening or closing of the control circuit. The signal amplification module can be an inverter. Specifically, the reference... Figure 3A schematic diagram of a reset circuit is shown, including an anti-static module 302, a switching module 304, and a signal amplification module 306. The anti-static module includes two diodes; the switching module includes two different sets of organic phototransistors (OPTs), denoted as OPTA and OPTB, respectively; and the signal amplification module includes four inverters, generally abbreviated as INV, denoted as INV1, INV2, INV3, and INV4, respectively. Specifically, the conduction state of OPTA is controlled by the level of the analog reference voltage signal (VCI). When the level of the analog reference voltage signal (VCI) is high, OPTA is turned on. The direction of the reset circuit signal is controlled by controlling the level of the analog reference voltage signal (VCI). Figure 3 In this diagram, VDDI is the digital power signal, which is the shared power supply for TPIC and DDIC. INV1 and INV2 are the input terminals for the digital power signal. VSSI is the common connection voltage (typically 0V). RESX_VDDI represents the voltage value of the input signal to INV1; RESX_DVDD represents the voltage value of the input signal to INV3.

[0059] refer to Figure 4 The diagram shows the structure of an inverter INV1, which can include P-Mos (P-type transistors) and N-Mos (N-type transistors). Figure 4 The inverter consists of an N-MOS and a P-MOS transistor. Their gates (G) are connected as the input, and their drains (D) are connected as the output. The source of the N-MOS transistor is grounded, and the source of the P-MOS transistor is connected to the power supply VDDI. When the input voltage of the inverter is approximately VDDI / 2, both the N-MOS and P-MOS transistors will conduct, resulting in leakage current. The direction of this current is... Figure 4 The direction of the middle arrow is from the source of the P-MOS to the source of the N-MOS.

[0060] For example, when a screen-off control command is triggered, the controller in the display device sends a screen-off command to the DDIC. Based on the screen-off command, the DDIC controls the display screen of the display device to turn off. Specifically, the screen-off can be controlled by disconnecting the power supply to the display screen of the display device.

[0061] Step 204: After controlling the display screen to turn off, trigger the generation of multiple level control commands and the corresponding level control timing sequences of the multiple level control commands.

[0062] The DDIC includes multiple level control instructions to control the level state of corresponding power signals in the reset circuit. These level states can be high or low. The DDIC's reset circuit can include inputs for three types of power signals: a reset circuit signal, an analog reference voltage signal, and a digital power signal. Therefore, the multiple level control instructions include control instructions for the level state of the reset circuit signal, the analog reference voltage signal, and the digital power signal.

[0063] The corresponding level control timing for multiple level control instructions can be as follows: the execution timing of the control instruction for the level state of the reset circuit signal is earlier than the execution timing of the control instruction for the level state of the analog reference voltage signal, and the execution timing of the control instruction for the level state of the analog reference voltage signal is earlier than the execution timing of the control instruction for the level state of the digital power supply signal.

[0064] Generally, the voltage value corresponding to the high level state of the reset circuit signal is 1.85V or 1.8V, and the voltage value corresponding to the low level state is 0V; the voltage value corresponding to the high level state of the analog reference voltage signal is 3V, and the voltage value corresponding to the low level state is 0V; the voltage value corresponding to the high level state of the digital power supply signal is generally 1.85V or 1.8V, and the voltage value corresponding to the low level state is 0V.

[0065] In practice, after the screen-off control command is triggered, the display device will enter three stages in sequence: the screen-off stage, the hibernation black screen stage, and the partial power-off stage.

[0066] Specifically, the screen-off phase is used to control the display screen of the display device to turn off. The sleep black screen phase is used to indicate that the display screen of the display device has turned off and to trigger the generation of multiple level control commands and their corresponding level control timing sequences. Specifically, after the display screen is successfully turned off based on the power chip, feedback is sent to the controller to indicate that the display screen is successfully turned off, thereby triggering the controller to generate multiple level control commands and their corresponding level control timing sequences. The partial power-off phase is used to perform a partial power-off operation based on the multiple level control commands and their corresponding level control timing sequences.

[0067] Step 206: Based on multiple level control commands and the level control timing, control the reset circuit signal and / or the analog reference voltage signal to be in a high-level state, and control the digital power supply signal to be in a high-level state.

[0068] The multiple level control instructions can be different categories of control instructions, and the classification of each category is based on the level state of the reset circuit signal and the analog reference voltage signal that need to be controlled. Specifically, the multiple level control instructions can be one of the first type, the second type, and the third type of control instructions.

[0069] For example, after triggering the generation of multiple level control commands and level control timing sequences, the controller sends the multiple level control commands and corresponding level control timing sequences to the DDIC to control the level states of the reset circuit signal, analog reference voltage signal, and digital power supply signal in the DDIC. Specifically, based on the multiple level control commands and level control timing sequences, the controller controls the reset circuit signal, analog reference voltage signal, and digital power supply signal to be in a high-level state, or controls the reset circuit signal to be in a high-level state, the analog reference voltage signal to be in a low-level state, and the digital power supply signal to be in a high-level state, or controls the reset circuit signal to be in a low-level state, the analog reference voltage signal to be in a high-level state, and the digital power supply signal to be in a high-level state.

[0070] In practical application, taking a mobile phone as an example, when the reset circuit signal and analog reference voltage signal of the DDIC in the mobile phone are controlled to be at a high level, and the digital power supply signal is controlled to be at a high level, the measured current of the VDDI power supply without disconnection is 0.15mA, which is less than the 3mA power supply current to the DDIC without disconnection in related technologies.

[0071] In the above display control method, when a screen-off control command is triggered, the display screen of the display device is controlled to turn off; after the display screen is controlled to turn off, multiple level control commands and corresponding level control timing sequences are generated; based on the multiple level control commands and level control timing sequences, the reset circuit signal and / or analog reference voltage signal are controlled to be in a high-level state, and the digital power supply signal is controlled to be in a high-level state, so as to avoid leakage current in the reset circuit in the DDIC, thereby reducing the standby power consumption of the display device.

[0072] In one embodiment, step 202 includes:

[0073] Step 2022: Based on a preset instruction triggering method, trigger the screen-off control instruction; the instruction triggering method includes either a button triggering method or a brightness duration triggering method.

[0074] Step 2024: When a screen-off control command is triggered, the display screen of the display device is turned off via the screen-off control command received by the DDIC.

[0075] The preset command triggering method can include either a button triggering method or a brightness duration triggering method. The button triggering method can be triggered by a button on the display device that turns off the screen; the brightness duration triggering method can be triggered based on a preset display brightness duration in the display device.

[0076] For example, when a screen-off control command is triggered, the controller in the display device sends a screen-off command to the DDIC. After receiving the screen-off command, the DDIC controls the display screen of the display device to turn off.

[0077] In the above embodiments, a screen-off control command is triggered based on a preset command triggering method. The screen-off control command received by the DDIC is used to control the display screen of the display device to turn off, so that the display device enters standby mode, thereby reducing the power consumption of the display device.

[0078] In one embodiment, the plurality of level control instructions include a first type of control instructions, the reset circuit includes a second signal amplification module, the second signal amplification module includes an input terminal for a data power signal; based on the plurality of level control instructions and the level control timing, controlling the reset circuit signal and / or the analog reference voltage signal to be in a high-level state includes:

[0079] When multiple level control instructions are of the first type, the reset circuit signal is controlled to be in a high-level state;

[0080] When the reset circuit signal is at a high level, the analog reference voltage signal is controlled to be at a high level.

[0081] While controlling the analog reference voltage signal to be at a high level, the data power supply signal is controlled to be at a low level.

[0082] The reset circuit in the DDIC includes a second signal amplification module, which includes an input terminal for a data power signal. This data power signal is used to control the display of data in the display device. Specifically, the structure of the second signal amplification module can be found in [reference needed]. Figure 3 The second signal amplification module 3062 may include two inverters, INV3 and INV4. Both INV3 and INV4 include the input terminals for the data power signal DVDD. The internal structures of INV3 and INV4 can be found in [reference needed]. Figure 4 The internal structure of an inverter.

[0083] For example, when multiple level control instructions are of the first type, the control reset circuit signal and the analog reference voltage signal are kept at a high level. Specifically, when multiple level control instructions are of the first type, the controller sends a first reset control instruction to the DDIC. After receiving the first reset control instruction, the DDIC maintains the level of the reset circuit signal in the control reset circuit at a high level. When the controller detects that the level of the reset circuit signal in the reset circuit is kept at a high level, it sends a first analog signal control instruction to the DDIC to maintain the level of the analog reference voltage signal in the reset circuit at a high level. When the controller detects that the level of the analog reference voltage signal in the reset circuit is kept at a high level, it sends a first data control instruction to the DDIC to power down the data power signal in the reset circuit, so that the data power signal is at a low level. When the data power signal is at a low level, the digital power signal is kept at a high level. Specifically, refer to... Figure 5 The diagram illustrates the timing sequence of the first type of control commands. It shows the power signal levels during the screen-on, screen-off, sleep / black screen, and partial power-off phases of the display device. In cases where multiple level control commands are first type control commands, the partial power-off phase can be considered the display device's deep sleep state (DTSB).

[0084] Specifically, the execution delay of each level control instruction can be set to control the timing of the reset circuit signal, analog reference voltage signal, data power signal, and digital power signal levels in the reset circuit. The execution delay of each level control instruction can be set based on actual conditions.

[0085] In practice, based on experience, the priority of triggering the generation of the first type of control command is set higher than the priority of triggering the generation of the second and third types of control commands.

[0086] In the above embodiments, when multiple level control instructions are first-type control instructions, the control reset circuit signal is in a high-level state; when the reset circuit signal is in a high-level state, the control analog reference voltage signal is in a high-level state; when the control analog reference voltage signal is in a high-level state, the control data power supply signal is in a low-level state. This achieves partial power-off when the display device is in standby mode and avoids leakage current in the reset circuit of the DDIC, thereby reducing the standby power consumption of the display device.

[0087] In one embodiment, the plurality of level control instructions include a second type of control instructions. Based on the plurality of level control instructions and the level control timing, the reset circuit signal and / or the analog reference voltage signal are controlled to be in a high-level state. The method further includes:

[0088] When multiple level control commands are type II control commands, the reset circuit signal is controlled to be in a low-level state;

[0089] When the reset circuit signal is in a low-level state, the analog reference voltage signal is controlled to be in a high-level state;

[0090] While controlling the analog reference voltage signal to be at a high level, the data power supply signal is controlled to be at a low level.

[0091] For example, when multiple level control instructions are type II control instructions, the control reset circuit signal is in a low-level state, and the control analog reference voltage signal is in a high-level state. Specifically, when multiple level control instructions are type II control instructions, the controller sends a second reset control instruction to the DDIC. After receiving the second reset control instruction, the DDIC maintains the level of the reset circuit signal in the control reset circuit at a low level. When it is detected that the level of the reset circuit signal in the reset circuit is maintained at a low level, the controller sends a second analog signal control instruction to the DDIC to maintain the level of the analog reference voltage signal in the reset circuit at a high level. When it is detected that the level of the analog reference voltage signal in the reset circuit is maintained at a high level, the controller sends a second data control instruction to the DDIC to power down the data power signal in the reset circuit, so that the data power signal is in a low-level state. Specifically, refer to... Figure 6 The diagram illustrates the timing sequence of the second type of control commands. It also shows the power signal levels during the display device's screen-on, screen-off, sleep / black screen, and partial power-off phases.

[0092] In the above embodiments, when multiple level control instructions are second-type control instructions, the control reset circuit signal is in a low-level state; when the reset circuit signal is in a low-level state, the control analog reference voltage signal is in a high-level state; when the control analog reference voltage signal is in a high-level state, the control data power supply signal is in a low-level state. This achieves partial power-off when the display device is in standby mode and avoids leakage current in the reset circuit of the DDIC, thereby reducing the standby power consumption of the display device.

[0093] In one embodiment, the plurality of level control instructions includes a third type of control instruction, and the step of controlling the reset circuit signal and / or the analog reference voltage signal to be in a high-level state based on the plurality of level control instructions and the level control timing further includes:

[0094] When multiple level control commands are third-type control commands, the reset circuit signal is controlled to be in a high-level state;

[0095] When the reset circuit signal is at a high level, the analog reference voltage signal is controlled to be at a low level.

[0096] When the analog reference voltage signal is at a low level, the data power supply signal is controlled to be at a low level.

[0097] For example, when multiple level control instructions are third-type control instructions, the control reset circuit signal is in a high-level state, and the control analog reference voltage signal is in a low-level state. Specifically, when multiple level control instructions are third-type control instructions, the controller sends a third reset control instruction to the DDIC. After receiving the third reset control instruction, the DDIC maintains the level of the reset circuit signal in the control reset circuit at a high-level state. When the controller detects that the level of the reset circuit signal in the reset circuit is maintained at a high-level state, the controller sends a third analog signal control instruction to the DDIC to maintain the level of the analog reference voltage signal in the reset circuit at a low-level state. When the controller detects that the level of the analog reference voltage signal in the reset circuit is maintained at a low-level state, the controller sends a third data control instruction to the DDIC to power down the data power supply signal in the reset circuit, so that the data power supply signal is in a low-level state. When the data power supply signal is controlled at a low-level state, the digital power supply signal is controlled at a high-level state. Specifically, refer to... Figure 7 The diagram illustrates the timing sequence of the third type of control commands. It also shows the power signal levels during the display device's screen-on, screen-off, sleep / black screen, and partial power-off phases.

[0098] In the above embodiments, when multiple level control instructions are third-type control instructions, the control reset circuit signal is in a high-level state. When the reset circuit signal is in a high-level state, the control analog reference voltage signal is in a low-level state. When the control analog reference voltage signal is in a low-level state, the control data power supply signal is in a low-level state. This achieves partial power-off when the display device is in standby mode and avoids leakage current in the reset circuit of the DDIC, thereby reducing the standby power consumption of the display device.

[0099] In one embodiment, the method further includes:

[0100] Upon receiving a screen-on command, the data power signal in the DDIC is set to a high level.

[0101] When the data power signal is at a high level, the analog reference voltage signal is controlled to be at a high level.

[0102] When the analog reference voltage signal is at a high level, the reset circuit signal is controlled to be at a high level.

[0103] The screen-on command can be triggered by a button, specifically by pressing a button on the display device to turn on the screen.

[0104] For example, when the controller receives a screen-on command, it triggers the generation of a screen-on command to control the screen to light up, and sends a fourth data control command to the DDIC to control the data power signal in the reset circuit to a high level. When the data power signal is at a high level, it sends a fourth analog signal control command to the DDIC to control the analog reference voltage signal in the reset circuit to a high level. When the analog reference voltage signal is at a high level, it sends a fourth reset control command to the DDIC to control the reset circuit signal to a high level.

[0105] In one embodiment, the voltage value corresponding to the high-level state of the reset circuit signal is equal to the voltage value corresponding to the high-level state of the digital power supply signal.

[0106] In practice, taking a mobile phone as an example, the voltage value corresponding to the high level state of the digital power signal is generally 1.85V or 1.8V. Therefore, the voltage value corresponding to the high level state of the reset circuit signal should be equal to the voltage value corresponding to the high level state of the digital power signal.

[0107] To better understand the complete process of display control in the embodiments of the present invention, a complete example is provided for illustration. (Refer to...) Figure 8 The diagram illustrates a flow chart of a control method in another embodiment, including the following steps:

[0108] Step 802: Trigger the screen-off control command based on the preset command triggering method; the command triggering method includes either the button triggering method or the brightness duration triggering method.

[0109] Step 804: When a screen-off control command is triggered, the display screen of the display device is turned off by receiving the screen-off control command through the DDIC.

[0110] Step 806: After the control display screen is turned off, trigger the generation of multiple level control commands and the corresponding level control timing sequences of the multiple level control commands.

[0111] Step 808: When multiple level control instructions are type 1 control instructions, control the reset circuit signal to be in a high-level state; when the reset circuit signal is in a high-level state, control the analog reference voltage signal to be in a high-level state; when the analog reference voltage signal is in a high-level state, control the data power supply signal to be in a low-level state.

[0112] Step 810: When multiple level control instructions are type II control instructions, control the reset circuit signal to be in a low-level state; when the reset circuit signal is in a low-level state, control the analog reference voltage signal to be in a high-level state; when the analog reference voltage signal is in a high-level state, control the data power supply signal to be in a low-level state.

[0113] Step 812: When multiple level control instructions are third-class control instructions, control the reset circuit signal to be in a high-level state; when the reset circuit signal is in a high-level state, control the analog reference voltage signal to be in a low-level state; when the analog reference voltage signal is in a low-level state, control the data power supply signal to be in a low-level state.

[0114] Step 814: When the data power signal is at a low level, control the digital power signal to be at a high level.

[0115] In this embodiment, when a screen-off control command is triggered, the display screen of the display device is controlled to turn off. After the display screen is turned off, multiple level control commands and corresponding level control timing sequences are generated. Based on the multiple level control commands and level control timing sequences, the reset circuit signal and / or analog reference voltage signal are controlled to be in a high-level state, and the digital power supply signal is controlled to be in a high-level state, so as to avoid leakage current in the reset circuit in the DDIC, thereby reducing the standby power consumption of the display device.

[0116] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0117] Based on the same inventive concept, this application also provides a display control device for implementing the display control method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more display control device embodiments provided below can be found in the limitations of the display control method described above, and will not be repeated here.

[0118] In one embodiment, such as Figure 9 As shown, a display control device is provided, applied to a display device. The display device includes a display driver circuit chip, which includes a reset circuit. The reset circuit includes a switching module and a first signal amplification module. The first signal amplification module includes a first inverter, which includes an input terminal for a digital power signal. The switching module includes an input terminal for an analog reference voltage signal, used to control the switching state by the level state of the analog reference voltage signal. The device includes: a display screen off-screen control module 902, a level control command generation module 904, and a level state control module 906, wherein:

[0119] The display screen off control module 902 is used to control the display screen of the display device to turn off when an off control command is triggered;

[0120] The level control instruction generation module 904 is used to trigger the generation of multiple level control instructions and the corresponding level control timing sequence after the display screen is turned off.

[0121] The level state control module 906 is used to control the reset circuit signal and / or the analog reference voltage signal to be in a high level state and to control the digital power supply signal to be in a high level state based on multiple level control commands and the level control timing.

[0122] In some embodiments, the display screen off control module 902 includes:

[0123] A screen-off control command triggering unit is used to trigger the screen-off control command based on a preset command triggering method; the command triggering method includes either a button triggering method or a brightness duration triggering method.

[0124] The display screen off control unit is used to control the display screen of the display device to turn off when an off-screen control command is triggered, by receiving the off-screen control command from the display driver circuit chip.

[0125] In some embodiments, the plurality of level control instructions include a first type of control instructions, the reset circuit includes a second signal amplification module, the second signal amplification module includes an input terminal for a data power signal; the level state control module 906 includes:

[0126] The first reset information control unit is used to control the reset circuit signal to be in a high-level state when multiple level control instructions are first-type control instructions;

[0127] The first analog reference voltage signal control unit is used to control the analog reference voltage signal to be in a high-level state when the reset circuit signal is in a high-level state;

[0128] The first data power signal control unit is used to control the data power signal to be in a low-level state when the analog reference voltage signal is in a high-level state.

[0129] In some embodiments, the plurality of level control instructions include a second type of control instructions, and the level state control module 906 further includes:

[0130] The second reset information control unit is used to control the reset circuit signal to be in a low-level state when multiple level control instructions are second-type control instructions;

[0131] The second analog reference voltage signal control unit is used to control the analog reference voltage signal to be in a high-level state when the reset circuit signal is in a low-level state.

[0132] The second data power signal control unit is used to control the data power signal to be in a low-level state when the analog reference voltage signal is in a high-level state.

[0133] In some embodiments, the plurality of level control instructions include a third type of control instructions, and the level state control module 906 further includes:

[0134] The third reset information control unit is used to control the reset circuit signal to be in a high-level state when multiple level control instructions are third-type control instructions;

[0135] The third analog reference voltage signal control unit is used to control the analog reference voltage signal to be in a low level state when the reset circuit signal is in a high level state.

[0136] The third data power signal control unit is used to control the data power signal to be in a low-level state when the analog reference voltage signal is in a low-level state.

[0137] In some embodiments, the level state control module 906 is further configured to: control the digital power signal to be in a high level state when the data power signal is in a low level state.

[0138] In some embodiments, the display control device further includes:

[0139] The data power signal control module is used to control the data power signal in the display driver circuit chip to be in a high-level state when a screen-on command is received;

[0140] An analog reference voltage signal control module is used to control the analog reference voltage signal to be in a high-level state when the data power supply signal is in a high-level state;

[0141] The reset circuit signal control module is used to control the reset circuit signal to be in a high-level state when the analog reference voltage signal is in a high-level state.

[0142] In some embodiments, the voltage value corresponding to the high-level state of the reset circuit signal is equal to the voltage value corresponding to the high-level state of the digital power supply signal.

[0143] Each module in the aforementioned display control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the display device in hardware form or independent of it, or stored in the memory of the display device in software form, so that the processor can call and execute the operations corresponding to each module.

[0144] In one embodiment, a display device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 10As shown, the display device includes a processor, memory, input / output interface, communication interface, display unit, and input device. The processor, memory, and input / output interface are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interface. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The input / output interface is used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When the computer program is executed by the processor, it implements a display control method. The display unit of the display device forms a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the display device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the display device, or external keyboards, touchpads, or mice, etc.

[0145] Those skilled in the art will understand that Figure 10 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the display device to which the present application is applied. A specific display device may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0146] In one embodiment, a display device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0147] When a screen-off control command is triggered, the display screen of the display device is turned off;

[0148] After the display screen is turned off, multiple level control commands and their corresponding level control timing sequences are triggered.

[0149] Based on multiple level control commands and the level control timing, the reset circuit signal and / or the analog reference voltage signal are controlled to be in a high-level state, and the digital power supply signal is controlled to be in a high-level state.

[0150] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0151] When multiple level control instructions are of the first type, the reset circuit signal is controlled to be in a high-level state;

[0152] When the reset circuit signal is at a high level, the analog reference voltage signal is controlled to be at a high level.

[0153] While controlling the analog reference voltage signal to be at a high level, the data power supply signal is controlled to be at a low level.

[0154] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0155] When multiple level control commands are type II control commands, the reset circuit signal is controlled to be in a low-level state;

[0156] When the reset circuit signal is in a low-level state, the analog reference voltage signal is controlled to be in a high-level state;

[0157] While controlling the analog reference voltage signal to be at a high level, the data power supply signal is controlled to be at a low level.

[0158] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0159] When multiple level control commands are third-type control commands, the reset circuit signal is controlled to be in a high-level state;

[0160] When the reset circuit signal is at a high level, the analog reference voltage signal is controlled to be at a low level.

[0161] When the analog reference voltage signal is at a low level, the data power supply signal is controlled to be at a low level.

[0162] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0163] When a screen-off control command is triggered, the display screen of the display device is turned off;

[0164] After the display screen is turned off, multiple level control commands and their corresponding level control timing sequences are triggered.

[0165] Based on multiple level control commands and the level control timing, the reset circuit signal and / or the analog reference voltage signal are controlled to be in a high-level state, and the digital power supply signal is controlled to be in a high-level state.

[0166] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0167] When multiple level control instructions are of the first type, the reset circuit signal is controlled to be in a high-level state;

[0168] When the reset circuit signal is at a high level, the analog reference voltage signal is controlled to be at a high level.

[0169] While controlling the analog reference voltage signal to be at a high level, the data power supply signal is controlled to be at a low level.

[0170] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0171] When multiple level control commands are type II control commands, the reset circuit signal is controlled to be in a low-level state;

[0172] When the reset circuit signal is in a low-level state, the analog reference voltage signal is controlled to be in a high-level state;

[0173] While controlling the analog reference voltage signal to be at a high level, the data power supply signal is controlled to be at a low level.

[0174] In one embodiment, when the computer program is executed by a processor, it also performs the following steps:

[0175] When multiple level control commands are third-type control commands, the reset circuit signal is controlled to be in a high-level state;

[0176] When the reset circuit signal is at a high level, the analog reference voltage signal is controlled to be at a low level.

[0177] When the analog reference voltage signal is at a low level, the data power supply signal is controlled to be at a low level.

[0178] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0179] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0180] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0181] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0182] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A display control method, characterized in that, The method is applied to a display device, which includes a display driver circuit chip. The display driver circuit chip includes a reset circuit. The reset circuit includes an input terminal for a reset circuit signal, a switching module, and a first signal amplification module. The first signal amplification module includes a first inverter, which includes an input terminal for a digital power signal. The switching module includes an input terminal for an analog reference voltage signal, used to control the switching state by the level state of the analog reference voltage signal. The method includes: When a screen-off control command is triggered, the display screen of the display device is turned off; After the display screen is turned off, multiple level control commands and their corresponding level control timing sequences are triggered. Based on multiple level control commands and the level control timing, the reset circuit signal and / or the analog reference voltage signal are controlled to be in a high-level state, and the digital power supply signal is controlled to be in a high-level state.

2. The method according to claim 1, characterized in that, The step of controlling the display screen of the display device to turn off when a screen-off control command is triggered includes: The screen-off control command is triggered based on a preset command triggering method; the command triggering method includes either a button triggering method or a brightness duration triggering method. When a screen-off control command is triggered, the display screen of the display device is turned off by receiving the screen-off control command through the display driver circuit chip.

3. The method according to claim 1, characterized in that, The multiple level control instructions include a first type of control instructions; the reset circuit includes a second signal amplification module, which includes an input terminal for a data power signal; controlling the reset circuit signal and / or the analog reference voltage signal to be in a high-level state based on the multiple level control instructions and the level control timing includes: When multiple level control instructions are of the first type, the reset circuit signal is controlled to be in a high-level state; When the reset circuit signal is at a high level, the analog reference voltage signal is controlled to be at a high level. While controlling the analog reference voltage signal to be at a high level, the data power supply signal is controlled to be at a low level.

4. The method according to claim 3, characterized in that, Multiple level control instructions include a second type of control instructions. The step of controlling the reset circuit signal and / or the analog reference voltage signal to be in a high-level state based on the multiple level control instructions and the level control timing further includes: When multiple level control commands are type II control commands, the reset circuit signal is controlled to be in a low-level state; When the reset circuit signal is in a low-level state, the analog reference voltage signal is controlled to be in a high-level state; While controlling the analog reference voltage signal to be at a high level, the data power supply signal is controlled to be at a low level.

5. The method according to claim 4, characterized in that, Multiple level control instructions, including a third type of control instruction, further include controlling the reset circuit signal and / or the analog reference voltage signal to be in a high-level state based on the multiple level control instructions and the level control timing. When multiple level control commands are third-type control commands, the reset circuit signal is controlled to be in a high-level state; When the reset circuit signal is at a high level, the analog reference voltage signal is controlled to be at a low level. When the analog reference voltage signal is at a low level, the data power supply signal is controlled to be at a low level.

6. The method according to claim 5, characterized in that, The control of the digital power signal to be in a high-level state includes: When the data power signal is in a low-level state, control the digital power signal to be in a high-level state; The voltage value corresponding to the high-level state of the reset circuit signal is equal to the voltage value corresponding to the high-level state of the digital power supply signal.

7. The method according to claim 1, characterized in that, The method further includes: Upon receiving a screen-on command, the data power signal in the control display driver circuit chip is set to a high level. When the data power signal is at a high level, the analog reference voltage signal is controlled to be at a high level. When the analog reference voltage signal is at a high level, the reset circuit signal is controlled to be at a high level.

8. A display control device, characterized in that, An application in a display device, the display device including a display driver circuit chip, the display driver circuit chip including a reset circuit, the reset circuit including a switching module and a first signal amplification module, the first signal amplification module including a first inverter, the first inverter including an input terminal for a digital power signal, the switching module including an input terminal for an analog reference voltage signal, used to control the switching state by the level state of the analog reference voltage signal; the device includes: The display screen off control module is used to control the display screen of the display device to turn off when an off control command is triggered. The level control instruction generation module is used to trigger the generation of multiple level control instructions and the corresponding level control timing sequence after the display screen is turned off. The level state control module is used to control the reset circuit signal and / or the analog reference voltage signal to be in a high level state, and to control the digital power supply signal to be in a high level state, based on multiple level control commands and the level control timing.

9. A display device comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 7.

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