Shift register circuit, shift register, and digital microfluidic chip

Abstract

The application discloses a shift register circuit, a shift register and a digital micro-fluidic chip. The shift register circuit comprises an input module, a first discharge module, a second discharge module and an output module. The input module is configured to receive an input signal. The first discharge module is configured to receive a first clock signal, and the second discharge module is configured to receive the first clock signal. The control end of the output module is coupled to the second end of the input module, and the output module is configured to receive a second clock signal. The first clock signal and the second clock signal are complementary clock signals. The first discharge module and the second discharge module are configured to shift the input signal received by the input module under the control of the first clock signal, so that the output module forms an output signal according to the second clock signal and outputs the output signal from the output end of the shift register circuit. In this way, the circuit structure of the shift register circuit can be simplified, and the manufacturing cost can be reduced.

Description

Technical Field

[0001] This application relates to the field of microfluidics, and in particular to shift register circuits, shift registers and digital microfluidic chips. Background Technology

[0002] Shift register circuits have been widely used in the flat panel display industry to provide scanning signals for active matrices. In active digital microfluidic chips, their main applications include providing driving voltage and facilitating the interaction between the digital microfluidic chip and an external controller, enabling line-by-line scanning of the droplet driving electrodes. In traditional active digital microfluidic chips, the row scanning signal is implemented by an external integrated circuit (G-COF). However, by using shift register circuits, the scanning driving circuit can be fabricated using the same process technology as thin-film transistors (TFTs) with only a few control signals provided by the external circuitry, achieving line-by-line scanning. Therefore, using shift register circuits eliminates the need for integrated circuits related to scanning drive, reducing manufacturing costs.

[0003] However, the voltage required to drive droplets typically reaches tens or even hundreds of volts, while the current shift register transmission circuits used in flat panel displays operate at relatively low voltages, which cannot meet the driving requirements of active digital microfluidic chips. Therefore, it is necessary to explore new shift register circuits. Summary of the Invention

[0004] This application provides a shift register circuit, a shift register, and a digital microfluidic chip, which can meet the voltage requirements of the digital microfluidic chip and simplify the circuit structure of the shift register circuit, thereby reducing manufacturing costs.

[0005] In a first aspect, this application provides a shift register circuit, comprising: an input module, wherein a control terminal and a first terminal of the input module are used to receive an input signal; wherein the first terminal of the input module serves as the input terminal of the shift register circuit; a first discharge module, wherein the input terminal of the first discharge module is used to receive a first clock signal, and the control terminal of the first discharge module is coupled to a second terminal of the input module; a second discharge module, wherein the first terminal of the second discharge module is used to receive the first clock signal, the second terminal of the second discharge module is grounded, and the control terminal of the second discharge module is coupled to the second terminal of the input module; and an output module, wherein the control terminal of the output module is coupled to the second terminal of the input module, the first terminal of the output module is used to receive a second clock signal, and the second terminal of the output module is coupled to a third terminal of the second discharge module; wherein the first clock signal and the second clock signal are complementary clock signals, and the second terminal of the output module serves as the output terminal of the shift register circuit; wherein the first discharge module and the second discharge module are used to shift the input signal received by the input module under the control of the first clock signal, so that the output module forms an output signal according to the second clock signal and outputs it from the output terminal of the shift register circuit.

[0006] The first discharge module includes: a first capacitor, whose first terminal serves as the input terminal of the first discharge module for receiving a first clock signal; a first transistor, whose control terminal is coupled to the second terminal of the first capacitor, whose first terminal is coupled to the second terminal of the input module, and whose second terminal is grounded; a second transistor, whose control terminal is coupled to the second terminal of the input module, whose first terminal is coupled to the second terminal of the first capacitor, and whose second terminal is grounded; a third transistor, whose control terminal is coupled to the second terminal of the first capacitor and coupled to the second terminal of the input module through the second capacitor, and whose second terminal is grounded; the second discharge module includes: a fourth transistor, whose first terminal is coupled to the first capacitor... The first terminal has its control terminal coupled to the second terminal of the input module; the fifth transistor has its control terminal coupled to the second terminal of the fourth transistor, its first terminal coupled to the second terminal of the output module, and its second terminal grounded; wherein, during the first time period, the first clock signal is high, the first transistor is cut off, the second transistor, the fourth transistor and the fifth transistor are turned on, the output signal output by the output module is low, and the second capacitor is charged; during the second time period, the first clock signal is low, the second clock signal changes from low to high, the second capacitor discharges, and the output signal output by the output module is high.

[0007] The shift register circuit further includes: a reset module, the first end of which is coupled to the second end of the input module, the second end of which is grounded, and the control end of the reset module for receiving a reset signal.

[0008] The reset module includes: a sixth transistor, whose control terminal is used to receive a first reset signal, its first terminal is coupled to the second terminal of the input module, and its second terminal is grounded; a seventh transistor, whose control terminal is used to receive a second reset signal, its first terminal is coupled to the second terminal of the input module, and its second terminal is grounded; wherein, in response to receiving the second reset signal, the seventh transistor performs an initial reset of the shift register circuit; during the operation of the shift register circuit, the sixth transistor performs a reset of the shift register circuit in response to receiving the first reset signal.

[0009] The pulse widths of the first clock signal and the second clock signal are equal to the pulse width of the input signal.

[0010] The input module includes an eighth transistor, whose control terminal and first terminal are used to receive input signals, and whose second terminal is coupled to the control terminal of the first discharge module.

[0011] The output module includes a ninth transistor. The control terminal of the ninth transistor is coupled to the second terminal of the input module. The first terminal of the ninth transistor is used to receive a second clock signal. The second terminal of the ninth transistor is coupled to the third terminal of the second discharge module.

[0012] Among them, the high-level second clock signal can reach 40V, and the shift register circuit 100 can operate at a frequency of 100KHz.

[0013] The shift register circuit can drive a 50pF load.

[0014] The transistor is an amorphous silicon thin-film transistor.

[0015] Secondly, this application provides a shift register that includes a plurality of cascaded shift register circuits as described in the first aspect above.

[0016] Thirdly, this application provides a digital microfluidic chip, including a shift register or multiple cascaded shift register circuits, wherein the shift register is as provided in the second aspect above, and the shift register circuit is as provided in the first aspect above.

[0017] The beneficial effects of this application are as follows: Unlike the prior art, the shift register circuit, shift register and digital microfluidic chip provided in this application include: an input module, a first discharge module, a second discharge module and an output module. The input module has a control terminal and a first terminal for receiving input signals; the first terminal of the input module serves as the input terminal of the shift register circuit. The input terminal of the first discharge module receives a first clock signal, and the control terminal of the first discharge module is coupled to the second terminal of the input module. The first terminal of the second discharge module receives the first clock signal, the second terminal of the second discharge module is grounded, and the control terminal of the second discharge module is coupled to the second terminal of the input module. The control terminal of the output module is coupled to the second terminal of the input module, the first terminal of the output module receives a second clock signal, and the second terminal of the output module is coupled to the third terminal of the second discharge module. The first and second clock signals are complementary clock signals, and the second terminal of the output module serves as the output terminal of the shift register circuit. The first and second discharge modules, under the control of the first clock signal, shift the input signal received by the input module so that the output module forms an output signal based on the second clock signal and outputs it from the output terminal of the shift register circuit. This satisfies the voltage requirements of the digital microfluidic chip, and by using the second clock signal to form the output signal, no additional voltage source is required, which simplifies the circuit structure of the shift register circuit and reduces manufacturing costs. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0019] Figure 1 This is a schematic diagram of an embodiment of the shift register circuit provided in this application;

[0020] Figure 2 This is a schematic diagram of another embodiment of the shift register circuit provided in this application;

[0021] Figure 3 This application provides Figure 2 A schematic diagram of the signal waveform in the shift register circuit;

[0022] Figure 4 This is a schematic diagram of another embodiment of the shift register circuit provided in this application;

[0023] Figure 5 This is a schematic diagram of another embodiment of the shift register circuit provided in this application;

[0024] Figure 6 This application provides Figure 5 A schematic diagram of the signal waveform in the shift register circuit;

[0025] Figure 7 This is a schematic diagram of the structure of an embodiment of the shift register provided in this application;

[0026] Figure 8 This application provides Figure 7 A schematic diagram of the signal waveform in the shift register. Detailed Implementation

[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0028] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0029] Digital microfluidics (DMF) technology offers advantages such as portability, high integrity, low cost, and high efficiency in fields like biology, medicine, and chemistry, and has broad application prospects. DMF control is mostly based on the principle of electrowetting-on-dielectric (EWOD). By controlling peripheral circuits to input modulated voltage signals to the electrode array, the distribution and movement of droplets can be arbitrarily controlled on the two-dimensional plane of the microfluidic chip.

[0030] Digital microfluidic chips with large pixel arrays are a prerequisite for high-throughput and automated on-chip processing of biological samples. However, most conventional digital microfluidic chips today use passive electrode arrays, where each pixel electrode is directly connected to the control circuitry via a separate wire. Increasing the number of pixels means increasing the number of huge signal lines and the complexity of the control circuitry, which greatly increases the design and manufacturing complexity of the array.

[0031] The solution to this problem is active matrix technology, which integrates thin film transistors (TFTs) into each pixel electrode. Each TFT is equivalent to an electronic switch, and applying a voltage to the gate can control the conduction and shutdown between the source and drain electrodes.

[0032] Shift register circuits have been widely used in the flat panel display industry to provide scanning signals for active matrices. In active digital microfluidic chips, their main applications include providing driving voltage and facilitating the interaction between the digital microfluidic chip and an external controller, enabling line-by-line scanning of the droplet driving electrodes. In traditional active digital microfluidic chips, the row scanning signal is implemented by an external integrated circuit (G-COF). However, by using shift register circuits, the scanning driving circuit can be fabricated using the same process technology as thin-film transistors (TFTs) with only a few control signals provided by the external circuitry, achieving line-by-line scanning. Therefore, using shift register circuits eliminates the need for integrated circuits related to scanning drive, reducing manufacturing costs.

[0033] However, the voltage required to drive droplets typically reaches tens or even hundreds of volts, while the current shift register transmission circuits used in flat panel displays operate at relatively low voltages, which cannot meet the driving requirements of active digital microfluidic chips. Therefore, it is necessary to explore new shift register circuits.

[0034] Based on this, this application provides a shift register circuit, a shift register, and a digital microfluidic chip. The shift register circuit includes an input module, a first discharge module, a second discharge module, and an output module. The input module has a control terminal and a first terminal for receiving input signals; the first terminal of the input module serves as the input terminal of the shift register circuit. The input terminal of the first discharge module receives a first clock signal, and the control terminal of the first discharge module is coupled to the second terminal of the input module. The first terminal of the second discharge module receives the first clock signal, the second terminal of the second discharge module is grounded, and the control terminal of the second discharge module is coupled to the second terminal of the input module. The control terminal of the output module is coupled to the second terminal of the input module, the first terminal of the output module receives a second clock signal, and the second terminal of the output module is coupled to the third terminal of the second discharge module. The first and second clock signals are complementary clock signals, and the second terminal of the output module serves as the output terminal of the shift register circuit. The first and second discharge modules, under the control of the first clock signal, shift the input signal received by the input module, so that the output module forms an output signal based on the second clock signal, which is output from the output terminal of the shift register circuit. This satisfies the voltage requirements of the digital microfluidic chip, and by using the second clock signal to form the output signal, no additional voltage source is needed, simplifying the circuit structure of the shift register circuit and reducing manufacturing costs. See any of the following embodiments for details.

[0035] See Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the shift register circuit provided in this application. The shift register circuit 100 includes: an input module 10, a first discharge module 20, a second discharge module 30, and an output module 40.

[0036] The input module 10 has a control terminal and a first terminal for receiving the input signal IN; the first terminal of the input module 10 serves as the input terminal of the shift register circuit 100. In one application scenario, the input signal IN can be provided by an upstream circuit, such as being output from the output terminal of the upstream circuit. If the shift register circuit 100 is the first circuit with a shift function, the input signal IN is provided by an external circuit.

[0037] The input terminal of the first discharge module 20 is used to receive the first clock signal CK, and the control terminal of the first discharge module 20 is coupled to the second terminal of the input module 10.

[0038] The first terminal of the second discharge module 30 is used to receive the first clock signal CK, the second terminal of the second discharge module 30 is grounded, and the control terminal of the second discharge module 30 is coupled to the second terminal of the input module 10.

[0039] The control terminal of the output module 40 is coupled to the second terminal of the input module 10, the first terminal of the output module 40 is used to receive the second clock signal XCK, and the second terminal of the output module 40 is coupled to the third terminal of the second discharge module 30; wherein, the first clock signal CK and the second clock signal XCK are complementary clock signals; the second terminal of the output module 40 serves as the output terminal of the shift register circuit 100.

[0040] In one application scenario, the first discharge module 20 and the second discharge module 30 are used to shift the input signal IN received by the input module 10 under the control of the first clock signal CK, so that the output module 40 generates an output signal OUT according to the second clock signal XCK and outputs it from the output terminal of the shift register circuit 100. It can be understood that at this time, the output signal OUT and the second clock signal XCK have the same level.

[0041] It is understandable that, since the first clock signal CK and the second clock signal XCK are complementary clock signals, when the first clock signal CK is high, the second clock signal XCK is low. When the second clock signal XCK is high, the first clock signal CK is low. That is, during the first time period, both the first clock signal CK and the input signal are high, and the second clock signal XCK is low, therefore the output signal OUT formed by the output module 40 is also low. During the second time period, the first clock signal CK and the input signal IN transition from high to low, and the second clock signal XCK also transitions to high, therefore the output signal OUT formed by the output module 40 is also high. Essentially, under the combined action of the first discharge module 20, the second discharge module 30, the first clock signal CK, the second clock signal XCK, and the output module 40, the input signal IN is shifted, so that when the input signal IN is high, the corresponding output signal OUT is low, and when the input signal IN transitions from high to low, the corresponding output signal OUT is high. The high-level input signal IN of the input shift register circuit 100 is shifted in time when it is output by the shift register circuit 100.

[0042] Furthermore, the output signal OUT of the shift register circuit 100 in this application is determined by the second clock signal XCK, which does not require an additional voltage source to support the output signal OUT, thus simplifying the circuit structure.

[0043] In this embodiment, the shift register circuit 100 includes: an input module 10, a first discharge module 20, a second discharge module 30, and an output module 40. The control terminal and a first terminal of the input module 10 are used to receive the input signal IN; and the first terminal of the input module 10 serves as the input terminal of the shift register circuit 100. The input terminal of the first discharge module 20 is used to receive the first clock signal CK, and the control terminal of the first discharge module 20 is coupled to the second terminal of the input module 10. The first terminal of the second discharge module 30 is used to receive the first clock signal CK, the second terminal of the second discharge module 30 is grounded, and the control terminal of the second discharge module 30 is coupled to the second terminal of the input module 10. The control terminal of the output module 40 is coupled to the second terminal of the input module 10, the first terminal of the output module 40 is used to receive the second clock signal XCK, and the second terminal of the output module 40 is coupled to the second discharge module 30. The third terminal of 0; wherein, the first clock signal CK and the second clock signal XCK are complementary clock signals, and the second terminal of the output module 40 serves as the output terminal of the shift register circuit 100; the first discharge module 20 and the second discharge module 30 are used to shift the input signal IN received by the input module 10 under the control of the first clock signal CK, so that the output module 40 forms an output signal OUT according to the second clock signal XCK and outputs it from the output terminal of the shift register circuit 100. This can meet the voltage requirements of the digital microfluidic chip, and by using the second clock signal XCK to form the output signal OUT, there is no need to set up an additional voltage source, which can simplify the circuit structure of the shift register circuit 100 and reduce the manufacturing cost.

[0044] See Figure 2 , Figure 2 This is a schematic diagram of another embodiment of the shift register circuit provided in this application. The shift register circuit 100 includes: an input module 10, a first capacitor C2, a first transistor T4, a second transistor T5, a third transistor T7, a fourth transistor T6, a fifth transistor T9, and an output module 40.

[0045] The first capacitor C2, the first transistor T4, the second transistor T5, and the third transistor T7 constitute the first discharge module 10 described above. The fourth transistor T6 and the fifth transistor T9 constitute the second discharge module 30 described above.

[0046] Specifically, the first terminal of the first capacitor C2 serves as the input terminal of the first discharge module 10 mentioned above, and is used to receive the first clock signal CK.

[0047] The control terminal of the first transistor T4 is coupled to the second terminal of the first capacitor C2, the first terminal of the first transistor T4 is coupled to the second terminal of the aforementioned input module 10, and the second terminal of the first transistor T4 is grounded.

[0048] The control terminal of the second transistor T5 is coupled to the second terminal of the input module 10, the first terminal of the second transistor T5 is coupled to the second terminal of the first capacitor C2, and the second terminal of the second transistor T5 is grounded.

[0049] The control terminal of the third transistor T7 is coupled to the second terminal of the first capacitor C2. The first terminal of the third transistor T7 is coupled to the second terminal of the input module 10 through the second capacitor C1. The second terminal of the third transistor T7 is grounded.

[0050] The first terminal of the fourth transistor T6 is coupled to the first terminal of the first capacitor C2, and the control terminal of the fourth transistor T6 is coupled to the second terminal of the aforementioned input module 10.

[0051] The control terminal of the fifth transistor T9 is coupled to the second terminal of the fourth transistor T6, the first terminal of the fifth transistor T9 is coupled to the second terminal of the output module 40, and the second terminal of the fifth transistor T9 is grounded.

[0052] During the first time period, the first clock signal CK is high, the first transistor T4 is off, the second transistor T5, the fourth transistor T6 and the fifth transistor T9 are on, the output signal output by the output module 40 is low, and the second capacitor C1 is charged.

[0053] During the second time period, the first clock signal CK is at a low level, the second clock signal XCK changes from a low level to a high level, the second capacitor C1 discharges, and the output signal output by the output module 40 is at a high level.

[0054] It is understandable that the first and second time lengths are determined by the operating frequency, and the second time length is located after the first time length.

[0055] Furthermore, combined with Figure 3 right Figure 2 The working principle of the shift register circuit 100 is explained below:

[0056] Among them, Figure 3 In this context, STV represents the input signal (corresponding to...). Figure 2 In the diagram, IN), CK represents the first clock signal. XCK represents the second clock signal, and G0 represents the output signal of this stage's shift register circuit (corresponding to...). Figure 2 (OUT in the middle).

[0057] During the 10-50µs interval, CK and STV are at low level, and XCK is at high level. The initial voltage at point P is set to zero, preventing the initial non-zero voltage from affecting the circuit operation.

[0058] During the 60-100µs interval, CK and STV are high, and XCK is low. STV is applied to point P through input module 10, causing T5, T6, and output module 40 to conduct. Point Q discharges through T5, remaining low, while T4 is off, and point P remains high. CK is applied to the gate of T9 through T6, causing T9 to conduct. Simultaneously, output module 40 also conducts, and XCK is low at this time. Therefore, the output is set to low, meaning G0 is low at this time.

[0059] During the 110-150µs interval, CK and STV are low, and XCK is high. At the end of the previous stage, the voltage at point P is high, and output module 40 remains on. XCK transitions from low to high. Due to the bootstrap effect of C1, the voltage at point P further increases, eliminating the influence of the threshold voltage of output module 40 to prevent the output from failing to reach a high level. Therefore, the output is set to high, meaning G0 is high at this time.

[0060] During the 160-200µs interval, XCK and STV are low, while CK is high. At this time, CK is high, the voltage at point Q is high, T5 is off, therefore T4 and T7 are on. The voltage across C1 discharges through T4 and T7 respectively, resetting the circuit. Therefore, the output is set low, i.e., G0 is low. Simultaneously, the discharge of C2, T4, and T7 eliminates the influence of the clock signal on the subsequent low-level output.

[0061] exist Figure 3 In this context, 60-100us corresponds to the first time length mentioned above, and 110-150us corresponds to the second time length mentioned above.

[0062] In this embodiment, the first capacitor C2, the first transistor T4, the second transistor T5, the third transistor T7, the fourth transistor T6, and the fifth transistor T9, under the control of the first clock signal CK, shift the input signal IN received by the input module 10, so that the output module 40 generates an output signal OUT according to the second clock signal XCK and outputs it from the output terminal of the shift register circuit 100. This can meet the voltage requirements of the digital microfluidic chip, and by using the second clock signal XCK to generate the output signal OUT, there is no need to set up an additional voltage source, which can simplify the circuit structure of the shift register circuit 100 and reduce the manufacturing cost.

[0063] See Figure 4 , Figure 4This is a schematic diagram of an embodiment of the shift register circuit provided in this application. The shift register circuit 100 includes: an input module 10, a first discharge module 20, a second discharge module 30, an output module 40, and a reset module 50. The first terminal of the reset module 50 is coupled to the second terminal of the input module 10, the second terminal of the reset module 50 is grounded, and the control terminal of the reset module 50 is used to receive a reset signal. In some embodiments, the reset signal can reset the entire shift register circuit 100. For example, it can perform an initial reset of the entire shift register circuit 100. Or, it can reset the entire shift register circuit 100 to receive and process the input signal of the next cycle.

[0064] Specifically, the reset module 50 includes a sixth transistor T2 (not shown) and a seventh transistor T3 (not shown).

[0065] The control terminal of the sixth transistor T2 is used to receive the first reset signal. The first terminal of the sixth transistor T2 is coupled to the second terminal of the input module 10, and the second terminal of the sixth transistor T2 is grounded.

[0066] The control terminal of the seventh transistor T3 is used to receive the second reset signal. The first terminal of the sixth transistor T2 is coupled to the second terminal of the input module 10, and the second terminal of the sixth transistor T2 is grounded.

[0067] In this embodiment, the seventh transistor T3 performs an initial reset on the shift register circuit 100 in response to receiving the second reset signal. That is, in some embodiments, the control terminal of the seventh transistor T3 is coupled to the initial reset signal generation circuit to receive the corresponding reset signal.

[0068] During the operation of the shift register circuit 100, the sixth transistor T2, in response to receiving the first reset signal, resets the shift register circuit 100 to receive and process the input signal of the next cycle. That is, in some embodiments, the control terminal of the sixth transistor T2 can be coupled to the output terminal of the next-level circuit so that the output signal of the next-level circuit can be used as a reset signal to reset the shift register circuit 100 of this stage, in preparation for receiving and processing the input signal of the next cycle.

[0069] See Figure 5 , Figure 5 This is a schematic diagram of an embodiment of the shift register circuit provided in this application. The shift register circuit includes: an eighth transistor T1, a first capacitor C2, a first transistor T4, a second transistor T5, a third transistor T7, a fourth transistor T6, a fifth transistor T9, a sixth transistor T2, a seventh transistor T3, and a ninth transistor T8.

[0070] The first capacitor C2, the first transistor T4, the second transistor T5, and the third transistor T7 constitute the first discharge module 10 described above, which can eliminate the influence of the clock signal on the circuit when there is no input. The fourth transistor T6 and the fifth transistor T9 constitute the second discharge module 30 described above.

[0071] The eighth transistor T1 constitutes the aforementioned input module 10. The control terminal and the first terminal of the eighth transistor T1 are used to receive input signals, and the second terminal of the eighth transistor T1 is coupled to the control terminal of the first discharge module.

[0072] The ninth transistor T8 constitutes the aforementioned output module 40. The control terminal of the ninth transistor T8 is coupled to the second terminal of the input module 10, the first terminal of the ninth transistor T8 is used to receive the second clock signal XCK, and the second terminal of the ninth transistor T8 is coupled to the third terminal of the second discharge module.

[0073] Specifically, the first and control terminals of T1 receive the input signal G[n-1]. The control terminal of T2 receives the reset signal G[n+1], and the control terminal of T3 receives the reset signal RST. The first terminals of T2 and T3 are coupled to the second terminal of T1, and the second terminals of T2 and T3 are grounded. The control terminal of T4 is coupled to the first terminal of C2, the first terminal of T4 is coupled to the second terminal of T1, and the second terminal of T4 is grounded. The control terminal of T5 is coupled to the second terminal of T1, the first terminal of T5 is coupled to the control terminal of T4, and the second terminal of T5 is grounded. The control terminal of T6 is coupled to the second terminal of T1, the first terminal of T6 is coupled to the second terminal of C2, and the second terminal of T6 is coupled to the control terminal of T9. The second terminal of C2 receives CK. The control terminal of T7 is coupled to the first terminal of C2, the first terminal of T7 is coupled to the first terminal of C1, and the second terminal of T7 is grounded. The second terminal of C1 is coupled to the second terminal of T1. The control terminal of T8 is coupled to the second terminal of C1, the first terminal of T8 receives XCK, and the second terminal of T8 is coupled to the first terminal of C1 and the first terminal of T9. The second terminal of T9 is grounded. The coupling point between T8 and T9 serves as the output terminal of the shift register circuit, outputting the output signal G[n].

[0074] In some embodiments, the output of the shift register circuit can be directly coupled to the corresponding scan line, that is, the output signal G[n] is output to the scan line. In multiple cascaded shift register circuits, the output signal of the current shift register circuit can be used as the input signal of the next-level shift register circuit and the reset signal of the previous-level shift register circuit.

[0075] Combination Figure 6 right Figure 5 The working principle of shift registers will be explained as follows:

[0076] Among them, Figure 6 In this context, STV represents the input signal (corresponding to...). Figure 5In this circuit, G[n-1]), CK represents the first clock signal, XCK represents the second clock signal, and G1 represents the output signal of the next stage circuit, which can be used as the first reset signal of the shift register circuit at this stage (corresponding to...). Figure 5 In G[n+1]), G0 represents the output signal of this stage shift register circuit (corresponding to...). Figure 5 In G[n]), RST represents the second reset signal.

[0077] During the 10-50µs interval, CK, STV, and G1 are at low levels, while XCK and RST are at high levels. T3 is turned on, and the initial voltage at point P is set to zero, preventing the non-zero initial voltage from affecting the circuit operation.

[0078] During the 60-100µs interval, CK and STV are high, while XCK, RST, and G1 are low. STV is applied to point P through T1, causing T5, T6, and T8 to conduct. Point Q is discharged through T5, remaining low, while T4 is off, and point P remains high. CK is applied to the gate of T9 through T6, causing T9 to conduct, and T8 also conducts. XCK is low at this time, therefore the output is set to low.

[0079] During the 110-150µs interval, CK, STV, RST, and G1 are at low levels, while XCK is at a high level. At the end of the previous stage, the voltage at point P is at a high level, T8 remains on, and XCK transitions from low to high. Due to the bootstrap effect of C1, the voltage at point P further increases, eliminating the influence of the T8 threshold voltage to prevent the output from failing to reach a high level.

[0080] During the 160-200µs interval, XCK, STV, and RST are low, while CK and G1 are high. G1 turns on T2, discharging point P through T2. At this time, CK is high, and the voltage at point Q is high. T5 is then off, causing T4 and T7 to conduct. The voltage across C1 discharges through T4 and T7 respectively, resetting the circuit. Simultaneously, the discharge of C2, T4, and T7 eliminates the influence of the clock signal on the subsequent low-level output.

[0081] In any embodiment of this application, the pulse widths of the first clock signal CK and the second clock signal XCK are equal to the pulse widths of the input signal.

[0082] In any embodiment of this application, the high-level second clock signal XCK can reach 40V, and the shift register circuit 100 can operate at a frequency of 100KHz, thereby enabling the shift register circuit 100 to drive a 50pF load.

[0083] The transistor mentioned in any embodiment of this application is an amorphous silicon thin-film transistor. Amorphous silicon (a-Si) is a type of thin-film transistor (TFT) technology. Compared with other types of thin-film transistors, amorphous silicon thin-film transistors have simpler manufacturing processes, lower costs, and higher operating voltages than other technologies such as LTPS (Low Temperature Polysilicon), reaching over 50V, which can meet the requirements of active digital microfluidic chips.

[0084] Specifically, this application provides a 9T2C shift register circuit applicable to digital microfluidic chips. Here, 9T2C represents 9 transistors and 2 capacitors. The shift register circuit 100 can increase the operating voltage of an amorphous silicon thin-film transistor-based shift register circuit to 40V, achieve an operating frequency of 100kHz, and drive a 50pF load.

[0085] The shift register circuit requires only 9 TFTs and 2 capacitors, simplifying the circuit structure and facilitating the integration of the scanning circuit onto the digital microfluidic chip. This also simplifies the driving and testing of the pixel electrodes in the digital microfluidic chip, saves on scan-driven integrated circuits, and reduces manufacturing costs. Furthermore, the high operating voltage of this shift register circuit provides a high-drive voltage option for the application of amorphous silicon thin-film transistors in digital microfluidic chips.

[0086] This application also provides a shift register comprising a plurality of cascaded shift register circuits. Each shift register circuit can be any of the shift register circuits described above. Specifically, the cascaded shift register circuits can be 4, 5, 6, 7, or 8, and can be configured according to actual needs. The shift register is a serial-in, parallel-out shift register. See [link to relevant documentation] for details. Figure 7 , Figure 7 This is a schematic diagram of an embodiment of the shift register circuit provided in this application. Figure 7 As shown, five shift register circuits ( Figure 7 The shift register circuits 1-5 are connected in sequence. The output of the previous shift register circuit is connected to the input of the next shift register circuit, and a measurement port is also brought out. The Gn+1 shift register circuit serves as the reset signal for the Gn-1 shift register circuit.

[0087] Combination Figure 8 right Figure 7 The working principle will be explained as follows:

[0088] Here, STV is the initial signal, RST is the initial reset signal, and CK and XCK are two complementary clock signals with the same pulse width as the STV signal. The CK and XCK signals of adjacent stages should be connected alternately. The load capacitance is 10pF. Figure 8 In this diagram, G0 represents the output signal of shift register circuit 1, G1 represents the output signal of shift register circuit 2, G2 represents the output signal of shift register circuit 3, G3 represents the output signal of shift register circuit 4, G4 represents the output signal of shift register circuit 5, and G5 represents the output signal of the next stage shift register circuit after shift register circuit 5. Figure 8 As can be seen from the waveform diagram, the above-mentioned shift register circuits can all be cascaded to realize multi-stage shift register circuits, and the output high level of each stage can reach about 40V, and the low level is close to 0V.

[0089] This application also provides a digital microfluidic chip, which includes a shift register. The shift register is as described above.

[0090] This application also provides a digital microfluidic chip, which includes multiple cascaded shift register circuits. Each shift register circuit is as described above.

[0091] In summary, the shift register circuit, shift register, and digital microfluidic chip provided in this application can increase the operating voltage of the shift register circuit based on amorphous silicon thin-film transistors to 40V, achieve an operating frequency of 100kHz, and drive a 50pF load. It is understood that the specific operating frequency can be determined according to the actual needs of the digital microfluidic chip.

[0092] Furthermore, the shift register circuit requires only 9 TFTs and 2 capacitors, simplifying the circuit structure and facilitating the integration of the scanning circuit onto the digital microfluidic chip. This also simplifies the driving and testing of the pixel electrodes in the digital microfluidic chip, saves on scan-driven integrated circuits, and reduces manufacturing costs. Additionally, the high operating voltage of this shift register circuit provides a high-drive voltage option for the application of amorphous silicon thin-film transistors in digital microfluidic chips.

[0093] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0094] If the integrated units in the other embodiments described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0095] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A shift register circuit, characterized in that, The shift register circuit includes: An input module, wherein the control terminal and the first terminal of the input module are used to receive input signals; wherein the first terminal of the input module serves as the input terminal of the shift register circuit; A first discharge module, wherein the input terminal of the first discharge module is used to receive a first clock signal, and the control terminal of the first discharge module is coupled to the second terminal of the input module; The second discharge module has a first terminal for receiving the first clock signal, a second terminal for grounding, and a control terminal for being coupled to the second terminal of the input module. An output module is provided, wherein the control terminal of the output module is coupled to the second terminal of the input module, the first terminal of the output module is used to receive a second clock signal, and the second terminal of the output module is coupled to the third terminal of the second discharge module; wherein the first clock signal and the second clock signal are complementary clock signals; wherein the second terminal of the output module serves as the output terminal of the shift register circuit. Wherein, the first discharge module and the second discharge module are used to shift the input signal received by the input module under the control of the first clock signal, so that the output module forms an output signal according to the second clock signal and outputs it from the output terminal of the shift register circuit; The first discharge module includes: The first capacitor has its first terminal serving as the input terminal of the first discharge module for receiving the first clock signal. The first transistor has its control terminal coupled to the second terminal of the first capacitor, its first terminal coupled to the second terminal of the input module, and its second terminal grounded. The second transistor has its control terminal coupled to the second terminal of the input module, its first terminal coupled to the second terminal of the first capacitor, and its second terminal grounded. The third transistor has its control terminal coupled to the second terminal of the first capacitor, its first terminal coupled to the second terminal of the input module through the second capacitor, and its second terminal grounded. The second discharge module includes: The fourth transistor has its first terminal coupled to the first terminal of the first capacitor and its control terminal coupled to the second terminal of the input module. The fifth transistor has its control terminal coupled to the second terminal of the fourth transistor, its first terminal coupled to the second terminal of the output module, and its second terminal grounded. During the first time period, the first clock signal is at a high level, the first transistor is off, the second transistor, the fourth transistor and the fifth transistor are on, the output signal output by the output module is at a low level, and the second capacitor is charged. During the second time period, the first clock signal is at a low level, the second clock signal changes from a low level to a high level, the second capacitor discharges, and the output signal output by the output module is at a high level.

2. The shift register circuit according to claim 1, characterized in that, The shift register circuit further includes: a reset module, the first terminal of which is coupled to the second terminal of the input module, the second terminal of which is grounded, and the control terminal of which is used to receive a reset signal.

3. The shift register circuit according to claim 2, characterized in that, The reset module includes: The sixth transistor has a control terminal for receiving a first reset signal, a first terminal coupled to a second terminal of the input module, and a second terminal grounded. The seventh transistor has a control terminal for receiving a second reset signal, a first terminal coupled to the second terminal of the input module, and a second terminal grounded. The seventh transistor performs an initial reset of the shift register circuit in response to receiving the second reset signal. During the operation of the shift register circuit, the sixth transistor, in response to receiving the first reset signal, resets the shift register circuit.

4. The shift register circuit according to claim 1, characterized in that, The input module includes an eighth transistor, the control terminal and the first terminal of the eighth transistor are used to receive the input signal, and the second terminal of the eighth transistor is coupled to the control terminal of the first discharge module.

5. The shift register circuit according to claim 1, characterized in that, The output module includes a ninth transistor, the control terminal of which is coupled to the second terminal of the input module, the first terminal of which is used to receive the second clock signal, and the second terminal of which is coupled to the third terminal of the second discharge module.

6. The shift register circuit according to claim 1, characterized in that, The high-level second clock signal can reach 40V, and the shift register circuit can operate at a frequency of up to 100KHz.

7. The shift register circuit according to claim 1, characterized in that, The shift register circuit can drive a 50pF load.

8. The shift register circuit according to any one of claims 1, 3, 4 or 5, characterized in that, The transistor is an amorphous silicon thin-film transistor.

9. The shift register circuit according to any one of claims 1-5, characterized in that, The pulse widths of the first clock signal and the second clock signal are equal to the pulse width of the input signal.

10. A shift register, characterized in that, The shift register includes a plurality of cascaded shift register circuits as described in any one of claims 1 to 9.

11. A digital microfluidic chip, characterized in that, It includes a shift register or multiple cascaded shift register circuits, wherein the shift register is the shift register as described in claim 10, and the shift register circuit is the shift register circuit as described in any one of claims 1-9.

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