Chip package structure, method and electronic device

Abstract

The application relates to a chip packaging structure, a method and an electronic device. The chip packaging structure comprises: a storage chip, the storage chip comprising a plurality of first solder ball bumps and a plurality of first conductive vias, wherein the arrangement density of the first solder ball bumps is greater than that of the first conductive vias; a control chip, the projection of the control chip and the storage chip in a first direction at least partially overlaps, the control chip is electrically connected with the storage chip through the first solder ball bumps and sends a data signal, an address signal or a control signal to the storage chip; wherein the first direction is perpendicular to the storage chip; a power management module, the projection of the power management module and the storage chip in the first direction at least partially overlaps, the power management module is electrically connected with the storage chip through the first conductive vias and supplies power to the storage chip. The above chip packaging structure, method and electronic device can reduce signal transmission loss and delay.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a chip packaging structure, method and electronic device. Background Technology

[0002] With the rapid development of fields such as AI (Artificial Intelligence) and HPC (High-performance computing), the requirements for memory bandwidth in chips are becoming increasingly demanding. Consequently, memory packaging integration based on HBM (High Bandwidth Memory) chips is becoming increasingly common. Currently, the mainstream packaging technology for XPU and HBM integration is 2.5D silicon interposer technology. HBM chips utilize a highly integrated TSV (Through Silicon Via) approach to route relevant signals to one side of the chip, and then interconnect with SOC (System on Chip) chips is achieved through a 2.5D silicon interposer.

[0003] In existing technologies, HBM typically interconnects with SoC chips via silicon bridges (silicon bridges) to transmit signals such as data, address, and clock. A 1024DQ SoC actually has over 1700 transmission lines. Standard designs use 2 / 2µm line width and spacing, generally with two signal layers. Considering constraints such as equal length, the actual trace length exceeds 5mm. However, with increasing transmission speeds, line width / spacing needs to increase, RDL (Redistributed Layer) thickness needs to increase, and DTC (Data Center) applications need to be integrated to meet packaging requirements. Furthermore, with future standard transmission speeds reaching even faster speeds (HBM4 reaches 12.8Gbps), existing packaging methods will struggle to meet the demands for signal integrity and bandwidth per unit length. Summary of the Invention

[0004] Therefore, it is necessary to address the problem of low bandwidth per unit length in existing technologies by providing a chip packaging structure, method, and electronic device that can reduce signal transmission loss and delay and increase bandwidth per unit length.

[0005] In a first aspect, this application provides a chip packaging structure, the packaging structure comprising:

[0006] A memory chip includes a plurality of first solder ball bumps and a plurality of first conductive vias; wherein the arrangement density of the first solder ball bumps is greater than the arrangement density of the first conductive vias.

[0007] The control chip and the memory chip have at least partial overlap in projection in a first direction. The control chip is electrically connected to the memory chip through a first solder ball bump and sends data signals, address signals, or control signals to the memory chip. The first direction is perpendicular to the memory chip.

[0008] The power management module at least partially overlaps with the projection of the memory chip in a first direction. The power management module is electrically connected to the memory chip through a first conductive via and supplies power to the memory chip.

[0009] In some embodiments, the packaging structure further includes:

[0010] The test module is used to test the memory chip based on the input data;

[0011] The memory chip includes a second conductive via, and the test module is electrically connected to the memory chip through the second conductive via and sends test signals to the memory chip module.

[0012] In some embodiments, the packaging structure includes a plurality of memory chips; the plurality of memory chips constitute a memory stack chip.

[0013] The memory chip includes a third conductive via, with a first solder bump and a second solder bump formed at both ends of the third conductive via. Two adjacent memory chips are electrically connected sequentially through the first solder bump, the first conductive via, and the second solder bump. The control chip is electrically connected to the memory chip through the first solder bump, the first conductive via, and the second solder bump, and sends data signals, address signals, or control signals to the memory chip.

[0014] In some embodiments, the control chip includes a control port physical layer, which is electrically connected to the memory chip through a first metal wiring layer.

[0015] The packaging structure also includes:

[0016] The system chip includes a system port physical layer; the system chip is electrically connected to the control port physical layer through the system port physical layer.

[0017] In some embodiments, the control chip includes a fourth conductive via, one end of which is electrically connected to a first metal wiring layer, and the other end of which has a third solder ball bump for connecting to a memory chip; a fourth solder ball bump is formed above the control port physical layer for connecting to the system port physical layer of the system chip.

[0018] In some embodiments, the surfaces of the system chip and the control chip opposite each other include a first region and a second region, wherein the first region is provided with a fifth solder ball bump and the second region is provided with a sixth solder ball bump, the fifth solder ball bump is used to connect to a fourth solder ball bump, and the sixth solder ball bump is used to connect to a second metal wiring layer for signal transmission routing, and the arrangement density of the fifth solder ball bump is greater than the arrangement density of the sixth solder ball bump.

[0019] In some embodiments, when the arrangement density of the fifth solder ball bump is greater than or equal to twice the arrangement density of the sixth solder ball bump, the dimension of the fourth solder ball bump in the first direction is greater than the dimension of the fifth solder ball bump in the first direction.

[0020] When the arrangement density of the fifth solder ball bump is less than twice the arrangement density of the sixth solder ball bump, the dimension of the sixth solder ball bump in the first direction is equal to the dimension of the fifth solder ball bump in the first direction.

[0021] In some embodiments, the packaging structure includes: a substrate;

[0022] An insulating layer is disposed on the surface of the substrate, and a second metal wiring layer is formed in the insulating layer. The second metal wiring layer is electrically connected to the system chip through a sixth solder ball bump.

[0023] Secondly, this application provides a chip packaging method for packaging a chip packaging structure as described in the first aspect or any possible embodiment of the first aspect, the method comprising:

[0024] A memory chip is provided, and a first conductive via, a second conductive via, and a third conductive via are formed on the memory chip. A first solder ball bump is formed at the end of the first conductive via located on the upper surface of the memory chip, and a second solder ball bump is formed at the end located on the lower surface. The arrangement density of the first solder ball bump is greater than the arrangement density of the second conductive via and the arrangement density of the third conductive via.

[0025] The first and second solder bumps of adjacent memory chips are connected sequentially to form a memory chip module;

[0026] A control chip is provided, a conductive via region is formed on the control chip, a metal wiring layer electrically connected to the conductive via region is formed on the upper surface of the control chip, a third solder ball bump electrically connected to the conductive via region is formed on the lower surface of the control chip, and a fourth solder ball bump electrically connected to the physical layer of the control port is formed on the upper surface of the control chip.

[0027] A system chip is provided, and a fifth solder ball bump and a sixth solder ball bump are formed on the surfaces of the system chip and the control chip, wherein the arrangement density of the fifth solder ball bump is greater than that of the sixth solder ball bump;

[0028] The fourth solder bump is connected via the fifth solder bump, and the second metal wiring layer is connected via the sixth solder bump.

[0029] Provides power management and testing modules;

[0030] The power management module is connected via the second conductive via, and the test module is connected via the third conductive via.

[0031] Thirdly, this application provides an electronic device including a chip package structure as described in the first aspect or any possible embodiment of the first aspect.

[0032] In the aforementioned chip packaging structure, the control chip and power management module are distributed and can be electrically connected through different areas of the memory chip, improving the flexibility of the chip packaging structure. Furthermore, the separation of different signal transmission areas reduces the complexity of the manufacturing process, reduces signal crosstalk, and improves the integrity of signal transmission. The arrangement density of the first solder ball bumps is greater than that of the first conductive vias, which can adapt to different signal transmission density requirements. The control chip and memory chip partially overlap in the direction perpendicular to the memory chip, and can be electrically connected through the first solder ball bumps in the overlapping area. This eliminates the need for a silicon adapter board, effectively shortening the data transmission distance and reducing transmission loss and delay of control signals. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a chip packaging structure 010 in one embodiment;

[0034] Figure 2 This is a schematic diagram of the structure of a memory chip in one embodiment;

[0035] Figure 3 This is a schematic diagram of the power management module and the test module in one embodiment;

[0036] Figure 4 This is a schematic diagram of the storage stack chip structure in one embodiment;

[0037] Figure 5 This is a schematic diagram of the storage stacking module in one embodiment;

[0038] Figure 6 This is a schematic diagram of the control chip structure in one embodiment;

[0039] Figure 7 This is a schematic diagram of the system chip structure in one embodiment;

[0040] Figure 8 This is a schematic diagram of the system chip structure in one embodiment;

[0041] Figure 9 This is a schematic diagram of chip packaging structure 2020 in one embodiment;

[0042] Figure 10 This is a schematic diagram of the structure of the substrate and the metal wiring layer in one embodiment;

[0043] Figure 11 This is a schematic diagram of the packaging steps for a storage stack chip in one embodiment;

[0044] Figure 12 This is a schematic diagram of the temporary bonding steps for the storage stacked chips in one embodiment;

[0045] Figure 13 This is a schematic diagram of the packaging steps for the control chip and system chip in one embodiment.

[0046] Figure 14 This is a schematic diagram of the wafer dicing steps in one embodiment.

[0047] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the appended symbols are explained as follows:

[0048] 010: Chip package structure one, 020: Chip package structure two, 100: Memory chip, 100_A: Upper surface (functional surface) of the memory chip, 100_B: Lower surface (substrate surface) of the memory chip, 101_A: Power signal pad, 101_B: Test signal pad, 101_C: Control signal pad, 102_A: First solder ball bump, 102_B: Second solder ball bump, 103_A: First conductive via, 103 _B: Second conductive via; 103_C: Third conductive via; 106: Memory chip without a third conductive via; 107: Adhesive layer; 108: Protective layer; 110: Memory stacked chip; 111: Management wafer; 112: Power solder ball bump; 113: Adapter solder ball bump; 114: Test solder ball bump; 115: Power management module; 116: Test module; 120: Memory stacked module; 200: Control chip; 201: Conductive via Hole region, 202: Control port physical layer, 203: Control chip insulating layer, 204: First metal wiring layer, 205: Third solder ball bump, 206: Support bump, 207: Fourth solder ball bump, 300_A: System chip one, 300_B: System chip two, 301: System port physical layer, 302: Sixth solder ball bump, 303: Fifth solder ball bump, 310: Metal seed layer, 400: Memory module fan-out structure wafer, 4 01: Interconnect solder ball; 410: Second metal wiring layer; 411: Bump; 412: Encapsulation pad; 420: Insulating layer; 421: System chip corresponding pad; 422: Control chip corresponding pad; 430: Underfill material; 431: Epoxy resin layer; 432: First wafer thinning layer; 500: Second wafer thinning layer; 510: Wafer dicing position; 600: Substrate; 600_B: Temporary bonding carrier; 601: Temporary bonding material. Detailed Implementation

[0049] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0050] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0052] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0053] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0054] It should be noted that when an element is referred to as being "fixed to" or "set on" another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or there may be an intervening element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only possible implementation.

[0055] With the rapid development of HBM technology, HBM has now evolved to HBM3, achieving a single data lane rate of 6.4Gbps, a maximum bit width of 1024 bits per chip, and a bandwidth of 819GB / s. To address the signal integrity issues brought about by increased bandwidth, the latest generation of HBM3 has made design compromises, increasing the PHY (Physical) size, which indirectly increases the bump spacing and changes the PHY position closer to the XPU chip. Taking the latest HBM3 as an example, its packaging structure integrates multiple slices of the core die through TSV interconnects, integrating all data channels; additionally, the TSV connects to the bank power supply. Each core die (DRAM) is homogeneous, enabling large-scale production. Currently, the mainstream approach is to use TCB-NCF (thermo-press bonding-non-conductive adhesive filling). This process allows for chip testing to obtain KGD (Known Good Die), thus improving the overall packaging yield. A more advanced method is to achieve multi-chip stacking through wafer-level hybrid-bonding, but the main drawback of this approach is its relatively low yield. The overall module after multi-chip DRAM stacking (4Hi, 8Hi, 16Hi) can be tested and screened, and the acquisition difficulty is relatively low. The base die mainly contains the relevant DRAM PHY, power supply, and test signals; the DRAM stacked chips are interconnected through TSV and DRAM PHY. Finally, HBM chips are formed through wafer-level packaging. The base die is usually larger than the DRAM stacked module, but this is mainly to accommodate the packaging process; most of the base die area is not functional.

[0056] Analysis of existing technologies revealed two main causes of the aforementioned technical problems. First, the transmission distance from the DRAM slice to the SOC_PHY is long. This transmission channel includes: 1. DRAM slice TSV; 2. base die RDL; 3. HBM_PHY; 4. silicon interposer RDL; 5. SOC_PHY. Its transmission length generally exceeds 6mm, with the main sources of length being 2 and 4. In existing technologies, the length of the base die RDL is limited by the HBM size, and the length of the silicon interposer RDL is limited by the side-by-side packaging method, making it impossible to reduce the length. Second, the architecture of HBM limits its packaging form. Even with a small bump pitch, crosstalk issues exist during transmission on the transmission line, making it difficult to achieve high-density and high-bandwidth interconnects per unit length.

[0057] Based on the above problems, this invention mainly considers optimizing the interconnection between DRAM (Distributed RAM, Random Access Memory) slices and base dies, as well as the interconnection with the HBM_PHY, to achieve system signal integrity optimization and adapt to future faster transmission rate standards. The original HBM architecture is decomposed into a module primarily composed of DRAM slices and a smaller HBM_PHY chip. DRAM slices are interconnected via TSVs to achieve bit-width expansion requirements, and the final data and address channels are integrated on the functional plane of the module. A chip for power management and testing is integrated below the stacked modules. The entire module can be tested and screened using a larger C4 (Controlled Collapse Chip Interconnect) to improve overall assembly yield. The HBM_PHY chip integrates TSV channels and corresponding HBM-related IPs. The TSVs are used for interconnection with the DRAM module, and the HBM IPs are interconnected with SOC chips through micro-bumps. This chip can achieve interconnection with SOC chips through a face-to-face interconnection method, reducing the total length of the transmission path.

[0058] Figure 1 A schematic diagram of a chip packaging structure 010 according to an embodiment of the present invention is shown. Figure 2 A schematic diagram of the structure of a memory chip 100 in one embodiment is shown. Figure 3 A schematic diagram of the power management module and test module in one embodiment is shown. Figures 1 to 3 As shown, the chip package structure 1010 includes:

[0059] The memory chip 100 includes a plurality of first solder ball bumps 102_A and a plurality of first conductive vias 103_A; wherein the arrangement density of the first solder ball bumps 102_A is greater than the arrangement density of the first conductive vias 103_A.

[0060] The control chip 200 and the memory chip 100 have at least partial overlap in projection in a first direction. The control chip 200 is electrically connected to the memory chip 100 through a first solder ball bump 102_A and sends data signals, address signals or control signals to the memory chip 100. The first direction is perpendicular to the memory chip 100.

[0061] The power management module 115 is at least partially overlapped with the projection of the memory chip 100 in the first direction. The power management module 115 is electrically connected to the memory chip 100 through the first conductive via 103_A and supplies power to the memory chip 100.

[0062] In some embodiments, such as Figure 2 As shown, the functional surface 100_A of the memory chip 100 is provided with multiple signal pads. These signal pads are divided into power signal pads 101_A, test signal pads 101_B, and control signal pads 101_C for data storage / address / control, according to their functions. The power signal pads 101_A and 101_B are located near the ends of the first conductive via 103_A and the second conductive via 103_B, respectively, close to the functional surface 100_A of the memory chip 100. A first solder bump 102_A is formed above the control signal pad 101_C for connecting to the control chip 200. On the substrate surface 100_B of the memory chip 100, second solder bumps 102_B are formed corresponding to the positions of the first solder bumps 102_A and the ends of the first conductive via 103_A and the second conductive via 103_B. Figure 3 As shown, the power management module 115 and the test module 116 are integrated on the management wafer 111. The power management module 115 and the test module 116 each have power ball bumps 112 and test ball bumps 114 for connecting to the memory chip 100. The power management module 115 and the test module 116 are connected to the ball bumps on the substrate surface of the management wafer 111 through conductive vias, thereby enabling them to connect to the metal wiring layer connected to the system chip and obtain power or test signals. When the chip package structure includes multiple power management modules 115, a set of power signal pads 101_A and a first conductive via 103_A can be respectively provided for each power management module 115, for example... Figure 3 or Figure 4 As shown, the packaging structure includes two power management modules 115, and a set of power signal pads 101_A and a first conductive via 103_A are respectively provided on both sides of the memory chip 100.

[0063] The power management module 115, the second solder ball bump 102_B, the first conductive via 103_A, and the power pad are electrically connected in sequence to form a data transmission channel for transmitting power signals to the memory chip 100. The control chip 200 is connected to the first solder ball bump 102_A to form a data transmission channel for transmitting control signals to the memory chip 100.

[0064] In the above chip packaging structure, the control chip 200 and the power management module 115 can be electrically connected through different areas of the memory chip 100, improving the flexibility of the chip packaging structure. Furthermore, the separation of different signal transmission areas reduces the complexity of the manufacturing process, reduces signal crosstalk, and improves the integrity of signal transmission. The arrangement density of the first solder ball bump 102_A is greater than that of the first conductive via 103_A, which can adapt to different signal transmission densities. Since the control chip 200 and the memory chip 100 need to partially overlap in the direction perpendicular to the memory chip 100, electrical connection can be achieved in the overlapping area through the first solder ball bump 102_A. This eliminates the need for a silicon adapter board, effectively shortening the data transmission distance and reducing transmission loss and delay of control signals. The first conductive via 103_A, the second conductive via 103_B, and the third conductive via 103_C can be vertical TSV channels.

[0065] In some embodiments, such as Figures 1 to 3 As shown, the packaging structure also includes:

[0066] Test module 116 is used to test memory chip 100 based on input data;

[0067] The memory chip 100 includes a second conductive via 103_B. The test module 116 is electrically connected to the memory chip 100 through the second conductive via 103_B and sends test signals to the memory chip 100 module.

[0068] The control chip 200, the second solder ball bump 102_B, the second conductive via 103_B, and the test signal pad 101_B are electrically connected in sequence to form a data transmission channel for transmitting test signals to the memory chip 100.

[0069] Figure 4 This is a schematic diagram of the structure of the storage stack chip 110 in one embodiment. For example... Figure 4As shown, in some embodiments, the packaging structure includes multiple memory chips 100; the multiple memory chips 100 constitute a memory stack chip 110; each memory chip 100 includes a third conductive via 103_C, with a first solder ball bump 102_A and a second solder ball bump 102_B formed at both ends of the third conductive via 103_C, wherein two adjacent memory chips 100 are electrically connected sequentially through the first solder ball bump 102_A, the first conductive via 103_A, and the second solder ball bump 102_B, and the control chip 200 is electrically connected to the memory chips 100 through the first solder ball bump 102_A, the third conductive via 103_C, and the second solder ball bump 102_B and sends data signals, address signals, or control signals to the memory chips. Adjacent memory chips 100 are bonded and fixed together by an adhesive layer 107, and the uppermost functional surface 100_A is protected by a protective layer 108.

[0070] like Figure 4 As shown, in the memory stack 110 formed by stacking multiple memory chips 100, the memory chip 100 located at the bottom layer, which is used for direct electrical connection with the power management module 115 and the test module 116, does not have a third conductive via 103_C. The first solder bump 102_A of this memory chip 100 is directly formed on its functional surface 100_A, and the second solder bump 102_B is directly formed on its substrate surface 100_B. The other memory chips 100 all have a third conductive via 103_C, and the two ends of the third conductive via 103_C are respectively connected to the first solder bump 102_A and the second solder bump 102_B. The bottom layer memory chip 100 is electrically connected to the adjacent memory chip 100 through the first solder bump 102_A, and the remaining adjacent memory chips 100 are electrically connected through the connection of the first solder bump 102_A, the third conductive via 103_C, and the second solder bump 102_B.

[0071] Figure 5 This is a schematic diagram of the structure of the storage stack module 120 in one embodiment. Figures 5 to 6 As shown, after multiple memory chips 100 form a memory stack chip 110, they are electrically connected to the power management module 115 and the test module 116 through the second solder ball bump 102_B of the substrate layer of the bottommost memory chip 100. The whole structure formed by the storage chip 111 and the management wafer is called the memory stack module 120.

[0072] In some embodiments, the control chip 200 includes a control port physical layer 202, which is electrically connected to the memory chip 100 through a first metal wiring layer 204; the package structure further includes a system chip, which includes a system port physical layer 301; the system chip 300 is electrically connected to the control port physical layer 202 through the system port physical layer 301.

[0073] In some embodiments, the control chip 200 includes a fourth conductive via, one end of which is electrically connected to the first metal wiring layer 204, and the other end of which is formed with a third solder bump 205, which is used to connect to the memory chip 100; a fourth solder bump 207 is formed above the control port physical layer 202, which is used to connect to the system port physical layer of the system chip 300.

[0074] Figure 6 This is a schematic diagram of the structure of the control chip 200 in one embodiment. For example... Figure 6 As shown, the control chip 200 includes a control port physical layer 202, a first metal wiring layer 204, and a conductive via region 201. One end of the conductive via region 201 is connected to the control port physical layer 202 through the first metal wiring layer 204, and the other end has a third solder ball bump 205 for connecting to the memory chip 100 or the memory stack module 120. A fourth solder ball bump 207 is formed above the control port physical layer 202 for connecting to the system chip. Support bumps 206 are also formed on the substrate layer of the control chip 200 outside the metal via region, providing support during the packaging process.

[0075] Figure 7 This is a schematic diagram of the system chip structure in one embodiment. Figure 8 This is a schematic diagram of the system chip structure in another embodiment. For ease of description, it will be... Figure 7 and Figure 8 The system chips in the code are referred to as System Chip 1 010 and System Chip 2 020, respectively. For example... Figure 7 As shown, the system chip includes a system port physical layer 301. A fifth solder bump 303 is formed on the system port physical layer 301. Since the system chip needs to provide IP functions in addition to other functions for the control chip 200, a sixth solder bump 302 is formed in the area of ​​the functional surface of the system chip other than the system port physical layer 301. The density requirements of the solder bumps are different when transmitting different signals. In order to facilitate connection, the arrangement density of the fifth solder bump 303 is the same as the arrangement density of the fourth solder bump 207 on the control chip 200. The arrangement density of the sixth solder bump 302 can be set according to the actual transmission requirements.

[0076] like Figure 7 or Figure 8As shown, in some embodiments, the surfaces of the system chip 300 and the control chip 200 opposite each other include a first region and a second region. The first region is provided with a fifth solder ball bump 303, and the second region is provided with a sixth solder ball bump 302. The fifth solder ball bump 303 is used to connect to the fourth solder ball bump 207, and the sixth solder ball bump 302 is used to connect to the second metal wiring layer 410 for signal transmission routing. The arrangement density of the fifth solder ball bump 303 is greater than the arrangement density of the sixth solder ball bump 302.

[0077] like Figure 7 As shown, in some embodiments, when the arrangement density of the fifth solder ball bump 303 is greater than or equal to twice the arrangement density of the sixth solder ball bump 302, the dimension of the sixth solder ball bump 302 in the first direction is greater than the dimension of the fifth solder ball bump 303 in the first direction; as Figure 8 As shown, when the arrangement density of the fifth solder ball bump 303 is less than twice the arrangement density of the sixth solder ball bump 302, the dimension of the sixth solder ball bump 302 in the first direction is equal to the dimension of the fifth solder ball bump 303 in the first direction.

[0078] Figure 9 This is a schematic diagram of the chip packaging structure in another embodiment. Figure 10 This is a schematic diagram of the substrate and metal wiring layer in one embodiment. Figures 8 to 10 As shown, the package structure includes: a substrate; an insulating layer 420 disposed on the surface of the substrate, wherein a second metal wiring layer 410 is formed in the insulating layer 420, and the second metal wiring layer 410 is electrically connected to the system chip 300 through a sixth solder ball bump 302.

[0079] like Figures 9 to 10 As shown, a temporary bonding material layer is coated on the substrate. A second metal wiring layer 410 and an insulating material layer are formed on the temporary bonding material layer through processes such as redistribution. Package pads and signal pads are electrically connected through the second metal wiring layer 410. Bumps 411 are provided on the second metal wiring layer 410 for connecting system chips, such as… Figure 11 As shown, the two ends of the bump 411 are respectively connected to the second metal wiring layer and the corresponding pad 421 of the system chip for connecting the system chip. The height of the bump 411 is adapted to the size of the memory stacking module 120, that is, the height of the bump 411 is not less than the height of the memory stacking module 120, so as to connect the system chip. Figures 10 to 11As shown, after the second metal wiring layer 410 is processed, the storage stack module 120 is mounted on the second metal wiring layer 410, and the solder ball bumps are protected by the underfill material 430. Then, the storage stack module 120 and the bumps are covered by the epoxy resin layer 431 to form a wafer-like structure. The thickness of the first wafer thinning layer 432 located above the storage stack module 120 is reduced by wafer thinning, so that the bumps on the surface of the storage stack module 120 and the bumps connecting the second metal wiring layer are exposed. The control chip corresponding pad 422 for connecting the control chip is formed by the rewiring process.

[0080] Based on the same inventive concept, this application also provides a chip packaging method based on the chip packaging structure described above. The solution provided by this method is similar to the solution described in the above-described apparatus; therefore, specific limitations in one or more chip packaging method embodiments provided below can be found in the above-described limitations regarding the chip stacking module 120. The method includes the following steps:

[0081] Provide such as Figure 5 The memory chip 100 shown has a first conductive via 103_A, a second conductive via 103_B, and a third conductive via 103_C formed on it. A first solder ball bump 102_A is formed at the end of the first conductive via 103_A located on the upper surface of the memory chip 100, and a second solder ball bump 102_B is formed at the end of the lower surface. The arrangement density of the first solder ball bump 102_A is greater than the arrangement density of the second conductive via 103_B and the arrangement density of the third conductive via 103_C.

[0082] The first solder ball bump 102_A and the second solder ball bump 102_B of adjacent memory chips 100 are connected in sequence to form a memory chip 100 module;

[0083] A control chip 200 is provided, on which a conductive via region 201 is formed, a metal wiring layer electrically connected to the conductive via region 201 is formed on the upper surface of the control chip 200, a third solder ball bump 205 electrically connected to the conductive via region 201 is formed on the lower surface of the control chip 200, and a fourth solder ball bump 207 electrically connected to the control port physical layer 202 is formed on the upper surface of the control chip 200.

[0084] A system chip is provided, and a fifth solder bump 303 and a sixth solder bump 302 are formed on the surfaces of the system chip and the control chip 200, wherein the arrangement density of the fifth solder bump 303 is greater than the arrangement density of the sixth solder bump 302.

[0085] The fourth solder bump 207 is connected via the fifth solder bump 303, and the second metal wiring layer 410 is connected via the sixth solder bump 302.

[0086] Provides a power management module 115 and a test module 116;

[0087] The power management module 115 is connected via the second conductive via 103_B, and the test module 116 is connected via the third conductive via 103_C.

[0088] In one exemplary embodiment, a chip packaging method is provided, the method comprising the following steps:

[0089] Step 102: Process the memory chip.

[0090] The single-chip memory 100 is processed with TSVs and bumps to enable signal routing and connection between the front functional surface 100_A and the back substrate surface 100_B of the memory chip. Specifically, the chip functional surface 100_A has connection points that can be used for subsequent processes, which can be divided into power signal pads 101_A, test signal pads 101_B, and control signal pads 101_C for data storage / address / control signals, depending on their function. Interconnected TSV structures are formed next to these pads, which are used to connect the vertical TSV channel 103_A of the power signal pad 101_A, the vertical TSV channel 103_B of the test signal pad 101_B, and the vertical TSV channel 103_C of the control signal pad 101_C, respectively. These vertical TSV channels eventually form second solder ball bumps 102_B for soldering on the substrate surface 100_B of the memory chip. On the front functional surface 100_A of the memory chip, the first solder ball bump 102_A corresponding to the control signal pad 101_C is reserved for subsequent interconnection with the control chip.

[0091] Step 104: Process the memory stack chips.

[0092] Multi-layer stacking (4Hi, 8Hi, 16Hi, etc.) can be implemented according to storage capacity requirements. Taking the traditional TCB-NCF process as an example, the following describes the process: Hi-1 layers of memory chips 100 are stacked and packaged using TCB-NCF. The interconnections between chips 100 are achieved through first solder bumps 102_A and second solder bumps 102_B. A NCF (non-flowing underfill) adhesive layer 107 is used to bond the chips together, achieving a reliable packaging structure. A protective layer 108 is added to the front side of the stacked memory chips 110, which will protect the first solder bumps 102_A in subsequent processes. A memory chip 106 without a vertical TSV channel 103_B and no connection 101_B is then prepared. Thus, the overall stacked memory chip 110 is assembled, mainly consisting of the Hi-1 layer of stacked memory chips 100 and the memory chip 106 without a vertical TSV channel 103_B. Prepare a management wafer 111 integrating power management and signal testing. Power ball bumps 112, corresponding to the second solder ball bumps 102_B of the memory stack chip 110, are formed on the wafer for interconnection. The overall power and testing components are connected to the transition solder ball bumps 113 of the management wafer 111 via TSVs. This ultimately forms the memory stack module 120.

[0093] Step 106: Process the control chip and SOC chip.

[0094] The data signals of the storage stack module 120 cannot be directly supplied to the SOC; they must be transmitted through the corresponding HBM control, logic layer, and physical layer. The control chip 200 performs this function. The control chip 200 interconnects with the first solder bump 102_A of the storage stack module 120 via a third solder bump 205, and with signals via a conductive via region 201. On the functional surface of the control chip 200, the first metal wiring layer 204 interconnects the signals with the control port physical layer (PHY_IP region) 202. Generally, the metal wiring layer uses copper or aluminum processes and is protected by an insulating layer 203 made of materials such as silicon nitride and silicon oxide. A fourth solder bump 207, corresponding to the system port physical layer (SOC PHY_IP region), is formed above the control port physical layer (PHY_IP region) 202. In addition to integrating the corresponding DRAM IP, the SOC chip 300 has many other IP functions. These IP functions require different bump densities. The difference between the bump spacing and the bump spacing on the system port physical layer 301 will fall into two categories. One is where the spacing of the sixth solder ball bump 302 is more than twice that of the fourth solder ball bump 207. In this case, it's difficult to make bumps of the same height. Therefore, the sixth solder ball bump 302, with a different specification than the fifth solder ball bump 303, is directly fabricated using conventional bump fabrication methods to obtain the SOC chip 300_A. The other case is... Figure 8 As shown, if the pitch ratio is less than 2, the bump heights of the two areas can be made the same, but the bump diameters will be set differently according to chip size and other requirements. The DRAM PHYIP adapter connection uses the relatively smaller fifth solder ball bump 303, while other areas use the relatively larger sixth solder ball bump 302.

[0095] Step 108: Fabricate the fan-out structure of the embedded memory stacked chip.

[0096] A wafer-level substrate 600 is prepared for temporarily supporting the chip. Depending on the process technology, this can be a silicon wafer or glass with a coefficient of thermal expansion that matches the subsequent processes. A temporary bonding material 601 of uniform thickness is coated on the substrate 600. This material can withstand subsequent processing without delamination, tearing, or deformation, and can be removed through specific processes. Generally, this material is compatible with the substrate 600. Rewiring and other processes are performed on the temporary bonding material, ultimately forming an insulating layer 420 with polyimide as the main material and a second metal wiring layer 410 for signal transmission routing. The wiring of the wiring layer interconnects the package pads 412 and the signal pads and bumps 411 of the chip.

[0097] Step 110: Mount the memory stack chip onto the embedded memory stack chip fan-out structure.

[0098] The bonding pads 113 of the memory stacking module 120 are physically protected by an underfill material 430. Then, the memory stacking module 120 and the bumps 411 are completely covered by an epoxy resin layer 431 and reconstructed into a wafer-like structure through wafer-level molding. The thickness of the first wafer thinning layer 432 above the memory stacking module 120 is reduced by wafer-level thinning, exposing the bumps and bumps 411 on the front side of the memory stacking module 120 for redistribution. Fan-out is achieved through the insulating layer 420 and the corresponding system chip pads 421 of the SOC 300 and the corresponding control chip pads 422 of the control chip 200, ultimately forming a complete embedded memory stacking chip fan-out structure wafer 400.

[0099] Step 112: Packaging and integration.

[0100] The individually diced control chip 200 is mounted onto the embedded memory stacked chip fan-out structure wafer 400. The third solder ball bump 205 on the chip forms an interconnect with the corresponding pad 422 of the system chip, while the support bump 206 provides support. The SOC chip 300_A is mounted onto the memory module fan-out structure wafer 400, with the sixth solder ball bump 302 on the chip forming an electrical interconnect with the corresponding pad 421 of the system chip. After mounting, underfill material 430 is used to protect the bumps of the chips. A wafer-level molding process is used to protect the entire reconstructed wafer with an epoxy resin layer 431. Then, a wafer molding thinning process is used to reduce the thickness of the second wafer thinning layer 500, exposing the substrate silicon of the SOC chip. Finally, a metal seed layer 310 is sputtered onto the back of the overall package using metal sputtering for the interface IMC of the subsequent heat sink, strengthening the packaged chip and the TIM thermal conductive adhesive.

[0101] Temporary bonding material 601 is applied to the sputtering surface, and the aforementioned fan-out structure and temporary bonding carrier 600_B are temporarily bonded. The bonding material and bonding carrier on the ball-planting surface are removed, and the relevant residues and seed layer are cleaned. Finally, wafer balls are planted on the packaging pad 412 to form interconnect balls 401. This temporary bonding scheme is selected based on the actual tolerance of the reconstructed wafer warpage process.

[0102] After debonding is completed, the particles are cut and sorted using wafer dicing, such as... Figure 14 510 is the wafer dicing position, ultimately resulting in a single embedded memory chip packaged as a fan-out module, i.e., chip package structure 010. If the SOC chip is... Figure 8 The structure shown below, after encapsulation, forms a shape like... Figure 9 The chip packaging structure shown is 020.

[0103] In one embodiment, an electronic device is provided, which includes the chip packaging structure in the above-described device embodiments, or includes the chip packaging structure obtained through the above-described method embodiments.

[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A chip packaging structure, characterized in that, The packaging structure includes: A memory chip, the memory chip including a plurality of first solder ball bumps and a plurality of first conductive vias; wherein the arrangement density of the first solder ball bumps is greater than the arrangement density of the first conductive vias; The functional surface of the memory chip has multiple signal pads, which are divided into power signal pads, test signal pads and control signal pads according to their functions. The power signal pads and test signal pads are located at the ends of the first and second conductive vias near the functional surface of the memory chip, respectively. A first solder ball bump is formed above the control signal pad for connecting to the control chip. On the substrate surface of the memory chip, a second solder ball bump is formed at the position corresponding to the first solder ball bump and at the ends of the first and second conductive vias. A control chip, the projection of which at least partially overlaps with that of the memory chip in a first direction, the control chip being electrically connected to the memory chip via the first solder ball bumps and sending data signals, address signals, or control signals to the memory chip; wherein, the first direction is perpendicular to the memory chip; A power management module, wherein the projection of the memory chip in the first direction at least partially overlaps with the projection of the memory chip, and the power management module is electrically connected to the memory chip through the first conductive via and supplies power to the memory chip; The power management module, the second solder ball bump, the first conductive via, and the power pad are electrically connected in sequence to form a data transmission channel for transmitting power signals to the memory chip. The control chip is connected to the first solder ball bump to form a data transmission channel for transmitting control signals to the memory chip.

2. The packaging structure according to claim 1, characterized in that, The packaging structure further includes: The testing module is used to test the memory chip based on the input data; The memory chip includes a second conductive via, and the test module is electrically connected to the memory chip through the second conductive via and sends a test signal to the memory chip module.

3. The packaging structure according to claim 1, characterized in that, The packaging structure includes multiple memory chips; the multiple memory chips constitute a memory stack chip. The memory chip includes a third conductive via, with a first solder bump and a second solder bump formed at both ends of the third conductive via. Two adjacent memory chips are electrically connected sequentially through the first solder bump, the first conductive via, and the second solder bump. A control chip is electrically connected to the memory chip through the first solder bump, the first conductive via, and the second solder bump and sends data signals, address signals, or control signals to the memory chip.

4. The packaging structure according to claim 1, characterized in that, The control chip includes a control port physical layer, which is electrically connected to the memory chip through a first metal wiring layer. The packaging structure further includes: The system chip includes a system port physical layer; the system chip is electrically connected to the control port physical layer through the system port physical layer.

5. The packaging structure according to claim 4, characterized in that, The control chip includes a fourth conductive via, one end of which is electrically connected to the first metal wiring layer, and the other end of which has a third solder ball bump for connecting to the memory chip; a fourth solder ball bump is formed above the control port physical layer for connecting to the system port physical layer of the system chip.

6. The packaging structure according to claim 5, characterized in that, The surfaces of the system chip and the control chip opposite each other include a first region and a second region. The first region is provided with a fifth solder ball bump, and the second region is provided with a sixth solder ball bump. The fifth solder ball bump is used to connect to the fourth solder ball bump, and the sixth solder ball bump is used to connect to the second metal wiring layer used for signal transmission routing. The arrangement density of the fifth solder ball bump is greater than that of the sixth solder ball bump.

7. The packaging structure according to claim 6, characterized in that, When the arrangement density of the fifth solder ball bump is greater than or equal to twice the arrangement density of the sixth solder ball bump, the dimension of the fourth solder ball bump in the first direction is greater than the dimension of the fifth solder ball bump in the first direction; When the arrangement density of the fifth solder ball bump is less than twice the arrangement density of the sixth solder ball bump, the dimension of the sixth solder ball bump in the first direction is equal to the dimension of the fifth solder ball bump in the first direction.

8. The packaging structure according to claim 6, characterized in that, The packaging structure includes: substrate; An insulating layer is disposed on the surface of the substrate, and a second metal wiring layer is formed therein. The second metal wiring layer is electrically connected to the system chip through a sixth solder ball bump.

9. A chip packaging method, characterized in that, For use in claim 1 The chip packaging structure described in any one of the 8, the method comprising: A memory chip is provided, and a first conductive via, a second conductive via, and a third conductive via are formed on the memory chip. A first solder ball bump is formed at the end of the first conductive via located on the upper surface of the memory chip, and a second solder ball bump is formed at the end located on the lower surface. The arrangement density of the first solder ball bump is greater than the arrangement density of the second conductive via and the arrangement density of the third conductive via. The first solder ball bumps and the second solder ball bumps of adjacent memory chips are connected in sequence to form a memory chip module; A control chip is provided, wherein a conductive via region is formed on the control chip, a metal wiring layer electrically connected to the conductive via region is formed on the upper surface of the control chip, a third solder ball bump electrically connected to the conductive via region is formed on the lower surface of the control chip, and a fourth solder ball bump electrically connected to the physical layer of the control port is formed on the upper surface of the control chip. A system chip is provided, wherein a fifth solder ball bump and a sixth solder ball bump are formed on the surface of the system chip opposite to the control chip, wherein the arrangement density of the fifth solder ball bump is greater than the arrangement density of the sixth solder ball bump; The fourth solder ball bump is connected through the fifth solder ball bump, and the second metal wiring layer is connected through the sixth solder ball bump; Provides power management and testing modules; The power management module is connected through the second conductive via, and the test module is connected through the third conductive via.

10. An electronic device, characterized in that, The chip packaging structure includes any one of claims 1-8.

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