GaN encapsulation structure

Abstract

This application discloses a GaN packaging structure, including: a packaging base island containing first base island pins and second base island pins; a control chip disposed on the packaging base island and a ceramic substrate with a copper layer on its upper surface; a GaN chip flip-chip disposed on the ceramic substrate; the gate electrode (G) of the GaN chip is located above and connected to the control pin of the control chip, the remaining electrode of the GaN chip is connected to the first base island pin through the copper layer, and the remaining pin of the control chip is connected to the second base island pin; and a molding compound for encapsulating the packaging base island, the control chip, the ceramic substrate, and the GaN chip. The technical solution disclosed in this application shortens the heat dissipation path and improves the heat dissipation performance of the packaged device by flip-chipping the GaN chip on the ceramic substrate with a copper layer on its upper surface, and reduces the package size by placing the GaN chip and the control chip on the same packaging base island and placing the gate electrode of the GaN chip above the control pin of the control chip.

Description

Technical Field

[0001] This application relates to the field of semiconductor device technology, and in particular to a GaN packaging structure. Background Technology

[0002] GaN (gallium nitride) has a wide bandgap, making it suitable for high-power, high-speed optoelectronic devices. GaN chips typically require interconnect packaging with control chips to improve device performance.

[0003] Currently, the GaN packaging structure consists of the GaN chip mounted upright on one packaging island and the control chip mounted upright on another packaging island. The control pins of the control chip are connected to the gate of the GaN chip via bonding wires. This GaN packaging structure not only has poor heat dissipation performance but also has a large package size.

[0004] In summary, improving the heat dissipation performance of GaN packaging structures and reducing their packaging volume are technical problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a GaN packaging structure to improve the heat dissipation performance of the GaN packaging structure and reduce the packaging volume of the GaN packaging structure.

[0006] To achieve the above objectives, this application provides the following technical solution:

[0007] A GaN packaging structure, comprising:

[0008] A package base island containing a first base island pin and a second base island pin;

[0009] The control chip and the ceramic substrate with a copper layer on the upper surface are disposed on the packaging base island;

[0010] A GaN chip is flip-chip disposed on the ceramic substrate; the gate electrode (G) of the GaN chip is located above and connected to the control pin of the control chip, the remaining electrode of the GaN chip is connected to the first base island pin through the copper layer, and the remaining pin of the control chip is connected to the second base island pin.

[0011] A molding compound used to encapsulate the packaging base island, the control chip, the ceramic substrate, and the GaN chip.

[0012] Optionally, the gate (G) of the GaN chip is located directly above the control pin.

[0013] Optionally, the gate (G) of the GaN chip is connected to the control pin via a copper pillar.

[0014] Optionally, the copper layer includes a first copper layer region and a second copper layer region. The first copper layer region is connected to the drain (D) electrode of the GaN chip and the drain base island pin of the first base island pin. The second copper layer region is connected to the source (S) electrode of the GaN chip and the source base island pin of the first base island pin.

[0015] Optionally, a magnetic bead connected to the first copper layer region is disposed in the first copper layer region.

[0016] Optionally, the magnetic bead is disposed in the first copper layer region, excluding the region directly opposite the drain electrode of the GaN chip.

[0017] Optionally, the first copper layer region is connected to the D-base island pin via a bonding wire, and the second copper layer region is connected to the S-base island pin via a bonding wire.

[0018] Optionally, the first copper layer region is connected to the D-base island pin via a first copper sheet, and the second copper layer region is connected to the S-base island pin via a second copper sheet.

[0019] Optionally, the remaining pins of the control chip are connected to the second base island pins via bonding wires.

[0020] Optionally, the remaining pins of the control chip are connected to the second base island pins via a third copper plate.

[0021] This application provides a GaN packaging structure, including: a packaging base island containing a first base island pin and a second base island pin; a control chip disposed on the packaging base island and a ceramic substrate with a copper layer on its upper surface; a GaN chip flip-chip disposed on the ceramic substrate; the gate electrode (G) of the GaN chip is located above and connected to the control pin of the control chip, the remaining electrode of the GaN chip is connected to the first base island pin through the copper layer, and the remaining pin of the control chip is connected to the second base island pin; and a molding compound for molding the packaging base island, the control chip, the ceramic substrate, and the GaN chip.

[0022] The technical solution disclosed in this application involves flip-chip mounting of the GaN chip on a ceramic substrate with a copper layer on its upper surface. This means the upper surface of the GaN chip (i.e., the surface with electrodes) is in contact with the copper layer on the upper surface of the ceramic substrate. This allows heat generated on the upper surface of the GaN chip to be transferred along the copper layer and the ceramic substrate to the packaging island, where it is then dissipated. This shortens the heat dissipation path, improves the heat dissipation performance of the GaN packaged device, reduces heat accumulation within the GaN packaged device, and ultimately improves its performance. Furthermore, by placing the GaN chip and the control chip on the same packaging island and positioning the gate (G) of the GaN chip above the control pin of the control chip, the package size of the GaN package structure can be reduced, and the connection length between the gate of the GaN chip and the control pin of the control chip can be shortened, thereby reducing the package inductance of the GaN packaged device.

[0023] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0024] Figure 1 A top view of a GaN packaging structure provided in an embodiment of this application;

[0025] Figure 2 This is a cross-sectional schematic diagram of a GaN packaging structure provided in an embodiment of this application.

[0026] The reference numerals in the attached figures are as follows:

[0027] 1-Packaging base island, 11-First base island pin, 12-Second base island pin, 13-Packaging base island body, 2-Control chip, 3-Ceramic substrate, 4-Copper layer, 41-First copper layer area, 42-Second copper layer area, 5-GaN chip, 6-Copper pillar, 7-Bond wire. Detailed Implementation

[0028] Currently, GaN packaging structures typically involve mounting the GaN chip upright on one packaging island and the control chip upright on another. The control pins of the control chip are connected to the gate of the GaN chip via wire bonding. However, this arrangement, requiring the GaN chip and control chip to be mounted on two separate packaging islands, results in a relatively large GaN package size. Furthermore, mounting the GaN chip upright on one island means that heat generated by the electrodes on the upper surface of the GaN chip is first transferred from the upper surface to the lower substrate, then from the lower substrate to the packaging island, and finally dissipated by the packaging island. This long heat dissipation path leads to low efficiency and heat accumulation within the GaN package, ultimately reducing its performance.

[0029] Therefore, this application provides a GaN packaging structure to improve the heat dissipation performance of the GaN packaging structure and reduce its size.

[0030] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0031] See Figure 1 and Figure 2 ,in, Figure 1 This paper shows a top view of a GaN packaging structure provided in an embodiment of this application. Figure 2 This illustration shows a cross-sectional schematic diagram of a GaN packaging structure provided in an embodiment of this application. The GaN packaging structure provided in this embodiment may include:

[0032] Package base island 1 includes a first base island pin 11 and a second base island pin 12;

[0033] The control chip 2 and the ceramic substrate 3 with a copper layer 4 on the upper surface are disposed on the packaging base island 1;

[0034] A GaN chip 5 is flip-chip disposed on a ceramic substrate 3; the gate electrode of the GaN chip 5 is located above and connected to the control pin of the control chip 2, the remaining electrode of the GaN chip 5 is connected to the first base island pin 11 through the copper layer 4, and the remaining pin of the control chip 2 is connected to the second base island pin 12.

[0035] A plastic encapsulation body used for plastic packaging of the base island 1, control chip 2, ceramic substrate 3 and GaN chip 5.

[0036] The GaN packaging structure provided in this application embodiment may include a packaging base island 1, a control chip 2, a ceramic substrate 3, a GaN chip 5, and a molding compound.

[0037] The packaging base island 1 includes a packaging base island body 13, a first base island pin 11, and a second base island pin 12. The packaging base island body 13, the first base island pin 11, and the second base island pin 12 are mutually insulated from each other, specifically by being separated (i.e., a gap is set between each pair). The packaging base island body 13 is used to house the control chip 2, the ceramic substrate 3, and the GaN chip 5. The first base island pin 11 is used for electrical connection with the corresponding electrode in the GaN chip 5, and the second base island pin 12 is used for electrical connection with the corresponding pin in the control chip 2.

[0038] Both the control chip 2 and the ceramic substrate 3 are disposed on the packaging island 1 (specifically, both are disposed on the packaging island body 13 of the packaging island). Specifically, the control chip 2 is disposed in the first region of the packaging island 1, and the ceramic substrate 3 is disposed in the second region of the packaging island 1. The first region and the second region are different regions of the packaging island 1. The upper surface of the ceramic substrate 3 (i.e., the side facing away from the packaging island 1) is coated with a copper layer 4 (i.e., the ceramic substrate 3 is a copper-clad ceramic substrate), and the lower surface of the ceramic substrate 3 (i.e., the side in contact with the packaging island 1) is insulated. The control chip 2 and the ceramic substrate 3 can be disposed on the packaging island 1 by means of adhesive or other methods. Specifically, the control chip 2 can be a PWM (Pulse Width Modulation) control chip, and the upper surface of the control chip 2 is provided with pins, including control pins for connecting to the gate (G) of the GaN chip 5. The lower surface of the control chip 2 is disposed on the packaging island 1, that is, the control chip 2 is disposed upright on the packaging island 1.

[0039] The GaN chip 5 has a planar structure, with electrodes on its upper surface, including a gate electrode (G), and a substrate on its lower surface. The GaN chip 5 is flip-chip mounted on a ceramic substrate 3, meaning the upper surface of the GaN chip 5 is in contact with the upper surface of the ceramic substrate 3 (specifically, through conductive adhesive), while the lower surface faces away from the ceramic substrate 3. The gate electrode of the GaN chip 5 is not in contact with the upper surface of the ceramic substrate 3; that is, the gate electrode is exposed outside the ceramic substrate 3. Furthermore, the gate electrode of the GaN chip 5 is located above the control pin of the control chip 2 (e.g., diagonally above, directly above, etc.) and is electrically connected to the control pin of the control chip 2. The remaining electrodes of the GaN chip 5 are in contact with the copper layer 4 covering the upper surface of the ceramic substrate 3 and are electrically connected to the first base island pin 11 through the copper layer 4. The remaining pins of the control chip 2, excluding the control pin, are electrically connected to the second base island pin 12. The molding compound is used to encapsulate the base island 1, the control chip 2, the ceramic substrate 3, and the GaN chip 5 to obtain a GaN package structure.

[0040] By flip-chipping the GaN chip 5 onto the ceramic substrate 3, the upper surface of the GaN chip 5 comes into contact with the copper layer 4 covering the upper surface of the ceramic substrate 3. This allows the heat generated on the upper surface of the GaN chip 5 to be dissipated sequentially through the copper layer 4, the ceramic substrate 3, and the packaging island 1, thereby shortening the heat dissipation path, enhancing the heat dissipation capacity of the GaN package structure, and reducing heat accumulation within the GaN package structure, thus improving the reliability and stability of the GaN package structure. Furthermore, by placing the GaN chip 5 and the control chip 2 on the same packaging island 1, the size of the GaN package structure can be reduced, facilitating miniaturization of the GaN package structure. It also shortens the electrical connection length between the gate (G) of the GaN chip 5 and the control pin of the control chip 2, thereby reducing the package inductance of the GaN package structure. Furthermore, by placing the GaN chip 5 and the control chip 2 on the same packaging base island 1, and by placing the gate of the GaN chip 5 above the control pin of the control chip 2, the GaN chip 5 and the control chip 2 can be stacked. Therefore, the volume of the GaN package structure can be further reduced, and the electrical connection length between the gate of the GaN chip 5 and the control pin of the control chip 2 can be further shortened, thereby further reducing the package inductance of the GaN package structure and improving the performance of the GaN package structure.

[0041] In the technical solution disclosed in this application, the GaN chip 5 is flip-chip disposed on a ceramic substrate 3 with a copper layer 4 on its upper surface. That is, the upper surface of the GaN chip 5 (i.e., the surface of the GaN chip 5 with electrodes) is in contact with the copper layer 4 on the upper surface of the ceramic substrate 3. This allows the heat generated on the upper surface of the GaN chip 5 to be transferred along the copper layer 4 and the ceramic substrate 3 to the packaging island 1, and then dissipated by the packaging island 1. This shortens the heat dissipation path, improves the heat dissipation performance of the GaN packaged device, reduces heat accumulation within the GaN packaged device, and thus improves the performance of the GaN packaged device. Furthermore, by placing the GaN chip 5 and the control chip 2 on the same packaging island 1 and positioning the gate (G) of the GaN chip 5 above the control pin of the control chip 2, the package size of the GaN package structure can be reduced, and the connection length between the gate of the GaN chip 5 and the control pin of the control chip 2 can be shortened, thereby reducing the package inductance of the GaN packaged device.

[0042] This application provides a GaN packaging structure in which the gate (G) of the GaN chip 5 is located directly above the control pin.

[0043] In this embodiment, the gate (G) of the GaN chip 5 can be located directly above the control pin of the control chip 2, so as to further shorten the electrical connection length between the gate of the GaN chip 5 and the control pin of the control chip 2, thereby further reducing the package inductance of the GaN package structure.

[0044] This application provides a GaN packaging structure in which the gate electrode of the GaN chip 5 is connected to the control pin via a copper pillar 6.

[0045] In this embodiment, the gate (G) electrode of the GaN chip 5 is electrically connected to the control pin of the control chip 2 via a copper pillar 6. One end of the copper pillar 6 is electrically connected to the G electrode of the GaN chip 5 via conductive adhesive (e.g., conductive silver paste), and the other end is electrically connected to the control pin of the control chip 2 via conductive adhesive.

[0046] Since the conductive area of ​​copper pillar 6 is relatively large, the packaging inductance of the GaN package structure can be reduced by the above method, so as to improve the performance of the GaN package structure.

[0047] The GaN packaging structure provided in this application embodiment includes a copper layer 4 that may include a first copper layer region 41 and a second copper layer region 42. The first copper layer region 41 is connected to the drain (D) electrode of the GaN chip 5 and the drain base island pin in the first base island pin 11, and the second copper layer region 42 is connected to the sink (S) electrode of the GaN chip 5 and the sink base island pin in the first base island pin 11.

[0048] In this embodiment, the copper layer 4 covering the upper surface of the ceramic substrate 3 may specifically include a first copper layer region 41 and a second copper layer region 42 that are mutually insulated (specifically, they can be separated to achieve mutual insulation). The first copper layer region 41 is electrically connected to the drain (D) terminal of the GaN chip 5 and the D terminal base island pin in the first package base island 1. The second copper layer region 42 is electrically connected to the source (S) terminal of the GaN and the S terminal base island pin in the first package base island 1. The D terminal base island pin and the S terminal base island pin in the first package base island 1 are mutually insulated (specifically, they can be separated to achieve mutual insulation).

[0049] The above-described electrical connection method not only enhances the heat dissipation capability of the GaN package structure, but also reduces the package inductance of the GaN package structure, thereby improving the performance of the GaN package structure.

[0050] This application provides a GaN packaging structure in which a magnetic bead connected to the first copper layer region 41 is disposed in the first copper layer region 41.

[0051] In this embodiment of the application, the first copper layer region 41 can be etched to form a gap, and a magnetic bead can be placed in the gap, and the two ends of the magnetic bead are electrically connected to the first copper layer region 41.

[0052] Among them, ferrite beads can be used to suppress high-frequency noise and spike interference. By setting ferrite beads connected to the first copper layer region 41 in the first copper layer region 41, the ferrite beads can be electrically connected to the drain (D) of the GaN chip 5 to suppress high-frequency noise on the drain of the GaN chip 5. This fundamentally solves the problem that when the voltage and current of the drain of the GaN chip 5 change (i.e., during the switching process of the GaN chip 5), Cgd (Miller capacitance, specifically gate-drain capacitance, a parasitic capacitance) is generated and coupled to the gate (G) of the GaN chip 5, causing oscillation at the gate of the GaN chip 5. This improves the reliability and stability of the GaN package structure.

[0053] This application provides a GaN packaging structure in which magnetic beads are disposed in the first copper layer region 41, excluding the region directly opposite the drain electrode of the GaN chip 5.

[0054] In this embodiment of the application, in order to reduce the difficulty of setting up the magnetic bead, the magnetic bead can be set in the area outside the region directly opposite the drain electrode of the GaN chip 5 in the first copper layer region 41 (specifically, it can be set in the area outside the region corresponding to the GaN chip 5 in the first copper layer region 41). That is, the first copper layer region 41 can be divided into two parts. The first part corresponds to the drain electrode of the GaN chip 5, and the second part is located outside the drain electrode of the GaN chip 5. The first part and the second part are a whole. The magnetic bead can be set in the second part to improve the convenience of setting up the magnetic bead.

[0055] The GaN packaging structure provided in this application embodiment has a first copper layer region 41 connected to the D base island pin via a bonding wire 7, and a second copper layer region 42 connected to the S base island pin via a bonding wire 7.

[0056] In this embodiment, the first copper layer region 41 of the copper layer 4 covering the upper surface of the ceramic substrate 3 can be electrically connected to the D-type base island pin of the first packaging base island 1 via bonding wire 7, and the second copper layer region 42 can be electrically connected to the S-type base island pin of the first packaging base island 1 via bonding wire 7.

[0057] By flip-chipping the GaN chip 5 and connecting its drain (D) terminal to the first copper layer region 41, and then connecting the first copper layer region 41 to the D base island pin via bonding wire 7, the length of bonding wire 7 can be shortened, thereby reducing the package inductance of the GaN package structure. Similarly, by flip-chipping the GaN chip 5 and connecting its source (S) terminal to the second copper layer region 42, and then connecting the second copper layer region 42 to the S base island pin via bonding wire 7, the length of bonding wire 7 can be shortened, thereby reducing the package inductance of the GaN package structure.

[0058] The GaN packaging structure provided in this application embodiment has a first copper layer region 41 connected to the D base island pin via a first copper sheet, and a second copper layer region 42 connected to the S base island pin via a second copper sheet.

[0059] In addition to being electrically connected via bonding wire 7, the first copper layer region 41 and the D base island pin can also be electrically connected via a first copper sheet. Furthermore, in addition to being electrically connected via bonding wire 7, the second copper layer region 42 and the S base island pin can also be electrically connected via a second copper sheet.

[0060] Since the conductive area of ​​the copper sheet is larger than that of the bonding wire 7, using the first copper sheet to electrically connect the first copper layer region 41 to the D base island pin and using the second copper sheet to electrically connect the second copper layer region 42 to the S base island pin can further reduce the package inductance of the GaN package structure.

[0061] In the GaN package structure provided in this application embodiment, the remaining pins of the control chip 2 are connected to the second base island pins 12 via bonding wires 7.

[0062] In this embodiment, each of the remaining pins in the control chip 2, excluding the control pin, can be connected to the corresponding pins in the second base island pin 12 via bonding wire 7, so as to realize the electrical connection between each of the remaining pins in the control chip 2 and the corresponding pins in the second base island pin 12, thereby facilitating the effective driving control of the GaN chip 5.

[0063] In the GaN packaging structure provided in this application embodiment, the remaining pins of the control chip 2 are connected to the second base island pin 12 through a third copper sheet.

[0064] In addition to being electrically connected to the corresponding pins in the second base island pin 12 via bonding wire 7, the remaining pins in the control chip 2 can also be electrically connected to the corresponding pins in the second base island pin 12 via a third copper sheet, so as to reduce the package inductance of the GaN package structure and improve the performance of the GaN package structure.

[0065] It should be noted that, in the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0066] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0067] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0068] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A GaN packaging structure, characterized in that, include: A package base island containing a first base island pin and a second base island pin; The control chip and the ceramic substrate with a copper layer on the upper surface are disposed on the packaging base island; A GaN chip is flip-chip disposed on the ceramic substrate; the gate electrode (G) of the GaN chip is located above and connected to the control pin of the control chip, the remaining electrode of the GaN chip is connected to the first base island pin through the copper layer, and the remaining pin of the control chip is connected to the second base island pin. A molding compound used to encapsulate the packaging base island, the control chip, the ceramic substrate, and the GaN chip.

2. The GaN packaging structure according to claim 1, characterized in that, The gate (G) of the GaN chip is located directly above the control pin.

3. The GaN packaging structure according to claim 2, characterized in that, The gate (G) of the GaN chip is connected to the control pin via a copper pillar.

4. The GaN packaging structure according to claim 1, characterized in that, The copper layer includes a first copper layer region and a second copper layer region. The first copper layer region is connected to the drain (D) electrode of the GaN chip and the drain base island pin of the first base island pin. The second copper layer region is connected to the sink (S) electrode of the GaN chip and the sink base island pin of the first base island pin.

5. The GaN packaging structure according to claim 4, characterized in that, A magnetic bead connected to the first copper layer region is disposed in the first copper layer region.

6. The GaN packaging structure according to claim 5, characterized in that, The magnetic beads are disposed in the first copper layer region, excluding the region directly opposite the drain electrode of the GaN chip.

7. The GaN packaging structure according to claim 4, characterized in that, The first copper layer region is connected to the D-base island pin via a bonding wire, and the second copper layer region is connected to the S-base island pin via a bonding wire.

8. The GaN packaging structure according to claim 4, characterized in that, The first copper layer region is connected to the D-base island pin via a first copper sheet, and the second copper layer region is connected to the S-base island pin via a second copper sheet.

9. The GaN packaging structure according to claim 1, characterized in that, The remaining pins of the control chip are connected to the pins of the second base island via bonding wires.

10. The GaN packaging structure according to claim 1, characterized in that, The remaining pins of the control chip are connected to the pins of the second base island via a third copper plate.

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