Capacitors embedded in interconnect structures and methods of forming the same

Abstract

A capacitor embedded in an interconnection structure and a method for forming the same, wherein the capacitor comprises: a substrate; a first electrode layer on the substrate, the first electrode layer comprising a first region, a second region and a boundary region; a high-K dielectric layer on the first electrode layer; a second electrode layer on the high-K dielectric layer, the second electrode layer comprising a first electrode part and a second electrode part; and a first lead structure on the first electrode layer, the first lead structure being connected to the boundary region. By connecting the first lead structure to the middle of the first electrode layer, the resistance through the first electrode layer can be effectively reduced, so that the quality factor of the capacitor is increased. Moreover, the overall structure of the capacitor is symmetrical, so that the capacitance of the capacitor tends to be stable, and the loss is effectively reduced, so that the quality factor of the capacitor is improved. In addition, without increasing the area of the first electrode layer, the integration of the device structure is not reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a capacitor embedded in an interconnect structure and a method for forming the same. Background Technology

[0002] In today's Very Large Scale Integration (VLSI) circuits, capacitors are commonly used passive components. Generally speaking, analog capacitors have shifted from the previous polysilicon-insulator-polysilicon (PIP) type to metal-insulator-metal (MIM) type because analog radio frequency circuits require capacitors with higher capacitance density.

[0003] One way to increase capacitance density is to reduce the thickness of the dielectric. However, if the dielectric thickness is too low, the electric field strength will be too high, leading to leakage current and a decrease in breakdown voltage. High-K dielectric metal-insulator-metal (HK MIM) capacitors have good application prospects due to their high capacitance density per unit area.

[0004] However, the HK MIM capacitors produced by existing technology still have many problems. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a capacitor embedded in an interconnect structure and a method for forming the same, so as to improve the performance of the capacitor.

[0006] To solve the above-mentioned technical problems, the present invention provides a capacitor embedded in an interconnect structure, comprising: a substrate; an interconnect layer on the substrate, the interconnect layer including a capacitor region; a first electrode layer on the capacitor region, the first electrode layer including a first region, a second region, and a boundary region arranged in a horizontal direction, the boundary region being located between the first region and the second region, the first region having a first length dimension in a horizontal direction, the second region having a second length dimension in a horizontal direction, the first length dimension being equal to the second length dimension; a high-k dielectric layer on the first electrode layer; a second electrode layer on the high-k dielectric layer, the second electrode layer including a first electrode portion and a second electrode portion that are mutually separated in a horizontal direction, an opening being provided between the first electrode portion and the second electrode portion; a first lead structure on the first electrode layer, the first lead structure penetrating the high-k dielectric layer exposed by the opening in a vertical direction and being connected to the boundary region; and a second lead structure on the second electrode layer, the second lead structure being connected to the first electrode portion and the second electrode portion respectively.

[0007] Optionally, the first lead structure includes: a plurality of first conductive plugs and a first conductive layer located on the plurality of first conductive plugs; the plurality of first conductive plugs respectively penetrate the high-K dielectric layer exposed by the opening in a vertical direction and are connected to the boundary region.

[0008] Optionally, the second lead structure includes: a plurality of second conductive plugs, a plurality of third conductive plugs, and a second conductive layer located on the plurality of second conductive plugs and the plurality of third conductive plugs; the plurality of second conductive plugs are respectively connected to the first electrode portion, and the plurality of third conductive plugs are respectively connected to the second electrode portion.

[0009] Optionally, the material of the high-K dielectric layer includes: hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide.

[0010] Optionally, the material of the first electrode layer is a metal nitride; the metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride.

[0011] Optionally, the material of the second electrode layer is a metal nitride; the metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride.

[0012] Optionally, the material of the first lead structure includes: copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum.

[0013] Optionally, the material of the second lead structure includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum.

[0014] Optionally, the first electrode portion has a third length dimension along the horizontal direction, and the second electrode portion has a fourth length dimension along the horizontal direction, wherein the third length dimension and the fourth length dimension are equal.

[0015] Optionally, the substrate includes: a base, and a device structure, an isolation structure, and a conductive layer located on the base.

[0016] Accordingly, the present invention also provides a method for forming a capacitor embedded in an interconnect structure, comprising: providing a substrate; forming an interconnect layer on the substrate, the interconnect layer including a capacitor region; forming a first electrode layer on the capacitor region, the first electrode layer including a first region, a second region, and a boundary region arranged in a horizontal direction, the boundary region being located between the first region and the second region, the first region having a first length dimension in a horizontal direction, the second region having a second length dimension in a horizontal direction, the first length dimension being equal to the second length dimension; forming a high-k dielectric layer on the first electrode layer; forming a second electrode layer on the high-k dielectric layer, the second electrode layer including a first electrode portion and a second electrode portion that are mutually separated in a horizontal direction, an opening being provided between the first electrode portion and the second electrode portion; forming a first lead structure on the first electrode layer and a second lead structure on the second electrode layer, the first lead structure penetrating the high-k dielectric layer exposed by the opening in a vertical direction and being connected to the boundary region, the second lead structure being connected to the first electrode portion and the second electrode portion respectively.

[0017] Optionally, the first lead structure includes: a plurality of first conductive plugs and a first conductive layer located on the plurality of first conductive plugs; the plurality of first conductive plugs respectively penetrate the high-K dielectric layer exposed by the opening in a vertical direction and are connected to the boundary region.

[0018] Optionally, the second lead structure includes: a plurality of second conductive plugs, a plurality of third conductive plugs, and a second conductive layer located on the plurality of second conductive plugs and the plurality of third conductive plugs; the plurality of second conductive plugs are respectively connected to the first electrode portion, and the plurality of third conductive plugs are respectively connected to the second electrode portion.

[0019] Optionally, the material of the high-K dielectric layer includes: hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide.

[0020] Optionally, the material of the first electrode layer is a metal nitride; the metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride.

[0021] Optionally, the material of the second electrode layer is a metal nitride; the metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride.

[0022] Optionally, the material of the first lead structure includes: copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum.

[0023] Optionally, the material of the second lead structure includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum.

[0024] Optionally, the method for forming the second electrode layer on the high-k dielectric layer includes: forming an initial second electrode layer on the high-k dielectric layer; and performing patterning processing on the initial second electrode layer to form the second electrode layer.

[0025] Optionally, the first electrode portion has a third length dimension along the horizontal direction, and the second electrode portion has a fourth length dimension along the horizontal direction, wherein the third length dimension and the fourth length dimension are equal.

[0026] Optionally, the substrate includes: a base, and a device structure, an isolation structure, and a conductive layer located on the base.

[0027] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0028] The capacitor embedded in the interconnect structure provided by this invention includes: a first lead structure located on the first electrode layer, the first lead structure penetrating the exposed high-k dielectric layer through the opening in a vertical direction and connected to the boundary region. Since the first lead structure is connected to the middle position of the first electrode layer, when the circuit is turned on, the current flows from the boundary region of the first electrode layer to the first region and the second region respectively. Therefore, the resistance flowing through the first electrode layer at this time is half of the total resistance of the two first electrode layers connected in parallel, and its resistance value is one-quarter of the total resistance of the first electrode layer, thereby improving the quality factor of the capacitor. Furthermore, the overall structure of the capacitor is symmetrical, making the capacitance value of the capacitor tend to be stable in high-frequency circuits and effectively reducing losses, thus improving the quality factor of the capacitor. In addition, since the first electrode layer is connected to the first lead structure at only one location, with the size of the second electrode plate fixed, there is no need to increase the area of ​​the first electrode layer, thus preventing a decrease in the integration density of the device structure.

[0029] In the method for forming a capacitor embedded in an interconnect structure provided by the present invention, the first lead structure penetrates the exposed high-k dielectric layer through the opening in a vertical direction and is connected to the boundary region. Since the first lead structure is connected to the middle position of the first electrode layer, when the circuit is turned on, the current flows from the boundary region of the first electrode layer to the first region and the second region respectively. Therefore, the resistance flowing through the first electrode layer at this time is half of the total resistance of the two first electrode layers connected in parallel, and its resistance value is one-quarter of the total resistance of the first electrode layer, thereby improving the quality factor of the capacitor. Furthermore, the overall structure of the capacitor is symmetrical, which makes the capacitance value of the capacitor tend to be stable in high-frequency circuits and can effectively reduce losses, thus improving the quality factor of the capacitor. In addition, since the first electrode layer is connected to the first lead structure at only one location, with the size of the second electrode plate fixed, there is no need to increase the area of ​​the first electrode layer, thus preventing a decrease in the integration density of the device structure. Attached Figure Description

[0030] Figure 1 and Figure 2 This is a schematic diagram of the structure of a capacitor;

[0031] Figure 3 and Figure 4 This is a schematic diagram of another type of capacitor embedded in an interconnect structure;

[0032] Figures 5 to 10 This is a schematic diagram of the steps in the method for forming a capacitor embedded in an interconnect structure according to an embodiment of the present invention. Detailed Implementation

[0033] As described in the background section, existing HK MIM capacitors still have many problems. These will now be explained in detail with reference to the accompanying drawings.

[0034] Figure 1 and Figure 2 This is a schematic diagram of the structure of a capacitor.

[0035] Please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1A schematic cross-sectional view along line AA shows a capacitor 10, comprising: a substrate 100; a first electrode layer 101 on the substrate 100; a high-k dielectric layer 102 on the first electrode layer 101; a second electrode layer 103 on the high-k dielectric layer 102, the second electrode layer 103 exposing a portion of the top surface of the high-k dielectric layer 102; a first lead structure 104 on the first electrode layer 101, the first lead structure 104 penetrating the high-k dielectric layer 102 in a vertical direction and connected to the first electrode layer 101; and a second lead structure 105 on the second electrode layer 103, the second lead structure 105 being connected to the second electrode layer 103.

[0036] In this embodiment, since the first lead structure 104 is connected to one side of the first electrode layer 101, the resistance flowing through the first electrode layer 101 when the circuit is on is the overall resistance, which is relatively large, thus reducing the quality factor of the capacitor 10. Furthermore, the overall structure of the capacitor 10 is asymmetrical. In high-frequency circuits, the performance of the capacitor 10 is calculated based on the scattering matrix. The capacitance value of the capacitor 10 actually includes four values: C11 (entering from port 1), C12 (entering from port 1 and exiting from port 2), C21 (entering from port 2 and exiting from port 1), and C22 (entering from port 2). If the structure of the capacitor 10 is asymmetrical, the capacitance values ​​C11 and C22 will differ significantly, leading to increased losses and a lower quality factor.

[0037] To address the aforementioned problems, another type of capacitor has been provided in the prior art, which will be described in detail below with reference to the accompanying drawings.

[0038] Figure 3 and Figure 4 This is a schematic diagram of the structure of a capacitor.

[0039] Please refer to Figure 3 and Figure 4 , Figure 4 yes Figure 3A schematic cross-sectional view along line BB shows a capacitor 20, comprising: a substrate 200; a first electrode layer 201 on the substrate 200, the first electrode layer 201 including a first line region I, a second region II, and a third region III arranged in a horizontal direction, the second region II being located between the first region I and the third region III; a high-k dielectric layer 202 on the first electrode layer 201; a second electrode layer 203 on the high-k dielectric layer 202, the second electrode layer 203 exposing a portion of the top surface of the high-k dielectric layer 202; a first lead structure 204 on the first electrode layer 201, the first lead structure 204 penetrating the high-k dielectric layer 202 in a vertical direction and connected to the first region I and the third region III; and a second lead structure 205 on the second electrode layer 203, the second lead structure 205 being connected to the second electrode layer 203.

[0040] In this embodiment, the first lead structure 204 is connected to the first region I and the third region III of the first electrode layer 201, respectively. Therefore, when the circuit is turned on, the resistance flowing through the first electrode layer 201 is half of the total resistance of the two first electrode layers 201 connected in parallel, and its resistance value is one-quarter of the total resistance of the first electrode layer 201, thereby improving the quality factor of the capacitor 20. Moreover, the overall structure of the capacitor 20 is symmetrical, which makes the capacitance value of the capacitor 20 tend to be stable in high-frequency circuits and can effectively reduce losses, thus improving the quality factor of the capacitor 20.

[0041] However, with the size of the second electrode plate 203 fixed, the area of ​​the first electrode layer 201 needs to be increased to accommodate the connection of the first pin structure 204, which reduces the integration density of the device structure. Moreover, the increased area of ​​the first electrode layer 201 does not increase the area of ​​the first electrode layer 201 and the second electrode layer 203 facing each other, and therefore hardly increases the capacitance of the capacitor 20.

[0042] To address the aforementioned problems, this invention provides a capacitor embedded in an interconnect structure and a method for forming the same. By connecting the first lead structure to the middle position of the first electrode layer, the resistance flowing through the first electrode layer can be effectively reduced, thereby increasing the capacitor's quality factor. Furthermore, the overall structure of the capacitor is symmetrical, which stabilizes the capacitance value and effectively reduces losses, further improving the capacitor's quality factor. Additionally, with a fixed second electrode plate size, there is no need to increase the area of ​​the first electrode layer, thus preventing a decrease in the integration density of the device structure.

[0043] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figures 5 to 10 This is a schematic diagram of the steps in the capacitor embedded in the interconnect structure and the method for forming it according to an embodiment of the present invention.

[0045] Please refer to Figure 5 Substrate 300 is provided.

[0046] In this embodiment, the substrate 300 includes: a substrate, and a device structure, an isolation structure, and a conductive layer (not shown) located on the substrate.

[0047] In this embodiment, the device structure includes: a transistor, a capacitor, a resistor, or an inductor.

[0048] Please refer to Figure 6 An interconnect layer (not shown) is formed on the substrate 300, the interconnect layer including a capacitor region (not shown); a first electrode layer 301 is formed in the capacitor region, the first electrode layer 301 including a first region I, a second region II and a boundary region A arranged in a horizontal direction, the boundary region A being located between the first region I and the second region II, the first region I having a first length dimension d1 in the horizontal direction, the second region II having a second length dimension d2 in the horizontal direction, the first length dimension d1 being equal to the second length dimension d2.

[0049] In this embodiment, the first electrode layer 301 is made of metal nitride. The first electrode layer 301 formed by the metal nitride material has good electrical properties, resulting in a capacitor with high reliability.

[0050] The metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride. In this embodiment, the material of the first electrode layer 301 is titanium nitride.

[0051] The formation process of the first electrode layer 301 includes: atomic layer deposition, plasma chemical vapor deposition, low-pressure chemical vapor deposition, sputtering deposition, ion beam deposition, or ion beam-assisted deposition. In this embodiment, the first electrode layer 301 is formed using atomic layer deposition.

[0052] The thickness of the first electrode layer 301 is 100 angstroms to 1000 angstroms. The significance of selecting the thickness range of the first electrode layer 301 is that if the thickness of the first electrode layer 301 is greater than 1000 angstroms, the overall thickness of the formed capacitor will be too thick, which is not conducive to the subsequent integration process; if the thickness of the first electrode layer 301 is less than 100 angstroms, device breakdown is likely to occur, resulting in leakage current and poor reliability of the formed capacitor.

[0053] Please refer to Figure 7 A high-k dielectric layer 302 is formed on the first electrode layer 301.

[0054] In this embodiment, since the high-k dielectric layer 302 has a very high dielectric constant, the storage density of the capacitor can be increased.

[0055] The high-k dielectric layer 302 includes: hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide. In this embodiment, the high-k dielectric layer 302 is made of hafnium oxide.

[0056] Please refer to Figure 8 A second electrode layer 303 is formed on the high-K dielectric layer 302. The second electrode layer 303 includes a first electrode portion 303a and a second electrode portion 303b that are separated from each other in the horizontal direction. An opening (not shown) is provided between the first electrode portion 303a and the second electrode portion 303b.

[0057] In this embodiment, the method for forming the second electrode layer 303 on the high-k dielectric layer 302 includes: forming an initial second electrode layer (not shown) on the high-k dielectric layer 302; and performing patterning processing on the initial second electrode layer to form the second electrode layer 303.

[0058] In this embodiment, the first electrode portion 303a has a third length dimension d3 along the horizontal direction, and the second electrode portion 303b has a fourth length dimension d4 along the horizontal direction, wherein the third length dimension d3 and the fourth length dimension d4 are equal.

[0059] In this embodiment, the material of the second electrode layer 303 is a metal nitride. The second electrode layer 303 formed by the metal nitride material has good electrical properties, thereby resulting in a capacitor with high reliability.

[0060] The metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride. In this embodiment, the material of the second electrode layer 303 is titanium nitride.

[0061] The formation process of the second electrode layer 303 includes: atomic layer deposition, plasma chemical vapor deposition, low-pressure chemical vapor deposition, sputtering deposition, ion beam deposition, or ion beam-assisted deposition. In this embodiment, the second electrode layer 303 is formed using atomic layer deposition.

[0062] The thickness of the second electrode layer 303 is 100 angstroms to 1000 angstroms. The significance of selecting the thickness range of the second electrode layer 303 is that if the thickness of the second electrode layer 303 is greater than 1000 angstroms, the overall thickness of the formed capacitor will be too thick, which is not conducive to the subsequent integration process; if the thickness of the second electrode layer 303 is less than 100 angstroms, device breakdown is likely to occur, resulting in leakage current and poor reliability of the formed capacitor.

[0063] Please refer to Figure 9 and Figure 10 , Figure 10 yes Figure 9 A cross-sectional view along the CC line shows that a first lead structure 304 is formed on the first electrode layer 301, and a second lead structure 305 is formed on the second electrode layer 303. The first lead structure 304 penetrates the high-K dielectric layer 302 exposed by the opening in a vertical direction and is connected to the boundary region A. The second lead structure 305 is connected to the first electrode portion 303a and the second electrode portion 303b, respectively.

[0064] In this embodiment, the first lead structure 304 vertically penetrates the exposed high-k dielectric layer 302 through the opening and connects to the boundary region A. Since the first lead structure 304 is connected to the middle position of the first electrode layer 301, when the circuit is turned on, current flows from the boundary region A of the first electrode layer 301 to the first region I and the second region II respectively. Therefore, the resistance flowing through the first electrode layer 301 at this time is half the total resistance of the two first electrode layers 301 connected in parallel, and its resistance value is one-quarter of the total resistance of the first electrode layer 301, thereby improving the quality factor of the capacitor. Furthermore, the overall structure of the capacitor is symmetrical, which makes the capacitance value of the capacitor tend to be stable in high-frequency circuits and can effectively reduce losses, thus improving the quality factor of the capacitor. In addition, since the first electrode layer 301 is connected to the first lead structure 304 at only one location, with the size of the second electrode plate 303 fixed, there is no need to increase the area of ​​the first electrode layer 301, thus preventing a decrease in the integration density of the device structure.

[0065] In this embodiment, the first lead structure 304 includes: a plurality of first conductive plugs 304a, and a first conductive layer 304b located on the plurality of first conductive plugs 304a; the plurality of first conductive plugs 304a respectively penetrate the high-K dielectric layer 302 exposed by the opening in a vertical direction, and are connected to the boundary region A.

[0066] In this embodiment, the second lead structure 305 includes: a plurality of second conductive plugs 305a, a plurality of third conductive plugs 305b, and a second conductive layer 305c located on the plurality of second conductive plugs 305a and the plurality of third conductive plugs 305b; the plurality of second conductive plugs 305a are respectively connected to the first electrode portion 303a, and the plurality of third conductive plugs 305b are respectively connected to the second electrode portion 303b.

[0067] The material of the first lead structure 304 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum. In this embodiment, the material of the first lead structure 304 is copper.

[0068] The material of the second lead structure 305 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum. In this embodiment, the material of the second lead structure 305 is copper.

[0069] Accordingly, this embodiment of the invention also provides a capacitor embedded in an interconnect structure; please refer to [further details]. Figure 9 and Figure 10 The system includes: a substrate 300; an interconnect layer on the substrate 300, the interconnect layer including a capacitor region; a first electrode layer 301 located in the capacitor region, the first electrode layer 301 including a first region I, a second region II, and a boundary region A arranged in a horizontal direction, the boundary region A being located between the first region I and the second region II, the first region I having a first length dimension d1 in the horizontal direction, the second region II having a second length dimension d3 in the horizontal direction, the first length dimension d1 being equal to the second length dimension d2; a high-k dielectric layer 302 located on the first electrode layer 301; and a high-k dielectric layer 302 located on the high-k dielectric layer 302. The second electrode layer 303 includes a first electrode portion 303a and a second electrode portion 303b that are horizontally separated from each other, with an opening between the first electrode portion 303a and the second electrode portion 303b; a first lead structure 304 located on the first electrode layer 301, the first lead structure 304 penetrating the high-K dielectric layer 302 exposed by the opening in a vertical direction and connected to the boundary region A; and a second lead structure 305 located on the second electrode layer 303, the second lead structure 305 being connected to the first electrode portion 303a and the second electrode portion 303b respectively.

[0070] In this embodiment, a first lead structure 304 is included, located on the first electrode layer 301. The first lead structure 304 vertically penetrates the exposed high-k dielectric layer 302 through the opening and is connected to the boundary region A. Since the first lead structure 304 is connected to the middle position of the first electrode layer 301, when the circuit is turned on, current flows from the boundary region A of the first electrode layer 301 to the first region I and the second region II respectively. Therefore, the resistance flowing through the first electrode layer 301 at this time is half of the total resistance of the two first electrode layers 301 connected in parallel, and its resistance value is one-quarter of the total resistance of the first electrode layer 301, thereby improving the quality factor of the capacitor. Furthermore, the overall structure of the capacitor is symmetrical, which makes the capacitance value of the capacitor tend to be stable in high-frequency circuits and can effectively reduce losses, thus improving the quality factor of the capacitor. In addition, since the first electrode layer 301 is connected to the first lead structure 304 at only one location, with the size of the second electrode plate 303 fixed, there is no need to increase the area of ​​the first electrode layer 301, thus preventing a reduction in the integration of the device structure.

[0071] In this embodiment, the high-k dielectric layer 302 is made of hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide. In this embodiment, the high-k dielectric layer 302 is made of hafnium oxide.

[0072] In this embodiment, the material of the first electrode layer 301 is a metal nitride.

[0073] The metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride. In this embodiment, the first electrode layer 301 is made of titanium nitride.

[0074] In this embodiment, the material of the second electrode layer 303 is a metal nitride.

[0075] The metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride. In this embodiment, the material of the second electrode layer 303 is titanium nitride.

[0076] The material of the first lead structure 304 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum. In this embodiment, the material of the first lead structure 304 is copper.

[0077] The material of the second lead structure 305 includes copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum. In this embodiment, the material of the second lead structure 305 is copper.

[0078] In this embodiment, the first lead structure 304 includes: a plurality of first conductive plugs 304a, and a first conductive layer 304b located on the plurality of first conductive plugs 304a; the plurality of first conductive plugs 304a respectively penetrate the high-K dielectric layer 302 exposed by the opening in a vertical direction, and are connected to the boundary region A.

[0079] In this embodiment, the second lead structure 305 includes: a plurality of second conductive plugs 305a, a plurality of third conductive plugs 305b, and a second conductive layer 305c located on the plurality of second conductive plugs 305a and the plurality of third conductive plugs 305b; the plurality of second conductive plugs 305a are respectively connected to the first electrode portion 303a, and the plurality of third conductive plugs 305b are respectively connected to the second electrode portion 303b.

[0080] In this embodiment, the first electrode portion 303a has a third length dimension d3 along the horizontal direction, and the second electrode portion 303b has a fourth length dimension d4 along the horizontal direction, wherein the third length dimension d3 and the fourth length dimension d4 are equal.

[0081] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A capacitor embedded in an interconnect structure, characterized in that, include: Substrate; An interconnect layer is located on the substrate, the interconnect layer including a capacitor region; A first electrode layer located in the capacitor region includes a first region, a second region, and a boundary region arranged in a horizontal direction. The boundary region is located between the first region and the second region. The first region has a first length dimension in the horizontal direction, and the second region has a second length dimension in the horizontal direction. The first length dimension is equal to the second length dimension. A high-k dielectric layer located on the first electrode layer; A second electrode layer is located on the high-k dielectric layer. The second electrode layer includes a first electrode portion and a second electrode portion that are horizontally separated from each other, and an opening is provided between the first electrode portion and the second electrode portion. A first lead structure located on the first electrode layer, the first lead structure penetrating the high-k dielectric layer exposed by the opening in a vertical direction, and connected to the boundary region; A second lead structure is located on the second electrode layer, and the second lead structure is connected to the first electrode portion and the second electrode portion respectively.

2. The capacitor embedded in the interconnect structure as described in claim 1, characterized in that, The first lead structure includes: a plurality of first conductive plugs and a first conductive layer located on the plurality of first conductive plugs; the plurality of first conductive plugs respectively penetrate the high-K dielectric layer exposed by the opening in a vertical direction and are connected to the boundary region.

3. The capacitor embedded in the interconnect structure as described in claim 1, characterized in that, The second lead structure includes: a plurality of second conductive plugs, a plurality of third conductive plugs, and a second conductive layer located on the plurality of second conductive plugs and the plurality of third conductive plugs; the plurality of second conductive plugs are respectively connected to the first electrode portion, and the plurality of third conductive plugs are respectively connected to the second electrode portion.

4. The capacitor embedded in the interconnect structure as described in claim 1, characterized in that, The materials of the high-K dielectric layer include: hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide.

5. The capacitor embedded in the interconnect structure as described in claim 1, characterized in that, The material of the first electrode layer is a metal nitride; the metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride.

6. The capacitor embedded in the interconnect structure as described in claim 1, characterized in that, The material of the second electrode layer is a metal nitride; the metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride.

7. The capacitor embedded in the interconnect structure as described in claim 1, characterized in that, The materials of the first lead structure include: copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum.

8. The capacitor embedded in the interconnect structure as described in claim 1, characterized in that, The materials for the second lead structure include: copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum.

9. The capacitor embedded in the interconnect structure as described in claim 1, characterized in that, The first electrode portion has a third length dimension along the horizontal direction, and the second electrode portion has a fourth length dimension along the horizontal direction, wherein the third length dimension and the fourth length dimension are equal.

10. The capacitor embedded in the interconnect structure as claimed in claim 1, characterized in that, The substrate includes: a base, and a device structure, an isolation structure, and a conductive layer located on the base.

11. A method for forming a capacitor embedded in an interconnect structure, characterized in that, include: Provide substrate; An interconnect layer is formed on the substrate, the interconnect layer including a capacitor region; A first electrode layer is formed in the capacitor region. The first electrode layer includes a first region, a second region, and a boundary region arranged in a horizontal direction. The boundary region is located between the first region and the second region. The first region has a first length dimension in the horizontal direction, and the second region has a second length dimension in the horizontal direction. The first length dimension is equal to the second length dimension. A high-k dielectric layer is formed on the first electrode layer; A second electrode layer is formed on the high-k dielectric layer. The second electrode layer includes a first electrode portion and a second electrode portion that are horizontally separated from each other, and an opening is provided between the first electrode portion and the second electrode portion. A first lead structure is formed on the first electrode layer, and a second lead structure is formed on the second electrode layer. The first lead structure penetrates the high-k dielectric layer exposed by the opening in a vertical direction and is connected to the boundary region. The second lead structure is connected to the first electrode portion and the second electrode portion, respectively.

12. The method for forming a capacitor embedded in an interconnect structure as described in claim 11, characterized in that, The first lead structure includes: a plurality of first conductive plugs and a first conductive layer located on the plurality of first conductive plugs; the plurality of first conductive plugs respectively penetrate the high-K dielectric layer exposed by the opening in a vertical direction and are connected to the boundary region.

13. The method for forming a capacitor embedded in an interconnect structure as described in claim 11, characterized in that, The second lead structure includes: a plurality of second conductive plugs, a plurality of third conductive plugs, and a second conductive layer located on the plurality of second conductive plugs and the plurality of third conductive plugs; the plurality of second conductive plugs are respectively connected to the first electrode portion, and the plurality of third conductive plugs are respectively connected to the second electrode portion.

14. The method for forming a capacitor embedded in an interconnect structure as described in claim 11, characterized in that, The materials of the high-K dielectric layer include: hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide.

15. The method for forming a capacitor embedded in an interconnect structure as described in claim 11, characterized in that, The material of the first electrode layer is a metal nitride; the metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride.

16. The method for forming a capacitor embedded in an interconnect structure as described in claim 11, characterized in that, The material of the second electrode layer is a metal nitride; the metal nitride includes titanium nitride, tantalum nitride, copper nitride, tungsten nitride, platinum nitride, aluminum nitride, nickel nitride, or cobalt nitride.

17. The method for forming a capacitor embedded in an interconnect structure as described in claim 11, characterized in that, The materials of the first lead structure include: copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum.

18. The method for forming a capacitor embedded in an interconnect structure as described in claim 11, characterized in that, The materials for the second lead structure include: copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum.

19. The method for forming a capacitor embedded in an interconnect structure as described in claim 11, characterized in that, The method for forming the second electrode layer on the high-k dielectric layer includes: forming an initial second electrode layer on the high-k dielectric layer; and performing patterning processing on the initial second electrode layer to form the second electrode layer.

20. The method for forming a capacitor embedded in an interconnect structure as described in claim 11, characterized in that, The first electrode portion has a third length dimension along the horizontal direction, and the second electrode portion has a fourth length dimension along the horizontal direction, wherein the third length dimension and the fourth length dimension are equal.

21. The method for forming a capacitor embedded in an interconnect structure as described in claim 11, characterized in that, The substrate includes: a base, and a device structure, an isolation structure, and a conductive layer located on the base.

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