Buck-boost converter and control circuit therefor

Abstract

The application discloses a kind of boost-buck converter and its control circuit. Including: conduction time control circuit, for setting the desired conduction time of first power switch in each switching cycle;First current comparator, for comparing the current of inductor with first current threshold;Second current comparator, for comparing the current of inductor with second current threshold;Logic circuit, for controlling boost-buck converter to work in pause phase of first power switch and fourth power switch off while second power switch and third power switch on in response to inductor current less than second current threshold;And feedback control circuit, for obtaining the duration of pause phase in each switching cycle, and adjusting the desired conduction time, first and second current threshold in next switching cycle according to duration feedback, so that desired conduction time and current threshold in circuit can be adjusted in real time when system load changes, improve the transient response speed of circuit.

Description

Technical Field

[0001] This invention relates to the field of power conversion technology, and more specifically to a buck-boost converter and its control circuit. Background Technology

[0002] Modern portable electronic devices are typically powered by a battery, which serves as direct current (DC) for the various electronic components within the device. However, these components often have different voltage requirements, so such devices usually employ one or more voltage converters that reduce the nominal voltage associated with the power supply to a voltage suitable for the different electronic components.

[0003] Existing DC / DC converters with wide input voltage ranges include cascaded buck-boost converters, H-bridge buck-boost converters, Cook converters, and SEPIC (Single Enable Primary Inductance Converter) structures. Among these, the H-bridge buck-boost converter (single inductor or non-inverting buck-boost converter) offers excellent performance.

[0004] Figure 1 A schematic circuit diagram of a buck-boost converter according to the prior art is shown. Figure 1 As shown, a prior art buck-boost converter 100 includes a control circuit 110 and an external power circuit. The power circuit includes one or more switching and filter elements (e.g., inductors and capacitors), which are configured to regulate the power transfer from the input to the output of the power converter in response to one or more switching drive signals from the control circuit 110.

[0005] like Figure 1 As shown, the power circuit is configured to convert the input voltage VIN into an output voltage VOUT, including power switches S1-S4, an inductor L, and an output capacitor COUT. When power switches S1 and S3 are on and power switches S2 and S4 are off, the inductor L stores energy. When power switches S1 and S3 are off and power switches S2 and S4 are on, the energy stored in the inductor L is supplied to the load connected to the output terminal. The control circuit 110 generates switch drive signals DRV1-DRV4 based on the output voltage VOUT of the power circuit and provides them to the power switches S1-S4 to control the on and off states of the switching elements S1-S4, thereby controlling the inductor L to output energy in discontinuous pulses.

[0006] COT (Constant On-Time) control mode is a common switching power supply control mode, often used in buck-boost converters. While COT control mode has advantages such as a simple control architecture and fast transient response, it also has some disadvantages, particularly in terms of transient response. For example, when the load changes abruptly from light to heavy or vice versa, COT control mode responds relatively slowly to current changes, potentially requiring several cycles to stabilize, which can lead to momentary fluctuations in the output voltage. Furthermore, COT control mode typically uses sense inductor current to control the power switch's off-time. In transient situations, the inductor current can change drastically, especially during load abrupt changes. This can cause the control loop to respond unstablely to transients, potentially leading to output voltage oscillations or overshoot. Summary of the Invention

[0007] In view of this, the purpose of the present invention is to provide a buck-boost converter and its control circuit, which can obtain the duration of the pause phase in each switching cycle and adjust the desired on-time, peak current threshold and valley current threshold of the buck-boost converter accordingly, thereby maintaining the stability of the duration of the pause phase in each switching cycle when the load condition changes, avoiding fluctuations in the output voltage and improving the transient response speed of the circuit.

[0008] According to one aspect of the present invention, a control circuit for a buck-boost converter is provided. The buck-boost converter includes a first power switch coupled between an input voltage and a first switching node, a second power switch coupled between the first switching node and a reference ground, a third power switch coupled between a second switching node and a reference ground, a fourth power switch coupled between the second switching node and an output voltage, and an inductor coupled between the first switching node and the second switching node. The control circuit includes: an on-time control circuit for setting a desired on-time of the first power switch in each switching cycle; a first current comparator for comparing the current of the inductor with a first current threshold and generating a first control signal when the current of the inductor is greater than the first threshold current; and a second current comparator for comparing the current of the inductor with the first current threshold current. The current of the inductor is compared with a second current threshold, and a second control signal is generated when the current of the inductor is less than the second threshold current, wherein the second current threshold is less than the first current threshold; a logic circuit receives the first control signal and the second control signal, and in each switching cycle, controls the third power switch to turn off and the fourth power switch to turn on in response to the first control signal, and controls the buck-boost converter to operate in a pause phase in response to the second control signal, wherein the first power switch and the fourth power switch are turned off and the second power switch and the third power switch are turned on; and a feedback control circuit is used to obtain the duration of the pause phase in each switching cycle, and to adjust the desired on-time, the first current threshold and the second current threshold in the next switching cycle based on the duration.

[0009] Optionally, the feedback control circuit controls the desired on-time, the first current threshold, and the second current threshold to have a change opposite to the duration of the pause phase.

[0010] Optionally, the feedback control circuit includes: an encoder for obtaining state information data representing the duration of the pause phase in each switching cycle; a decoder for converting the state information data output by the encoder into first to third gear selection signals; a desired conduction time adjustment module for providing a corresponding adjustment voltage signal to the conduction time control circuit based on the first gear selection signal to adjust the desired conduction time; a peak current threshold reference generation module for generating a first current threshold reference voltage representing the first current threshold based on a second gear selection signal; and a valley current threshold reference generation module for generating a second current threshold reference voltage representing the second current threshold based on a third gear selection signal, wherein the desired conduction time adjustment module has multiple voltage output states, different first gear selection signals correspond to different voltage output states; the peak current threshold reference generation module has multiple voltage output states, different second gear selection signals correspond to different voltage output states; and the valley current threshold reference generation module has multiple voltage output states, different third gear selection signals correspond to different voltage output states.

[0011] Optionally, the encoder is a reversible counter, and the state information data corresponds to the count value of the reversible counter.

[0012] Optionally, the duration of the pause phase, from largest to smallest, corresponds one-to-one with the count value, from smallest to largest.

[0013] Optionally, the desired on-time adjustment module, the peak current threshold reference generation module, and the valley current threshold reference generation module are digital-to-analog converters, and the first to third gear selection signals are switch control signals that can be recognized by the switch in the digital-to-analog converter.

[0014] Optionally, the desired conduction time is obtained based on the input voltage, the output voltage, and the adjustment voltage signal.

[0015] Optionally, the on-time control circuit is configured to generate a third control signal in each switching cycle when the on-time of the first power switch reaches the desired on-time, the logic circuit responding to the third control signal to control the first power switch to turn off and the second power switch to turn on, and in each switching cycle, responding to the first control signal to control the third power switch to turn off and the fourth power switch to turn on.

[0016] Optionally, it further includes: a PWM comparator for comparing an error amplification signal related to the output voltage with the output voltage, and generating a pulse width modulation signal when the output voltage is less than the error amplification signal; and a mode selection circuit for controlling the buck-boost converter to operate in buck mode, boost mode, or buck-boost mode based on the comparison of the input voltage and the output voltage, wherein the logic circuit controls the first power switch and the third power switch to be turned on and the second power switch and the fourth power switch to be turned off in response to the pulse width modulation signal in each switching cycle, or controls the first power switch and the fourth power switch to be turned on and the second power switch and the third power switch to be turned off.

[0017] According to another aspect of the present invention, a buck-boost converter is provided, comprising: a first power switch coupled between an input voltage and a first switching node; a second power switch coupled between the first switching node and a reference ground; a third power switch coupled between a second switching node and a reference ground; a fourth power switch coupled between the second switching node and an output voltage; an inductor coupled between the first switching node and the second switching node; and the control circuit described above. Attached Figure Description

[0018] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0019] Figure 1 A schematic circuit diagram of a prior art buck-boost converter is shown.

[0020] Figure 2 A schematic circuit diagram of a buck-boost converter according to an embodiment of the present invention is shown.

[0021] Figures 3A to 3D Schematic circuit diagrams of the power circuits of the buck-boost converter in various operating stages under the control of the control circuit according to embodiments of the present invention are shown respectively.

[0022] Figure 4 The diagram shows a waveform of a buck-boost converter operating in buck mode according to an embodiment of the present invention.

[0023] Figure 5 The diagram shows a waveform of a buck-boost converter operating in boost mode according to an embodiment of the present invention.

[0024] Figure 6 The diagram shows a waveform of a buck-boost converter according to an embodiment of the present invention operating in buck-boost mode.

[0025] Figure 7A schematic structural diagram of the feedback control circuit in a buck-boost converter according to an embodiment of the present invention is shown. Detailed Implementation

[0026] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0027] Many specific details of the invention, such as the structure, materials, dimensions, processing methods, and techniques of the components, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0028] It should be understood that, in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic connection. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to the other element, or there may be intermediate elements; the connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them. Furthermore, the paired transistors involved in this invention are mutually matched transistors, and unless otherwise specified, are identical in size and / or type.

[0029] In the context of this invention, when a transistor is in an "off" state, it blocks current and / or conducts essentially no current. Conversely, when a transistor is in an "on" state, it conducts current significantly. For example, in one embodiment, the high-voltage transistor includes an N-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET), wherein a high voltage is provided between a first terminal (i.e., the drain) and a second terminal (i.e., the source) of the transistor. In some embodiments, an integrated control circuit can be used to drive the power switch when regulating the energy supplied to the load. Additionally, for the purposes of this disclosure, "ground" or "ground potential" in this invention refers to a reference voltage or potential relative to which all other voltages or potentials of an electronic circuit or integrated circuit (IC) are defined or measured.

[0030] DC-DC converters can be implemented as switch-mode power supplies (SMPS). DC converters can be used in a variety of circuits to provide a DC output signal by converting a DC input signal. For example, DC converters can be used in systems where power is supplied to a load by a battery, particularly where the battery voltage may vary over time (e.g., when the battery is depleted). Examples of such systems include automotive applications, personal electronic devices, Internet of Things (IoT) connected devices, or other battery-powered applications. Input and output signals can have similar or opposite polarities. SMPS converters include buck, boost, buck-boost, and other types. A buck DC-DC converter operates to provide an output voltage (VOUT) equal to or lower than the input signal voltage (VIN). A boost converter operates to provide a VOUT greater than or equal to VIN. A buck-boost converter combines the functionality of both buck and boost converters. A buck-boost converter includes one or more inductors. A series inductor is energized by the input signal and then de-energized to provide the output signal.

[0031] Figure 2 A schematic circuit diagram of a buck-boost converter according to an embodiment of the present invention is shown. The buck-boost converter 200 of this embodiment includes a power circuit 201 and a control circuit 203 coupled to the power circuit 201. The power circuit 201 includes one or more switching and filter elements (e.g., inductors and capacitors), which are configured to regulate the power transfer from the input to the output of the power converter in response to one or more switching drive signals from the control circuit 203. In some embodiments, one or more switches in the power circuit are integrated with the control circuit 203 to form an integrated circuit chip.

[0032] like Figure 2As shown, the power circuit 201 is a buck-boost converter architecture that converts the input voltage VIN at the input terminal to the output voltage VOUT at the output terminal. The power circuit 201 can be configured to operate in multiple modes (e.g., buck mode, boost mode, or buck-boost mode). The power circuit 201 includes at least power switches S1-S4, an inductor L, and an output capacitor COUT. Power switch S1 has a first terminal, a second terminal, and a control terminal, with its first terminal coupled to the input voltage VIN. Power switch S2 has a first terminal, a second terminal, and a control terminal, with its first terminal coupled to the second terminal of power switch S1 and its second terminal coupled to a reference ground. Inductor L has a first terminal and a second terminal, and the common terminal of power switches S1 and S2 forms a first switching node SW1, with the first terminal of inductor L coupled to this first switching node SW1. Power switch S3 has a first terminal, a second terminal, and a control terminal, with its second terminal connected to the reference ground. Power switch S4 has a first terminal, a second terminal, and a control terminal. Its first terminal is coupled to the first terminal of power switch S3, and its second terminal is coupled to the output voltage VOUT. Output capacitor COUT is coupled between the second terminal of power switch S4 and reference ground. The common terminal of power switches S3 and S4 forms a second switching node SW2, and the second terminal of inductor L is coupled to this second switching node SW2. In one example, power switches S1~S4 can be any controllable semiconductor switching device, such as a field-effect transistor (e.g., an n-type or p-type metal-oxide-semiconductor field-effect transistor MOSFET), a bipolar transistor, or an insulated-gate bipolar transistor (IGBT).

[0033] exist Figure 2In the example, control circuit 203 includes at least logic circuit 220 configured to control gate drivers 216 and 218 to control the on and off states of power switches S1-S4 in power circuit 201, thereby controlling inductor L to output energy in discontinuous pulses, thus providing a desired output voltage VOUT based on a given input voltage VIN. Gate drivers 216 and 218 may include charge pumps, which are not shown for simplicity. Logic circuit 220 is coupled to the control terminals (e.g., transistor gates) of power switches S1 and S2 via gate driver 216 and to the control terminals (e.g., transistor gates) of power switches S3 and S4 via gate driver 218. Gate driver 216 is configured to generate drive signals DRV1 and DRV2 based on the control signal Ton_Buck output from logic circuit 220 to control the on and off states of power switches S1 and S2. Generally, drive signals DRV1 and DRV2 are complementary signals. To prevent switches S1 and S2 from shooting through, gate driver 216 typically includes a dead-time control circuit to introduce a dead time Tdelay between drive signals DRV1 and DRV2. Gate driver 218 is configured to generate drive signals DRV3 and DRV4 based on the control signal Ton_Boost output from logic circuit 220 to control the on and off of power switches S3 and S4. Generally, drive signals DRV3 and DRV4 are complementary signals. Similarly, to prevent switches S3 and S4 from shooting through, gate driver 218 also includes a dead-time control circuit to introduce a dead time Tdelay between drive signals DRV3 and DRV4.

[0034] Although gate drivers 216 and 218 are shown as two separate modules for simplicity of illustration, in some instances, the functionality of gate drivers 216 and 218 is implemented through more (e.g., one gate driver per transistor) or fewer (e.g., one gate driver for all four transistors) modules. In some embodiments, logic circuitry 220 may be implemented as a processing unit separate from control circuitry 203 or as part of a larger processing device. In some embodiments, logic circuitry 220 (and control circuitry 203) may be implemented using a processor (e.g., a microprocessor or microcontroller) or an application-specific integrated circuit (ASIC).

[0035] As previously described, the power circuit 201 of this embodiment can be configured to operate in multiple modes and switch between multiple modes, including but not limited to buck mode, boost mode, and buck-boost mode. The control circuit 203 of this embodiment also includes a mode selection circuit 214, which compares the input voltage VIN and the output voltage VOUT, and provides the logic circuit 220 with a buck mode signal Buck_mode, a boost mode signal Boost_mode, and a buck-boost mode signal Bk_bst_mode based on the comparison result, so that the power circuit 201 operates in the various modes.

[0036] exist Figure 2 In the illustrated embodiment, the control circuit 203 further includes an error amplifier 222 and a comparator 223. The error amplifier 222 has an inverting input coupled to a feedback signal VFB of the output voltage VOUT and a non-inverting input configured to receive a reference voltage VREF. For example, the feedback signal VFB of the output voltage VOUT is obtained through a resistor divider network consisting of voltage divider resistors Ra and Rb, which are coupled in series between the output voltage VOUT and a reference ground. At their common node, a feedback signal VFB representing the output voltage VOUT is generated and coupled to the inverting input of the error amplifier 222. The error amplifier 222 compares the feedback signal VFB with the reference voltage VREF, thereby generating an amplified error signal VEA at the output between the feedback signal VFB and the reference voltage VREF.

[0037] Generally, a compensation network consisting of resistors and capacitors (not shown in the figure) is also provided between the output of the error amplifier 222 and the reference ground. Furthermore, although Figure 2 The embodiment shown uses an error amplifier 222, but those skilled in the art will know that other suitable analog or digital circuits are equally applicable, as long as they can achieve the error amplification function.

[0038] The comparator 223 has a non-inverting input coupled to the output of the error amplifier 222 and an inverting input coupled to the output voltage VOUT. The comparator 222 compares the output voltage VOUT with the error amplification signal VEA and generates a pulse width modulation (PWM) signal based on the comparison result. The output of the comparator 223 is the input to logic circuit 220, which is therefore configured to detect the state of the output voltage VOUT based on the output of the comparator 223. The function of logic circuit 220 is described in further detail below.

[0039] The control circuit 203 also includes a current comparator 226, which has a non-inverting input coupled to the first switching node SW1 and an inverting input configured to receive a peak current threshold reference voltage IPEAK_REF. The first switching node SW1 has a voltage related to (e.g., proportional to) the current (IL) flowing through the inductor L. This voltage can be obtained, for example, by sampling the current flowing through the inductor L (or power switch S1) using a sampling resistor, current transformer, or current mirror, for simplicity. Figure 2 The sampling resistor is not shown. The current comparator 226 therefore compares the inductor current IL with the peak current threshold reference voltage IPEAK_REF and outputs the signal IPEAK in response to the inductor current IL being greater than the peak current threshold reference voltage IPEAK_REF.

[0040] The control circuit 203 also includes a current comparator 228 having an inverting input coupled to the second switching node SW2 and a non-inverting input configured to receive a valley current threshold reference voltage IVALLEY_REF. As described above, the second switching node SW2 has a voltage related to (e.g., proportional to) the inductor current IL. The current comparator 228 therefore compares the inductor current IL with the valley current threshold reference voltage IVALLEY_REF and outputs the signal IVALLEY in response to the inductor current IL being less than the valley current threshold reference voltage IVALLEY_REF. The outputs of current comparators 226 and 228 are inputs to logic circuit 220, which can therefore be configured to detect the state of the inductor current IL based on current comparators 226 and 228, the function of which is described in further detail below.

[0041] Control circuit 203 also includes an on-time control circuit 224 (e.g., a timer) coupled to logic circuit 220. On-time control circuit 224 is configured to start timing when power switch S1 is turned on, for setting the on-time of power switch S1 in each switching cycle. For example, the on-time control circuit 224 is configured to start timing when power switch S1 is turned on in each switching cycle and provide a signal COT to logic circuit 220 when the on-time of power switch S1 reaches a desired on-time Ton. In some examples, the on-time control circuit 224 also receives an input voltage VIN and an output voltage VOUT as inputs for determining the desired on-time Ton of power switch S1 in each switching cycle. The functionality of on-time control circuit 224 and logic circuit 220 is described in further detail below.

[0042] In some embodiments, to prevent reverse current in the circuit, the control circuit 203 further includes a zero-crossing detection circuit 227 coupled to the logic circuit 220. The zero-crossing detection circuit 227 has an input coupled to the first switching node SW1 and an output coupled to the logic circuit 220. The zero-crossing detection circuit 227 is configured to detect the inductor current IL and generate a zero-crossing detection signal ZCD to the logic circuit 220 when the inductor current IL crosses zero (e.g., the inductor current IL is less than or equal to zero). The logic circuit 220 turns off both power switches S1 and S4 and turns on both power switches S2 and S3 based on the zero-crossing detection signal ZCD. In practical applications, the zero-crossing detection circuit 227 can determine whether the current flowing through the inductor L has crossed zero by detecting the current flowing through switch S1 or S4.

[0043] According to the teachings of this embodiment, the control circuit 203 controls the buck-boost converter with a combination of constant on-time (COT) control and peak current mode (PCM) control. Figures 3A to 3D Schematic circuit diagrams of the power circuits of the buck-boost converter in this embodiment, under the control of the control circuit 203, are shown respectively. As described below, in Figures 3A to 3D The four-stage operation shown allows the power circuit 201 to operate in buck mode, boost mode, or buck-boost mode.

[0044] in, Figure 3A The power circuit 201 in the boost turn-on phase is shown. During the boost turn-on phase, power switches S1 and S3 are turned on, while power switches S2 and S4 are turned off. Therefore, as... Figure 3A The current path is formed as indicated by the arrows, and the inductor L is energized by the input voltage VIN. During the boost turn-on phase, the output capacitor COUT provides the energy (stored prior to this phase) to the output (e.g., the output voltage VOUT).

[0045] Figure 3B A power circuit 201 is shown in either the boost-off or buck-on phase. During the boost-off or buck-on phase, power switches S1 and S4 are on, while power switches S2 and S3 are off. Therefore, as shown by... Figure 3B The current path is formed as shown by the arrow in the diagram, and the input terminal VIN is coupled to the output terminal VOUT through the inductor L.

[0046] Figure 3C The power circuit 201 in the buck shutdown phase is shown. During the buck shutdown phase, power switches S2 and S4 are turned on, while power switches S1 and S3 are turned off. Therefore, as... Figure 3CThe current path is formed as shown by the arrow in the diagram, and the inductor L is de-energized by providing energy to the output (e.g., the output voltage VOUT).

[0047] Figure 3D The power circuit 201 in the pause phase is shown. During the pause phase, power switches S2 and S3 are turned on, while power switches S1 and S4 are turned off. Therefore, as shown by... Figure 3D The current path is formed as indicated by the arrows. During the pause phase, energy is stored in the power circuit 201 because the inductor L is short-circuited, thus flowing through... Figure 3D The current in the loop shown is approximately constant, decreasing slightly due to the combination of the time constant of inductor L and resistive losses. In some embodiments, logic circuit 220 keeps power circuit 201 in a pause phase as long as the output voltage VOUT is greater than the target threshold voltage. Introducing a pause phase in some embodiments allows for reduced energy flow to the output while preventing energy from being added to power circuit 201 (e.g., by energizing inductor L by the input voltage VIN, such as...). Figure 3A (As shown in the diagram). Therefore, a balance is maintained between the energy delivered to the power circuit 201 and the energy consumed at the output, and this balance is independent of the magnitudes of the input voltage VIN and the output voltage VOUT. Thus, introducing a pause phase into the power circuit 201 can reduce switching losses due to regulation activities, lower the quiescent power consumption of the buck-boost converter, and reduce the switching frequency, thereby reducing electromagnetic interference (EMI).

[0048] Figures 4 to 6 The following diagrams illustrate the waveforms of the buck-boost converter in this embodiment operating in buck mode, boost mode, and buck-boost mode. Figures 3A to 3D as well as Figures 4 to 6 The working principle of the buck-boost converter in this embodiment under various modes will be explained in detail.

[0049] like Figure 4 As shown, when the input voltage VIN is greater than the output voltage VOUT, the mode selection circuit 214 provides a buck mode signal Buck_mode to the logic circuit 220, enabling the logic circuit 220 to control the power circuit 201 to operate in buck mode. In buck mode, when the output voltage VOUT is less than the error amplification signal VEA, the comparator 223 outputs a valid (e.g., high-level) pulse width modulation signal PWM. The logic circuit 220 controls the power circuit 201 to operate during the buck enable phase based on the high-level PWM signal. Figure 3BAs shown, during the buck turn-on phase, power switches S1 and S4 are turned on, while power switches S2 and S3 are turned off. At this time, the input voltage VIN charges the inductor L, and the inductor current IL rises. The turn-on time of the buck turn-on phase is controlled by the on-time control circuit 224. When the on-time of power switch S1 reaches the desired on-time Ton, the logic circuit 220 controls the power circuit 201 to operate during the buck turn-off phase according to the signal COT. Figure 3C As shown, during the buck shutdown phase, power switches S2 and S4 are turned on, while power switches S1 and S3 are turned off. At this time, inductor L transfers energy to the output VOUT, thus the inductor current IL decreases. When the inductor current IL decreases to the valley current threshold reference voltage IVALLEY_REF or the zero-crossing detection circuit 227 detects that the inductor current IL is 0, logic circuit 220 controls power circuit 201 to operate during the pause phase based on the signal IVALLEY generated by current comparator 228 or the zero-crossing detection signal ZCD generated by zero-crossing detection circuit 227. Figure 3D As shown, during the pause phase, power switches S2 and S3 are turned on, while power switches S1 and S4 are turned off. At this time, energy is stored in power circuit 201. Because the energy flow to the output is reduced, switching losses and static power consumption are decreased. The comparator 223 outputs a high-level pulse width modulation (PWM) signal again until the output voltage VOUT is again less than the error amplification signal VEA. This process repeats continuously until the output voltage VOUT is approximately equal to the error amplification signal VEA.

[0050] like Figure 5 As shown, when the input voltage VIN is less than the output voltage VOUT, the mode selection circuit 214 outputs a boost mode signal Boost_mode to the logic circuit 220, enabling the logic circuit 220 to control the power circuit 201 to operate in boost mode. In boost mode, when the output voltage VOUT is less than the error amplification signal VEA, the comparator 223 outputs a high-level pulse width modulation signal PWM. The logic circuit 220 controls the power circuit 201 to operate during the boost enable phase based on the high-level pulse width modulation signal PWM. Figure 3A As shown, during the boost turn-on phase, power switches S1 and S3 are turned on, while power switches S2 and S4 are turned off. At this time, the inductor L is energized by the input voltage VIN, and the inductor current IL rises. When the inductor current IL rises to the peak current threshold reference voltage IPEAK_REF, the current comparator 226 outputs the signal IPEAK. The logic circuit 220 controls the logic circuit 201 to operate during the boost turn-off phase based on the signal IPEAK. Figure 3BAs shown, during the boost shutdown phase, power switches S1 and S4 are turned on, while power switches S2 and S3 are turned off. At this time, the input voltage VIN is coupled to the output terminal VOUT through inductor L, and the inductor current IL continuously decreases. When the inductor current IL decreases to the valley current threshold reference voltage IVALLEY_REF or the zero-crossing detection circuit 227 detects that the inductor current IL is 0, the logic circuit 220 controls the power circuit 201 to operate during the pause phase based on the signal IVALLEY generated by the current comparator 228 or the zero-crossing detection signal ZCD generated by the zero-crossing detection circuit 227. Figure 3D As shown, during the pause phase, power switches S2 and S3 are turned on, while power switches S1 and S4 are turned off. At this time, energy is stored in power circuit 201. Because the energy flow to the output is reduced, switching losses and static power consumption are decreased. The comparator 223 outputs a high-level pulse width modulation (PWM) signal again until the output voltage VOUT is again less than the error amplification signal VEA. This process repeats continuously until the output voltage VOUT is approximately equal to the error amplification signal VEA.

[0051] like Figure 6 As shown in Figure 3A, when the input voltage VIN is close to the output voltage VOUT, the mode selection circuit 214 outputs a buck-boost mode signal Bk_bst_mode to the logic circuit 220, enabling the logic circuit 220 to control the power circuit 201 to operate in buck-boost mode. In buck-boost mode, when the output voltage VOUT is less than the error amplification signal VEA, the comparator 223 outputs a high-level pulse width modulation signal PWM. The logic circuit 220 controls the power circuit 201 to operate in the boost turn-on phase based on the high-level PWM signal. As shown in Figure 3A, during the boost turn-on phase, power switches S1 and S3 are turned on, while power switches S2 and S4 are turned off. At this time, the inductor L is energized by the input voltage VIN, and the inductor current IL rises. When the inductor current IL rises to the peak current threshold reference voltage IPEAK_REF, the current comparator 226 outputs the signal IPEAK. The logic circuit 220 controls the logic circuit 201 to operate in the boost turn-off or buck turn-on phase based on the signal IPEAK. Figure 3B As shown, during the boost shutdown phase, power switches S1 and S4 are turned on, while power switches S2 and S3 are turned off. At this time, the input voltage VIN is coupled to the output terminal VOUT through inductor L, and the inductor current IL rises continuously with a smaller slope. When the on-time of power switch S1 reaches the desired on-time Ton, logic circuit 220 controls power circuit 201 to operate during the buck shutdown phase according to signal COT, as follows... Figure 3CAs shown, during the buck shutdown phase, power switches S2 and S4 are turned on, while power switches S1 and S3 are turned off. At this time, inductor L transfers energy to the output VOUT, thus the inductor current IL decreases. When the inductor current IL decreases to the valley current threshold reference voltage IVALLEY_REF or the zero-crossing detection circuit 227 detects that the inductor current IL is 0, logic circuit 220 controls power circuit 201 to operate during the pause phase based on the signal IVALLEY generated by current comparator 228 or the zero-crossing detection signal ZCD generated by zero-crossing detection circuit 227. Figure 3D As shown, during the pause phase, power switches S2 and S3 are turned on, while power switches S1 and S4 are turned off. At this time, energy is stored in power circuit 201. Because the energy flow to the output is reduced, switching losses and static power consumption are decreased. The comparator 223 outputs a high-level pulse width modulation (PWM) signal again until the output voltage VOUT is again less than the error amplification signal VEA. This process repeats continuously until the output voltage VOUT is approximately equal to the error amplification signal VEA.

[0052] As described above, while the buck-boost converter in this embodiment can reduce energy flow at the output terminal by introducing pause phases at certain stages, thereby reducing switching losses due to regulation and lowering the static power consumption of the buck-boost converter, this approach can affect the transient response of the circuit during load changes. For example, if the pause phase duration TD is short, the system may restart the switching operation quickly during load changes, thus providing a faster transient response. However, excessively rapid switching may cause overshoot or oscillation of the output voltage VOUT. If the pause phase duration TD is long, the switching frequency may be slowed down, thereby reducing output voltage oscillation. However, this may also lead to a slower transient response, especially during load changes, resulting in the inability to adjust the output voltage in a timely manner and causing output voltage fluctuations.

[0053] To address the transient response issue caused by the introduction of a pause phase, continue to refer to... Figure 2In this embodiment, the control circuit 203 of the buck-boost converter 200 also includes a feedback control circuit 230. The input of the feedback control circuit 230 is coupled to the logic circuit 220 to obtain the duration TD of the pause phase in each switching cycle, and adjust the expected on-time Ton, peak current threshold reference voltage IPEAK_REF, and valley current threshold reference voltage IVALLEY_REF in the on-time control circuit 224 in the next switching cycle according to the duration TD. Taking the buck mode as an example, when the system load suddenly increases, if the expected on-time Ton and peak current threshold reference voltage IPEAK_REF remain unchanged, the duration TD of the pause phase in the subsequent switching cycle will decrease; similarly, when the system load suddenly decreases, if the expected on-time Ton and peak current threshold reference voltage IPEAK_REF remain unchanged, the duration TD of the pause phase in the subsequent switching cycle will increase, and the change in the pause phase time may cause fluctuations in the output voltage VOUT. The feedback control circuit 230 in this embodiment can adjust the peak current threshold reference voltage IPEAK_REF and the desired conduction time Ton based on the detected change in the duration TD of the pause phase, thereby maintaining the stability of the duration TD of the pause phase under different load conditions and achieving the purpose of output voltage regulation.

[0054] In some embodiments, the desired on-time Ton, peak current threshold reference voltage IPEAK_REF, and valley current threshold reference voltage IVALLEY_REF change in opposite directions to the duration TD of the pause phase through adjustments made by the feedback control circuit 230. For example, when the system load increases, the duration TD of the pause phase decreases, and the feedback control circuit 230 increases the desired on-time Ton, peak current threshold reference voltage IPEAK_REF, and valley current threshold reference voltage IVALLEY_REF based on the decreased pause duration TD; conversely, when the system load decreases, the duration TD of the pause phase increases, and the feedback control circuit 230 decreases the desired on-time Ton, peak current threshold reference voltage IPEAK_REF, and valley current threshold reference voltage IVALLEY_REF based on the increased pause duration TD. This maintains the stability of the pause duration TD across multiple switching cycles when the system load changes, preventing fluctuations in the output voltage.

[0055] Figure 7 A schematic structural diagram of the feedback control circuit in a buck-boost converter according to an embodiment of the present invention is shown. Figure 7As shown, in some embodiments, the feedback control circuit 230 includes an encoder 231, a decoder 232, a desired on-time adjustment module 233, a peak current threshold reference generation module 234, and a valley current threshold reference generation module 235.

[0056] Encoder 231 is used to obtain state information data Data in each switching cycle, which represents the duration TD of the pause phase.

[0057] The decoder 232 is connected to the encoder 231 and is used to convert the status information data Data output by the encoder 231 into gear selection signals D1 to D3.

[0058] In some embodiments, the encoder 231 can be a reversible counter, and the plurality of state information data Data are the count values ​​of the reversible counter, with different count values ​​corresponding to different durations of the pause phase. In some embodiments, the duration TD of the pause phase, from largest to smallest, corresponds one-to-one with the count values, from smallest to largest. In this embodiment, the count value can be 10 four-bit binary numbers, and to correspond with the encoder 231, the decoder 232 in this embodiment is a 4-16 bit decoder. Of course, this correspondence is only a preferred embodiment of the present invention, and those skilled in the art can use other correspondence methods in certain situations.

[0059] The desired on-time adjustment module 233 provides a corresponding adjustment voltage signal Regulate to the on-time control circuit 224 based on the gear selection signal D1, so as to adjust the desired on-time Ton in the on-time control circuit 224. For example, in this embodiment, the desired on-time Ton = K × (VIN - VOUT) + Tx, where Tx is controlled by the output of the desired on-time adjustment module 233. In some embodiments, the desired on-time adjustment module 233 has multiple voltage output states, and different gear selection signals D1 correspond to different voltage output states.

[0060] The peak current threshold reference generation module 234 is used to generate the peak current threshold reference voltage IPEAK_REF according to the gear selection signal D2. Similarly, the peak current threshold reference generation module 234 also has multiple voltage output states, with different gear selection signals D2 corresponding to different voltage output states.

[0061] The valley current threshold reference generation module 235 is used to generate the peak current threshold reference voltage IPEAK_REF according to the gear selection signal D3. Similarly, the valley current threshold reference generation module 235 also has multiple voltage output states, with different gear selection signals D2 corresponding to different voltage output states.

[0062] In some embodiments, the desired on-time adjustment module 233, the peak current threshold reference generation module 234, and the valley current threshold reference generation module 235 can be implemented using a digital-to-analog converter (DAC). The range selection signals D1 to D3 can be switch control signals recognizable by the switches in the DAC. The range selection signals D1 to D3 achieve different voltage output states by changing the number and position of the on control switches in the DAC. Furthermore, the DAC can be a weighted resistor type DAC or a weighted current type DAC; this invention does not impose any limitations on this comparison.

[0063] In summary, the buck-boost converter and its control circuit provided by the present invention include a feedback control circuit. The feedback control circuit is used to obtain the duration of the pause phase in each switching cycle, and can adjust the desired conduction time, peak current threshold and valley current threshold of the circuit according to the obtained duration. Thus, the desired conduction time and current threshold in the circuit can be adjusted in real time when the system load changes, avoiding output voltage fluctuations and improving the transient response speed of the circuit.

[0064] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0065] As described above, these embodiments of the present invention do not exhaustively cover all details, nor do they limit the invention to the specific embodiments described. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A control circuit for a buck-boost converter, the buck-boost converter comprising a first power switch coupled between an input voltage and a first switching node, a second power switch coupled between the first switching node and a reference ground, a third power switch coupled between a second switching node and a reference ground, a fourth power switch coupled between the second switching node and an output voltage, and an inductor coupled between the first switching node and the second switching node, the control circuit comprising: A conduction time control circuit is used to set the desired conduction time of the first power switch in each switching cycle; A first current comparator is used to compare the current of the inductor with a first current threshold, and generate a first control signal when the current of the inductor is greater than the first threshold current. A second current comparator is used to compare the current of the inductor with a second current threshold, and to generate a second control signal when the current of the inductor is less than the second threshold current, wherein the second current threshold is less than the first current threshold. A logic circuit receives the first control signal and the second control signal, and in each switching cycle, controls the third power switch to turn off and the fourth power switch to turn on in response to the first control signal, and controls the buck-boost converter to operate in a pause phase in response to the second control signal, where the first power switch and the fourth power switch are off and the second power switch and the third power switch are on; and A feedback control circuit is used to obtain the duration of the pause phase in each switching cycle, and to adjust the desired on-time, the first current threshold, and the second current threshold in the next switching cycle based on the duration.

2. The control circuit according to claim 1, wherein, The feedback control circuit controls the desired on-time, the first current threshold, and the second current threshold to change in the opposite direction to the duration of the pause phase.

3. The control circuit according to claim 2, wherein, The feedback control circuit includes: An encoder is used to obtain state information data characterizing the duration of the pause phase in each switching cycle; A decoder, which converts the status information data output by the encoder into first to third gear selection signals; A desired conduction time adjustment module is used to provide a corresponding adjustment voltage signal to the conduction time control circuit based on a first gear selection signal, so as to adjust the desired conduction time. A peak current threshold reference generation module, used to generate a first current threshold reference voltage characterizing the first current threshold based on a second gear selection signal; and The valley current threshold reference generation module is used to generate a second current threshold reference voltage representing the second current threshold based on the third gear selection signal. The desired conduction time adjustment module has multiple voltage output states, with different first-level selection signals corresponding to different voltage output states; the peak current threshold reference generation module has multiple voltage output states, with different second-level selection signals corresponding to different voltage output states; and the valley current threshold reference generation module has multiple voltage output states, with different third-level selection signals corresponding to different voltage output states.

4. The control circuit according to claim 3, wherein, The encoder is a reversible counter, and the state information data corresponds to the count value of the reversible counter.

5. The control circuit according to claim 4, wherein, The duration of the pause phase, from largest to smallest, corresponds one-to-one with the count value, from smallest to largest.

6. The control circuit according to claim 3, wherein, The desired on-time adjustment module, the peak current threshold reference generation module, and the valley current threshold reference generation module are digital-to-analog converters. The first to third gear selection signals are switch control signals that can be recognized by the switch in the digital-to-analog converter.

7. The control circuit according to claim 3, wherein, The desired conduction time is obtained based on the input voltage, the output voltage, and the adjustment voltage signal.

8. The control circuit according to claim 1, wherein, The conduction time control circuit is used to generate a third control signal in each switching cycle when the conduction time of the first power switch reaches the desired conduction time. The logic circuit responds to the third control signal by controlling the first power switch to turn off and the second power switch to turn on.

9. The control circuit according to claim 1, further comprising: A PWM comparator is used to compare an error amplification signal related to the output voltage with the output voltage, and to generate a pulse width modulation signal when the output voltage is less than the error amplification signal; as well as A mode selection circuit is used to control the buck-boost converter to operate in buck mode, boost mode, or buck-boost mode based on a comparison of the input voltage and the output voltage. In each switching cycle, the logic circuit controls the first power switch and the third power switch to be turned on in response to the pulse width modulation signal, while the second power switch and the fourth power switch are turned off, or... The first power switch and the fourth power switch are turned on, while the second power switch and the third power switch are turned off.

10. A buck-boost converter, comprising: A first power switch coupled between the input voltage and the first switching node; A second power switch coupled between the first switching node and reference ground; A third power switch coupled between the second switching node and the reference ground; A fourth power switch coupled between the second switching node and the output voltage; as well as An inductor coupled between the first switching node and the second switching node; as well as The control circuit according to any one of claims 1-9.

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