A multi-channel burst signal extraction and analysis device based on FPGA

Abstract

The application relates to a multi-channel burst signal extraction and analysis device based on FPGA and belongs to the technical field of digital signal processing. The device comprises a bus control module, a preprocessing channelization module, a signal detection module, a data delay module and a signal extraction and analysis module and the like. The device is characterized in that the number of burst channels in satellite communication is large and the channels are random, digital channelization and signal frequency domain detection and analysis technology are fully utilized, any bandwidth and any time length of burst signals are completely and efficiently extracted, signal analysis of signals of a specific system is completed, time, frequency and data information of the burst signals are obtained, and a foundation is laid for subsequent signal processing. Compared with the prior art, the application has strong real-time performance, can simultaneously complete multi-channel burst signal extraction and analysis, is suitable for single-chip FPGA implementation, is favorable for reducing the equipment size and reducing the equipment cost.

Description

Technical Field

[0001] This invention belongs to the field of signal processing technology, specifically referring to an FPGA-based multi-channel burst signal extraction and analysis device that can be used for real-time processing of satellite downlink signals. Background Technology

[0002] In today's highly information-driven era, communication has become the "lifeline" of modern society. As an important component of the communication field, satellite communication has advantages such as long communication distance, large communication capacity, flexible networking, large coverage area, and good security. It occupies a very important position in both civilian and military fields. Therefore, understanding and mastering the distribution and parameters of satellite signals in specific frequency bands (such as the number of signals, frequency, bandwidth, data, etc.) is of great significance.

[0003] Currently, domestic methods primarily employ data acquisition or real-time processing to process satellite communication link signals and gain a preliminary understanding of the link's communication characteristics. Extracting internal communication features requires continuous signal reception over extended periods. However, acquisition devices have limited continuous acquisition time and low real-time processing capabilities, making long-term continuous reception difficult. Furthermore, existing real-time processing equipment typically acquires data from a specific number of channels, failing to fully cover all frequency points within the bandwidth.

[0004] With the advancement of integrated circuit technology, the application of ultra-high-speed samplers and large-scale FPGA chips can overcome hardware performance bottlenecks. Therefore, exploring a device capable of extracting narrowband digital burst signals and improving the real-time performance and processing capabilities of equipment is an urgent need for long-term continuous processing of satellite signals and obtaining internal communication characteristics. Summary of the Invention

[0005] The technical problem to be solved by this invention is to avoid the shortcomings of the aforementioned background technology and provide a multi-channel burst signal extraction and analysis device based on FPGA. This device is designed and implemented based on an FPGA platform and uses burst detection technology to extract multi-channel burst signal data. It not only avoids the problems of low real-time processing capability and limited number of channels in previous devices, but also features high integration, reliable algorithm performance, ease of implementation, and low equipment cost.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A multi-channel burst signal extraction and analysis device based on FPGA includes a bus control module 1, a preprocessing channelization module 2, a signal detection module 3, a data delay module 4, and a signal extraction and analysis module 5 implemented on FPGA. The FPGA has an LVDS high-speed data bus interface.

[0008] Bus control module 1 is used to set the burst signal detection threshold, channelization delay time, extract the data transmission address and sub-channel frequency bandwidth, send the data transmission address and sub-channel frequency bandwidth to the preprocessing channelization module 2, send the burst signal detection threshold to the signal detection module 3, and send the channelization delay time to the data delay module 4.

[0009] Preprocessing channelization module 2 is used to divide the raw sampled data input via the high-speed data bus interface into 2 equal parts. n The sub-channel data is processed in parallel, n≥1, and then the sub-channel data and channel number are serially sent into the data delay module 4;

[0010] The signal detection module 3 is used to perform a fast Fourier transform on the raw sampled data input via the high-speed data bus interface, compare the fast Fourier transform result with the burst signal detection threshold, obtain the start time, end time and signal occurrence channel number of the burst signal, and send the result to the signal extraction and analysis module 5.

[0011] The data delay module 4 is used to delay the serial sub-channel data output by the preprocessing channelization module 2 according to the channelization delay time output by the bus control module 1, and then send the delayed serial sub-channel data and the corresponding channel number to the signal extraction module 5.

[0012] The signal extraction and analysis module 5 is used to extract and analyze the delayed data output by the data delay module 4 based on the start time, end time and signal occurrence channel number output by the signal detection module 3.

[0013] The preprocessing channelization module 2 includes one or more frequency conversion filtering units connected in series. The first frequency conversion filtering unit includes an up-conversion module 201, a down-conversion module 202, and a serial filtering module 203. The k-th frequency conversion filtering unit includes 2 k-2 The system includes a group of frequency converter modules and a serial filter decimation module 204, where k ≥ 2. Each group of frequency converter modules includes an up-conversion module 201 and a down-conversion module 202. The output of one frequency converter module in the preceding frequency conversion filter unit corresponds to the input of a group of frequency converter modules in the following frequency conversion filter unit.

[0014] The upconversion module 201 performs upconversion on the sampled data, shifting the data to half the negative frequency position;

[0015] The downconversion module 202 performs a downconversion operation on the sampled data, shifting the data to half the positive frequency.

[0016] The serial filtering module 203 performs filtering operations on the up-conversion and down-conversion data in this frequency conversion filtering unit and outputs the filtered data of the two sub-channels.

[0017] The serial filtering and extraction module 204 performs filtering and extraction operations on the up-conversion and down-conversion data in this frequency conversion filtering unit to obtain data from multiple equally spaced sub-channels.

[0018] The signal detection module 3 includes a threshold storage module 301, a Fourier transform module 302, and an amplitude comparison module 303; wherein,

[0019] The threshold storage module 301 receives the burst signal detection threshold information output by the bus control module 1, stores the amplitude threshold information of the corresponding frequency point, and then sends the amplitude threshold value to the amplitude comparison module 303 according to the frequency point sequence number sent by the Fourier transform module 302.

[0020] The Fourier transform module 302 performs continuous fast Fourier transform on the original sampled data and sends the transformed spectrum amplitude result and frequency point sequence number to the amplitude comparison module 303.

[0021] The amplitude comparison module 303 receives the spectrum amplitude result and frequency point sequence number output by the Fourier transform module 302, as well as the amplitude threshold value of the corresponding frequency point output by the threshold storage module 301. If the spectrum amplitude continuously exceeds the threshold value within a set number of times, the signal is considered to have appeared. If the spectrum amplitude that has appeared within a set number of times is continuously lower than the threshold value, the signal is considered to have disappeared. The start time, end time, and signal occurrence channel number of the burst signal are sent to the signal extraction and analysis module 5.

[0022] The data delay module 4 includes a data write module 401 and a data read module 402; wherein,

[0023] The data writing module 401 receives the serial sub-channel data and channel number output by the preprocessing channelization module 2, and stores the sub-channel data into a corresponding data storage stack according to the channel number;

[0024] The data read module 402 receives the channelization delay time output by the bus control module 1, reads the data written by the data write module 401 after multiple cycles based on the channelization delay time, and then sends it to the signal extraction and analysis module 5.

[0025] The signal extraction and analysis module 5 includes a data extraction module 501 and a signal analysis module 502; wherein,

[0026] The data extraction module 501 receives the serial sub-channel data and channel number output by the data delay module 4, as well as the start time, end time, and signal occurrence channel number of the burst signal output by the signal detection module 3. Based on the above information, it extracts the data of the corresponding channel and outputs it to the signal analysis module 502 and simultaneously outputs it to the outside.

[0027] The signal analysis module 502 receives the extracted data output by the data extraction module 501 and obtains the precise frequency of the signal by performing high-order squared spectrum analysis on the data.

[0028] Compared with the prior art, the present invention has the following advantages:

[0029] 1. The present invention employs a real-time processing device, which can realize the function of real-time extraction of burst signals and accurate measurement of frequency and time.

[0030] 2. This invention is based on high-speed sampling and large-scale high-speed FPGA chip implementation, and can realize signal extraction of arbitrary duration and bandwidth. Attached Figure Description

[0031] Figure 1 This is a block diagram illustrating the principle of a narrowband digital channelization device in an embodiment of the present invention.

[0032] Figure 2 yes Figure 1 Block diagram of the principle of the preprocessing channelization module 2.

[0033] Figure 3 yes Figure 1 Block diagram of the principle of signal detection module 3.

[0034] Figure 4 yes Figure 1 Block diagram of the principle of data delay module 4.

[0035] Figure 5 yes Figure 1 The principle block diagram of the signal extraction and analysis module 5. Detailed Implementation

[0036] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0037] Reference Figures 1 to 5 A multi-channel burst signal extraction and analysis device based on FPGA includes a bus control module 1, a preprocessing channelization module 2, a signal detection module 3, a data delay module 4, and a signal extraction and analysis module 5 implemented based on FPGA.

[0038] Figure 1 This is a schematic block diagram of the device. The embodiments are as follows: Figure 1Connection lines. The FPGA has an LVDS high-speed data bus interface, wherein the bus control module 1 is used to set the burst signal detection threshold, channelization delay time, extract the data transmission address and sub-channel frequency bandwidth, and send the data transmission address and sub-channel frequency bandwidth to the preprocessing channelization module 2, and send the burst signal detection threshold to the signal detection module 3, and send the channelization delay time to the data delay module 4; the preprocessing channelization module 2 is used to divide the raw sampled data input via the high-speed data bus interface into 2 equal parts. n The system processes parallel sub-channel data (n≥1), then serially inputs the sub-channel data and channel number into the data delay module 4; the signal detection module 3 performs a Fast Fourier Transform on the raw sampled data input via the high-speed data bus interface, compares the Fast Fourier Transform result with the burst signal detection threshold to obtain the start time, end time, and signal occurrence channel number of the burst signal, and sends the result to the signal extraction and analysis module 5; the data delay module 4 delays the serial sub-channel data output by the preprocessing channelization module 2 according to the channelization delay time output by the bus control module 1, and then sends the delayed serial sub-channel data and the corresponding channel number to the signal extraction module 5; the signal extraction and analysis module 5 extracts data and performs signal analysis on the delayed data output by the data delay module 4 according to the start time, end time, and signal occurrence channel number output by the signal detection module 3.

[0039] In the above-described device, the preprocessing channelization module 2 includes one or more frequency conversion filtering units connected in series, such as... Figure 2 As shown, the first frequency conversion filter unit includes an up-conversion module 201, a down-conversion module 202, and a serial filter module 203. The k-th frequency conversion filter unit includes 2 (k-2) The system comprises a frequency conversion module and a serial filtering and decimation module 204, where k ≥ 2. Each frequency conversion module includes an up-conversion module 201 and a down-conversion module 202. The output of one frequency conversion module in the preceding frequency conversion and filtering unit corresponds to the input of a frequency conversion module in the following frequency conversion and filtering unit. Specifically, the up-conversion module 201 performs an up-conversion operation on the sampled data, shifting the data to half of the negative frequency. The down-conversion module 202 performs a down-conversion operation on the sampled data, shifting the data to half of the positive frequency. The serial filtering module 203 performs a filtering operation on the up- and down-converted data in this frequency conversion and filtering unit, outputting two filtered sub-channel data. The serial filtering and decimation module 204 performs a filtering and decimation operation on the up- and down-converted data in this frequency conversion and filtering unit, obtaining data from multiple equally spaced sub-channels.

[0040] The function of signal detection module 3 is to detect the frequency, occurrence time, and end time of burst signals in the sampled data. For example... Figure 3As shown, the system includes a threshold storage module 301, a Fourier transform module 302, and an amplitude comparison module 303. The threshold storage module 301 receives the burst signal detection threshold information output by the bus control module 1, stores the amplitude threshold information for the corresponding frequency point, and then sends the amplitude threshold value to the amplitude comparison module 303 according to the frequency point sequence number sent by the Fourier transform module 302. The Fourier transform module 302 performs continuous fast Fourier transform on the original sampled data and sends the transformed spectrum amplitude result and frequency point sequence number to the amplitude comparison module 303. The amplitude comparison module 303 receives the spectrum amplitude result and frequency point sequence number output by the Fourier transform module 302, as well as the amplitude threshold value for the corresponding frequency point output by the threshold storage module 301. If the spectrum amplitude continuously exceeds the threshold value within a set number of iterations, the signal is considered to have appeared; if the spectrum amplitude that has already appeared within the set number of iterations is continuously below the threshold value, the signal is considered to have disappeared. The start time, end time, and signal occurrence channel number of the burst signal are sent to the signal extraction and analysis module 5.

[0041] The function of data delay module 4 is to perform data delay on the sub-channel data output by preprocessing channelization module 2. For example... Figure 4 As shown, the data delay module 4 includes a data writing module 401 and a data reading module 402. The data writing module 401 receives the serial sub-channel data and channel number output by the preprocessing channelization module 2, and stores the sub-channel data into a corresponding data storage stack according to the channel number. The data reading module 402 receives the channelization delay time output by the bus control module 1, reads the data written by the data writing module 401 after multiple cycles according to the channelization delay time, and then sends it to the signal extraction and analysis module 5.

[0042] The function of signal extraction and analysis module 5 is to extract delayed sub-channel data based on the detection results and to analyze the signal. For example... Figure 5 As shown, the signal extraction and analysis module 5 includes a data extraction module 501 and a signal analysis module 502. The data extraction module 501 receives the serial sub-channel data and channel number output by the data delay module 4, as well as the start time, end time, and signal occurrence channel number of the burst signal output by the signal detection module 3. Based on the above information, it extracts the data of the corresponding channel and outputs it to the signal analysis module 502 and simultaneously outputs it to the outside. The signal analysis module 502 receives the extracted data output by the data extraction module 501 and obtains the precise frequency of the signal by performing high-order squared spectrum analysis on the data.

[0043] The above-mentioned device can be implemented using a commercially available FPGA chip, model XC7VSX690T. The bus control module 1, preprocessing channelization module 2, signal detection module 3, data delay module 4, and signal extraction and analysis module 5 can be implemented using the FPGA chip's internal resources such as lookup tables, triggers, digital signal processing units, and embedded memory.

[0044] This device has strong real-time performance and can simultaneously extract and analyze multi-channel burst signals. It is suitable for implementation on a single FPGA, which helps to reduce the size and cost of the device.

Claims

1. A multi-channel burst signal extraction and analysis device based on FPGA, characterized in that: The system includes a bus control module (1), a preprocessing channelization module (2), a signal detection module (3), a data delay module (4), and a signal extraction and analysis module (5) implemented on an FPGA. The FPGA has an LVDS high-speed data bus interface. The bus control module (1) is used to set the burst signal detection threshold, channelization delay time, extract the data transmission address and sub-channel frequency bandwidth, send the data transmission address and sub-channel frequency bandwidth to the preprocessing channelization module (2), send the burst signal detection threshold to the signal detection module (3), and send the channelization delay time to the data delay module (4). The preprocessing channelization module (2) is used to divide the raw sampled data input via the high-speed data bus interface into 2n parallel sub-channel data, n≥1, and then send the sub-channel data and channel number serially into the data delay module (4). The signal detection module (3) is used to perform fast Fourier transform on the raw sampled data input via the high-speed data bus interface, compare the fast Fourier transform result with the burst signal detection threshold, obtain the start time, end time and signal occurrence channel number of the burst signal, and send the result to the signal extraction and analysis module (5). The data delay module (4) is used to delay the serial sub-channel data output by the preprocessing channelization module (2) according to the channelization delay time output by the bus control module (1), and then send the delayed serial sub-channel data and the corresponding channel number to the signal extraction module (5). The signal extraction and analysis module (5) is used to extract and analyze the delayed data output by the data delay module (4) based on the start time, end time and signal occurrence channel number output by the signal detection module (3).

2. The FPGA-based multi-channel burst signal extraction and analysis device according to claim 1, characterized in that: The preprocessing channelization module (2) includes one or more frequency conversion filtering units connected in series. The first frequency conversion filtering unit includes an up-conversion module (201), a down-conversion module (202), and a serial filtering module (203). The k-th frequency conversion filtering unit includes 2(k-2) groups of frequency conversion modules and a serial filtering decimation module (204), where k ≥ 2. Each group of frequency conversion modules includes an up-conversion module (201) and a down-conversion module (202). The output of a frequency conversion module in the preceding frequency conversion filtering unit corresponds to the input of a group of frequency conversion modules in the following frequency conversion filtering unit. The upconversion module (201) performs upconversion on the sampled data, shifting the data to half the negative frequency position; The downconversion module (202) performs a downconversion operation on the sampled data, shifting the data to half the positive frequency. The serial filtering module (203) performs filtering operations on the up- and down-converted data in this frequency conversion filtering unit and outputs the filtered data of the two sub-channels. The serial filtering and extraction module (204) performs filtering and extraction operations on the data after up-conversion and down-conversion in this frequency conversion filtering unit to obtain data from multiple equally spaced sub-channels.

3. The FPGA-based multi-channel burst signal extraction and analysis device according to claim 1, characterized in that: The signal detection module (3) includes a threshold storage module (301), a Fourier transform module (302), and an amplitude comparison module (303); wherein, The threshold storage module (301) receives the burst signal detection threshold information output by the bus control module (1), stores the amplitude threshold information of the corresponding frequency point, and then sends the amplitude threshold value into the amplitude comparison module (303) according to the frequency point sequence number sent by the Fourier transform module (302). The Fourier transform module (302) performs continuous fast Fourier transform on the original sampled data and sends the transformed spectrum amplitude result and frequency point sequence number to the amplitude comparison module (303); The amplitude comparison module (303) receives the spectrum amplitude result and frequency point sequence number output by the Fourier transform module (302) and the amplitude threshold value of the corresponding frequency point output by the threshold storage module (301). If the spectrum amplitude exceeds the threshold value continuously within a set number of times, it is considered that the signal has appeared. If the spectrum amplitude that has appeared within a set number of times is continuously lower than the threshold value, it is considered that the signal has disappeared. The start time, end time and channel number of the burst signal are sent to the signal extraction and analysis module (5).

4. The FPGA-based multi-channel burst signal extraction and analysis device according to claim 1, characterized in that: The data delay module (4) includes a data write module (401) and a data read module (402); wherein, The data writing module (401) receives the serial sub-channel data and channel number output by the preprocessing channelization module (2), and stores the sub-channel data into a corresponding data storage stack according to the channel number; The data read module (402) receives the channelization delay time output by the bus control module (1), reads the data written by the data write module (401) after multiple cycles based on the channelization delay time, and then sends it to the signal extraction and analysis module (5).

5. The FPGA-based multi-channel burst signal extraction and analysis device according to claim 1, characterized in that: The signal extraction and analysis module (5) includes a data extraction module (501) and a signal analysis module (502); wherein, The data extraction module (501) receives the serial sub-channel data and channel number output by the data delay module (4), as well as the start time, end time and signal occurrence channel number of the burst signal output by the signal detection module (3). Based on the above information, it extracts the data of the corresponding channel and outputs it to the signal analysis module (502) and outputs it to the outside at the same time. The signal analysis module (502) receives the extracted data output by the data extraction module (501) and obtains the precise frequency of the signal by performing high-order squared spectrum analysis on the data.

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