A semiconductor structure and a method of fabricating the same

Abstract

Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same. The structure includes a substrate, a semiconductor pillar on the substrate, and a gate pillar above the semiconductor pillar, the semiconductor pillar and the gate pillar both extending in a direction perpendicular to a substrate plane; a first word line extending in a first direction, the first word line surrounding the semiconductor pillar, the first direction being parallel to the substrate plane; and a semiconductor layer above the semiconductor pillar, the semiconductor layer surrounding at least a sidewall of the gate pillar.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for preparing the same. Background Technology

[0002] With technological advancements, semiconductor devices are becoming increasingly smaller, constantly evolving towards miniaturization and higher integration. Dynamic random access memory (DRAM), as a semiconductor device that allows for high-speed, random data writing and reading, is widely used in data storage devices. However, the structure of DRAM still presents many challenges that require improvement. Summary of the Invention

[0003] This disclosure provides a semiconductor structure, including:

[0004] Substrate;

[0005] The semiconductor pillars located on the substrate and the gate pillars located above the semiconductor pillars, both extending in a direction perpendicular to the plane of the substrate;

[0006] A first word line extending along a first direction, the first word line surrounding the semiconductor pillar, the first direction being parallel to the substrate plane;

[0007] A semiconductor layer located above the semiconductor pillar, the semiconductor layer at least surrounding the sidewall of the gate pillar.

[0008] In some embodiments, the gate pillar and the semiconductor pillar correspond one-to-one.

[0009] In some embodiments, the top of the semiconductor pillar is electrically connected to the bottom of the gate pillar.

[0010] In some embodiments, the orthogonal projections of the semiconductor pillar and the gate pillar onto the substrate plane at least partially overlap, and the gate pillar and the semiconductor pillar are made of the same material.

[0011] In some embodiments, the semiconductor pillar includes a first electrode, a first channel region, and a second electrode distributed from bottom to top, and the first electrode, the first channel region, and the second electrode have the same conductivity type.

[0012] In some embodiments, the semiconductor layer includes a first sub-section, a second sub-section, and a third sub-section connected together, the first sub-section covering the top surface of the gate pillar, the second sub-section covering the sidewall of the gate pillar, and the third sub-section partially covering the upper surface of the substrate between adjacent gate pillars.

[0013] In some embodiments, the semiconductor structure further includes:

[0014] A second word line extending along the first direction, the second word line surrounds one end of the second sub-part adjacent to the semiconductor pillar, and covers the upper surface of the third sub-part;

[0015] A first bit line and a second bit line extending along a second direction, the second direction being parallel to the substrate plane and perpendicular to the first direction, the first bit line being located below the semiconductor pillar and electrically connected to the lower part of the semiconductor pillar, and the second bit line being located above the semiconductor layer and electrically connected to the first sub-part.

[0016] In some embodiments, the semiconductor structure further includes:

[0017] A first gate dielectric layer is located between the first word line and the semiconductor pillar, and the first gate dielectric layer surrounds the first channel region and the second electrode;

[0018] The second gate dielectric layer includes a first sublayer and a second sublayer connected together. The first sublayer is located between the gate pillar and the semiconductor layer, covering the sidewalls and top of the gate pillar. The second sublayer covers the upper surface of the substrate between adjacent gate pillars.

[0019] In some embodiments, the semiconductor structure further includes:

[0020] A first gate dielectric layer is located between the first word line and the semiconductor pillar, and the first gate dielectric layer surrounds the first channel region and the second electrode;

[0021] A second gate dielectric layer covers the sidewalls and top of the gate pillar;

[0022] A fourth dielectric layer covers the upper surface of the substrate between adjacent gate pillars.

[0023] In some embodiments, the semiconductor pillar and the semiconductor layer comprise at least one or a combination of indium oxide, tin oxide, In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, In-Ga oxides, In-Ga-Zn oxides, In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, and Sn-Al-Zn oxides.

[0024] In some embodiments, the semiconductor structure further includes a word line isolation structure extending along a first direction, the word line isolation structure being located between any two adjacent first word lines to isolate adjacent first word lines.

[0025] In some embodiments, the semiconductor structure further includes: a first dielectric layer located above the substrate and a second dielectric layer located above the first dielectric layer, wherein the semiconductor pillar and the first word line are located in the first dielectric layer, and the gate pillar, the semiconductor layer and the second word line are located in the second dielectric layer.

[0026] This disclosure also provides a method for fabricating a semiconductor structure, including:

[0027] Provide substrate;

[0028] A pillar is formed on the substrate, the pillar comprising a semiconductor pillar, the pillar extending in a direction perpendicular to the plane of the substrate;

[0029] A first character line is formed extending along a first direction, the first character line surrounding a portion of the pillar, the first direction being parallel to the substrate plane.

[0030] In some embodiments, after forming the first word line, the method further includes:

[0031] A gate pillar is formed directly above the semiconductor pillar, and the gate pillar extends in a direction perpendicular to the substrate plane;

[0032] A semiconductor layer is formed, the semiconductor layer at least surrounding the sidewall of the gate pillar.

[0033] In some embodiments, prior to forming the pillars on the substrate, the method further includes:

[0034] An insulating layer is formed on the substrate;

[0035] An etching process is performed on the insulating layer to form a plurality of first trenches extending along a second direction on the insulating layer, the second direction being parallel to the substrate plane and perpendicular to the first direction;

[0036] Conductive material is filled into a plurality of first trenches to form a plurality of first lines extending along a second direction.

[0037] In some embodiments, after filling a plurality of first trenches with conductive material to form a plurality of first lines extending along a second direction, the method further includes:

[0038] Form the first dielectric layer;

[0039] The first dielectric layer is etched to form a plurality of second trenches extending in a first direction within the first dielectric layer;

[0040] Insulating material is filled into multiple second trenches to form multiple word line isolation structures extending along the first direction.

[0041] In some embodiments, forming pillars on the substrate includes:

[0042] The first dielectric layer is etched to form a plurality of first channel vias, the first channel vias exposing the first bit line;

[0043] The first channel hole is filled with semiconductor material to form the pillar, the pillar comprising a semiconductor pillar;

[0044] Forming a first word line extending along a first direction, the first word line surrounding the semiconductor pillar, the first direction being parallel to the substrate plane, including:

[0045] Multiple third grooves are formed that extend along the first direction and are located between the isolation structures of two adjacent word lines;

[0046] A first gate dielectric layer is formed in the third trench, the first gate dielectric layer surrounding a portion of the semiconductor pillar;

[0047] A first word line is formed within the third trench, and the first word line surrounds a portion of the first gate dielectric layer.

[0048] In some embodiments, a gate pillar is formed directly above the semiconductor pillar, including:

[0049] A second dielectric layer is formed, and the second dielectric layer is etched to form a plurality of second channel holes exposing the top of the semiconductor pillars within the second dielectric layer;

[0050] The gate pillar is formed within the second channel aperture;

[0051] After forming the gate pillar, the method further includes:

[0052] The top surface and sidewalls of the gate pillar are exposed;

[0053] A second gate dielectric layer is deposited, the second gate dielectric layer including portions surrounding the sidewalls and top of the gate pillar, and a portion covering the upper surface of the first dielectric layer;

[0054] A semiconductor material layer and a word line material layer are sequentially formed on the second gate dielectric layer. The semiconductor material layer is conformal to the second gate dielectric layer, and the word line material layer fills the gaps between adjacent semiconductor material layers.

[0055] The semiconductor material layer and the word line material layer are etched to form a semiconductor layer and a plurality of second word lines extending along a first direction, respectively.

[0056] In some embodiments, after forming the semiconductor layer, the method further includes:

[0057] Forming a third dielectric layer;

[0058] The third dielectric layer is etched to form a fourth trench extending along the second direction, and the upper surface of the semiconductor layer is exposed to the fourth trench.

[0059] A second bit line is formed within the fourth trench.

[0060] In some embodiments, forming pillars on the substrate includes:

[0061] A pillar is formed on the substrate, the pillar being higher than the substrate surface and extending in a direction perpendicular to the substrate plane; the pillar includes a semiconductor pillar and a gate pillar, the gate pillar being located directly above the semiconductor pillar;

[0062] After forming the first word line, the method further includes forming a semiconductor layer, the semiconductor layer at least surrounding the sidewall of the gate pillar.

[0063] In some embodiments, prior to forming the pillars on the substrate, the method further includes:

[0064] Multiple first lines extending along the second direction are formed on the substrate;

[0065] Form the first dielectric layer;

[0066] Multiple word line isolation structures extending along a first direction are formed within the first dielectric layer.

[0067] In some embodiments, forming pillars on the substrate includes:

[0068] The first dielectric layer is etched to form a plurality of first channel vias, the first channel vias exposing the first bit line;

[0069] A semiconductor material layer is formed, which covers the upper surface of the first dielectric layer and fills the first channel hole;

[0070] The semiconductor material layer is etched to form the pillar, the portion of the pillar located within the first channel hole is defined as a semiconductor pillar, and the portion of the pillar located directly above the first channel hole is defined as a gate pillar.

[0071] In some embodiments, forming a first letter extending along a first direction includes:

[0072] Multiple third grooves are formed that extend along the first direction and are located between the isolation structures of two adjacent word lines;

[0073] A gate dielectric layer is formed, the gate dielectric layer including a first gate dielectric layer surrounding a portion of the semiconductor pillar, and a second gate dielectric layer surrounding the sidewalls and top of the gate pillar;

[0074] A first word line is formed within the third trench, and the first word line surrounds a portion of the first gate dielectric layer.

[0075] In some embodiments, after forming the first letter line, the method further includes:

[0076] A semiconductor material layer and a word line material layer are sequentially formed on the second gate dielectric layer, wherein the semiconductor material layer at least covers the second gate dielectric layer, and the word line material layer fills the gaps between adjacent semiconductor material layers.

[0077] The semiconductor material layer and the word line material layer are etched to remove a portion of the semiconductor material layer and the word line material layer located above the word line isolation structure, so as to form a semiconductor layer and a plurality of second word lines extending along a first direction.

[0078] The semiconductor structure and its fabrication method provided in this disclosure include: a substrate; semiconductor pillars on the substrate and a gate pillar above the semiconductor pillars, both extending in a direction perpendicular to the substrate plane; a first word line extending in a first direction, surrounding the semiconductor pillars, the first direction being parallel to the substrate plane; and a semiconductor layer above the semiconductor pillars, the semiconductor layer at least surrounding the sidewalls of the gate pillars. Thus, the semiconductor pillars at the bottom and the semiconductor layer above them are vertically distributed. When a transistor structure is subsequently formed on the semiconductor pillars and semiconductor layer, the area occupied by the projection of two transistors on the substrate can be significantly reduced. Compared with the method of two transistors being laid flat on the substrate, this disclosure embodiment can effectively improve the integration density of the semiconductor structure.

[0079] Details of one or more embodiments of this disclosure will be set forth in the following drawings and description. Other features and advantages of this disclosure will become apparent from the specification, drawings, and claims. Attached Figure Description

[0080] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0081] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure;

[0082] Figure 2 A schematic diagram of another structure of the semiconductor structure provided in this embodiment of the disclosure;

[0083] Figure 3 A schematic diagram of yet another semiconductor structure provided in an embodiment of this disclosure;

[0084] Figure 4 A flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0085] Figures 5 to 22 A process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0086] Figure 23 A schematic diagram of another structure of the semiconductor structure provided in this embodiment of the disclosure;

[0087] Figures 24 to 29 A process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure. Detailed Implementation

[0088] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0089] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0090] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0091] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0092] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0093] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0094] Currently, common dynamic random access memories (DRAMs) typically consist of a single transistor and a capacitor (1T1C) forming a memory cell, with the capacitor used to store data. However, 1T1C DRAMs have high requirements for the amount of charge the capacitor can store, and reading from the capacitor is destructive, requiring rewriting after the read operation, increasing power consumption. Furthermore, the complex manufacturing process and large size of the capacitor make miniaturization a challenge.

[0095] Therefore, engineers developed dual-transistor capacitor-free (2T0C) dynamic random access memory, which typically consists of a read transistor and a write transistor in a single memory structure. However, the structure of dual-transistor capacitor-free (2T0C) dynamic random access memory also presents many problems that need to be solved.

[0096] Based on this, the following technical solutions are proposed for embodiments of this disclosure:

[0097] This disclosure provides a semiconductor structure, which includes:

[0098] Substrate;

[0099] Semiconductor pillars located on the substrate and gate pillars located above the semiconductor pillars, both extending in a direction perpendicular to the substrate plane;

[0100] A first word line extending along a first direction, the first word line surrounding a semiconductor pillar, the first direction being parallel to the substrate plane;

[0101] A semiconductor layer located above the semiconductor pillar, the semiconductor layer at least surrounding the sidewalls of the gate pillar.

[0102] In this embodiment, the semiconductor pillar at the bottom and the semiconductor layer above it are arranged vertically. When a transistor structure is subsequently formed on the semiconductor pillar and the semiconductor layer, the area occupied by the projection of the two transistors on the substrate can be significantly reduced. Compared with the method of laying the two transistors flat on the substrate, this embodiment can effectively improve the integration of the semiconductor structure.

[0103] To make the above-mentioned objects, features, and advantages of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. In describing the embodiments of this disclosure in detail, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and the schematic diagrams are merely examples and should not limit the scope of protection of this disclosure.

[0104] Figure 1 A schematic diagram of a semiconductor structure provided in an embodiment of this disclosure; Figure 2 A schematic diagram of another structure of the semiconductor structure provided in this embodiment of the disclosure; Figure 3This is a schematic diagram of yet another semiconductor structure provided in the embodiments of this disclosure.

[0105] The semiconductor structure provided in the embodiments of this disclosure will be further described in detail below with reference to the accompanying drawings.

[0106] like Figure 1 , Figure 2 and Figure 3 As shown, the semiconductor structure includes:

[0107] Substrate 10;

[0108] Semiconductor pillar 13 located on substrate 10 and gate pillar 18 located above semiconductor pillar 13, both semiconductor pillar 13 and gate pillar 18 extend in a direction perpendicular to the plane of substrate 10;

[0109] A first word line WL1 extends along a first direction, and the first word line WL1 surrounds the semiconductor pillar 13. The first direction is parallel to the plane of the substrate 10.

[0110] A semiconductor layer 16 is located above the semiconductor pillar 13, and the semiconductor layer 16 at least surrounds the sidewall of the gate pillar 18.

[0111] In some embodiments, the gate pillar 18 and the semiconductor pillar 13 correspond one-to-one.

[0112] Here, the substrate can be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate.

[0113] In some embodiments, the semiconductor pillar 13 and the semiconductor layer 16 include at least one or a combination of indium oxide, tin oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, and Sn-Al-Zn oxide.

[0114] However, the materials for the semiconductor pillars and semiconductor layers can also include In-Hf-Zn oxides, In-La-Zn oxides, In-Ce-Zn oxides, In-Pr-Zn oxides, In-Nd-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, and In-Lu-Zn ​​oxides; as well as quaternary metal oxides such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, and In-Hf-Al-Zn oxides.

[0115] In some embodiments, the materials used as semiconductor pillars and semiconductor layers may be selected to contain at least indium (In) or zinc (Zn). Materials containing both indium (In) and zinc (Zn) are particularly preferred. In addition to the elements mentioned above, materials may also contain the stabilizer element gallium (Ga), which can reduce electrical characteristic deviations in the final formed transistor.

[0116] Optionally, the materials for the semiconductor pillars and semiconductor layers include, but are not limited to, indium gallium zinc oxide (IGZO), such as materials with the chemical formula InGaZnO4.

[0117] In one specific embodiment, the materials of the semiconductor pillars and the semiconductor layer include In x Ga y Zn 1-x-y O, where x is greater than or equal to 0 or less than or equal to 1, and y is greater than or equal to 0 or less than or equal to 1.

[0118] Understandably, in practice, a portion of the semiconductor pillar can be used as the channel region, and the semiconductor layer can be used as the channel region, and transistor structures for write operations and read operations can be formed on this basis respectively.

[0119] In some embodiments, when oxide semiconductor materials are used as the materials for semiconductor pillars and semiconductor layers, that is, when oxide semiconductor materials are used as the channel regions of transistor structures for writing and transistor structures for reading, the higher carrier mobility and lower leakage current of oxide semiconductor materials can effectively reduce the leakage current of the two transistor structures, improve the on / off current ratio and current driveability of the two transistor structures, improve the access speed of the semiconductor structure, and reduce power consumption.

[0120] Understandably, in a dual-transistor capacitor-free (2T0C) dynamic random access memory structure, a transistor structure based on a semiconductor pillar can be used as a write transistor of the semiconductor structure, while a transistor structure based on a semiconductor layer can be used as a read transistor of the semiconductor structure. A write transistor and a read transistor together form a memory cell to realize the information reading operation.

[0121] Compared with semiconductor structures with capacitors, the structure provided in this disclosure does not require additional capacitor manufacturing, has a simple process, and does not require rewriting after reading, thus reducing power consumption.

[0122] In some embodiments, the semiconductor pillar 13 includes a first electrode 131, a first channel region 132, and a second electrode 133 distributed from bottom to top, and the first electrode 131, the first channel region 132, and the second electrode 132 have the same conductivity type.

[0123] When the semiconductor pillar is made of indium gallium zinc oxide (IGZO), not only can the leakage current of the write transistor structure be effectively reduced, but also the floating body effect in the write transistor structure can be effectively prevented because the first electrode, the first channel region and the second electrode have the same conductivity type.

[0124] Here, the first electrode 131, the first channel region 132, and the second electrode 133 can be used as the first source / drain region, the channel region, and the second source / drain region of the write transistor, respectively.

[0125] In some embodiments, the semiconductor layer 16 includes a first sub-part 161, a second sub-part 162, and a third sub-part 163 connected together. The first sub-part 161 covers the top surface of the gate pillar 18, the second sub-part 162 covers the sidewall of the gate pillar 18, and the third sub-part 163 partially covers the upper surface of the substrate 10 between adjacent gate pillars 18.

[0126] Here, the semiconductor layer can be used as the channel region of the read transistor, and because the second sub-part of the semiconductor layer covers (surrounds) the sidewall of the gate pillar, the channel region of the read transistor has a larger channel size. Compared with the structure in which the channel region is only provided on one side of the gate, the structure provided by the embodiments of this disclosure can effectively prevent the occurrence of short-channel effect.

[0127] Continue to refer to Figure 1 and Figure 2 As can be seen, in some embodiments, the semiconductor structure further includes:

[0128] The first gate dielectric layer 14 is located between the first word line WL1 and the semiconductor pillar 13, and the first gate dielectric layer 14 surrounds the first channel region 132 and the second electrode 133.

[0129] The second gate dielectric layer 15 includes a first sublayer 151 and a second sublayer 152 connected together. The first sublayer 151 is located between the gate pillar 18 and the semiconductor layer 16, covering the sidewalls and top of the gate pillar 18. The second sublayer 152 covers the upper surface of the substrate 10 between adjacent gate pillars 18.

[0130] Continue to refer to Figure 3 As can be seen, in some other embodiments, the semiconductor structure further includes:

[0131] The first gate dielectric layer 14 is located between the first word line WL1 and the semiconductor pillar 13, and the first gate dielectric layer 14 surrounds the first channel region 132 and the second electrode 133.

[0132] The second gate dielectric layer 15 covers the sidewalls and top of the gate pillar 18;

[0133] The fourth dielectric layer L4 covers the upper surface of the substrate 10 between adjacent gate pillars 18.

[0134] In practice, the materials of the first gate dielectric layer and the second gate dielectric layer include, but are not limited to, oxides, nitrides, oxynitrides, and other insulating materials. In some specific embodiments, the materials of the first gate dielectric layer and the second gate dielectric layer can be one or a combination of aluminum oxide, silicon oxide, silicon nitride, etc.

[0135] The formation processes of the first gate dielectric layer and the second gate dielectric layer include, but are not limited to, atomic layer deposition processes.

[0136] Since the second gate dielectric layer includes a portion of the upper surface of the substrate covering the space between adjacent gate pillars, an electrical isolation effect can be achieved between the structure located at the lower part and around the semiconductor pillar and the structure located at the upper part and around the gate pillar, preventing mutual interference between the structures.

[0137] In some embodiments, the semiconductor structure further includes:

[0138] The second word line WL2 extends along the first direction, surrounds one end of the second sub-part 162 adjacent to the semiconductor pillar 13, and covers the upper surface of the third sub-part 163;

[0139] The first bit line BL1 and the second bit line BL2 extend along the second direction, which is parallel to the plane of the substrate 10 and perpendicular to the first direction. The first bit line BL1 is located below the semiconductor pillar 13 and is electrically connected to the lower part of the semiconductor pillar 13. The second bit line BL2 is located above the semiconductor layer 16 and is electrically connected to the first sub-part 161.

[0140] Here, the second word line can be used as the source or drain region of the read transistor, and the second bit line can be used as the drain or source region of the read transistor. In some embodiments, the second word line is used as the source region of the read transistor, and the second bit line is used as the drain region of the read transistor. However, this is not a limitation; in some other embodiments, the second word line can be used as the drain region of the read transistor, and the second bit line can be used as the source region of the read transistor. No specific limitation is made here.

[0141] In this embodiment, since the second word line surrounds the second sub-section of the semiconductor layer that serves as the channel region, the contact area between the second word line and the channel region is increased, which helps to reduce the contact resistance between the second word line and the channel region, thereby reducing the power consumption of the read transistor.

[0142] In practice, the first word line can be electrically connected to the first electrode of the semiconductor pillar. When a suitable voltage is applied to the first word line, the write transistor is turned on. At this time, by applying a suitable voltage to the first word line, charge can be injected through the semiconductor pillar into the gate (i.e., the gate pillar) of the read transistor. The change in the amount of charge contained in the gate (i.e., the gate pillar) can affect the resistance state of the read transistor, thereby realizing the distinction between "0" and "1" in actual operation.

[0143] Here, the gate of the read transistor is used as the node for information storage, thus eliminating the need for a separate capacitor structure.

[0144] Since the charge in the writing transistor needs to be injected into the gate pillar of the reading transistor through the semiconductor pillar during this process, the relative position, connection relationship, and material properties between the semiconductor pillar and the gate pillar will affect the charge transfer speed and efficiency.

[0145] In one embodiment of this disclosure, such as Figure 1 As shown, the top of the semiconductor pillar 13 is electrically connected to the bottom of the gate pillar 18.

[0146] Here, the material of the semiconductor pillar can be an oxide semiconductor material, and the material of the gate pillar can be one or more of the following, including but not limited to tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy.

[0147] In this embodiment, the top of the second electrode of the semiconductor pillar is directly electrically connected to the bottom of the gate pillar, meaning that a source / drain region of the write transistor and the gate of the read transistor are directly electrically connected without the aid of other conductive lines. Compared to the conventional structure where a source / drain region of the write transistor and the gate of the read transistor are electrically connected via interconnects, this embodiment effectively shortens the charge flow path when the write transistor injects charge into the gate of the read transistor, thereby effectively improving the information transmission speed and efficiency of the semiconductor structure.

[0148] In another embodiment of this disclosure, such as Figure 2 As shown, the orthographic projections of the semiconductor pillar and the gate pillar on the substrate plane at least partially overlap, and the gate pillar and the semiconductor pillar are made of the same material.

[0149] In this embodiment, the orthogonal projections of the semiconductor pillar and the gate pillar on the substrate plane at least partially overlap, that is, the orthogonal projections of the write transistor and the read transistor on the substrate plane at least partially overlap, thereby making the memory cell structure consisting of one write transistor and one read transistor occupy less substrate surface area. This means that on a substrate of the same planar size, the semiconductor structure provided in this embodiment can form a larger number of memory cells, that is, the semiconductor structure in this embodiment can have a higher integration density.

[0150] It is understandable that when the orthogonal projections of the semiconductor pillar and the gate pillar on the substrate plane completely overlap, that is, when the orthogonal projections of the write transistor and the read transistor on the substrate plane completely overlap, the semiconductor structure provided in this embodiment can form a better number of memory cells, that is, the semiconductor structure in this embodiment can have better integration.

[0151] Furthermore, compared to conventional structures where a source / drain region of the write transistor uses a semiconductor material and the gate of the read transistor uses a metal material, in this embodiment, the gate pillar and the semiconductor pillar are made of the same material. That is, a source / drain region of the write transistor and the gate of the read transistor have the same material. This eliminates the need to worry about increased contact resistance caused by the metal-induced gap state effect between the metal and semiconductor materials when the source / drain region of the write transistor is electrically connected to the gate of the read transistor. This effectively reduces the overall power consumption of the semiconductor structure.

[0152] Understandably, the materials for the semiconductor pillars and gate pillars may include at least one or a combination of indium oxide, tin oxide, In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, In-Ga oxides, In-Ga-Zn oxides, In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, and Sn-Al-Zn oxides.

[0153] In some embodiments, both the semiconductor pillar and the gate pillar can be made of oxide semiconductor materials, such as InGaZnO4.

[0154] In one specific embodiment, the materials of the semiconductor pillars and gate pillars include In x Ga y Zn 1-x-y O, where x is greater than or equal to 0 or less than or equal to 1, and y is greater than or equal to 0 or less than or equal to 1.

[0155] In yet another embodiment of this disclosure, such as Figure 3 As shown, the gate pillar 18 and the semiconductor pillar 13 are directly electrically connected.

[0156] In this embodiment, the gate pillar and the semiconductor pillar are a single, directly electrically connected structure. That is, the channel region and source / drain region of the write transistor are integrated with the gate of the read transistor. This means that a source / drain region of the write transistor and the gate of the read transistor can be directly electrically connected without the aid of other conductive lines. Compared to conventional structures where the two are electrically connected via interconnects, this embodiment effectively shortens the charge flow path when the write transistor injects charge into the gate of the read transistor, thereby effectively improving the information transmission speed and efficiency of the semiconductor structure. Furthermore, when the write transistor needs to inject charge into the gate of the read transistor through its source / drain region, the absence of contact resistance due to the integrated structure effectively prevents the semiconductor structure from generating excessive heat during use, thus effectively improving the performance of the semiconductor structure.

[0157] In addition, in actual processes, the structure consisting of gate pillars and semiconductor pillars can be formed in the same process step, which significantly reduces the complexity of the process and is conducive to improving production efficiency.

[0158] In some embodiments, such as Figure 1 and Figure 2 As shown, the semiconductor structure also includes: a first dielectric layer L1 located above the substrate 10 and a second dielectric layer L2 located above the first dielectric layer L1, the semiconductor pillar 13 and the first word line WL1 located in the first dielectric layer L1, and the gate pillar 18, the semiconductor layer 16 and the second word line WL2 located in the second dielectric layer L2.

[0159] Optionally, the semiconductor structure further includes a word line isolation structure 12 extending along a first direction, the word line isolation structure 12 being located between any two adjacent first word lines WL1 to isolate adjacent first word lines WL1.

[0160] In this embodiment, the word line isolation structure is located within the first dielectric layer. The material of the word line isolation structure may include, but is not limited to, oxides, nitrides, oxynitrides, etc., specifically, at least one or a combination of silicon oxide, silicon nitride, silicon oxynitride, etc.

[0161] This disclosure also provides a method for fabricating a semiconductor structure, such as... Figure 4 As shown, the method includes the following steps:

[0162] Step S101: Provide a substrate;

[0163] Step S102: Form pillars on the substrate, the pillars including semiconductor pillars, the pillars extending in a direction perpendicular to the plane of the substrate;

[0164] Step S103: Form a first character line extending along a first direction, the first character line surrounding a portion of the pillar, the first direction being parallel to the substrate plane.

[0165] The method for fabricating the semiconductor structure provided in the embodiments of this disclosure will be further described below with reference to the accompanying drawings.

[0166] Figures 5 to 22 A process flow diagram of a method for fabricating a semiconductor structure according to an embodiment of this disclosure; Figure 23 This is a schematic diagram of another structure of the semiconductor structure provided in the embodiments of this disclosure.

[0167] First, execute step S101, as follows: Figure 5 As shown, a substrate is provided.

[0168] Here, the substrate can be a semiconductor substrate; specifically, it includes at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one specific embodiment, the substrate is a silicon substrate.

[0169] Next, proceed to step S102, as follows: Figure 10 As shown, pillars are formed on the substrate, the pillars including semiconductor pillars, and the pillars extend in a direction perpendicular to the plane of the substrate.

[0170] In some embodiments, such as Figure 6 As shown, before forming the semiconductor pillar 13 on the substrate 10, the method further includes:

[0171] An insulating layer 11 is formed on the substrate 10;

[0172] An etching process is performed on the insulating layer 11 to form a plurality of first trenches T1 extending along a second direction on the insulating layer 11, the second direction being parallel to the plane of the substrate 10 and perpendicular to the first direction;

[0173] Conductive material is filled into multiple first trenches T1 to form multiple first lines BL1 extending along a second direction.

[0174] Here, the materials of the insulating layer include, but are not limited to, oxides, nitrides, and oxynitrides. In some specific embodiments, the materials of the insulating layer may include, but are not limited to, silicon oxide.

[0175] In practice, the insulating layer and conductive material can be formed using one or more thin film deposition processes; specifically, thin film deposition processes include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or combinations thereof.

[0176] In some embodiments, such as Figure 7 and Figure 8 As shown, after filling a plurality of first trenches T1 with conductive material to form a plurality of first lines BL1 extending along the second direction, the method further includes:

[0177] Form the first dielectric layer L1;

[0178] The first dielectric layer L1 is etched to form a plurality of second trenches T2 extending along a first direction within the first dielectric layer L1;

[0179] Insulating material is filled into multiple second trenches T2 to form multiple word line isolation structures 12 extending along the first direction.

[0180] Here, the material of the first dielectric layer includes, but is not limited to, one or a combination of oxides, nitrides, oxynitrides, and other insulating materials. Specifically, the material of the first dielectric layer may include, but is not limited to, silicon oxide and silicon nitride.

[0181] Furthermore, the process for forming the first dielectric layer can be the same as or different from the process for forming the insulating layer; no specific limitations are made here.

[0182] In some embodiments, such as Figures 9 to 10 As shown, a pillar P is formed on the substrate, including:

[0183] The first dielectric layer L1 is etched to form a plurality of first channel holes H1, the first channel holes H1 exposing the first bit line BL1;

[0184] Semiconductor material is filled into the first channel hole H1 to form a pillar P, the pillar including a semiconductor pillar 13.

[0185] In actual process, the first dielectric layer L1 can be etched from top to bottom to form multiple first channel holes H1. The multiple first channel holes H1 are located in the first dielectric layer L1 between two adjacent word line isolation structures 12.

[0186] In some embodiments, the semiconductor pillar 13 may include a first electrode 131, a first channel region 132, and a second electrode 133 distributed from bottom to top, and the first electrode 131, the first channel region 132, and the second electrode 133 have the same conductivity type. It is understood that the first electrode 131, the first channel region 132, and the second electrode 133 may be used as the first source / drain region, the channel region, and the second source / drain region of a transistor, respectively.

[0187] In this embodiment, the material of the semiconductor pillar includes at least one or a combination of indium oxide, tin oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, and Sn-Al-Zn oxide.

[0188] Optionally, the semiconductor pillar material includes, but is not limited to, indium gallium zinc oxide (IGZO), such as materials with the chemical formula InGaZnO4.

[0189] In one specific embodiment, the material of the semiconductor pillar includes In x Ga y Zn 1-x-y O, where x is greater than or equal to 0 or less than or equal to 1, and y is greater than or equal to 0 or less than or equal to 1.

[0190] Understandably, in practice, a transistor structure based on the semiconductor pillar can be formed by subsequently creating control gate lines, such as word lines, on part of the sidewalls of the semiconductor pillar to control the conduction or shutdown of the channel region. When the semiconductor pillar material is indium gallium zinc oxide (IGZO), that is, when the channel region of the transistor structure is made of indium gallium zinc oxide (IGZO), not only can the leakage current of the transistor structure be effectively reduced, but also, because the first electrode, the first channel region, and the second electrode have the same conductivity type, the floating body effect in the transistor structure can be effectively prevented.

[0191] Understandably, in this embodiment, the transistor structure formed based on semiconductor pillars can be used as a write transistor for memory.

[0192] Finally, proceed with step S103, as follows: Figure 11 and Figure 12 As shown, a first word line WL1 is formed extending along a first direction, the first word line WL1 surrounds a portion of the pillar P, and the first direction is parallel to the substrate plane.

[0193] In some embodiments, a first word line WL1 is formed extending along a first direction, the first word line WL1 surrounding the semiconductor pillar 13, the first direction being parallel to the plane of the substrate 10, including:

[0194] Multiple third grooves T3 are formed, extending along the first direction and located between two adjacent word line isolation structures 12;

[0195] A first gate dielectric layer 14 is formed in the third trench T3, and the first gate dielectric layer 14 surrounds a portion of the semiconductor pillar 13;

[0196] A first word line WL1 is formed in the third trench T3, and the first word line WL1 surrounds a portion of the first gate dielectric layer 14.

[0197] In some specific embodiments, forming a third trench T3 includes:

[0198] A portion of the first dielectric layer L1 is removed to form a plurality of third trenches T3 extending along the first direction and located between two adjacent word line isolation structures 12, the bottom of the third trenches T3 being flush with the upper surface of the first electrode 131.

[0199] Understandably, in actual operation, the first gate dielectric layer 14 surrounds the sidewalls of the first channel region 132 and the second electrode 133 in the semiconductor pillar 13, and the upper surface of the first word line WL1 is flush with the upper surface of the first channel region 132.

[0200] In some embodiments, such as Figure 13 As shown, after forming the first character line WL1, the method further includes:

[0201] The first dielectric layer L1 is continued to be filled in the gap between the first word line WL1 and the semiconductor pillar 13, so that the top surface of the first dielectric layer L1 is flush with the upper surface of the second electrode 133 of the semiconductor pillar.

[0202] Thus, multiple transistor structures have been formed within the first dielectric layer. Understandably, these multiple transistor structures can be used as write transistors for memory.

[0203] In some embodiments, such as Figures 16 to 20As shown, after forming the first word line WL1, the method further includes: forming a gate pillar 18 directly above the semiconductor pillar 13, the gate pillar 18 extending in a direction perpendicular to the plane of the substrate 10;

[0204] A semiconductor layer 16 is formed, the semiconductor layer 16 at least surrounding the sidewall of the gate pillar 18.

[0205] In some embodiments, such as Figures 14 to 20 As shown, a gate pillar 18 is formed directly above the semiconductor pillar 13, including:

[0206] A second dielectric layer L2 is formed, and the second dielectric layer L2 is etched to form a plurality of second channel holes H2 that expose the top of the semiconductor pillar 13 within the second dielectric layer L2;

[0207] A gate pillar 18 is formed within the second channel hole H2;

[0208] After forming the gate pillar 18, the method further includes:

[0209] The top surface and sidewalls of the gate pillar 18 are exposed;

[0210] A second gate dielectric layer 15 is deposited, the second gate dielectric layer 15 including portions surrounding the sidewalls and top of the gate pillar 18, and a portion covering the upper surface of the first dielectric layer L1;

[0211] A semiconductor material layer 16a and a word line material layer WL2a are sequentially formed on the second gate dielectric layer 15. The semiconductor material layer 16a is conformally formed with the second gate dielectric layer 15, and the word line material layer WL2a fills the gaps between adjacent semiconductor layers 16a.

[0212] The semiconductor material layer 16a and the word line material layer WL2a are etched to form the semiconductor layer 16 and multiple second word lines WL2 extending along the first direction, respectively.

[0213] In actual operation, after the gate pillar 18 is formed in the second channel hole H2, the top surface and sidewalls of the gate pillar 18 can be exposed by removing the second dielectric layer L2. In subsequent processes, after the semiconductor material layer 16a and the word line material layer WL2a are sequentially formed on the second gate dielectric layer 15, the semiconductor layer 16 and multiple second word lines WL2 extending along the first direction can be formed by removing a portion of the semiconductor material layer 16a and the word line material layer WL2a located above the word line isolation structure 12.

[0214] Here, the material of the gate pillar may be one or more of the following, including but not limited to tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), metal silicide, and metal alloy.

[0215] In practice, the materials of the first gate dielectric layer and the second gate dielectric layer can be the same or different. Optionally, the materials of the first gate dielectric layer and the second gate dielectric layer include, but are not limited to, oxides, nitrides, oxynitrides, and other insulating materials. In some specific embodiments, the materials of the first gate dielectric layer and the second gate dielectric layer can be one or a combination of alumina, silicon oxide, and silicon nitride.

[0216] The formation processes of the first gate dielectric layer and the second gate dielectric layer include, but are not limited to, atomic layer deposition processes.

[0217] In this embodiment, since the second gate dielectric layer includes a portion covering the upper surface of the first dielectric layer and word line isolation structure between adjacent gate pillars, the structure located at the lower part and around the semiconductor pillars can form an electrical isolation effect with the structure located at the upper part and around the gate pillars, preventing mutual interference between the structures.

[0218] Optionally, in some embodiments, such as Figure 19 As shown, after depositing the semiconductor material layer 16a and before forming the word line material layer WL2a, the method may further include:

[0219] The semiconductor material layer 16a is etched along the second direction to remove a portion of the semiconductor material layer 16a located between the gate pillars 18, so as to form a plurality of gaps extending along the second direction between the gate pillars 18.

[0220] The voids are filled with a fifth dielectric layer, L5.

[0221] In this way, by performing two etching processes on the semiconductor material layer, the semiconductor layers located around each gate pillar can be made independent of each other. Even if other material layers are subsequently formed on the semiconductor layer to form the transistor structure, the final transistor structure can maintain its independence.

[0222] In some embodiments, such as Figure 20 and Figure 21 As shown, after forming the semiconductor layer 16, the method further includes:

[0223] Forming a third dielectric layer L3;

[0224] The third dielectric layer L3 is etched to form a fourth trench T4 extending along the second direction, and the upper surface of the semiconductor layer 16 is exposed to the fourth trench T4.

[0225] The second bit line BL2 is formed within the fourth trench T4.

[0226] Thus, multiple transistor structures are formed within the second dielectric layer. The gate pillar can be used as the gate of the transistor structure, the semiconductor layer can be used as the channel region of the transistor structure, the second word line can be used as the source or drain region of the read transistor, and the second bit line can be used as the drain or source region of the transistor structure.

[0227] It should be noted that when the second word line is used as the source region of the transistor structure, the second bit line is used as the drain region of the transistor structure. However, this is not the only possibility. In some other embodiments, the second word line can also be used as the drain region of the read transistor, while the second bit line is used as the source region of the read transistor. In practice, this can be flexibly adjusted, and no specific restrictions are imposed here.

[0228] In this embodiment, since the second word line surrounds part of the semiconductor layer that serves as the channel region, the contact area between the second word line and the channel region is increased, which helps to reduce the contact resistance between the second word line and the channel region, thereby reducing the power consumption of the transistor structure.

[0229] Understandably, this multi-transistor structure can be used as a read transistor for memory.

[0230] Understandably, in this embodiment, the top of the second electrode of the semiconductor pillar is directly electrically connected to the bottom of the gate pillar, meaning that a source / drain region of the write transistor and the gate of the read transistor are directly electrically connected without the aid of other conductive lines. Compared to the conventional structure where a source / drain region of the write transistor and the gate of the read transistor are electrically connected via interconnects, this embodiment effectively shortens the charge flow path when the write transistor injects charge into the gate of the read transistor, thereby effectively improving the information transmission speed and efficiency of the semiconductor structure.

[0231] Optional, such as Figure 22 As shown, after forming the second bit line BL2, the method further includes forming an insulating layer 17 on the second bit line BL2, the insulating layer 17 being used to protect the second bit line BL2.

[0232] like Figure 23 As shown, this disclosure also provides another semiconductor structure, the fabrication process of which is similar to... Figures 5 to 22 The fabrication process of the semiconductor structure provided is basically the same. The difference lies in the material arrangement between the gate pillar and the semiconductor pillar, which is different from the previous embodiment.

[0233] In this embodiment, the materials of the semiconductor pillar and the gate pillar include at least one or a combination of indium oxide, tin oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, and Sn-Al-Zn oxide.

[0234] Optionally, the gate pillar and the semiconductor pillar can be made of the same material. In some embodiments, both the semiconductor pillar and the gate pillar can be made of oxide semiconductor materials, such as InGaZnO4.

[0235] Understandably, in this embodiment, the transistor structure formed based on the semiconductor pillar can be used as a write transistor of the semiconductor structure, while the transistor structure formed based on the semiconductor layer can be used as a read transistor of the semiconductor structure. A write transistor and a read transistor together form a storage unit for implementing information reading operations.

[0236] Compared with semiconductor structures with capacitors, the structure provided in this disclosure does not require additional capacitor manufacturing, has a simple process, and does not require rewriting after reading, thus reducing power consumption.

[0237] In addition, in this embodiment, the orthogonal projections of the semiconductor pillar and the gate pillar on the substrate plane at least partially overlap, that is, the orthogonal projections of the write transistor and the read transistor on the substrate plane at least partially overlap, thereby making the memory cell structure composed of a write transistor and a read transistor occupy less substrate surface area. This means that on a substrate of the same planar size, the semiconductor structure provided by this disclosure embodiment can form a larger number of memory cells, that is, the semiconductor structure of this disclosure embodiment can have a higher integration.

[0238] It is understandable that when the orthogonal projections of the semiconductor pillar and the gate pillar on the substrate plane completely overlap, that is, when the orthogonal projections of the write transistor and the read transistor on the substrate plane completely overlap, the semiconductor structure provided in this embodiment can form a better number of memory cells, that is, the semiconductor structure in this embodiment can have better integration.

[0239] Furthermore, compared to conventional structures where a source / drain region of the write transistor uses a semiconductor material and the gate of the read transistor uses a metal material, in this embodiment, the gate pillar and the semiconductor pillar are made of the same material. That is, a source / drain region of the write transistor and the gate of the read transistor have the same material. This eliminates the need to worry about increased contact resistance caused by the gate-induced gap state effect between the metal and semiconductor materials when the source / drain region of the write transistor is electrically connected to the gate of the read transistor. This effectively reduces the overall power consumption of the semiconductor structure.

[0240] In addition to the methods described in the embodiments above, other methods can be used to obtain a semiconductor structure for information processing purposes in another embodiment of this disclosure. Unlike the previous embodiment, in this embodiment, the pillar comprises two parts: a semiconductor pillar and a gate pillar, and both parts are formed in the same process step.

[0241] Figures 24 to 29 A process flow diagram of a method for fabricating a semiconductor structure according to another embodiment of this disclosure.

[0242] The following description, with reference to the accompanying drawings, details a method for fabricating a semiconductor structure according to another embodiment of the present disclosure.

[0243] In this embodiment, the substrate material can be the same as or different from that in the previous embodiment; no specific limitations are imposed.

[0244] First, such as Figures 24 to 25 As shown, a pillar P is formed on the substrate 10, including:

[0245] A pillar P is formed on the substrate 10. The pillar P is higher than the surface of the substrate 10 and extends in a direction perpendicular to the plane of the substrate 10. The pillar P includes a semiconductor pillar 13 and a gate pillar 18, with the gate pillar 18 located directly above the semiconductor pillar 13.

[0246] In actual processes, such as Figures 6 to 8 As shown, before forming the pillar P on the substrate 10, the method further includes:

[0247] Multiple first lines BL1 extending along the second direction are formed on the substrate 10;

[0248] Form the first dielectric layer L1;

[0249] Multiple word line isolation structures 12 extending along a first direction are formed within the first dielectric layer L1.

[0250] In some embodiments, such as Figure 9 , Figures 24 to 25 As shown, a pillar P is formed on the substrate 10, including:

[0251] The first dielectric layer L1 is etched to form a plurality of first channel holes H1, the first channel holes H1 exposing the first bit line BL1;

[0252] A semiconductor material layer 16a is formed, which covers the upper surface of the first dielectric layer L1 and fills the first channel hole H1.

[0253] The semiconductor material layer 16a is etched to form a pillar P. The portion of the pillar P located inside the first channel hole H1 is defined as a semiconductor pillar 13, and the portion of the pillar P located directly above the first channel hole H1 is defined as a gate pillar 18.

[0254] In actual process, the first dielectric layer L1 can be etched from top to bottom to form multiple first channel holes H1. The multiple first channel holes H1 are located in the first dielectric layer L1 between two adjacent word line isolation structures 12.

[0255] Optionally, in some embodiments, etching the semiconductor material layer 16a to form the pillar P includes:

[0256] The semiconductor material layer 16a is etched to remove the semiconductor material layer 16a outside the area defined by the orthogonal projection of the first channel hole H1 on the substrate 10. The semiconductor material layer 16a remaining in the first channel hole H1 and the semiconductor material layer 16a located directly above the first channel hole H1 constitute the pillar P.

[0257] In this embodiment, the semiconductor material layer comprises at least one or a combination of indium oxide, tin oxide, In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, and Sn-Al-Zn oxide.

[0258] Optionally, the semiconductor material layer may be made of materials including, but not limited to, indium gallium zinc oxide (IGZO), such as materials with the chemical formula InGaZnO4.

[0259] In one specific embodiment, the material of the semiconductor material layer includes In x Ga y Zn 1-x-y O, where x is greater than or equal to 0 or less than or equal to 1, and y is greater than or equal to 0 or less than or equal to 1.

[0260] In this embodiment, the semiconductor pillar 13 located in the first channel hole H1 may include a first electrode 131, a first channel region 132 and a second electrode 133 distributed from bottom to top, and the first electrode 131, the first channel region 132 and the second electrode 133 have the same conductivity type.

[0261] Understandably, in actual operation, the first electrode 131, the first channel region 132, and the second electrode 133 in the semiconductor pillar 13 can be used as the first source / drain region, the channel region, and the second source / drain region of the transistor, respectively.

[0262] In practice, a transistor structure based on the semiconductor pillar can be formed by subsequently creating control gate lines, such as word lines, on part of the sidewalls of the semiconductor pillar to control the conduction or shutdown of the channel region. When the semiconductor pillar material is indium gallium zinc oxide (IGZO), that is, when the channel region of the transistor structure is made of indium gallium zinc oxide (IGZO), not only can the leakage current of the transistor structure be effectively reduced, but also, since the first electrode, the first channel region, and the second electrode have the same conductivity type, the floating body effect in the transistor structure can be effectively prevented.

[0263] Optionally, in this embodiment, the transistor structure formed based on semiconductor pillars can be used as a write transistor for memory.

[0264] Next, as Figure 26 As shown, the first character line WL1 extending along the first direction includes:

[0265] Multiple third grooves T3 are formed, extending along the first direction and located between two adjacent word line isolation structures 12;

[0266] A gate dielectric layer is formed, comprising a first gate dielectric layer 14 surrounding a portion of the semiconductor pillar 13, and a second gate dielectric layer 15 surrounding the sidewalls and top of the gate pillar 18;

[0267] A first word line WL1 is formed in the third trench T3, and the first word line WL1 surrounds a portion of the first gate dielectric layer 14.

[0268] In some specific embodiments, forming a third trench T3 includes:

[0269] A portion of the first dielectric layer L1 is removed to form a plurality of third trenches T3 extending along the first direction and located between two adjacent word line isolation structures 12, the bottom of the third trenches T3 being flush with the upper surface of the first electrode 131.

[0270] Understandably, in actual operation, the first gate dielectric layer 14 surrounds the sidewalls of the first channel region 132 and the second electrode 133 in the semiconductor pillar 13, and the upper surface of the first word line WL1 is flush with the upper surface of the first channel region 132.

[0271] Thus, multiple transistor structures have been formed within the first dielectric layer. Understandably, these multiple transistor structures can be used as write transistors for memory.

[0272] Optionally, in some embodiments, such as Figure 27 As shown, after forming the first character line WL1, the method further includes:

[0273] The first dielectric layer L1 is continued to be filled in the gap above the first word line WL1 and between the semiconductor pillars 13, so that the top surface of the first dielectric layer L1 is flush with the upper surface of the second electrode 133 of the semiconductor pillars; and,

[0274] A fourth dielectric layer L4 is formed, which covers the upper surface of the substrate 10 between adjacent gate pillars 18.

[0275] Understandably, since the fourth dielectric layer covers the upper surface of the substrate between adjacent gate pillars, the structure located at the bottom and around the semiconductor pillars can be electrically isolated from the structure located at the top and around the gate pillars, preventing mutual interference between the structures.

[0276] Then, as Figure 29 As shown, a semiconductor layer 16 is formed, which at least surrounds the sidewall of the gate pillar 18.

[0277] In some embodiments, such as Figure 27 and Figure 29 As shown, after forming the first character line, the method also includes:

[0278] A semiconductor material layer 16a and a word line material layer WL2a are sequentially formed on the second gate dielectric layer 15. The semiconductor material layer 16a at least covers the second gate dielectric layer 15, and the word line material layer WL2a fills the gaps between adjacent semiconductor material layers 16a.

[0279] Etch semiconductor material layer 16a and word line material layer WL2a to remove a portion of semiconductor material layer 16a and word line material layer WL2a located above word line isolation structure 12, so as to form semiconductor layer 16 and multiple second word lines WL2 extending along the first direction, respectively.

[0280] Here, the semiconductor layer 16 includes a first sub-section 161, a second sub-section 162, and a third sub-section 163 connected together. The first sub-section 161 covers the top surface of the gate pillar 18, the second sub-section 162 covers the sidewall of the gate pillar 18, and the third sub-section 163 partially covers the upper surface of the substrate 10 between adjacent gate pillars 18.

[0281] Understandably, the semiconductor layer can be used as the channel region of the transistor, and because the second sub-part of the semiconductor layer covers (surrounds) the sidewall of the gate pillar, the channel region of the transistor has a larger channel size. Compared with the structure in which the channel region is only provided on one side of the gate, the structure provided by the embodiments of this disclosure can effectively prevent the occurrence of short-channel effects.

[0282] Optionally, in some embodiments, after forming the semiconductor layer 16, the method further includes:

[0283] Forming a third dielectric layer L3;

[0284] The third dielectric layer L3 is etched to form a fourth trench T4 extending along the second direction, and the upper surface of the semiconductor layer 16 is exposed to the fourth trench T4.

[0285] The second bit line BL2 is formed within the fourth trench T4.

[0286] Thus, multiple transistor structures are formed within the second dielectric layer. The gate pillar can be used as the gate of the transistor structure, the semiconductor layer can be used as the channel region of the transistor structure, the second word line can be used as the source or drain region of the read transistor, and the second bit line can be used as the drain or source region of the transistor structure.

[0287] It should be noted that when the second word line is used as the source region of the transistor structure, the second bit line is used as the drain region of the transistor structure. However, this is not the only possibility. In some other embodiments, the second word line can also be used as the drain region of the read transistor, while the second bit line is used as the source region of the read transistor. In practice, this can be flexibly adjusted, and no specific restrictions are imposed here.

[0288] In this embodiment, since the second word line surrounds the second sub-section of the semiconductor layer that serves as the channel region, the contact area between the second word line and the channel region is increased, which helps to reduce the contact resistance between the second word line and the channel region, thereby reducing the power consumption of the transistor structure.

[0289] Understandably, this multi-transistor structure can be used as a read transistor for memory.

[0290] In this embodiment, the gate pillar and the semiconductor pillar are a single, directly electrically connected structure. That is, the channel region and source / drain region of the write transistor are integrated with the gate of the read transistor. This means that a source / drain region of the write transistor and the gate of the read transistor can be directly electrically connected without the aid of other conductive lines. Compared to conventional structures where the two are electrically connected via interconnects, this embodiment effectively shortens the charge flow path when the write transistor injects charge into the gate of the read transistor, thereby effectively improving the information transmission speed and efficiency of the semiconductor structure. Furthermore, when the write transistor needs to inject charge into the gate of the read transistor through its source / drain region, the absence of contact resistance due to the integrated structure effectively prevents the semiconductor structure from generating excessive heat during use, thus effectively improving the performance of the semiconductor structure.

[0291] In addition, in actual processes, the structure consisting of gate pillars and semiconductor pillars can be formed in the same process step, which significantly reduces the complexity of the process and is conducive to improving production efficiency.

[0292] Furthermore, compared to semiconductor structures with capacitors, the structure provided in this disclosure does not require additional capacitor manufacturing, has a simple process, and does not require rewriting after reading, thus reducing power consumption.

[0293] The semiconductor structure provided in this disclosure is applicable to memory structures, including but not limited to three-dimensional dynamic random access memory (3D DRAM).

[0294] It should be noted that the semiconductor device fabrication method provided in this disclosure can be applied to DRAM structures or other semiconductor devices, and is not limited thereto. The embodiments of the semiconductor device fabrication method provided in this disclosure and the embodiments of the semiconductor devices belong to the same concept; the technical features in the technical solutions described in each embodiment can be arbitrarily combined without conflict.

[0295] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; The semiconductor pillars located on the substrate and the gate pillars located above the semiconductor pillars, both extending in a direction perpendicular to the plane of the substrate; A first word line extending along a first direction, the first word line surrounding the semiconductor pillar, the first direction being parallel to the substrate plane; A semiconductor layer located above the semiconductor pillar, the semiconductor layer at least surrounding the sidewall of the gate pillar; The semiconductor layer includes a first sub-section, a second sub-section, and a third sub-section connected together. The first sub-section covers the top surface of the gate pillar, the second sub-section covers the sidewall of the gate pillar, and the third sub-section partially covers the upper surface of the substrate between adjacent gate pillars. The semiconductor structure also includes: A second word line extending along the first direction, the second word line surrounds one end of the second sub-part adjacent to the semiconductor pillar, and covers the upper surface of the third sub-part; A first bit line and a second bit line extending along a second direction, the second direction being parallel to the substrate plane and perpendicular to the first direction, the first bit line being located below the semiconductor pillar and electrically connected to the lower part of the semiconductor pillar, and the second bit line being located above the semiconductor layer and electrically connected to the first sub-part.

2. The structure according to claim 1, characterized in that, The gate pillars and the semiconductor pillars correspond one-to-one.

3. The structure according to claim 1, characterized in that, The top of the semiconductor pillar is electrically connected to the bottom of the gate pillar.

4. The structure according to claim 1, characterized in that, The semiconductor pillar and the gate pillar have at least partial overlap in their orthogonal projections onto the substrate plane, and the gate pillar and the semiconductor pillar are made of the same material.

5. The structure according to claim 1, characterized in that, The semiconductor pillar includes a first electrode, a first channel region, and a second electrode distributed from bottom to top, and the first electrode, the first channel region, and the second electrode have the same conductivity type.

6. The structure according to claim 5, characterized in that, The semiconductor structure also includes: A first gate dielectric layer is located between the first word line and the semiconductor pillar, and the first gate dielectric layer surrounds the first channel region and the second electrode; The second gate dielectric layer includes a first sublayer and a second sublayer connected together. The first sublayer is located between the gate pillar and the semiconductor layer, covering the sidewalls and top of the gate pillar. The second sublayer covers the upper surface of the substrate between adjacent gate pillars.

7. The structure according to claim 5, characterized in that, The semiconductor structure also includes: A first gate dielectric layer is located between the first word line and the semiconductor pillar, and the first gate dielectric layer surrounds the first channel region and the second electrode; A second gate dielectric layer covers the sidewalls and top of the gate pillar; A fourth dielectric layer covers the upper surface of the substrate between adjacent gate pillars.

8. The structure according to claim 1, characterized in that, The semiconductor pillar and the semiconductor layer comprise at least one or a combination of indium oxide, tin oxide, In-Zn oxides, Sn-Zn oxides, Al-Zn oxides, In-Ga oxides, In-Ga-Zn oxides, In-Al-Zn oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides, and Sn-Al-Zn oxides.

9. The structure according to claim 1, characterized in that, The semiconductor structure further includes a word line isolation structure extending along a first direction, the word line isolation structure being located between any two adjacent first word lines to isolate adjacent first word lines.

10. The structure according to claim 1, characterized in that, The semiconductor structure further includes: a first dielectric layer located above the substrate and a second dielectric layer located above the first dielectric layer, wherein the semiconductor pillar and the first word line are located in the first dielectric layer, and the gate pillar, the semiconductor layer and the second word line are located in the second dielectric layer.

11. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; A pillar is formed on the substrate, the pillar comprising a semiconductor pillar, the pillar extending in a direction perpendicular to the plane of the substrate; A first character line is formed extending along a first direction, the first character line surrounds a portion of the pillar, and the first direction is parallel to the substrate plane; After forming the first character line, the method further includes: A gate pillar is formed directly above the semiconductor pillar, and the gate pillar extends in a direction perpendicular to the substrate plane; A semiconductor layer is formed, the semiconductor layer at least surrounding the sidewall of the gate pillar; The semiconductor layer includes a first sub-section, a second sub-section, and a third sub-section connected together. The first sub-section covers the top surface of the gate pillar, the second sub-section covers the sidewall of the gate pillar, and the third sub-section partially covers the upper surface of the substrate between adjacent gate pillars. The semiconductor structure also includes: A second word line extending along the first direction, the second word line surrounds one end of the second sub-part adjacent to the semiconductor pillar, and covers the upper surface of the third sub-part; A first bit line and a second bit line extending along a second direction, the second direction being parallel to the substrate plane and perpendicular to the first direction, the first bit line being located below the semiconductor pillar and electrically connected to the lower part of the semiconductor pillar, and the second bit line being located above the semiconductor layer and electrically connected to the first sub-part.

12. The method according to claim 11, characterized in that, Before forming the pillars on the substrate, the method further includes: An insulating layer is formed on the substrate; An etching process is performed on the insulating layer to form a plurality of first trenches extending along a second direction on the insulating layer, the second direction being parallel to the substrate plane and perpendicular to the first direction; Conductive material is filled into a plurality of first trenches to form a plurality of first lines extending along a second direction.

13. The method according to claim 12, characterized in that, After filling a plurality of first trenches with conductive material to form a plurality of first lines extending along a second direction, the method further includes: Form the first dielectric layer; The first dielectric layer is etched to form a plurality of second trenches extending along a first direction within the first dielectric layer; Insulating material is filled into multiple second trenches to form multiple word line isolation structures extending along the first direction.

14. The method according to claim 13, characterized in that, Forming pillars on the substrate includes: The first dielectric layer is etched to form a plurality of first channel vias, the first channel vias exposing the first bit line; The first channel hole is filled with semiconductor material to form the pillar, the pillar comprising a semiconductor pillar; Forming a first word line extending along a first direction, the first word line surrounding the semiconductor pillar, the first direction being parallel to the substrate plane, including: Multiple third grooves are formed that extend along the first direction and are located between the isolation structures of two adjacent word lines; A first gate dielectric layer is formed in the third trench, the first gate dielectric layer surrounding a portion of the semiconductor pillar; A first word line is formed within the third trench, and the first word line surrounds a portion of the first gate dielectric layer.

15. The method according to claim 14, characterized in that, A gate pillar is formed directly above the semiconductor pillar, comprising: A second dielectric layer is formed, and the second dielectric layer is etched to form a plurality of second channel holes exposing the top of the semiconductor pillars within the second dielectric layer; The gate pillar is formed within the second channel aperture; After forming the gate pillar, the method further includes: The top surface and sidewalls of the gate pillar are exposed; A second gate dielectric layer is deposited, the second gate dielectric layer including portions surrounding the sidewalls and top of the gate pillar, and a portion covering the upper surface of the first dielectric layer; A semiconductor material layer and a word line material layer are sequentially formed on the second gate dielectric layer. The semiconductor material layer is conformal to the second gate dielectric layer, and the word line material layer fills the gaps between adjacent semiconductor material layers. The semiconductor material layer and the word line material layer are etched to form a semiconductor layer and a plurality of second word lines extending along a first direction, respectively.

16. The method according to claim 11, characterized in that, After forming the semiconductor layer, the method further includes: Forming a third dielectric layer; The third dielectric layer is etched to form a fourth trench extending along the second direction, and the upper surface of the semiconductor layer is exposed to the fourth trench. A second bit line is formed within the fourth trench.

17. The method according to claim 11, characterized in that, Forming pillars on the substrate includes: A pillar is formed on the substrate, the pillar being higher than the substrate surface and extending in a direction perpendicular to the substrate plane; the pillar includes a semiconductor pillar and a gate pillar, the gate pillar being located directly above the semiconductor pillar; After forming the first word line, the method further includes forming a semiconductor layer, the semiconductor layer at least surrounding the sidewall of the gate pillar.

18. The method according to claim 17, characterized in that, Before forming the pillars on the substrate, the method further includes: Multiple first lines extending along the second direction are formed on the substrate; Form the first dielectric layer; Multiple word line isolation structures extending along a first direction are formed within the first dielectric layer.

19. The method according to claim 18, characterized in that, Forming pillars on the substrate includes: The first dielectric layer is etched to form a plurality of first channel vias, the first channel vias exposing the first bit line; A semiconductor material layer is formed, which covers the upper surface of the first dielectric layer and fills the first channel hole; The semiconductor material layer is etched to form the pillar, the portion of the pillar located within the first channel hole is defined as a semiconductor pillar, and the portion of the pillar located directly above the first channel hole is defined as a gate pillar.

20. The method according to claim 19, characterized in that, Forming the first character line extending along the first direction includes: Multiple third grooves are formed that extend along the first direction and are located between the isolation structures of two adjacent word lines; A gate dielectric layer is formed, the gate dielectric layer including a first gate dielectric layer surrounding a portion of the semiconductor pillar, and a second gate dielectric layer surrounding the sidewalls and top of the gate pillar; A first word line is formed within the third trench, and the first word line surrounds a portion of the first gate dielectric layer.

21. The method according to claim 20, characterized in that, After forming the first character line, the method further includes: A semiconductor material layer and a word line material layer are sequentially formed on the second gate dielectric layer, wherein the semiconductor material layer at least covers the second gate dielectric layer, and the word line material layer fills the gaps between adjacent semiconductor material layers. The semiconductor material layer and the word line material layer are etched to remove a portion of the semiconductor material layer and the word line material layer located above the word line isolation structure, so as to form a semiconductor layer and a plurality of second word lines extending along a first direction.

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