Magnetic random access memory and method of manufacturing the same, electronic device

Abstract

A magnetic random access memory and a manufacturing method thereof and an electronic device, the magnetic random access memory comprising: a plurality of array-distributed storage units, each of the storage units comprising a magnetic tunnel junction and a read transistor, the magnetic tunnel junctions of the storage units located in the same row being connected to a read bit line at one end and connected to the read transistor at the other end; a plurality of first write transistors arranged in the column direction in sequence at the periphery of the storage units and connected to a first write signal line; a plurality of second write transistors arranged in the row direction in sequence at the periphery of the storage units and connected to a second write signal line; the first write signal line and the second write signal line being configured to drive the magnetic field direction of the free layer of the magnetic tunnel junction to flip; wherein the read transistor is a buried gate transistor. The magnetic random access memory of the embodiment has the advantages of high storage density, small read current, simple structure, low manufacturing cost, etc.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of semiconductor devices, and particularly to a magnetic random access memory and its manufacturing method, and an electronic device. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is a type of random access memory that stores data using magnetoresistive properties. Toggle-MRAM, a magnetically driven MRAM, is the first generation of magnetic random access memory. Toggle-MRAM possesses excellent characteristics such as unlimited erase / write cycles, good high-temperature stability, and radiation resistance, making it a promising candidate for applications in aerospace, automotive, and electronics industries. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0004] This application provides a magnetic random access memory, its manufacturing method, and an electronic device. The magnetic random access memory has advantages such as high storage density, low read current, simple structure, and low manufacturing cost.

[0005] This application provides a magnetic random access memory, including:

[0006] Multiple memory cells arrayed on a substrate, each memory cell including a magnetic tunnel junction and a read transistor, the magnetic tunnel junction including a free layer capable of reversing the direction of a magnetic field;

[0007] One end of each of the magnetic tunnel junctions of the memory cells located in the same row is connected to a read bit line, and the other end of each of the magnetic tunnel junctions is connected to the read transistor; it also includes: a plurality of first write transistors arranged sequentially in the column direction around the periphery of the memory cells distributed in the array, each of the first write transistors being connected to one end of a first write signal line, and the other end of the first write signal line being disposed on the first side of the free layer of the magnetic tunnel junction;

[0008] A plurality of second write transistors are arranged sequentially in the row direction around the memory cells distributed in the array. Each second write transistor is connected to one end of a second write signal line, and the other end of the second write signal line is disposed on the second side of the free layer of the magnetic tunnel junction opposite to the first side.

[0009] The projections of the free layer, the first write signal line disposed on the first side of the free layer, and the second write signal line disposed on the second side of the free layer onto the substrate of each magnetic tunnel junction have an overlapping region;

[0010] The first write signal line and the second write signal line are configured to drive the magnetic field direction of the free layer to flip via signals;

[0011] The readout transistor is a buried gate transistor.

[0012] In embodiments of this application, the read transistor may include a source, a drain, a semiconductor layer, and a gate;

[0013] The source and the drain are both located on the substrate and are spaced apart, and the projections of the source and the drain on the substrate do not overlap;

[0014] The semiconductor layer is disposed between the source and the drain and is ring-shaped. The outer surface of the ring semiconductor layer is in contact with the source and the drain. The gate is located inside the ring semiconductor layer and is surrounded by the ring semiconductor layer.

[0015] In embodiments of this application, the read transistors of two adjacent memory cells located in the same row may share a single source.

[0016] In embodiments of this application, the magnetic random access memory may further include read word lines extending along the column direction, the read word lines being connected to the gate.

[0017] In embodiments of this application, the magnetic tunnel junction may further include a bottom electrode and an interconnect line. The free layer of the magnetic tunnel junction is disposed on the bottom electrode, one end of the interconnect line is connected to the bottom electrode, and the other end of the interconnect line is connected to the read transistor.

[0018] In embodiments of this application, the magnetic tunnel junction may further include a top electrode, which is disposed on the side of the free layer away from the bottom electrode, and the magnetic tunnel junction can be connected to the read bit line through the top electrode.

[0019] In embodiments of this application, the read bit line may extend along the row direction.

[0020] In embodiments of this application, the magnetic random access memory may further include a first write signal line address decoder and driver and a second write signal line address decoder and driver, wherein the first write signal line address decoder and driver is connected to the first write transistor and the second write signal line address decoder and driver is connected to the second write transistor.

[0021] This application embodiment also provides a method for manufacturing the magnetic random access memory as described in the above application embodiment, including:

[0022] The read transistor was fabricated using a dynamic random access memory (DRAM) process platform.

[0023] The first write transistor and / or the second write transistor are fabricated using a dynamic random access memory process platform, and the first write transistor is connected to the first write signal line, and the second write transistor is connected to the second write signal line.

[0024] The magnetic tunnel junction is formed, and one end of the magnetic tunnel junction is connected to the read bit line, while the other end of the magnetic tunnel junction is connected to the read transistor.

[0025] This application also provides an electronic device, including the magnetic random access memory as described in the above embodiments of this application.

[0026] The magnetic random access memory in this application uses buried gate transistors as read transistors, which can increase the density of read transistors, thereby increasing the storage density of the magnetic random access memory and reducing the manufacturing cost of the magnetic random access memory.

[0027] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0028] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0029] Figure 1 A schematic diagram of a longitudinal cross-section of a magnetic random access memory, which is an exemplary embodiment of this application;

[0030] Figure 2 A logic circuit diagram of a magnetic random access memory as an exemplary embodiment of this application;

[0031] Figure 3 A schematic diagram of a longitudinal cross-section of another magnetic random access memory, which is an exemplary embodiment of this application;

[0032] Figure 4 This is a manufacturing process flow diagram of a magnetic random access memory, which is an exemplary embodiment of this application.

[0033] The meanings of the various symbols in the attached diagram are as follows:

[0034] 10-First write transistor; 11-Second source; 12-Second drain; 13-Second semiconductor layer; 14-Second gate; 20-Second write transistor; 30-First write signal line; 40-Second write signal line; 50-Magnetic tunnel junction; 60-Read transistor; 61-First source; 62-First drain; 63-First semiconductor layer; 64-First gate; 70-Read bit line; 80-Read word line; 90-Bottom electrode; 100-Interconnect line; 110-Top electrode; 120-Dielectric; 130-First write signal line address decoder and driver; 140-Second write signal line address decoder and driver; 150-First write transistor group; 160-Second write transistor group; 170-Memory cell; 180-Substrate; 1000-Memory array. Detailed Implementation

[0035] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0036] This application provides a magnetic random access memory. Figure 1 A schematic diagram of a longitudinal cross-section of a magnetic random access memory, which is an exemplary embodiment of this application; Figure 2 This is a logic circuit diagram of a magnetic random access memory (RAM) as an exemplary embodiment of this application. Figure 1 and Figure 2 As shown, the magnetic random access memory of this application embodiment includes: a plurality of memory cells 170 arrayed on a substrate, a first write transistor 10, a second write transistor 20, a first write signal line 30 and a second write signal line 40;

[0037] Among them, such as Figure 2 As shown, each memory cell 170 includes a magnetic tunnel junction 50 and a read transistor 60. The magnetic tunnel junction 50 includes a free layer that can reverse the magnetic field direction. One end of each magnetic tunnel junction 50 of the memory cells 170 in the same row is connected to... Figure 1 The read bit line 70 is connected, or is connected to Figure 2 One end of the magnetic tunnel junction 50 is connected to a read bit line 70, and the other end of the magnetic tunnel junction 50 is connected to a read transistor 60; for example, the magnetic tunnel junction 50 may sequentially include a reference layer, a barrier layer, and a free layer, wherein the free layer may be connected to... Figure 1 The read bit line 70 is connected, and the reference layer can be connected to the read transistor 60;

[0038] Multiple first write transistors 10 are located around the array-distributed memory cells 170 and arranged sequentially in the column direction. One end of each first write transistor 10 (e.g., it may be the source) is connected to one end of a first write signal line 30, and the other end of the first write signal line 30 is disposed on the first side of the free layer of the magnetic tunnel junction 50.

[0039] Multiple second write transistors 20 are located around the array-distributed memory cells 170 and are arranged sequentially in the row direction. One end of the second write transistor 20 (e.g., it may be the source) is connected to a second write signal line 40, and the other end of the second write signal line 40 is disposed on the second side of the free layer of the magnetic tunnel junction 50 opposite to the first side.

[0040] The free layer of each magnetic tunnel junction 50, the first write signal line 30 disposed on the first side of the free layer, and the second write signal line 40 disposed on the second side of the free layer have overlapping regions on the substrate 180; the first write signal line 30 and the second write signal line 40 are configured to drive the magnetic field direction of the free layer to reverse through a signal. For example, the first write signal line 30 and the second write signal line 40 are configured to generate a signal that can drive the magnetic field direction of the free layer to reverse after a current is applied.

[0041] Wherein, the read transistor 60 is a buried-gate transistor. In embodiments of this application, such as... Figure 1 As shown, the read transistor 60 can be disposed on the semiconductor substrate 180. The read transistor 60 includes a first gate 64, which can be formed in a trench of the substrate 180, thereby forming a buried gate transistor with the gate buried in the substrate.

[0042] The magnetic random access memory in this application uses buried gate transistors as read transistors. The gate of the buried gate transistor is buried (e.g., buried in the substrate) and does not occupy space in the semiconductor device separately. Therefore, the density of read transistors can be increased, thereby increasing the storage density of the magnetic random access memory and reducing the manufacturing cost of the magnetic random access memory.

[0043] Figure 1 The left and right sides respectively represent the longitudinal cross-sectional structural diagrams of the first write transistor 10 and the memory cell 170 located in the same row as the first write transistor 10. At this time, the write transistor (i.e., the first write transistor 10) is connected to the first write signal line 30, but disconnected from the second write signal line 40 (as shown by the dashed line on the left side of the diagram); or, Figure 1The left and right sides respectively represent the longitudinal cross-sectional structural diagrams of the second write transistor 20 and the memory cell 170 located in the same column as the second write transistor 20. At this time, the write transistor (i.e. the second write transistor 20) is connected to the second write signal line 40, but disconnected from the first write signal line 30 (as shown by the dashed line between the left and right sides of the first write signal line 30).

[0044] In the embodiments of this application, such as Figure 2 As shown, the first write signal line 30 can extend along the row direction, and the second write signal line 40 can extend along the column direction.

[0045] In embodiments of this application, the magnetic random access memory can be disposed on a semiconductor substrate, with both the row direction and the column direction parallel to the substrate and extending in a plane parallel to the substrate.

[0046] In the embodiments of this application, such as Figure 1 As shown, the read transistor 60 may include a first source 61, a first drain 62, a first semiconductor layer 63, and a first gate 64. The first source 61 and the first drain 62 are both located on the substrate 180 and are spaced apart, with no overlap in their projections on the substrate 180. The first semiconductor layer 63 is disposed between the first source 61 and the first drain 62 and is annular. The outer surface of the annular first semiconductor layer 63 contacts the first source 61 and the first drain 62. The first gate 64 is located inside the first semiconductor layer 63 and is surrounded by the first semiconductor layer 63. The read word line 80 extends along the column direction and is connected to the first gate 64. A gate insulating layer is also disposed between the first semiconductor layer 63 and the first gate 64 to isolate the first gate 64 and the first semiconductor layer 63 (not shown in the figure).

[0047] In the embodiments of this application, such as Figure 2 As shown, multiple storage cells can be arranged along the row and column directions to form a storage array 1000, such as... Figure 1 As shown, the read transistors 60 of two adjacent memory cells in the row direction can share a first source 61.

[0048] In the embodiments of this application, such as Figure 1 As shown, the magnetic tunnel junction 50 of each memory cell may further include a bottom electrode 90 and an interconnect line 100. The reference layer, barrier layer and free layer of the magnetic tunnel junction 50 are stacked on the bottom electrode 90. One end of the interconnect line 100 is connected to the bottom electrode 90, and the other end of the interconnect line 100 is connected to the first drain 62 of the read transistor 60, thereby realizing the connection between the magnetic tunnel junction 50 and the read transistor 60.

[0049] In embodiments of this application, the interconnect can be a metal contact post. The material of the metal contact post can be selected from any one or more of tungsten, copper, tantalum, titanium nitride, carbon nitride, and molybdenum; for example, it can be tungsten.

[0050] In exemplary embodiments of this application, as Figure 1 As shown, one end of the magnetic tunnel junction 50 can be directly connected to the read bit line 70. Figure 3 This is a schematic cross-sectional view of another magnetic random access memory as an exemplary embodiment of this application. Alternatively, as... Figure 3 As shown in the exemplary embodiment of this application, each magnetic tunnel junction 50 may further include a top electrode 110, which may be disposed on one side of the free layer. The magnetic tunnel junction 50 may be connected to the read bit line 70 through the top electrode 110. In this case, the read bit line 70 and the first write signal line 30 may share a single signal line. When the read bit line 70 and the first write signal line 30 share a single signal line, this shared signal line may function as either the read bit line 70 or the first write signal line 30 at different times, thus allowing them to share a single signal line. Moreover, when the read bit line 70 and the first write signal line 30 share a single signal line, the distance between the first write signal line 30 and the magnetic tunnel junction 50 may be closer, which is more conducive to achieving the reversal of the magnetic field direction of the free layer of the magnetic tunnel junction 50.

[0051] In the embodiments of this application, such as Figure 2 As shown, the read bit line 70 can extend along the row direction. In... Figure 2 The magnetic random access memory shown may include multiple read bit lines 70 extending along the row direction; it may also include multiple read word lines 80 extending along the column direction. Each column of read transistors corresponds to one read word line, and each read word line is connected to the gate of each read transistor in a column.

[0052] In the embodiments of this application, the magnetic random access memory can be a magnetic field reversal type magnetic random access memory (toggle-MRAM), specifically, the reversal of the magnetic direction of the free layer is controlled by a signal.

[0053] In the embodiments of this application, each of the memory cells may include a magnetic tunnel junction and a read transistor, that is, the memory cell is a 1T 1MTJ structure.

[0054] In the embodiments of this application, the read transistors can be fabricated using a Dynamic Random Access Memory (DRAM) process platform. For example, the read transistors in the embodiments of this application can be fabricated using the DRAM process platform's data storage array transistor fabrication process to obtain a high-density read transistor array.

[0055] The read transistors of magnetic random access memory require relatively low read current, while the drive current of the DRAM process platform is also relatively low, making it ideal for fabricating read transistors with low read current. In addition, the DRAM process platform is suitable for fabricating transistors with simple structure, high density, and low power consumption, and also has low energy consumption. Therefore, the DRAM process platform can be used to fabricate read transistors with simple structure, high density, and low power consumption, and can reduce the manufacturing cost of magnetic random access memory.

[0056] In the embodiments of this application, the first write transistor and / or the second write transistor can be fabricated using a dynamic random access memory (DRAM) process platform. While the write transistors in a magnetic random access memory (MRMemory) require a large write current, they are not a 1T 1MTJ structure; multiple MTJs can share a single write transistor. Therefore, a DRAM process platform can be used to fabricate the first write transistor and / or the second write transistor, which have a large write current. Using a DRAM process platform to fabricate write transistors with a simple structure can reduce the manufacturing cost of the MRMemory.

[0057] In embodiments of this application, the first write transistor and / or the second write transistor may be planar transistors.

[0058] In the embodiments of this application, such as Figure 1 As shown, the first write transistor 10 (or the second write transistor 20) may include a second source 11, a second drain 12, a second semiconductor layer 13, and a second gate 14. The second semiconductor layer 13 is disposed between the second source 11 and the second drain 12, and extends along the row direction. The second gate 14 is disposed on one side of the second semiconductor layer 13. Additionally, a gate insulating layer (not shown) may be disposed between the second gate 14 and the second semiconductor layer 13.

[0059] In embodiments of this application, the material of the gate insulating layer (including the gate insulating layer of the read transistor and the gate insulating layer of the write transistor) can be selected from any one or more of silicon oxide (e.g., SiO2) and high dielectric constant (K) materials, such as hafnium oxide (e.g., HfO2), zirconium oxide (e.g., ZrO), and aluminum oxide (e.g., Al2O3). The gate insulating layer can be a single-layer or multi-layer structure; for example, it can be a bilayer structure formed of SiO2 and a high-K material.

[0060] In the embodiments of this application, such as Figure 1 As shown, the first write transistor 10 and the first write signal line 30, or the second write transistor 20 and the second write signal line 40, can be connected via an interconnect line 100. For example, one end of the interconnect line 100 can be connected to the second source 11 of the first write transistor 10 or the second write transistor 20, and the other end of the interconnect line 100 can be connected to the first write signal line 30 or the second write signal line 40. The interconnect line 100 can be a metal contact post. The material of the metal contact post can be selected from any one or more of tungsten and molybdenum; for example, it can be tungsten.

[0061] In the embodiments of this application, such as Figure 1 As shown, the blank spaces of the magnetic random access memory (e.g., the blank spaces around the magnetic tunnel junction 50, the blank spaces between the bottom electrode 90 and the read transistor 60, etc.) can be filled with dielectric 120.

[0062] In the embodiments of this application, the dielectric material may be selected from any one or more of silicon dioxide, silicon nitride, silicon carbonitride, and silicon carbonitride.

[0063] In the embodiments of this application, such as Figure 2 As shown, the magnetic random access memory may further include a first write signal line address decoder and driver 130 and a second write signal line address decoder and driver 140. The first write signal line address decoder and driver 130 is connected to the first write transistor 10, and the second write signal line address decoder and driver 140 is connected to the second write transistor 20. The first write signal line address decoder and driver 130 and the first write transistor 10 form a first write transistor group 150, and the second write signal line address decoder and driver 140 and the second write transistor 20 form a second write transistor group 160.

[0064] In embodiments of this application, the magnetic tunnel junction may include multiple film layers; for example, the magnetic tunnel junction may include a reference layer, a barrier layer, and a free layer; for another example, the magnetic tunnel junction may include a synthetic antiferromagnetic layer, a reference layer, a barrier layer, and a free layer; for yet another example, the magnetic tunnel junction may include a synthetic antiferromagnetic layer, a ferromagnetic coupling layer, a reference layer, a barrier layer, and a free layer.

[0065] In embodiments of this application, the total thickness of the magnetic tunnel junction can be from 15 nm to 30 nm, and it has a bottom pinned or top pinned structure. For example, the total thickness of the magnetic tunnel junction can be 20 nm.

[0066] In embodiments of this application, the reference layer has magnetic polarization invariance, and the reference layer generally comprises [Co / Ni]. n Co / (Ru or Ir) / Co[Ni / Co] m [Co / Pd] n Co / (Ru or Ir) / Co[Pd / Co] m Or [Co / Pt] n Co / (Ru or Ir) / Co[Pt / Co] m The superlattice multilayer film structure has 0≤m≤3, 2≤n≤7, and can achieve ferromagnetic coupling with cobalt iron boron (CoFeB), cobalt ferrode (CoFe) / cobalt iron boron (CoFeB), cobalt ferrode (CoFe) / nickel iron alloy (NiFe), cobalt boron (CoB), or iron boron (FeB) through lattice isolation layers; the total thickness of the reference layer can be from 4nm to 15nm.

[0067] In the embodiments of this application, the material of the barrier layer can be a non-magnetic metal oxide, such as magnesium oxide (MgO), zinc magnesium oxide (MgZnO), boron magnesium oxide (MgBO), aluminum magnesium oxide (MgAlO), preferably magnesium oxide (MgO); the thickness of the barrier layer can be 0.5nm-2.5nm.

[0068] In the embodiments of this application, the free layer has variable magnetic polarization, and the material of the free layer can be cobalt iron boron (CoFeB), CoFe / cobalt iron boron (CoFeB), iron (Fe) / cobalt iron boron (CoFeB), cobalt iron boron (CoFeB) / tungsten (W) / cobalt iron boron (CoFeB), cobalt iron boron (CoFeB) / molybdenum (Mo) / cobalt iron boron (CoFeB); the thickness of the free layer can be from 0.8 nm to 2.3 nm.

[0069] In embodiments of this application, the material of the bottom electrode may include any one or more of Ta, TaN, W, WN, Ti, TiN, Co, Cu, Al, and Pt. For example, the material of the bottom electrode may be TaN or TiN. The bottom electrode may be single-layered or multi-layered.

[0070] In the embodiments of this application, the material of the top electrode may include any one or more of Ta, TaN, W, WN, Ti, TiN, Co, Cu, Al and Pt; the thickness of the top electrode may be from 20nm to 100nm, for example, it may be 20nm, 40nm, 50nm, 60nm, 80nm, or 100nm.

[0071] In embodiments of this application, the material of the read bit line may include any one or more of tungsten, copper, cobalt, and titanium.

[0072] In embodiments of this application, the materials of the first gate (or read word line) and / or the second gate may be indium tin oxide (ITO), etc. ITO material has low resistance;

[0073] The materials of the first semiconductor layer and the second semiconductor layer can be metal oxide semiconductor materials. For example, the materials of the first semiconductor layer and the second semiconductor layer can be independently selected from indium gallium zinc oxide (IGZO), zinc stannate (ZTO), indium zinc oxide (IZO), and zinc oxide (ZnO). x Indium tungsten oxide (InWO), indium zinc tin oxide (IZTO), indium oxide (InO) x For example, In2O3, tin oxide (SnO) x For example, SnO2), titanium oxide (TiO2) x ), zinc oxide (Zn) x O y N z ), magnesium zinc oxide (Mg x Zn y O z Zirconium indium zinc oxide (Zr) x In y Zn z O a ), Hafnium indium zinc oxide (Hf x In y Zn z O a ), aluminum tin indium zinc oxide (Alx Sn y In z Zn a O d ), silicon indium zinc oxide (Si x In y Zn z O a ), aluminum zinc tin oxide (Al x Zn y Sn z O a Gallium zinc tin oxide (Ga) x Zn y Sn z O a Zirconium zinc tin oxide (Zr) x Zn y Sn z O a ) and indium gallium silicon oxide (InGaSiO) x Any one or more of the following. For example, the material of the semiconductor layer can be IGZO.

[0074] In the embodiments of this application, the materials of the first gate (or read word line) and / or the second gate can each be independently selected from any one or more of polycrystalline silicon and polycrystalline silicon germanium; the materials of the first semiconductor layer and the second semiconductor layer can each be independently selected from any one or more of group IVA semiconductor materials, for example, the materials of the first semiconductor layer and the second semiconductor layer can be monocrystalline silicon.

[0075] In addition, the material of the first gate can also be tungsten, titanium nitride (TiN), etc.

[0076] This application also provides a method for manufacturing the magnetic random access memory as described above. Figure 4 This is a manufacturing process flow diagram of a magnetic random access memory, which is an exemplary embodiment of this application. Figure 4 As shown in the embodiments of this application, the method for manufacturing the magnetic random access memory includes:

[0077] The read transistor 60 was fabricated using a dynamic random access memory (DRAM) fabrication platform.

[0078] A first write transistor 10 and / or a second write transistor 20 are fabricated using a dynamic random access memory process platform, and the first write transistor 10 is connected to a first write signal line 30, and the second write transistor 20 is connected to a second write signal line 40.

[0079] A magnetic tunnel junction 50 is formed, and one end of the magnetic tunnel junction 50 is connected to the read bit line 70, while the other end of the magnetic tunnel junction 50 is connected to the read transistor 60.

[0080] This application also provides an electronic device, which may include a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, and a power bank, etc.

[0081] While the embodiments disclosed in this application are as described above, the content is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A magnetic random access memory, characterized in that, include: Multiple memory cells arrayed on a substrate, each memory cell including a magnetic tunnel junction and a read transistor, the magnetic tunnel junction including a free layer capable of reversing the direction of a magnetic field; One end of each magnetic tunnel junction of a memory cell located in the same row is connected to a read bit line, and the other end of each magnetic tunnel junction is connected to the read transistor; it also includes: A plurality of first write transistors are arranged sequentially in the column direction around the memory cells distributed in the array. Each first write transistor is connected to one end of a first write signal line, and the other end of the first write signal line is disposed on the first side of the free layer of the magnetic tunnel junction. A plurality of second write transistors are arranged sequentially in the row direction around the memory cells distributed in the array. Each second write transistor is connected to one end of a second write signal line, and the other end of the second write signal line is disposed on the second side of the free layer of the magnetic tunnel junction opposite to the first side. The projections of the free layer, the first write signal line disposed on the first side of the free layer, and the second write signal line disposed on the second side of the free layer onto the substrate of each magnetic tunnel junction have an overlapping region; The first write signal line and the second write signal line are configured to drive the magnetic field direction of the free layer to flip via signals; The readout transistor is a buried gate transistor.

2. The magnetic random access memory according to claim 1, wherein, The readout transistor includes a source, a drain, a semiconductor layer, and a gate; The source and the drain are both located on the substrate and are spaced apart, and the projections of the source and the drain on the substrate do not overlap; The semiconductor layer is disposed between the source and the drain and is ring-shaped. The outer surface of the ring semiconductor layer is in contact with the source and the drain. The gate is located inside the ring semiconductor layer and is surrounded by the ring semiconductor layer.

3. The magnetic random access memory according to claim 2, wherein, The read transistors of two adjacent memory cells located in the same row share a single source.

4. The magnetic random access memory according to claim 2 or 3 further includes read word lines extending along the column direction, the read word lines being connected to the gate.

5. The magnetic random access memory according to any one of claims 1 to 3, wherein, The magnetic tunnel junction further includes a bottom electrode and an interconnect. The free layer of the magnetic tunnel junction is disposed on the bottom electrode. One end of the interconnect is connected to the bottom electrode, and the other end of the interconnect is connected to the read transistor.

6. The magnetic random access memory according to claim 5, wherein, The magnetic tunnel junction also includes a top electrode, which is disposed on the side of the free layer away from the bottom electrode, and the magnetic tunnel junction is connected to the read bit line through the top electrode.

7. The magnetic random access memory according to any one of claims 1 to 3, wherein, The read bit lines extend along the row direction.

8. The magnetic random access memory according to claim 1 further includes a first write signal line address decoder and driver and a second write signal line address decoder and driver, wherein the first write signal line address decoder and driver are connected to the first write transistor, and the second write signal line address decoder and driver are connected to the second write transistor.

9. A method for manufacturing a magnetic random access memory according to any one of claims 1 to 8, characterized in that, include: The read transistor was fabricated using a dynamic random access memory (DRAM) process platform. The first write transistor and / or the second write transistor are fabricated using a dynamic random access memory process platform, and the first write transistor is connected to the first write signal line, and the second write transistor is connected to the second write signal line. The magnetic tunnel junction is formed, and one end of the magnetic tunnel junction is connected to the read bit line, while the other end of the magnetic tunnel junction is connected to the read transistor.

10. An electronic device, characterized in that, Includes a magnetic random access memory according to any one of claims 1 to 8.

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