Accelerated read, modify, write operations

Abstract

An article of manufacture includes a non-transitory machine-readable medium. The medium includes instructions. The instructions, when read and executed by a processor, cause the processor to determine that a first input instruction in a code stream to be executed will perform a read-modify-write operation, determine that the first input instruction will target a memory location, and based on the determination that the first input instruction will perform the read-modify-write operation and the determination that the first input instruction will target the memory location, convert the first input instruction to a second input instruction to target the memory location with a mask to cause an atomic operation to implement the read-modify-write operation.

Description

[0001] Priority

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 285,769, filed December 3, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to computer processing, and more specifically to accelerated read, modify, and write operations. Background Technology

[0004] Computer processors (e.g., microprocessors, central processing units (CPUs), digital signal processors (DSPs), digital signal controllers (DSCs), but not limited thereto) can perform read, write, and modify operations as part of setting, clearing, or toggling bits as part of instructions executed on memory. However, the inventors of the examples of this disclosure have discovered that reading from peripheral memory can experience latency issues. Therefore, read-modify-write instructions can cause further latency.

[0005] The examples disclosed herein address one or more of these problems. Attached Figure Description

[0006] Figure 1 This is an illustration of an exemplary system for accelerating read, modify, and write instructions according to examples of this disclosure.

[0007] Figure 2 This is a more detailed illustration of an exemplary system for accelerating read, modify, and write instructions, based on examples of this disclosure.

[0008] Figure 3 This is a diagram illustrating the latency of accelerated read, modify, and write command execution according to examples of this disclosure.

[0009] Figure 4 This is an illustration of an exemplary method for generating accelerated read, modify, and write instructions according to examples of this disclosure.

[0010] Figure 5 This is a more detailed illustration of an exemplary method for generating accelerated read, modify, and write instructions according to examples of this disclosure.

[0011] Figure 6 This is an illustration of an exemplary method for executing accelerated read, modify, and write instructions according to examples of this disclosure.

[0012] Figure 7 This is a more detailed illustration of an exemplary method for executing accelerated read, modify, and write instructions according to examples of this disclosure. Detailed Implementation

[0013] Figure 1 This is an illustration of an exemplary system 100 for accelerated read-modify-write (RMW) instructions. RMW instructions can include any suitable instructions that, when executed by the processor, include operations such as reading a value, modifying a value, and writing the modified value back to the memory location from which the original value was read. These operations may be referred to as RWM operations. System 100 can use RMW instructions such as binary set (BSET), binary clear (BCLR), binary toggle (BTOG), logical AND or bitwise AND (AND), logical OR or bitwise OR (OR), or logical XOR or bitwise XOR (XOR). Examples of such instructions are shown in... Figure 1 This is shown as instruction 108. System 100 can be configured to modify or replace instruction 108 with another instruction 110. By modifying or replacing instruction 108 with instruction 110, system 100 can facilitate the reduction of bus latency caused during RMW operation. Instruction 110 can be executed by the target processor.

[0014] RMW operations can be performed at any suitable memory location. In particular, system 100 can be configured to modify or replace instruction 108 with instruction 110 when instruction 108 is to be executed at an external memory location such as a special function register (SFR).

[0015] Instruction 108 can be included in a series of instructions executed by a target processor (which may or may not be shown). This series of instructions can be represented as follows: Figure 1 Code stream 102. Other instructions may be included in code stream 102, but are not shown. Code stream 102 may be implemented in any suitable manner, such as data structures, records, files, or partially processed code.

[0016] System 100 can be configured such that, upon the generation of instruction 110, bit manipulation initially specified to be performed by instruction 108 is not performed directly by the target processor, but by an entity (such as control logic, digital circuitry, analog circuitry, or any combination thereof) located near or within the target peripheral device of the target processor, wherein bit manipulation will be performed on the data of the target peripheral device. Such an entity may be, for example, within the target peripheral device, a bus pad, or a local bus interface. The bus pad may include any suitable interface adapter or bridge that allows data to be moved to or out of elements of system 100 using different bus protocols. Such a bus pad may be implemented in any suitable manner, such as analog circuitry, digital circuitry, or any suitable combination thereof.

[0017] Executing instruction 110 instead of instruction 108 by the target processor eliminates the need for the target processor to read and manipulate data as part of the RMW operation that executes instruction 108. Instead, the target processor's operational latency can be reduced to the latency attributable to literal value writing, since literal value writing can be used to offload the RMW operation to the digital circuit system.

[0018] To generate instruction 110 based on instruction 108, the processor may load and execute the instruction. The instruction may be stored on article 106. Article 106 may include a non-transitory machine-readable medium. This medium may include the instruction. When the instruction is read and executed by processor 104, the processor may identify a first input instruction (such as instruction 108) in code stream 102 that will be executed by the target processor, determine that the first input instruction (such as instruction 108) will perform an RMW operation, determine that instruction 108 will target a memory location, and translate instruction 108 into instruction 110 based on the determination that instruction 108 will perform an RMW operation and the determination that instruction 108 will target a memory location. In one example, instruction 110 may target a memory location using a mask. Instruction 110 may target a memory location using a mask by causing an operation to be performed at the memory location (but only on certain bits of the memory location according to the mask). When instruction 110 is executed, targeting a memory location with a mask may cause an atomic operation to be performed to perform the RMW operation. The mask identifies the bits that will be manipulated in the memory location by the RMW operation.

[0019] Figure 2 This is a more detailed illustration of an exemplary system 200 for accelerating read, modify, and write commands. System 200 may be implemented in whole or in part. Figure 1 System 100. System 200 may include any suitable entity (such as development machine 216) for generating code to be executed, and any suitable entity (such as microcontroller 218) for executing that code. Other suitable entities may be used, or the same entities may be used to generate and execute the code.

[0020] Development machine 216 may include processor 208, which is communicatively coupled to memory 210. Memory 210 may include instructions that, when loaded and executed by processor 208, cause development machine 216 to perform the functions described herein. In particular, development machine 216 may include software 204 configured to generate instructions in code stream 206, which will be executed by microcontroller 218. Software 204 may be implemented by instructions in memory 210 that are executed by processor 208. Software 204 may include, for example, a compiler, linker, interpreter, or any suitable entity for generating code stream 206.

[0021] When executing software 204, processor 208 can generate code stream 206 from source code stream 202. Source code stream 202 may include any suitable number and type of instructions, such as instruction 212. When executing software 204, processor 208 may replace or modify instruction 212 with instruction 214 in code stream 206.

[0022] As discussed above in the context of instruction 102, instruction 212 can be used to perform an RMW operation. Instruction 212 can perform such an RMW operation at a memory location. The memory location can be a processor peripheral device (denoted as peripheral device X) or within a processor peripheral device. Instruction 212 can specify the bit to be manipulated by the RMW operation (given as bit Y). Instruction 212 can specify more than one such bit.

[0023] Code stream 206 can be executed by any suitable entity, such as processor 220 of microcontroller 218. Microcontroller 218 may include any suitable processor peripheral, such as peripheral X 222. Processor peripheral (e.g., peripheral X 222) may include any suitable analog circuit system, digital circuit system, or combination thereof for offloading the execution of various processes of processor 220, such as (but not limited to) pulse width modulation, analog-to-digital conversion, digital-to-analog conversion, timers, counters, clocks, switch-mode power supplies, universal serial bus interfaces and controllers, controller area network interfaces and controllers, transmitters, receivers, transceivers, universal asynchronous receivers and transceivers, local interconnect network bus interfaces, inter-integrated circuit interfaces, serial peripheral interfaces, display drivers, graphics processors, charging time measurement units, digital signal processors, voltage protectors, boundary scanners, sample and hold circuits, quadrant encoder interfaces, encryption and decryption circuits, direct memory access controllers, configurable logic units, flip-flops, comparators, operational amplifiers, programmable gain amplifiers, voltage references, current bias generators, current sinks, or current sources. Processor peripherals can be included in the same die as the processor. Instructions 212 can be provided to modify data to be used by such peripherals by accessing a given memory location 232. Memory location 232 can be included in or adjacent to peripheral X 222. Processor 220 can include any suitable memory for use by processor 220, such as memory 224. Furthermore, memory 224 can be included in or adjacent to processor 220. Processor 220 accesses memory 224 much faster than processor 220 accesses memory 230.

[0024] When executing software 204, processor 208 can determine that the RMW operation of instruction 212 will be executed on a processor peripheral device of the target processor (such as peripheral device X 222 of processor 220). This determination can be made with reference to a memory location targeted by instruction 212, which may be a special function register (SFR) of the processor peripheral device. Based on the determination that the RMW operation will be executed on the processor peripheral device, processor 208 can translate instruction 212 into instruction 214 when executing software 204. Instruction 214, when executed by processor 220, can be configured to cause the processor peripheral device specified by the memory location of instruction 212 to atomically execute the RMW operation of instruction 212. Therefore, when executing software 204, processor 208 can be configured to determine that instruction 212 targets a specific bit (specified as bit Y) of the memory location of the target peripheral device, and based on the determination that instruction 212 will perform an RMW operation and target bit Y, translate instruction 212 into instruction 214 to target the memory location using a mask that identifies bit Y.

[0025] When executing software 204, processor 208 can be configured to generate instruction 214 such that the RMW operation of instruction 212 is executed by the peripheral device specified by the memory location of instruction 212 in any suitable manner. When executing software 204, processor 208 can be configured to generate instruction 212 as a move instruction, such as a MOVL instruction. The MOVL instruction may include a mask that targets one or more bits manipulated by the original instruction 212, specified by Y. The MOVL instruction may include a sideband function. The sideband function may include generating a signal that directs the function to the target. When used in conjunction with a mask, the sideband function may be bit-specific, affecting only certain bits identified by the mask. The sideband function may instruct the peripheral device to perform an RMW operation on the bits of the memory location according to the mask. The sideband function may be specified by a bit code and may identify the operation to be performed by instruction 212 on one or more bits specified by Y, such as set, clear, toggle, "AND", "OR", or "XOR". For example, sideband function code 000 can specify a bit set (BSET) operation; 001 can specify a bit clear (BCLR) operation; 010 can specify a bit toggle (BTOG) operation; 011 can specify an AND operation; 100 can specify an OR operation; and 101 can specify an XOR operation. Instruction 214 can specify a memory location that can be read by peripheral device X 222 to retrieve other contents of instruction 214, such as the mask and sideband functions.

[0026] For example, processor 208 may be configured to generate instruction 214 to include MOVL instructions when executing software 204, the MOVL instructions having a mask specifying one or more affected bits Y, as well as sideband functionality.

[0027] When executing software 204, processor 208 can be configured to specify MOVL instructions to move the mask and sideband functionality to any suitable peripheral memory location. In one example, processor 208 can be configured to specify MOVL instructions to move the mask values ​​and sideband functionality to a memory location of processor 220, rather than a memory location at peripheral device X 222. Therefore, the MOVL instructions can move the mask values ​​and sideband functionality to memory 224 instead of memory 230. The MOVL instructions can be configured to move the mask values ​​and sideband functionality to, for example, memory location 226, which could be the SFR of peripheral device X in memory 224 of processor 220. In another example not shown, memory location 226 could be located in memory (such as memory 230 of peripheral device X 222).

[0028] Peripheral device X 222 can be configured to read the contents written to memory location 226 by an MOVL operation. Based on these contents, peripheral device X 222 can be configured to perform an RMW operation specified by source instruction 212. Peripheral device X 222 can be configured to perform such an operation using any suitable mechanism, such as control logic 228. Control logic 228 can be implemented by analog circuitry, digital circuitry, or any suitable combination thereof. Control logic 228 can perform the RMW specified by a sideband function on one or more bits specified by a mask. Control logic 228 can be included in the peripheral bus bridge of peripheral device X 222, but can still be considered as included in peripheral device X 222. Control logic 228 can perform a read from memory location 232, use the mask and the operation specified by the sideband function, and write the result back to memory location 232. The RMW operation can be performed using atomic operations. Unlike processor 220, atomic operations with respect to the RMW operation can be atomic with respect to control logic 228. The atomic nature of an operation can include the fact that once initiated, the operation cannot be interrupted and can function as a single operation, but is implemented in multiple steps or cycles.

[0029] While and after performing the MOVL operation, processor 220 can continue to operate and execute other instructions. Therefore, for processor 220, performing the RMW operation results in the same operation latency as writing a literal value. This is in contrast to processor 220 executing instruction 212 and directly performing the RMW operation (which would have a longer latency).

[0030] As an example, code flow 202 may include instances of instructions 212 that specify the following pseudocode, which is given for illustrative purposes and is not considered as direct syntax for execution:

[0031] [OR,XOR,AND,BSET,BCLR,BTOG]BIT(Y)IN[SFRX]

[0032] When executing software 204, processor 208 can recognize instruction 212, which includes a valid opcode (OR, XOR, AND, BSET, BCLR, BTOG) and a valid target specification (SFRX - (in peripheral device X 222)). When executing software 204, processor 208 can generate a mask to match the length and position of a bit (Y). A bit (Y) can specify more than one bit. For an example bit 1 in the second-lowest bit position, this can be given as:

[0033] MASK[BYTE LENGTH]={0 0 0 0 0 0 1 0}

[0034] When executing software 204, processor 208 can recognize the sideband function corresponding to the opcode from instruction 212. This can be given as SIDEBAND[3], and instruction 214 can therefore be generated and given, for example:

[0035] MOVL(MASK+SIDEBAND,SFRX)

[0036] The combination of mask and sideband is moved to the peripheral memory location.

[0037] Figure 3 This is a diagram illustrating the latency of executing accelerated read, modify, and write instructions. A MOVL operation executed by processor 220 can take a single execution loop. However, an RMW operation of an RMW instruction can take significantly longer than a single execution loop. Therefore, by performing an RMW operation (which can be atomic) by moving a value executed by peripheral device 222, processor 220 does not experience the long latency that would occur if RMW operations were performed by processor 220.

[0038] Figure 4 This is an illustration of an exemplary method 400 for generating accelerated read, modify, and write instructions. Method 400 can be executed by any suitable mechanism, such as by instructions utilizing article 106. Figure 1 System 100 or processor 104, or Figure 2 The development machine 216, software 204, or processor 208 and memory 210 are used to execute the method. Method 400 may include... Figure 4 The steps may be more or fewer. The steps of method 400 may optionally be repeated, omitted, performed in a different order, performed recursively, performed in parallel with each other, or performed in parallel with other instances of method 400.

[0039] At position 405, the first input instruction to be executed in the code stream can be identified.

[0040] At 410, it can be determined that the first input instruction will perform a read-modify-write operation to target the memory location.

[0041] At 415, based on the determination that the first input instruction will perform a read-modify-write operation to target a memory location, the first input instruction can be converted into a second input instruction and the memory location can be targeted using a mask so that the atomic operation performs the read-modify-write operation.

[0042] Figure 5 This is a more detailed illustration of an exemplary method 500 for generating accelerated read, modify, and write instructions. Method 500 can be executed by any suitable mechanism, such as by instructions utilizing article 106. Figure 1 System 100 or processor 104, or by Figure 2 The development machine 216, processor 208, software 204, and memory 210 are used to execute the method. Method 500 may include... Figure 5 The steps may be more or fewer. The steps of method 500 may optionally be repeated, omitted, performed in a different order, performed recursively, performed in parallel with each other, or performed in parallel with other instances of method 500. Method 500 may fully or partially implement method 400.

[0043] At position 505, the first input instruction to be executed in the code stream can be identified. The first input instruction is a binary set, binary clear, binary toggle, AND, OR, or XOR instruction.

[0044] At 510, it can be determined that the first input instruction will perform a read-modify-write operation to target a specific bit of the memory location.

[0045] At point 515, it can be determined that the read-modify-write operation of the first input instruction will be performed by the processor peripheral device.

[0046] At 520, it can be determined that the first input instruction will target a specific bit of the memory location.

[0047] At 525, based on the determination that the first input instruction will perform a read-modify-write operation targeting a memory location and will be executed by a processor peripheral device, the first input instruction can be converted into a second input instruction. This may include steps 530 through 550.

[0048] At 530, a second input instruction can be implemented to target a memory location using a mask, causing an atomic operation to perform a read-modify-write operation. Based on the determination that the first input instruction will target a specific bit of the memory location, a mask can be used to identify that specific bit of the memory location.

[0049] At 535, a second input instruction can be implemented to cause atomic operations to be performed by the processor peripheral device using a mask.

[0050] At 540, the second input instruction may include bit-specific sideband functionality to instruct the processor peripheral device to perform a read-modify-write operation on a specific location according to a mask.

[0051] At point 545, the second input instruction can be implemented as a MOVL instruction to move the mask and bit-specific sideband functionality to an external memory location. The MOVL instruction will be executed with the operation delay of writing the literal value to the target processor.

[0052] Figure 6 This is an illustration of an exemplary method 600 for executing accelerated read, modify, and write instructions. Method 600 can be executed by any suitable mechanism, such as... Figure 2 The microcontroller 218, processor 220, peripheral device X 222, or control logic 228 are executed. Method 600 may include... Figure 6 The steps may be more or fewer. The steps of method 600 may optionally be repeated, omitted, performed in a different order, performed recursively, performed in parallel with each other, or performed in parallel with other instances of method 600.

[0053] At position 605, input instructions can be loaded onto the processor.

[0054] At 610, input instructions can be executed on the processor. This can include performing read-modify-write operations at memory locations using masks, such that atomic operations perform read-modify-write operations.

[0055] Figure 7 This is a more detailed illustration of an exemplary method 600 for executing accelerated read, modify, and write instructions. Method 700 can be executed by any suitable mechanism, such as... Figure 2 The microcontroller 218, processor 220, peripheral device X 222, or control logic 228 are executed. Method 700 may include... Figure 7 The steps of method 700 may be more or fewer. The steps of method 700 may optionally be repeated, omitted, performed in a different order, performed recursively, performed in parallel with each other, or performed in parallel with other instances of method 700. Method 700 may fully or partially implement method 500.

[0056] At point 705, input instructions can be loaded onto the processor. Input instructions can target specific bits of a memory location. Input instructions can be MOVL instructions that move a mask and bit-specific sidebands to an external memory location. Bit-specific sidebands can define RMW operations. RMW operations can be binary set, binary clear, binary toggle, AND, OR, or XOR operations.

[0057] At 710, at the processor, executable instructions cause atomic operations to be performed, including an RMW operation and the use of a mask. The mask can be used to identify specific bits of the memory location to which the RMW operation will be performed.

[0058] At instruction 715, starting from the execution of the instruction, the MOVL instruction can be used to move the mask and bit-specific sideband functionality to the peripheral memory location, causing atomic operations to be performed. Bit-specific sideband functionality can be used to instruct processor peripherals to perform read-modify-write operations on specific locations according to the mask, thereby causing the processor's peripherals to execute.

[0059] At 720, execution at the processor can be terminated, while execution at the peripheral device continues, causing the operation of writing to the processor's literal value to be delayed in order to execute the atomic instruction.

[0060] Examples of this disclosure may include an article of manufacture. The article of manufacture may include a non-transitory machine-readable medium. The medium may include instructions. These instructions, when read and executed by a processor, may cause the processor to determine that a first input instruction to be executed in a code stream will perform a read-modify-write operation, determine that the first input instruction will target a memory location, and, based on the determination that the first input instruction will perform a read-modify-write operation and the determination that the first input instruction will target a memory location, convert the first input instruction into a second input instruction to target the memory location with a mask so that an atomic operation performs the read-modify-write operation.

[0061] In conjunction with any of the above implementation schemes, the instruction can cause the processor to determine that the read-modify-write operation of the first input instruction will be performed by the processor peripheral device, and based on the determination that the read-modify-write operation of the first input instruction will be performed by the processor peripheral device, convert the first input instruction into a second input instruction so that the read-modify-write operation is performed by the processor peripheral device.

[0062] In combination with any of the above implementation schemes, the instruction can cause the processor to convert the first input instruction into a second input instruction by including bit-specific sideband functionality, so as to instruct the processor peripheral device to perform a read-modify-write operation on the bits of the memory location according to the mask.

[0063] In combination with any of the above implementation schemes, the instruction can cause the processor to implement the second input instruction as a MOVL instruction to move the mask and bit-specific sideband functionality to a peripheral memory location.

[0064] In conjunction with any of the above embodiments, the instruction may cause the processor to determine that the first input instruction will target a specific bit of a memory location, and based on the determination that the first input instruction will perform a read-modify-write operation and will target a specific bit of a memory location, to convert the first input instruction into a second input instruction to target the memory location using a mask. The mask can be used to identify the specific bit of the memory location.

[0065] In combination with any of the above implementation schemes, the first input instruction can be a binary set, binary clear, binary toggle, AND, OR, or XOR instruction.

[0066] In combination with any of the above implementation schemes, the second input instruction can target a memory location using a mask such that atomic operations are performed with a read-modify-write operation that is delayed in order to write a text value to the target processor.

[0067] Examples of this disclosure may include an article of manufacture. The article of manufacture may include a non-transitory machine-readable medium. The medium may include instructions. When read and executed by a processor, the instructions may cause the processor to perform a read-modify-write operation by using a mask at a memory location, such that atomic operations perform the read-modify-write operation.

[0068] Combining any of the examples above, atomic operations can be executed by the processor's peripheral devices, and instructions can cause the processor to cause the peripheral devices to perform atomic operations with a mask.

[0069] Combining any of the examples above, the instruction can cause the processor to issue a bit-specific sideband function to instruct the processor peripheral device to perform a read-modify-write operation based on a mask bitwise, causing the processor peripheral device to perform an atomic operation.

[0070] Combining any of the examples above, the instruction can cause the processor to use the MOVL instruction to move the mask and bit-specific sideband functionality to an external memory location to perform an atomic operation.

[0071] Combining any of the examples above, the input instruction can target a specific bit of a memory location, and the instruction will cause the processor to target the memory location with a mask, which is used to identify the specific bit of the memory location.

[0072] Combining any of the examples above, a read-modify-write operation can be a binary set, binary clear, binary toggle, AND, OR, or XOR operation.

[0073] Combining any of the examples above, the instruction can cause the processor to perform an atomic operation by delaying the operation of writing the processor's literal value.

[0074] Examples of this disclosure may include a microcontroller. A microcontroller may include a processor. A processor may be configured to execute any of the instructions in the examples above.

[0075] Examples of this disclosure may include peripheral circuitry. Peripheral circuitry may be implemented using analog circuitry systems, digital circuitry systems, control logic, or any suitable combination thereof. Peripheral circuitry may perform operations on behalf of a processor peripheral device to execute any of the instructions in the examples above.

[0076] Examples of this disclosure may include an apparatus. This apparatus may include any of the microcontroller and peripheral circuitry described in the examples above. The peripheral circuitry may be included within the microcontroller and may be decoupled from the microcontroller's processor.

[0077] Examples of this disclosure may include methods for performing operations of any of the above-described articles of manufacture, microcontrollers, processors, peripheral circuits, or devices.

[0078] Examples of this disclosure may include a method. This method may include loading an input instruction on a processor and executing the input instruction on the processor, the input instruction causing a read-modify-write operation, including using a mask at a memory location to cause an atomic operation to perform the read-modify-write operation.

[0079] Combining any of the examples above, a method may include causing the processor's processor peripherals to perform atomic operations using a mask.

[0080] Combining any of the examples above, a method may include causing a processor peripheral device to use a bit-specific sideband function to instruct the processor peripheral device to perform a read-modify-write operation based on a mask bitwise operation to perform an atomic operation.

[0081] Combining any of the examples above, a method may include using MOVL instructions to move a mask and bit-specific sideband functionality to an external memory location to execute atomic instructions.

[0082] Combining any of the examples above, the input instruction can target a specific bit of a memory location, and the method includes causing the execution of an atomic instruction by targeting the memory location with a mask used to identify the specific bit of the memory location.

[0083] Combining any of the examples above, a read-modify-write operation can be a binary set, binary clear, binary toggle, AND, OR, or XOR operation.

[0084] Combining any of the examples above, a method may include causing an operation at the processor to write to a literal value of the processor to delay the execution of an atomic instruction.

[0085] Examples of this disclosure may include a method. The method may include identifying a first input instruction to be executed in a code stream, determining that the first input instruction will perform a read-modify-write operation targeting a memory location, and based on determining that the first input instruction will perform a read-modify-write operation targeting a memory location, converting the first input instruction into a second input instruction to target the memory location with a mask such that an atomic operation performs the read-modify-write operation.

[0086] In combination with any of the above examples, the method may include determining that a read-modify-write operation of a first input instruction will be performed by a processor peripheral device, and based on determining that a read-modify-write operation of a first input instruction will be performed by a processor peripheral device, converting the first input instruction into a second input instruction such that the processor peripheral device performs an atomic operation using a mask.

[0087] Combining any of the above examples, converting a first input instruction into a second input instruction may include providing bit-specific sideband functionality to instruct processor peripherals to perform read-modify-write operations bit-by-bit according to a mask.

[0088] Combining any of the examples above, the method may include implementing the second input instruction as a MOVL instruction to move the mask and bit-specific sideband functionality to a peripheral memory location.

[0089] In combination with any of the above examples, the method may include determining that a first input instruction will target a specific bit of a memory location, and based on determining that the first input instruction will perform a read-modify-write operation and will target a specific bit of a memory location, converting the first input instruction into a second input instruction to target the memory location with a mask, the mask being used to identify the specific bit of the memory location.

[0090] Combining any of the above examples, the first input instruction can be a binary set, binary clear, binary toggle, AND, OR, or XOR instruction.

[0091] Combining any of the examples above, the second input instruction is executed with an operation delay for writing a literal value to the target processor, targeting the memory location with an available mask, so that the atomic operation performs a read-modify-write operation.

[0092] Although example implementations have been described above, other variations and implementations may be made by this disclosure without departing from the substance and scope of these implementations.

Claims

1. An article of manufacture comprising a non-transitory machine-readable medium, the medium including instructions that, when read and executed by a processor, cause the processor to: It is determined that the first input instruction in the code stream to be executed by the processor of the microcontroller will perform a read-modify-write operation; It is determined that the first input instruction will target a memory location included in the peripheral devices of the processor of the microcontroller; Based on determining that the first input instruction will execute the read-modify-write operation and determining that the first input instruction will target the memory location, the first input instruction is converted into a second input instruction to target the memory location with a mask so that the atomic operation performs the read-modify-write operation; It is determined that the read-modify-write operation of the first input instruction will be executed by the peripheral device of the processor of the microcontroller; as well as Based on the determination that the read-modify-write operation of the first input instruction will be executed by the peripheral device of the processor of the microcontroller, the first input instruction is converted into the second input instruction so that the read-modify-write operation is executed by the peripheral device of the processor of the microcontroller; as well as The first input instruction is converted into the second input instruction by including bit-specific sideband functionality to instruct the peripheral device of the processor of the microcontroller to perform the read-modify-write operation on the bits of the memory location according to the mask.

2. The article of manufacture according to claim 1, wherein the instructions cause the processor to implement the second input instruction as an MOVL instruction to move the mask and the bit-specific sideband function to the memory location.

3. The article of manufacture according to claim 1, wherein the instructions further cause the processor to determine that the first input instruction will target a specific bit of the memory location, and in order to convert the first input instruction into the second input instruction, the instructions further cause the processor to target the memory location with the mask based on the determination that the first input instruction will perform the read-modify-write operation and will target the specific bit of the memory location, the mask being used to identify the specific bit of the memory location.

4. The article of manufacture according to claim 1, wherein the first input instruction is a binary set, binary clear, binary switch, AND, OR, or XOR instruction.

5. The article of manufacture according to any one of claims 1 to 4, wherein the second input instruction targets the memory location with the mask such that the atomic operation performs the read-modify-write operation with an operational delay for writing a text value to the processor of the microcontroller.

6. A method for executing accelerated read, modify, and write instructions, the method comprising: Identify the first input instruction in the code stream to be executed by the processor of the microcontroller; The first input instruction is determined to perform a read-modify-write operation, targeting the memory location included in the peripheral devices of the processor of the microcontroller; Based on the determination that the first input instruction will execute the read-modify-write operation to target the memory location, the first input instruction is converted into a second input instruction to target the memory location with a mask so that the atomic operation performs the read-modify-write operation; as well as It is determined that the read-modify-write operation of the first input instruction will be executed by the peripheral device of the processor of the microcontroller; The conversion of the first input instruction into the second input instruction includes, based on determining that the read-modify-write operation of the first input instruction will be executed by the peripheral device of the processor of the microcontroller, converting the first input instruction into the second input instruction such that the atomic operation is executed by the peripheral device of the processor of the microcontroller using the mask; Converting the first input instruction into the second input instruction includes providing bit-specific sideband functionality to instruct the peripheral device to perform the read-modify-write operation bit-by-bit according to the mask.

7. The method of claim 6, wherein the method comprises implementing the second input instruction as an MOVL instruction to move the mask and the bit-specific sideband function to the memory location.

8. The method of claim 6, the method comprising determining that the first input instruction will target a specific bit of the memory location, wherein converting the first input instruction into the second input instruction comprises, based on determining that the first input instruction will perform the read-modify-write operation and will target the specific bit of the memory location, converting the first input instruction into the second input instruction to target the memory location with the mask, the mask being used to identify the specific bit of the memory location.

9. The method of claim 6, wherein the first input instruction is a binary set, binary clear, binary toggle, AND, OR, or XOR instruction.

10. The method of claim 6, wherein the second input instruction is executed with an operational delay for writing a text value to the processor of the microcontroller to target the memory location with the mask, such that the atomic operation performs the read-modify-write operation.

11. An article of manufacture comprising a non-transitory machine-readable medium, the medium comprising instructions that, when read and executed by a processor, cause the processor to execute a first input instruction, the first input instruction performing a read-modify-write operation by using a mask at a memory location of a peripheral device of a microcontroller such that an atomic operation performs the read-modify-write operation; in: The atomic operations will be performed by the peripheral devices of the microcontroller; The instruction will cause the processor to cause the peripheral device of the microcontroller to perform the atomic operation using the mask; the instruction will cause the processor to cause the peripheral device of the microcontroller to perform the atomic operation by issuing a second input instruction including bit-specific sideband functionality to instruct the peripheral device of the microcontroller to perform the read-modify-write operation bit-by-bit according to the mask.

12. The article of manufacture of claim 11, wherein the instructions cause the processor to perform the atomic operation by moving the mask and the bit-specific sideband function to the memory location using MOVL instructions.

13. The article of manufacture of claim 11, wherein the input instruction targets a specific bit of the memory location, and the instruction causes the processor to target the memory location with the mask, the mask being used to identify the specific bit of the memory location.

14. The article of manufacture according to claim 11, wherein the read-modify-write operation is a binary set, binary clear, binary switch, AND, OR, or XOR operation.

15. The article of manufacture of claim 11, wherein the instructions cause the processor to perform the atomic operation by causing an operation delay in writing the text value of the processor.

16. A method for executing accelerated read, modify, and write instructions, the method comprising: Load the first input instruction onto the processor; The first input instruction is executed on the processor, the first input instruction causing a read-modify-write operation, including using a mask on the memory location of the microcontroller's peripheral device to cause an atomic operation to perform the read-modify-write operation; Cause the peripheral device to perform the atomic operation using the mask; and This causes the peripheral device to perform the atomic operation using a second input instruction that includes bit-specific sideband functionality, instructing the peripheral device to perform the read-modify-write operation bit-by-bit according to the mask.

17. The method of claim 16, the method comprising moving the mask and the bit-specific sideband functionality to the memory location using MOVL instructions to cause the atomic operation to be performed.

18. The method of claim 16, wherein the input instruction targets a specific bit of the memory location, and the method includes causing the atomic operation to be performed by targeting the memory location with the mask used to identify the specific bit of the memory location.

19. The method of claim 16, wherein the read-modify-write operation is a binary set, binary clear, binary toggle, AND, OR, or XOR operation.

20. The method of claim 16, wherein the method includes performing the atomic operation by causing an operational delay at the processor to write a literal value of the processor.

Images