A circuit verification method and device based on automatic test vector generation

Abstract

A circuit verification method and device based on automatic test vector generation. In the circuit verification method, a target line in a circuit under test is subjected to the following: determining a first logic cone to be detected in a fan-out logic cone corresponding to the target line (S701); determining a second logic cone to be detected in a fan-in logic cone corresponding to the target line according to the first logic cone (S702); generating a first CNF based on the first logic cone and the second logic cone, and detecting the target line by using the first CNF to obtain a first detection result (S703); and if the first logic cone is a partial region in the fan-out logic cone and the first detection result satisfies a first set condition corresponding to the first logic cone, determining a first verification result of the target line according to the first detection result (S704). The circuit verification method and device can reduce the amount of calculation and improve the verification efficiency.

Description

Technical Field

[0001] This application relates to the field of chip verification, and in particular to a circuit verification method and apparatus based on automatic test vector generation. Background Technology

[0002] With the rapid development of semiconductor technology, larger-scale integrated circuits can be integrated on smaller components, and the enhanced chip manufacturing capabilities have provided more possibilities for the development of smart devices.

[0003] Currently, mainstream central processing units (CPUs) have reached 7-14 nanometers in manufacturing process, with some under development reaching 4nm or even higher. More advanced manufacturing processes allow for the integration of more transistors within the CPU and graphics processing unit (GPU), enabling processors to offer more functionality and higher performance. Simultaneously, these processes allow for further reduction in the core area of ​​the processor, meaning more CPUs and GPUs can be manufactured on the same wafer size. New materials and processes enhance product performance, making more complex electronic devices possible. However, their increased difficulty in control and the accompanying larger-scale integrated circuits present greater challenges to chip testing, thus reducing production yield and increasing manufacturing costs.

[0004] After the chip circuit design is completed, the chip circuit needs to be verified to check for defects. Automatic test pattern generation (ATPG) technology is one of the important techniques that discovers circuit defects and promotes yield improvement by generating test vectors. In the experiment, the test vector is used as the hypothetical input to the circuit under test (CUT). If the output value does not conform to the expectation, a fault or defect is considered to have been found.

[0005] A traditional ATPG testing method is based on the satisfiability (SAT) algorithm. When performing ATPG testing based on SAT, each line of the circuit under test (TUT) needs to be tested. Each line is the connection between two gate circuits in the TUT. A conjunctive normal form (CNF) is generated for each line and solved. The CNF for each line is generated based on the circuit structure and circuit propagation characteristics. After generating the CNF, it is input into the SAT solver for solving. The SAT solver is a black-box solver; after inputting the CNF, the test results can be directly obtained. Specifically, the test results for each line include two types: hard-to-detect faults and detectable faults. Hard-to-detect faults indicate that regardless of the input value given to the TUT, the same output value will be obtained. In this case, it is necessary to determine whether the tested line is redundant. Detectable faults are circuit faults that, within a set time period, can be determined based on the output value of the TUT after assuming the input value. When the SAT solver finds a detectable fault, it can also output a test vector, which can be used to detect circuit faults.

[0006] As the complexity of the circuit structure of the circuit under test increases, the time required to generate the CNF (Card Notation) also increases. For example, for a circuit under test with tens of thousands of gates, the time to generate the CNF during serial computation is much longer than the time to solve the CNF, increasing the verification time of the chip circuit and reducing the efficiency of chip circuit verification. Summary of the Invention

[0007] This application provides a circuit verification method and apparatus based on automatic test vector generation, which is used to improve the detection efficiency of chip circuits.

[0008] In a first aspect, embodiments of this application provide a circuit verification method based on automatic test vector generation, the method comprising:

[0009] The following process is performed on a target line in the circuit under test, wherein the circuit under test includes multiple lines, any one of which is a connection between two connected gate circuits, and the target line is any one of the multiple lines: A first logic cone to be tested is determined in the fan-out logic cone corresponding to the target line; wherein the fan-out logic cone is the region composed of gate circuits that pass from the target line to the output terminal of the circuit under test; Based on the first logic cone, a second logic cone to be tested is determined in the fan-in logic cone corresponding to the target line; wherein the fan-in logic cone is the region composed of gate circuits that pass from the input terminal of the circuit under test to the target line, and the second logic cone is the region composed of gate circuits in the fan-in logic cone that affect the output value of the first logic cone; A first conjunction expression (CNF) is generated based on the first logic cone and the second logic cone, and the target line is tested using the first CNF to obtain a first detection result; wherein the first detection result is used to indicate the fault type of the target line; if the first logic cone is a partial region in the fan-out logic cone, and the first detection result satisfies a first set condition corresponding to the first logic cone, then a first verification result of the target line is determined based on the first detection result.

[0010] In the above method, a first logic cone to be tested is determined from the fan-out logic cones corresponding to the target line in the circuit under test, and a second logic cone is determined from the fan-in logic cones. A first CNF is generated based on the first and second logic cones. That is, in the circuit verification method based on ATPG provided in this application embodiment, CNFs are no longer directly generated based on all fan-out and all fan-in logic cones, thereby reducing the complexity of CNF generation and shortening the CNF generation time. The target line is detected using the first CNF to obtain a first detection result. If the first logic cone is a part of the fan-out logic cones, and the first detection result satisfies the first set condition corresponding to the first logic cone, then the first verification result of the target line is determined based on the first detection result. Through this method, the first verification result of the target line can be generated based on the first detection result corresponding to a part of the logic cones, reducing the amount of computation while ensuring the accuracy of the verification result, thereby improving the verification efficiency.

[0011] In one possible design, the method further includes: if the first logic cone is the entire region in the fan-out logic cone, then determining the first verification result based on the first detection result.

[0012] In one possible design, the method further includes: if the first logic cone is a partial region of the fan-out logic cone, and the first detection result does not meet the first set condition, then the first logic cone to be detected is re-determined in the fan-out logic cone; wherein the first logic cones determined in different instances are not completely the same.

[0013] With this design, when the first detection result does not meet the first set condition, the first logic cone can be redefined until the first detection result meets the first set condition. By successively determining the first logic cone and its corresponding first detection result, the method of incrementally dividing the first logic cone and performing detection is realized, which reduces the amount of computation, thereby reducing the time to generate CNF and improving efficiency.

[0014] In one possible design, determining the first logic cone to be detected in the fan-out logic cone corresponding to the target line includes: determining the first logic cone in the fan-out logic cone according to a preset initial depth value and a first step length value, wherein the initial depth value characterizes the distance between the target line and the gate circuit.

[0015] In one possible design, the first setting condition is that the fault type in the first detection result is a difficult-to-detect fault.

[0016] Through the above design, the first logic cone can be divided from the fan-out logic cone according to the depth. Since solving CNF is a SAT problem, when the first detection result corresponding to the CNF generated based on the first logic cone and its corresponding second logic cone is a hard-to-detect fault, it means that there is no solution that makes the proposition "assuming the target line has a fault" true. Therefore, the first verification result corresponding to the target line can be determined to be a hard-to-detect fault. It can be seen that the ATPG method provided in this application can obtain the verification result of the target line without solving the entire region of the fan-out logic cone and the fan-in logic cone, thus improving the verification efficiency.

[0017] In one possible design, determining the first logic cone to be detected within the fan-out logic cone corresponding to the target line includes:

[0018] The first logic cone is determined in the fan-out logic cone based on the preset number of output terminals and the second step size value.

[0019] In one possible design, the first detection result includes a fault type and a test vector, the test vector being used to detect circuit faults in the circuit under test; the first setting condition is that the fault type in the first detection result is a detectable fault.

[0020] Through the above design, the first logic cone can be determined from the fan-out logic cone based on the number of output terminals. Since solving CNF is a SAT problem, when the first detection result of the CNF generated based on the first logic cone and its corresponding second logic cone is a detectable fault, it means that there exists a solution that makes the proposition "assuming the target line has a fault" true. Then, it is not necessary to verify other parts of the fan-out logic cone except for the first logic cone. It is also possible to determine that the fault type of the target line is a detectable fault and to determine the test vector, thus achieving efficient verification of the target line fault.

[0021] In one possible design, the method further includes: determining a third logic cone to be detected in the fan-out logic cone; and determining a fourth logic cone to be detected in the fan-in logic cone, wherein the third logic cone is different from the first logic cone, and the fourth logic cone is a region in the fan-in logic cone composed of gate circuits that affect the output value of the third logic cone; generating a second CNF based on the third logic cone and the fourth logic cone, and using the second CNF to detect the target line to obtain a second detection result; wherein the second detection result is used to indicate the fault type of the target line; when the first verification result is not determined, if the third logic cone is a part of the fan-out logic cone, and the second detection result satisfies the second setting condition corresponding to the third logic cone, then the second verification result corresponding to the target line is determined according to the second detection result, and the detection of the target line using the first CNF is stopped; when the first verification result has been determined, the detection of the target line using the second CNF is stopped.

[0022] This design allows for simultaneous detection of the target line using two methods. For example, the first logic cone can be divided based on depth, and the third logic cone can be divided based on the number of output terminals; or the first logic cone can be divided based on the number of output terminals, and the third logic cone can be divided based on depth. When using both methods to detect the target line, once the verification result for one method is obtained, the detection thread for the other method can be stopped, further improving the efficiency of ATPG detection of the target line.

[0023] In one possible design, the first CNF includes at least one clause generated based on gates in the first logic cone and the second logic cone.

[0024] In one possible design, the detection of the target line using the first CNF includes: if the number of clauses contained in the first CNF is greater than or equal to a set threshold, performing satisfiability SAT on each of the at least one clause, and determining the SAT result of each clause; and taking the intersection of the SAT results of the at least one clause as the first detection result.

[0025] With this design, if the number of clauses contained in the first CNF is greater than or equal to a set threshold, it indicates that the first CNF is relatively complex. Instead of using the SAT black-box solution method, each clause contained in the first CNF is solved separately, and the solution result of at least one clause is used as the first detection result, so as to simplify the CNF solution process and reduce the time required for CNF solution.

[0026] In one possible design, the first CNF includes at least one target clause corresponding to at least one target sub-circuit in the first logic cone, and at least one target clause corresponding to at least one target sub-circuit in the second logic cone, wherein the target sub-circuit and the target clause correspond one-to-one; each target sub-circuit includes at least one gate circuit.

[0027] In one possible design, before determining the first logic cone to be detected in the fan-out logic cone corresponding to the target line, the method further includes: if the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than a first set threshold, then determining the target sub-circuit in the fan-in logic cone based on the gate circuits in the fan-in logic cone, and determining the target sub-circuit in the fan-out logic cone based on the gate circuits in the fan-out logic cone.

[0028] In one possible design, the target sub-circuit is a fan-out region (FFR).

[0029] With the above design, when the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than the first set threshold, the FFR in the circuit under test can be identified to decompose the circuit under test, thereby simplifying the results of the circuit under test, making it easier to generate the first CNF, and enabling efficient detection even for large-scale circuits.

[0030] In one possible design, before determining the first logic cone to be detected in the fan-out logic cone corresponding to the target line, the method further includes: if the number of gates contained in the fan-in logic cone and the fan-out logic cone is greater than a second set threshold, then simplifying two equivalent gates in the fan-in logic cone and the fan-out logic cone into a single gate for generating a clause in CNF; wherein the second set threshold is less than the first set threshold, and the two equivalent gates are two gates with the same input and the same output.

[0031] The above design simplifies the equivalent gate circuits in the circuits corresponding to the fan-in logic cone and the fan-out logic cone, thereby reducing the number of gate circuits that need to be considered when generating the first CNF, thus reducing the difficulty of generating the first CNF and improving the efficiency of circuit verification.

[0032] Secondly, embodiments of this application provide an automatic test vector generation device, including a generation unit and a detection unit;

[0033] The generation unit is configured to perform the following process on a target line in the circuit under test, wherein the circuit under test includes multiple lines, any one of which is a connection between two connected gate circuits, and the target line is any one of the multiple lines: determining a first logic cone to be tested in the fan-out logic cone corresponding to the target line; wherein the fan-out logic cone is the region composed of gate circuits that pass from the target line to the output terminal of the circuit under test; determining a second logic cone to be tested in the fan-in logic cone corresponding to the target line based on the first logic cone; wherein the fan-in logic cone is the region composed of gate circuits that pass from the input terminal of the circuit under test to the target line, and the second logic cone is the region composed of gate circuits in the fan-in logic cone that affects the output value of the first logic cone; generating a first conjunction expression (CNF) based on the first logic cone and the second logic cone;

[0034] The detection unit is configured to: detect the target line using the first CNF to obtain a first detection result; wherein the first detection result is used to indicate the fault type of the target line; if the first logic cone is a part of the fan-out logic cone and the first detection result satisfies the first set condition corresponding to the first logic cone, then determine the first verification result of the target line based on the first detection result.

[0035] In one possible design, the detection unit is further configured to: determine the first verification result based on the first detection result if the first logic cone is the entire region of the fan-out logic cone.

[0036] In one possible design, the generation unit is further configured to: if the first logic cone is a partial region of the fan-out logic cone, and the first detection result does not meet the first set condition, then redetermine the first logic cone to be detected in the fan-out logic cone; wherein, the first logic cones determined in different instances are not completely identical.

[0037] In one possible design, the generation unit is specifically used to: determine the first logic cone in the fan-out logic cone according to a preset initial depth value and a first step length value, wherein the initial depth value characterizes the distance between the target line and the gate circuit.

[0038] In one possible design, the first setting condition is that the fault type in the first detection result is a difficult-to-detect fault.

[0039] In one possible design, the generation unit is specifically used to: determine the first logic cone in the fan-out logic cone according to the preset number of output terminals and the second step size value.

[0040] In one possible design, the first detection result includes a fault type and a test vector, the test vector being used to detect circuit faults in the circuit under test; the first setting condition is that the fault type in the first detection result is a detectable fault.

[0041] In one possible design, the generation unit is further configured to: determine a third logic cone to be detected in the fan-out logic cone; and determine a fourth logic cone to be detected in the fan-in logic cone, wherein the third logic cone is different from the first logic cone, and the fourth logic cone is a region in the fan-in logic cone composed of gate circuits that affect the output value of the third logic cone; and generate a second CNF based on the third logic cone and the fourth logic cone.

[0042] The detection unit is further configured to: detect the target line using the second CNF to obtain a second detection result; wherein the second detection result is used to indicate the fault type of the target line; when the first verification result is not determined, if the third logic cone is a part of the fan-out logic cone, and the second detection result satisfies the second setting condition corresponding to the third logic cone, then the second verification result corresponding to the target line is determined according to the second detection result, and the detection of the target line using the first CNF is stopped; when the first verification result has been determined, the detection of the target line using the second CNF is stopped.

[0043] In one possible design, the first CNF includes at least one clause generated based on gates in the first logic cone and the second logic cone.

[0044] In one possible design, the detection unit is specifically used to: if the number of clauses contained in the first CNF is greater than or equal to a set threshold, perform satisfiability SAT on the at least one clause respectively, and determine the SAT solution result of each clause; and take the intersection of the SAT solution results of the at least one clause as the first detection result.

[0045] In one possible design, the first CNF includes at least one target clause corresponding to at least one target sub-circuit in the first logic cone, and at least one target clause corresponding to at least one target sub-circuit in the second logic cone, wherein the target sub-circuit and the target clause correspond one-to-one; each target sub-circuit includes at least one gate circuit.

[0046] In one possible design, the automatic test vector generation device further includes a circuit decomposition unit, which is configured to: before the generation unit determines the first logic cone to be detected in the fan-out logic cone corresponding to the target line, if the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than a first set threshold, determine the target sub-circuit in the fan-in logic cone based on the gate circuits in the fan-in logic cone, and determine the target sub-circuit in the fan-out logic cone based on the gate circuits in the fan-out logic cone.

[0047] In one possible design, the target sub-circuit is a fan-out region (FFR).

[0048] In one possible design, the automatic test vector generation device further includes a circuitized simplification element, which is used to: before the generation unit determines the first logic cone to be tested in the fan-out logic cone corresponding to the target line, if the number of gates contained in the fan-in logic cone and the fan-out logic cone is greater than a second set threshold, then simplify two equivalent gates in the fan-in logic cone and the fan-out logic cone into a single gate for generating a clause of CNF; wherein the second set threshold is less than the first set threshold, and the two equivalent gates are two gates with the same input and the same output.

[0049] Thirdly, embodiments of this application provide an automatic test vector generation apparatus, including at least one processor coupled to at least one memory, the at least one processor being used to read a computer program stored in the at least one memory to execute the method provided in the first aspect above.

[0050] Fourthly, embodiments of this application also provide a chip connected to a memory, the chip being used to read and execute a software program stored in the memory, and to execute the method provided in any of the above aspects.

[0051] Fifthly, embodiments of this application also provide a chip system including a processor for supporting a computer device in implementing the methods provided in any of the above aspects. In one possible design, the chip system further includes a memory for storing programs and data necessary for the computer device. The chip system may be composed of chips or may include chips and other discrete devices.

[0052] Sixthly, embodiments of this application also provide a computer program that, when run on a computer, causes the computer to perform the methods provided in any of the above aspects.

[0053] In a seventh aspect, embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a computer, causes the computer to perform the method provided in any of the above aspects. Attached Figure Description

[0054] Figure 1 This is a simple circuit diagram;

[0055] Figure 2 This is a schematic diagram of a fan-out node;

[0056] Figure 3 This is a schematic diagram of a fanless region FFR;

[0057] Figure 4 This is a schematic diagram of a logic cone;

[0058] Figure 5 This is a schematic diagram of a fan-in logic cone and a fan-out logic cone;

[0059] Figure 6a This is a schematic diagram of the solution process of a D algorithm;

[0060] Figure 6b This is a schematic diagram of the SAT algorithm solution process;

[0061] Figure 7 A flowchart of a circuit verification method based on automatic test vector generation provided in this application embodiment;

[0062] Figure 8 A schematic diagram of a fan-out logic cone corresponding to a target line and a first logic cone provided for embodiments of this application;

[0063] Figure 9 A schematic diagram illustrating a sequence decision calculation method provided in an embodiment of this application;

[0064] Figure 10 A schematic diagram illustrating a first logic cone partitioning method provided in an embodiment of this application;

[0065] Figure 11 A flowchart of a method for detecting target lines based on a first logical cone partitioning method provided in an embodiment of this application;

[0066] Figure 12 A schematic diagram illustrating a second method of partitioning the first logic cone as provided in an embodiment of this application;

[0067] Figure 13 A flowchart of a method for detecting target lines based on a second first logical cone partitioning method provided in an embodiment of this application;

[0068] Figure 14 A flowchart of a circuit verification method based on automatic test vector generation provided in this application embodiment;

[0069] Figure 15 A diagram showing the comparison between the circuit verification method based on automatic test vector generation provided in this application embodiment and the existing circuit verification method based on automatic test vector generation.

[0070] Figure 16 This is a schematic diagram of the structure of the automatic test vector generation device provided in the embodiments of this application;

[0071] Figure 17 This is a schematic diagram of another automatic test vector generation device provided in an embodiment of this application. Detailed Implementation

[0072] To facilitate understanding of the embodiments of this application, the following terms related to the embodiments of this application are introduced:

[0073] 1) Gate circuits: Unit circuits used to implement basic logic operations and compound logic operations are called gate circuits. Commonly used gate circuits include AND gate, OR gate, NOT gate, NAND gate, NOR gate, AND-OR-NOT gate, and XOR gate.

[0074] 2) A line refers to the connection between any two gate circuits in a circuit. For example, Figure 1 The diagram is a simple circuit diagram in which gate circuit a is connected to gate circuit b, and gate circuit a is also connected to gate circuit c. The connection between gate circuit a and gate circuit b, and the connection between gate circuit a and gate circuit c are the lines mentioned in the embodiments of this application.

[0075] 3) Fan-out: When a node is the output node of one logic gate and the input node of multiple logic gates, this node is called a fan-out node, such as... Figure 2 Node 'a' in the diagram is a fan-out node.

[0076] A fan-out free region (FFR) refers to the region that does not include the sub-circuits corresponding to fan-out nodes, for example, Figure 3 In the circuit shown, each triangular box contains an FFR.

[0077] 4) A logic cone refers to a cone-shaped region composed of multiple logic gates, such as... Figure 4This is a schematic diagram of a logic cone.

[0078] Fan-in logic cone refers to the region consisting of logic gates that the circuit passes through from the input terminal to the target line; fan-out logic cone refers to the region consisting of logic gates that the circuit passes through from the target line to the output terminal. Figure 5 This is a schematic diagram of a fan-in logic cone and a fan-out logic cone.

[0079] Generally, when verifying a circuit, the number of fan-out nodes and the depth of the logic cone both affect the difficulty of circuit testing. In particular, the more fan-out nodes and the deeper the logic cone, the longer the circuit verification time and the greater the difficulty.

[0080] 5) Automatic Test Pattern Generation (ATPG) is a programming language used to detect fault types in multiple lines of a circuit under test. When verifying a circuit using ATPG, the fault type of each line can be determined, such as whether it is a detectable fault or a difficult-to-detect fault. If the fault type is determined to be a detectable fault, the automatically generated test vectors are used to test the semiconductor device. The test vectors are sequentially loaded onto the device's input terminals, and the output signals are collected and compared with pre-calculated output vectors to determine the test results and detect circuit faults.

[0081] 6) Conjunctive normal form (CNF) is a standard form of propositional formulas, primarily used to solve logical judgments involving propositional formulas. The conjunctive form of a proposition is not unique. A propositional conjunctive form can be obtained through a truth table or through equivalent transformations. The propositional connectives that can be included in a CNF formula are AND, OR, and NOT.

[0082] 7) The satisfiability (SAT) problem determines whether there exists an interpretation that satisfies a given proposition. In other words, it asks whether the variables of a given propositional formula can be consistently replaced with the values ​​TRUE or FALSE. If the formula evaluates to TRUE, it is said to be satisfiable. If there is no assignment that can make the propositional formula TRUE, that is, if for all possible variable assignments the result of the propositional formula is FALSE, then the formula is said to be unsatisfiable.

[0083] 8) A netlist is a file used in circuit design to describe the interconnections between circuit components. It is generally a text file that follows a relatively simple tagging syntax.

[0084] A chip is an integrated circuit manufactured on the surface of a semiconductor wafer, representing a method of circuit miniaturization. With advancements in chip manufacturing processes, larger-scale integrated circuits can be integrated onto smaller components, and this increased chip manufacturing capability provides more possibilities for the development of smart devices.

[0085] After the chip circuit design is completed, it needs to be verified to check for defects. The circuit contains multiple gate circuits; some large-scale chips may contain tens of thousands of gate circuits. The chip circuit verification process requires testing the lines between any two connected gate circuits. Possible circuit faults on each line are divided into two types: detectable faults and hard-to-detect faults. Detectable faults are those where, within a set time, given the input value of the circuit under test, the fault can be determined based on the output value of the circuit under test. Hard-to-detect faults are those where the same output value is obtained regardless of the input value given to the circuit under test. In this case, it is necessary to determine whether the line being tested is redundant.

[0086] In summary, verifying chip circuits requires ensuring both accuracy and efficiency / coverage. The ATPG (Automatic Test Detection) method can be used for circuit verification. ATPG can detect both detectable and difficult-to-detect faults in the circuit. When a fault is determined to be detectable, a test vector can be generated, which can then be used for fault detection. Two common ATPG testing methods are described below:

[0087] Method 1: ATPG detection method based on D algorithm

[0088] When performing ATPG detection based on the D algorithm, multiple lines in the circuit under test are tested separately. Assuming that any line is faulty, an initial set of assigned values ​​is selected and propagated from the circuit input to the circuit output according to the logic rules of the circuit under test. When the propagation reaches a point where there are no further circuit branches to continue and no conflict occurs, the implicit value of each connection line in the circuit under test can be inferred. Then, the location of the fault can be determined by comparing it with the truth table of the circuit under test. If a conflict occurs during the propagation process, that is, if a line is assumed to be faulty but no fault occurs during the propagation process, then a new line needs to be selected for testing.

[0089] Using the above method, the D algorithm can be stopped when a circuit fault is detected, indicating that the fault type corresponding to the currently detected line is a detectable fault. In actual fault detection, the allocation of fault detection for the circuit under test can be adjusted according to the detection results, such as prioritizing logically easier-to-detect faults. If the entire search space is exhausted or the set number of detections or detection time is exceeded without obtaining a solution for circuit fault detection, the D algorithm is stopped and the fault type corresponding to the currently detected line is considered a difficult-to-detect fault.

[0090] As described above, the detection efficiency of ATPG detection based on the D algorithm is affected by the choice of initial assignment values. An inappropriate initial assignment value can severely impact the detection time of the circuit under test. Furthermore, ATPG detection based on the D algorithm often requires exhausting the search space to determine if the fault type is a difficult-to-detect fault, resulting in long processing times and high costs.

[0091] Method 2: ATPG detection method based on SAT algorithm

[0092] When performing ATPG detection based on the SAT algorithm, each line of the circuit under test needs to be inspected. A Channel Function (CNF) is generated for each line and solved. The CNF for each line is generated based on the circuit structure and propagation characteristics. Taking the detection of the target line as an example, the CNF corresponding to the target line is generated, which can be used to describe the proposition "assuming the target line has a fault".

[0093] After generating the CNF corresponding to the target line, the CNF needs to be satisfied (SAT) solved. Specifically, solving the SAT for the CNF corresponding to the target line can be understood as determining whether there exists a set of variable values ​​that makes the proposition "assuming the target line has a fault" true. The result of the SAT solution for the CNF corresponding to the target line can be either satisfied or unsatisfiable. When the result of the SAT solution for the CNF corresponding to the target line is satisfied, it means that there exists a set of variable values ​​that makes the proposition "assuming the target line has a fault" true, and the fault type of the target line is a detectable fault. At this time, the determined set of variable values ​​can be used as test vectors. When detecting circuit faults in the circuit under test, the test vectors can be used as input values ​​of the circuit under test to obtain the output values ​​of the circuit under test. By comparing the accurate output values ​​with the actual output values ​​of the circuit under test, the circuit fault can be detected. When the result of SAT solving the CNF corresponding to the target line is unsatisfactory, it means that there is no set of variable values ​​that can make the proposition "assuming the target line has a fault" true. In other words, no matter what input values ​​are given, the proposition "assuming the target line has a fault" is not true. Then the fault type of the target line is a hard-to-detect fault. At this time, it is necessary to check whether the target line is a redundant line.

[0094] In practice, solving the CNF corresponding to the target line using the Satisfaction-Based Test (SAT) algorithm can be done by inputting the CNF into a black-box solver. After inputting the CNF corresponding to the target line into the SAT solver, the SAT solution result can be directly obtained. Specifically, the SAT solver can output that the SAT solution result of the CNF corresponding to the target line is satisfactory and output test vectors, in which case the fault type of the target line can be determined as a detectable fault; or the SAT solver can output that the SAT solution result of the CNF corresponding to the target line is unsatisfactory, in which case the fault type of the target line can be determined as a difficult-to-detect fault.

[0095] Figure 6a This is a schematic diagram of the solution process of a D algorithm. Figure 6b This is a schematic diagram illustrating the solution process of the SAT algorithm. Both the D algorithm and the SAT algorithm are branch-and-bound algorithms; however, the D algorithm is a heuristic algorithm, while the SAT algorithm is a symbolic computation method. See [link to documentation]. Figure 6a Although both rely on a tree search process, in the D algorithm, each branch of the tree represents a solution, such as... Figure 6a In the process of solving the D algorithm, one branch corresponds to Figure 6a The circuit shown represents a single value for a node. However, the SAT method, due to the nature of symbolic computation, allows each node to represent a set of solutions. (See reference...) Figure 6b The diagram illustrates the SAT algorithm, where the numbers in curly braces {} represent the indices of the four variables. For example, {1, 2, 3, 4} indicates the variables are {1, 1, 1, 1}, and {3, -4} indicates the third variable is 1, the fourth variable is 0, and the remaining variables can be either 1 or 0. Figure 6b As shown in the SAT algorithm solution process, each node can represent a set of solutions, which can contain multiple cases. Therefore, theoretically, the SAT method is more suitable for solving and judging difficult cases that approach global traversal.

[0096] However, as the complexity of the circuit structure under test increases, the time to generate CNFs during ATPG testing based on SAT also becomes increasingly longer. For example, for a circuit under test with tens of thousands of gates, the time to generate CNFs during serial computation is much longer than the time to solve CNFs, increasing the verification time of the chip circuit and reducing the efficiency of chip circuit verification.

[0097] In summary, all commonly used ATPG detection methods currently available suffer from low efficiency.

[0098] To address the aforementioned issues, this application provides a circuit verification method based on automatic test pattern generation (ATPG) to improve circuit verification efficiency.

[0099] Figure 7 This document provides a flowchart of an ATPG-based circuit verification method according to an embodiment of this application. This ATPG-based circuit verification method can be applied to ATPG devices and also to ATPG modules within chips. For example, the ATPG module can be an ATPG module in an electronic design automation (EDA) process. The following describes the ATPG-based circuit verification method provided in this application using an ATPG device as an example. In specific implementation, the ATPG device needs to detect each line in the circuit under test; that is, it needs to traverse every line in the circuit under test. The following describes the ATPG-based circuit verification method provided in this application using the detection of a target line as an example. The target line is any one of the multiple lines included in the circuit under test. When the ATPG device detects the target line, it performs the following steps:

[0100] S701: The ATPG device determines the first logic cone to be detected in the fan-out logic cone corresponding to the target line.

[0101] Optionally, Figure 8 A schematic diagram of a fan-out logic cone corresponding to a target line and a first logic cone provided in an embodiment of this application, referencing... Figure 8 In (a), the fan-out logic cone is the region formed by the gate circuits that the target line passes through to the output terminal of the circuit under test. Therefore, it can be assumed that the value of the target line may affect the input value and / or output value of each gate circuit in the fan-out logic cone.

[0102] In one optional implementation, when the ATPG device of this application determines the first logic cone from the fan-out logic cone corresponding to the target line, it can determine a portion of the depth region from the fan-out logic cone as the first logic cone. For example, referring to... Figure 8 In (b), logic cone a is a partial depth region within the fan-out logic cone, so logic cone a can be used as the first logic cone; or the ATPG device can further determine the region containing a portion of the output terminals from the fan-out logic cone as the first logic cone, for example, see reference. Figure 8 In (c), logic cone b is the region of the fan-out logic cone that contains part of the output terminal, so logic cone b can be used as the first logic cone.

[0103] It should be noted that in the circuit verification method based on ATPG provided in this application embodiment, when detecting the target line, the ATPG device can first take a portion of the fan-out logic cone corresponding to the target line as the first logic cone. If the first detection result corresponding to the target line cannot be determined based on the first logic cone, the first logic cone can be re-divided, such as by increasing the area of ​​the first logic cone, thereby achieving an incremental division method. It is understood that when the ATPG device performs multiple divisions of the first logic cone, the largest first logic cone that can be determined is the entire area of ​​the fan-out logic cone, for example... Figure 8 As shown in (d), when determining the first logic cone according to depth, the largest first logic cone that the ATPG device can determine is the entire region of the fan-out logic cone.

[0104] S702: The ATPG device determines the second logic cone to be detected in the fan-in logic cone corresponding to the target line based on the first logic cone.

[0105] refer to Figure 8 The fan-in logic cone is the region consisting of gate circuits that pass from the input terminal of the circuit under test to the target line. The ATPG device can determine the region consisting of gate circuits that affect the output value of the first logic cone from the fan-in logic cone, and use the determined region as the second logic cone. The second logic cone can be a part or all of the region in the fan-in logic cone.

[0106] The ATPG device in this application embodiment can determine the fault type of the target line by detecting the gate circuits contained in the first logic cone and the second logic cone.

[0107] S703: The ATPG device generates a first conjunction expression CNF based on the first logic cone and the second logic cone, and uses the first CNF to detect the target line to obtain a first detection result; wherein, the first detection result is used to indicate the fault type of the target line.

[0108] Optionally, the ATPG device can detect the target line using the first CNF by performing a SAT solution on the first CNF, determining the SAT solution result of the first CNF, and determining the first detection result based on the SAT solution result of the first CNF. As described above regarding the SAT solution problem, the SAT solution result of the first CNF may be unsatisfiable or satisfiable. If the SAT solution result of the first CNF is unsatisfiable, it means that regardless of the input value of the circuit under test, the proposition "assuming a fault exists in the target line" corresponding to the first CNF does not hold. In this case, the first detection result determined based on the solution result of the first CNF is a difficult-to-detect fault. If the SAT solution result of the first CNF is satisfiable, it means that there exists a set of vector values. When this set of vector values ​​is used as the input value of the circuit under test, the proposition "assuming a fault exists in the target line" corresponding to the first CNF can be satisfied. In this case, the first detection result determined based on the solution result of the first CNF is a detectable fault, and the determined set of vector values ​​can be used as test vectors, which can be used to detect faults in the circuit under test.

[0109] Optionally, the first CNF includes at least one clause, which is generated based on the gates in the first and second logic cones. Each clause can represent a constraint. The first CNF, consisting of at least one clause, can be used to describe the proposition "assuming the target line has a fault". When the SAT solution of the first CNF is satisfiable, it means that there exists a set of vectors that makes the first CNF true, that is, there exists a set of vectors that makes the proposition "assuming the target line has a fault" true. In this case, the first detection result is a detectable fault, and when the target line has a fault, the fault can be detected. When the SAT solution of the first CNF is unsatisfiable, it means that there does not exist a set of vectors that makes the first CNF true, that is, the proposition "assuming the target line has a fault" is not true. In this case, the first detection result is a difficult-to-detect fault, and it is necessary to check whether the target line is a redundant line.

[0110] To further improve the efficiency of target line detection, this application embodiment also provides a SAT solving method. Specifically, before solving the first CNF, it is determined whether the number of clauses contained in the first CNF is less than a set threshold. When the number of clauses contained in the first CNF is less than the set threshold, the first CNF is input to the SAT solver, and the SAT solving result output by the SAT solver is obtained.

[0111] When the number of clauses contained in the first CNF is greater than or equal to a set threshold, a looking-ahead sequential decision-making method can be used to solve the first CNF. This method is an online prediction optimization method that can predict the final decision in advance through optimized intermediate results. For example, Figure 9is a schematic diagram of a sequential decision method, in which at least one clause is solved in parallel, and the SAT solution result of each clause is determined. It can be understood that the first CNF may include multiple clauses, each clause corresponds to a constraint condition, and the result obtained by performing SAT solving on the first CNF is a result that satisfies all constraint conditions corresponding to all clauses. When only one of the clauses is subjected to SAT solving, the obtained solution result only satisfies one constraint condition. That is, the result of SAT solving on one clause is an intermediate result, which is not the SAT solving result corresponding to the first CNF, but the range of the SAT solving result obtained by performing SAT solving on one clause is larger than that of the SAT solving result of the first CNF. Therefore, the SAT solving result of each clause is an upper bound of the SAT solving result of the first CNF. After performing SAT solving on at least one clause included in the first CNF, the ATPG device can simplify the SAT solving results of at least one clause, for example, the intersection of the SAT solving results of at least one clause is taken as the SAT solving result of the first CNF.

[0112] Optionally, when the looking-ahead sequential decision method is used to solve the first CNF, the ATPG device may also extract clauses in the first CNF for solving by means of sampling. For example, when the first CNF includes N clauses, M clauses may be randomly sampled for parallel solving, where M<N, and the remaining N-M clauses are solved at the same time, and then the intersection of the obtained multiple SAT solving results is used as the SAT solving result of the first CNF. In actual calculation, we can also extract K clauses at the same time to enhance the result of online prediction, where K is an integer greater than 1.

[0113] S704: If the first logic cone is a partial area in the fan-out logic cone, and the first detection result satisfies the first setting condition corresponding to the first logic cone, the ATPG device determines the first verification result of the target line according to the first detection result.

[0114] In an optional embodiment, when the first logic cone is a partial area in the fan-out logic cone, and the first detection result satisfies the first setting condition corresponding to the first logic cone, the ATPG device may determine the first verification result of the target line according to the first detection result, for example, using the first detection result as the first verification result.

[0115] It is understandable that when detecting a target line, directly generating a CNF based on the fan-out and fan-in logic cones corresponding to the target line can ensure the accuracy of the detection results. However, as mentioned earlier, when the circuit structure is complex, generating a CNF based on the fan-out and fan-in logic cones and performing SAT on the CNF is time-consuming, resulting in low circuit verification efficiency. Therefore, this application proposes that a first logic cone can be determined from the fan-out logic cones. When the first logic cone is a part of the fan-out logic cones, the first verification result cannot be directly generated based on the first detection result. Instead, a first set condition needs to be set. When the first detection result meets the first set condition, the first verification result is generated based on the first detection result to ensure the accuracy of the first verification result.

[0116] It should be noted that different partitioning methods of the first logic cone can result in different first logic cones, and the first logic cones under different partitioning methods correspond to different first setting conditions. The first logic cones obtained under different partitioning methods and the methods for determining the first verification result in the embodiments of this application are described below:

[0117] Method 1: The ATPG device determines the first logic cone in the fan-out logic cone based on the initial depth value and the first step length value.

[0118] It should be noted that the initial depth value refers to the distance between the target line and the gate circuit.

[0119] like Figure 10 This is a schematic diagram of the first logic cone partitioning method. Optionally, when the ATPG device determines the fault type of the target line, it can first partition a region with a depth equal to the initial depth value from the first logic cone as the first logic cone. For example, the partitioned first logic cone can be... Figure 10 The logic cone a in the first logic cone; the ATPG device uses the region composed of gate circuits that affect the output value of the first logic cone in the fan-in region as the second logic cone. A first CNF is generated based on the first and second logic cones, and the first CNF is solved using SAT to obtain the first detection result.

[0120] Under the partitioning method provided in Method 1, the first setting condition corresponding to the first logic cone is: the fault type in the first detection result is a difficult-to-detect fault, which can also be understood as the SAT solution result of the first CNF being unsatisfactory; that is, when the fault type in the first detection result is a difficult-to-detect fault, the ATPG device can determine the first verification result of the target line based on the first detection result, such as the ATPG device can use the first detection result as the first verification result.

[0121] Understandably, performing a Satisfaction Test (SAT) on the first CNF (Center for Functional Levels) determines whether there exists a set of vector values ​​that makes the result of the first CNF true, thus validating the proposition "assuming the target line has a fault." When the SAT result of the first CNF is unsatisfactory, it means there is no set of vector values ​​that makes the result of the first CNF true. Therefore, even increasing the depth of the first logic cone cannot determine a set of vector values ​​that makes the result of the first CNF true. Thus, the first detection result of the target line based on the first CNF corresponding to the current first logic cone can be considered the first verification result of the target line. This method ensures the accuracy of the target line detection result without generating CNFs for the entire fan-in and fan-out regions, thereby improving the efficiency of circuit verification.

[0122] Furthermore, when the first detection result does not meet the first set condition, that is, when the SAT solution result of the first CNF is satisfactory, the ATPG device can return to the step of determining the first logic cone and the second logic cone. At this time, the ATPG device can determine the first logic cone from the fan-out logic cone based on the initial depth value and the first step length value. For example, by adding a first step length value to the initial depth value to determine a depth value, the ATPG device will use the region corresponding to that depth value in the fan-out logic cone as the first logic cone, as shown in the reference. Figure 10 The first logic cone is determined to be logic cone b, thus completing the re-division of the first logic cone. Similarly, the region in the fan-out logic cone that affects the output value of the first logic cone is determined, and this region is used as the re-divided second logic cone. The first CNF is generated again based on the first and second logic cones, and the steps of detecting the target line based on the first CNF are repeated.

[0123] Optionally, the ATPG device can repeat the steps of determining the first logic cone and the second logic cone, and detecting the target line based on the first CNF, until the fault type in the first detection result is a difficult-to-detect fault; or when the first logic cone determined by the ATPG device is the entire area of ​​the fan-out logic cone, it is not necessary to judge whether the first detection result meets the first set condition again, and the first verification result can be determined directly based on the first detection result.

[0124] It should be noted that when the ATPG device redetermines the first logic cone, it can add a set number of first step length values ​​to the depth value of the first logic cone determined in the previous step. This allows for the determination of the first logic cone incrementally. Compared with the existing method of directly detecting the target line based on the fan-out and fan-in regions, this reduces the amount of computation and improves the efficiency of circuit verification.

[0125] The following example further illustrates the method for detecting target lines based on Method 1. Figure 11This is a flowchart of a method for detecting target lines based on method 1. The method may include the following steps:

[0126] S1101: The ATPG device determines the first logic cone from the fan-out logic cone and the second logic cone from the fan-in logic cone based on the initial depth value.

[0127] S1102: The ATPG device generates a first CNF based on a first logic cone and a second logic cone.

[0128] S1103: The ATPG device performs SAT calculation on the first CNF to obtain the first detection result.

[0129] S1104: The ATPG device determines whether the fault type in the first detection result is a difficult-to-detect fault; if yes, proceed to S1105; otherwise, proceed to S1106.

[0130] S1105: The first verification result of the ATPG device determining the target line is a difficult-to-detect fault.

[0131] S1106: The ATPG device determines whether the first logic cone is the entire region in the fan-out logic cone; if yes, proceed to S1107, otherwise proceed to S1108.

[0132] S1107: The ATPG device determines that the first verification result of the target line is a detectable fault and acquires the test vector.

[0133] S1108: The ATPG device re-determines the first logic cone from the fan-out logic cone based on the first step length value, and determines the second logic cone from the fan-in logic cone.

[0134] Method 2: The ATPG device determines the first logic cone in the fan-out logic cone based on the preset number of output terminals and the second step size value.

[0135] like Figure 12 This is a schematic diagram of the second method for dividing the first logic cone. Optionally, when the ATPG device determines the fault type of the target line, it can first divide the first logic cone into a region containing a preset number of output terminals as the first logic cone. For example, the divided first logic cone can be... Figure 12 The logic cone a in the first logic cone; the ATPG device uses the region composed of gate circuits that affect the output value of the first logic cone in the fan-in region as the second logic cone. A first CNF is generated based on the first and second logic cones, and the first CNF is solved using SAT to obtain the first detection result.

[0136] Under the partitioning method provided in Method 2, the first setting condition corresponding to the first logic cone is: the fault type in the first detection result is a detectable fault, which can also be understood as the SAT solution result of the first CNF is SAT; that is, when the first detection result is a detectable fault, the ATPG device can determine the first verification result of the target line based on the first detection result, such as the ATPG device can use the first detection result as the first verification result.

[0137] Understandably, performing a Satisfaction Test (SAT) on the first CNF (Center for Functional Linear Array) determines whether a set of vector values ​​exists that makes the result of the first CNF true. When the SAT result of the first CNF is satisfactory, it indicates the existence of a set of vector values ​​that makes the result of the first CNF true. A true result for the first CNF means that the proposition assuming a fault in the target line is valid. In other words, if the proposition that the target line is faulty is already valid within the current first logic cone, increasing the number of output terminals in the first logic cone will not change the result that "a set of vectors exists that makes the result of the first CNF true." Therefore, the first detection result of the target line based on the first CNF corresponding to the current first logic cone can be considered the first verification result of the target line. This method ensures the accuracy of the target line detection result without needing to generate CNFs for the entire fan-in and fan-out regions, thereby improving the efficiency of circuit verification.

[0138] Furthermore, when the first detection result does not meet the first preset condition, that is, when the SAT solution result of the first CNF is unsatisfactory, the ATPG device can return to the step of determining the first logic cone and the second logic cone. At this time, the ATPG device can determine the first logic cone from the fan-out logic cone based on a preset number of output terminals and a second step size value. For example, by adding a second step size value to the preset number of output terminals to determine a quantity value, the region of the fan-out area containing the output terminal with that data value is taken as the first logic cone, thereby completing the re-division of the first logic cone. For example, the re-divided first logic cone can be... Figure 12 Similarly, the ATPG device can determine the region in the fan-out logic cone that affects the output value of the first logic cone and use that region as the redefined second logic cone.

[0139] It should be noted that the first logic cone after the ATPG device is repartitioned may include the previously determined first logic cone; or the first logic cone after the ATPG device is repartitioned may not include the previously determined first logic cone, such as the first logic cone obtained after repartitioning being... Figure 12If the first logic cone c in the re-divided logic cone does not include the first logic cone determined in the previous step, the first logic cone can still be divided according to the preset number of output terminals when re-dividing the logic cone. That is, the second step value can be 0 at this time.

[0140] After redetermining the first logic cone and the second logic cone, the ATPG device can generate the first CNF again based on the first logic cone and the second logic cone, and repeat the step of detecting the target line based on the first CNF.

[0141] Optionally, the ATPG device can repeat the steps of determining the first logic cone and the second logic cone, and detecting the target line based on the first CNF, until the fault type in the first detection result is a detectable fault; or when the first logic cone determined by the ATPG device is the entire area of ​​the fan-out logic cone, or when all the determined first logic cones have traversed the entire area of ​​the fan-out logic cone, it is not necessary to determine whether the first detection result meets the first set condition again, and the first verification result can be determined directly based on the first detection result.

[0142] It should be noted that when the ATPG device redetermines the first logic cone, it can add a set number of second step values ​​to the number of output terminals of the first logic cone determined in the previous step. This allows for the determination of the first logic cone incrementally, which reduces the amount of computation and improves the efficiency of circuit verification compared to the existing method of directly detecting the target line based on the fan-out and fan-in regions.

[0143] The following example further illustrates the method for detecting target lines based on Method 2. Figure 13 This is a flowchart of a method for detecting target lines based on method 2. The method may include the following steps:

[0144] S1301: The ATPG device determines the first logic cone from the fan-out logic cone and the second logic cone from the fan-in logic cone based on a preset number of output terminals.

[0145] S1302: The ATPG device generates a first CNF based on a first logic cone and a second logic cone.

[0146] S1303: The ATPG device performs SAT calculation on the first CNF to obtain the first detection result.

[0147] S1304: The ATPG device determines whether the fault type in the first detection result is a detectable fault; if yes, proceed to S1305; otherwise, proceed to S1306.

[0148] S1305: The ATPG device determines that the first verification result of the target line is a detectable fault and acquires the test vector.

[0149] S1306: The ATPG device determines whether the first logic cone is the entire region of the fan-out logic cone or whether all first logic cones have traversed the entire region of the fan-out logic cone; if yes, proceed to S1307, otherwise proceed to S1308.

[0150] S1307: The first verification result of the ATPG device determining the target line is a difficult-to-detect fault.

[0151] S1308: The ATPG device re-determines the first logic cone from the fan-out logic cone based on the second step size value, and determines the second logic cone from the fan-in logic cone.

[0152] In one optional embodiment of this application, the ATPG device can employ a dual-thread method to detect the target line. One thread can detect the target line according to the method provided in Method 1, while the other thread can detect the target line according to the method provided in Method 2. Specifically, the ATPG device can initiate a first thread to determine a first logic cone and a second logic cone, thereby generating a first CNF to detect the target line and determine a first verification result. Simultaneously, the ATPG device can also initiate a second thread to determine a third logic cone and a fourth logic cone, and generate a second CNF based on the third and fourth logic cones. The target line is then detected based on the second CNF to determine a second verification result. The methods for determining the third and fourth logic cones in the second thread, and the methods for detecting the target line based on the second CNF, can be found in the implementations of Method 1 or Method 2 described above; repeated details will not be elaborated further. It should be noted that the methods for determining the first and third logic cones differ when the ATPG device employs a dual-thread method to detect the target line. Once one of the two threads determines the verification result, the other thread can be stopped. For example, if the first thread determines the first verification result first, the second thread can be stopped; or if the second thread determines the second verification result first, the first thread can be stopped.

[0153] Using the above method, the ATPG device can determine whether the fault type of the target line is a difficult-to-detect fault or a detectable fault through two threads. Once the verification result is determined by one thread, the detection of the target line can be terminated, further improving the efficiency of circuit verification.

[0154] As described above regarding the chip circuits, some chips contain large-scale integrated circuits, such as those integrating tens of thousands of gate circuits. For chips with large-scale circuits, this application embodiment can further decompose and / or simplify the circuits during verification. The circuit decomposition and simplification methods provided in this application embodiment are described below:

[0155] 1. Circuit decomposition processing method

[0156] Before determining the first logic cone to be detected from the fan-out logic cone, the ATPG device determines at least one target sub-circuit in the fan-in logic cone and at least one target sub-circuit in the fan-out logic cone if it determines that the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than a first set threshold. The target sub-circuit may be an FFR.

[0157] Optionally, the ATPG device determines that the number of gates contained in the fan-in logic cone and the fan-out logic cone is greater than a first preset threshold. Specifically, the ATPG device determines that the number of gates in the fan-in logic cone and the fan-out logic cone satisfies at least one of the following conditions:

[0158] Condition 1: The total number of gate circuits is greater than the first set threshold;

[0159] Condition 2: The number of fan-inlet circuits is greater than the first set threshold;

[0160] Condition 3: The number of fan-out door circuits is greater than the first set threshold.

[0161] The first set threshold can be an empirical value.

[0162] Optionally, after determining that the number of gates contained in the fan-in and fan-out logic cones is greater than a first set threshold, the ATPG device can identify the FFRs in the fan-in and fan-out logic cones and treat each FFR as a target sub-circuit. After determining the first and second logic cones, when generating the first CNF based on the gates within the first and second logic cones, the ATPG device can generate corresponding clauses for each target sub-circuit contained in the first and second logic cones, with one clause for each target sub-circuit. It is understood that the conditions for a fault to propagate to any output within an FFR are the same; therefore, the fault propagation of the root node within an FFR can be represented by a single clause. This method simplifies the generation of the first CNF, thereby reducing the time required for CNF generation and improving the efficiency of circuit verification.

[0163] 2. Circuit simplification methods

[0164] Before determining the first logic cone to be detected from the fan-out logic cone, if the number of gates contained in the fan-in logic cone and the fan-out logic cone is greater than a second set threshold, the ATPG device simplifies two equivalent gates in the fan-in logic cone and the fan-out logic cone into a single gate for generating a clause of CNF; wherein the two equivalent gates are two gates with the same input and the same output.

[0165] Optionally, the second set threshold can be less than the first set threshold. That is, in practice, it is not necessary to perform circuit decomposition and / or circuit simplification on all circuits. When the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than the second set threshold, circuit simplification is initiated. When the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than the first set threshold, circuit decomposition is initiated.

[0166] Optionally, the ATPG device determines that the number of gates contained in the fan-in logic cone and the fan-out logic cone is greater than a second preset threshold. Specifically, the ATPG device determines that the number of gates in the fan-in logic cone and the fan-out logic cone satisfies at least one of the following conditions:

[0167] Condition 1: The total number of gate circuits is greater than the second set threshold;

[0168] Condition 2: The number of fan-inlet circuits is greater than the second set threshold;

[0169] Condition 3: The number of fan-out door circuits is greater than the second set threshold.

[0170] The second set threshold can be an empirical value.

[0171] In one optional implementation, when simplifying the circuits corresponding to the fan-in and fan-out logic cones, the circuit can be converted from a gate-level netlist to a sum of product (SOP) format, constructing a hash table corresponding to the fan-in and fan-out logic cones. Initial circuit simplification is performed using a lookup method. Specifically, if the hash table indicates that two gates with the same input also have the same output, they can be considered equivalent. Further, a random pattern can be generated to evaluate the equivalence of two gates with the same input. For example, an accurate calculation can be performed using a SAT solver to determine if two gates are completely equivalent. After determining that two gates are equivalent, they can be simplified into a single gate for generating CNFs.

[0172] Optionally, the simplification process can be stopped after the number of gate circuits is reduced to less than or equal to a set threshold, or the simplification process can be stopped when there are no equivalent gate circuits in the circuit.

[0173] This method simplifies equivalent gate circuits in the circuits corresponding to the fan-in logic cone and the fan-out logic cone, thereby reducing the number of gate circuits that need to be considered when generating the first CNF, thus reducing the difficulty of generating the first CNF and improving the efficiency of circuit verification.

[0174] It should be noted that the circuit decomposition processing method can be executed by the circuit decomposition module in the ATPG device, and the circuit simplification processing method can be executed by the circuit simplification module in the ATPG device. Both the circuit decomposition module and the circuit simplification module can be plug-and-play modules.

[0175] The circuit verification method based on ATPG provided in this application will be further described below with a specific example. Figure 14 A flowchart of a circuit verification method based on ATPG provided for embodiments of this application is included, the method comprising the following steps:

[0176] S1401: The ATPG device determines the fan-out logic cone and fan-in logic cone corresponding to the target line currently being traversed.

[0177] S1402: The ATPG device determines whether the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than the first set threshold; if yes, proceed to S1403; otherwise, proceed to S1404.

[0178] S1403: The ATPG device determines the target sub-circuit in the fan-in logic cone and the target sub-circuit in the fan-out logic cone; wherein the target sub-circuit is FFR.

[0179] S1404: The ATPG device determines whether the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than the second set threshold; if yes, proceed to S1405; otherwise, proceed to S1406 and S1412.

[0180] S1405: The ATPG device simplifies two equivalent gates within the fan-in logic cone and the fan-out logic cone into a single gate for generating CNF clauses.

[0181] S1406: The ATPG device starts the first thread, determines the first logic cone to be detected in the fan-out logic cone based on the initial depth value and the first step length value, and determines the second logic cone to be detected in the fan-in logic cone based on the first logic cone.

[0182] S1407: The ATPG device generates a first CNF based on the first logic cone and the second logic cone, performs SAT on the first CNF, and obtains the first detection result.

[0183] S1408: The ATPG device determines whether the fault type in the first detection result is a difficult-to-detect fault; if yes, proceed to S1409; otherwise, proceed to S1410.

[0184] S1409: The ATPG device determines, based on the first detection result, that the fault type of the target line in the first verification result is a difficult-to-detect fault.

[0185] S1410: The ATPG device determines whether the first logic cone is the entire region of the fan-out logic cone; if yes, proceed to S1411, otherwise proceed to S1406.

[0186] S1411: The ATPG device determines that the first verification result is a detectable fault in the target line and generates a test vector.

[0187] S1412: The ATPG device starts the second thread, determines the third logic cone to be detected in the fan-out logic cone according to the preset number of output terminals and the second step size value, and determines the fourth logic cone to be detected in the fan-in logic cone according to the third logic cone.

[0188] S1413: The ATPG device generates a second CNF based on the third and fourth logic cones, performs SAT on the second CNF, and obtains the second detection result.

[0189] S1414: The ATPG device determines whether the fault type in the second detection result is a detectable fault; if yes, proceed to S1415; otherwise, proceed to S1416.

[0190] S1415: The ATPG device determines the fault type of the target line as a detectable fault based on the second detection result and obtains the test vector.

[0191] S1416: The ATPG device determines whether the third logic cone is the entire region of the fan-out logic cone or whether the entire third logic cone has traversed the entire region of the fan-out logic cone; if yes, proceed to S1417, otherwise proceed to S1412.

[0192] S1417: The ATPG device determines that the second verification result indicates that the fault type of the target line is a difficult-to-detect fault.

[0193] S1418: When the ATPG device determines that a first verification result has been obtained but a second verification result has not been obtained, it stops the second thread and outputs the first verification result; or when it determines that a second verification result has been obtained but a first verification result has not been obtained, it stops the first thread and outputs the second verification result.

[0194] The following section further describes the effects of the ATPG-based circuit verification method provided in this application, based on test results of multiple complex examples of combined circuits.

[0195] First, several challenging circuits tested in the embodiments of this application are introduced. Table 1 shows four circuits with different integration scales:

[0196] Table 1

[0197] b17 52 45339 b19 126 261358 b17-3 145 123360 b17-5 234 203664

[0198] Among them, b17-5 has reached the logic cone depth of industrial large-scale circuits.

[0199] The first set of test results consists of the results of testing the difficult-to-detect faults (i.e., redundant faults and aborted faults that cannot be solved within a given time) of the four circuits shown in Table 1 above. These faults are called difficult examples because, from an optimization perspective, their worst case requires a full traversal of the search space, which is a difficult example for heuristic detection methods. The results are shown in Table 2.

[0200] Table 2

[0201]

[0202] The second set of tests, based on the ATPG-based circuit verification method provided in this application and existing ATPG-based circuit verification methods, shows the test results after testing the circuit under test b17-3. The ATPG-based circuit verification method provided in this application includes circuit simplification. The results of the second set of tests are shown in Table 3.

[0203] Table 3

[0204]

[0205] The third set of tests, based on the ATPG-based circuit verification method provided in this application and existing ATPG-based circuit verification methods, shows the test results after testing the circuit b17-5 under test. The ATPG-based circuit verification method provided in this application includes circuit simplification. The results of the third set of tests are shown in Table 4.

[0206] Table 4

[0207]

[0208] Based on the test results in Table 1-3, the following conclusions can be drawn:

[0209] 1. Through comparisons of different scales, the circuit verification method based on ATPG provided in this application shows that, compared with the original ATPG detection method based on the SAT algorithm, the advantages become more and more prominent as the circuit scale increases.

[0210] 2. The circuit verification method based on ATPG provided in this application can exceed the coverage of existing circuit verification methods based on ATPG within a certain time limit. A detailed analysis follows:

[0211] (1) For medium-depth circuit under test b17-3, the circuit verification method based on ATPG provided in this application embodiment can complete the verification of more than 90% of the faults that cannot be detected by the existing circuit verification method based on ATPG in twice the time, improving the coverage by 0.59%; and the circuit verification method based on ATPG provided in this application embodiment can complete the verification of 70% of the faults that cannot be detected by the existing circuit verification method based on ATPG in less time, improving the coverage by 0.47%.

[0212] (2) For the circuit under test b17-5, which has the largest depth, the circuit verification method based on ATPG provided in this application embodiment can complete the verification of nearly 90% of the faults that cannot be detected by the existing circuit verification method based on ATPG in twice the time, improving the coverage by more than 0.77%; and the circuit verification method based on ATPG provided in this application embodiment can complete the verification of about 70% of the faults that cannot be detected by the existing circuit verification method based on ATPG in the same test time as the existing circuit verification method based on ATPG, improving the coverage by 0.9%.

[0213] Furthermore, when the sequential decision-making method using looking-ahead computation proposed in this application is used to solve the first CNF, the test results for the large-scale circuit verification problem are shown in Table 5:

[0214] Table 5

[0215]

[0216] As can be seen from Table 5, when performing SAT calculation on the first CNF, sampling a clause once can improve the efficiency by an average of 42.77%, and sampling a clause multiple times can improve the efficiency by an average of 46.84%. It is evident that the sequence decision method using looking ahead computation provided in this application embodiment has a significant improvement in the efficiency of SAT calculation for CNF.

[0217] The test results of the circuit simplification method provided in this application for circuit verification problems can be found in Table 6:

[0218] Table 6

[0219]

[0220] As can be seen from Table 6, the performance of the ATPG method is improved by an average of 28.04% after adding the simplification module.

[0221] Finally, the circuit verification method based on ATPG provided in this application embodiment is compared with the existing circuit verification method based on ATPG, such as... Figure 15 As shown, the circuit verification method based on ATPG provided in this application has better performance than existing circuit verification methods based on ATPG in terms of both growth rate and total growth time in CNF generation and CNF SAT solution.

[0222] In summary, the circuit verification method based on ATPG provided in this application fully utilizes the symbolic computation characteristics of SAT, dividing the detection process into core modules such as circuit decomposition, circuit simplification, incremental computation, and online prediction (Looking ahead). This effectively avoids the computational bottlenecks of SAT in ATPG, such as the excessively long generation time of CNF (Cellular Function Tree) which may even exceed the solution time, and the difficulty in including hidden structural information of the circuit in CNF. The circuit verification method based on ATPG provided in this application can be directly used for the detection of difficult examples, thereby effectively improving coverage.

[0223] This application also provides an automatic test vector generation device 1600. Figure 16 This is a schematic diagram of the automatic test vector generation device provided in an embodiment of this application. (See also...) Figure 16 As shown, the automatic test vector generation device 1600 includes a processor 1601, a memory 1602, and a bus 1603. The processor 1601 and the memory 1602 communicate via the bus 1603, or via other means such as wireless transmission. The memory 1602 stores instructions, and the processor 1601 executes the instructions stored in the memory 1602. The memory 1602 stores program code, and the processor 1601 can call the program code stored in the memory 1602 to perform the following operations:

[0224] The following procedure is performed on the target line in the circuit under test, wherein the circuit under test comprises multiple lines, any one of which is a connection between two connected gate circuits, and the target line is any one of the multiple lines:

[0225] In the fan-out logic cone corresponding to the target line, a first logic cone to be tested is determined; wherein, the fan-out logic cone is the region composed of gate circuits that the path from the target line to the output terminal of the circuit under test is traversed.

[0226] Based on the first logic cone, a second logic cone to be tested is determined in the fan-in logic cone corresponding to the target line; wherein, the fan-in logic cone is the region composed of gate circuits from the input terminal of the circuit under test to the target line, and the second logic cone is the region composed of gate circuits in the fan-in logic cone that affect the output value of the first logic cone;

[0227] Generate a first conjunctive expression CNF based on the first logic cone and the second logic cone;

[0228] The processor 1601 is used for:

[0229] The target line is detected using the first CNF to obtain a first detection result; wherein, the first detection result is used to indicate the fault type of the target line;

[0230] If the first logic cone is a portion of the fan-out logic cone, and the first detection result satisfies the first set condition corresponding to the first logic cone, then the first verification result of the target line is determined based on the first detection result.

[0231] In one embodiment, the processor 1601 is further configured to: if the first logic cone is the entire region in the fan-out logic cone, then determine the first verification result based on the first detection result.

[0232] In one embodiment, the processor 1601 is further configured to: if the first logic cone is a partial region of the fan-out logic cone and the first detection result does not meet the first set condition, then redetermine the first logic cone to be detected in the fan-out logic cone; wherein, the first logic cones determined in different instances are not completely the same.

[0233] In one embodiment, the processor 1601 is specifically configured to: determine the first logic cone in the fan-out logic cone according to a preset initial depth value and a first step length value, wherein the initial depth value characterizes the distance between the target line and the gate circuit.

[0234] In one implementation, the first setting condition is that the fault type in the first detection result is a difficult-to-detect fault.

[0235] In one embodiment, the processor 1601 is specifically used to: determine the first logic cone in the fan-out logic cone according to a preset number of output terminals and a second step size value.

[0236] In one embodiment, the first detection result includes a fault type and a test vector, the test vector being used to detect circuit faults in the circuit under test; the first setting condition is that the fault type in the first detection result is a detectable fault.

[0237] In one embodiment, the processor 1601 is further configured to: determine a third logic cone to be detected in the fan-out logic cone; and determine a fourth logic cone to be detected in the fan-in logic cone, wherein the third logic cone is different from the first logic cone, and the fourth logic cone is a region in the fan-in logic cone composed of gate circuits that affect the output value of the third logic cone; and generate a second CNF based on the third logic cone and the fourth logic cone.

[0238] The processor 1601 is further configured to: detect the target line using the second CNF to obtain a second detection result; wherein the second detection result is used to indicate the fault type of the target line; when the first verification result is not determined, if the third logic cone is a part of the fan-out logic cone, and the second detection result satisfies the second setting condition corresponding to the third logic cone, then the second verification result corresponding to the target line is determined according to the second detection result, and the detection of the target line using the first CNF is stopped; when the first verification result has been determined, the detection of the target line using the second CNF is stopped.

[0239] In one implementation, the first CNF includes at least one clause, which is generated based on gate circuits in the first logic cone and the second logic cone.

[0240] In one embodiment, the processor 1601 is specifically configured to: if the number of clauses contained in the first CNF is greater than or equal to a set threshold, perform satisfiability SAT on the at least one clause respectively, and determine the SAT solution result of each clause; and take the intersection of the SAT solution results of the at least one clause as the first detection result.

[0241] In one implementation, the first CNF includes at least one target clause corresponding to at least one target sub-circuit in the first logic cone, and at least one target clause corresponding to at least one target sub-circuit in the second logic cone, wherein the target sub-circuit and the target clause correspond one-to-one; each target sub-circuit includes at least one gate circuit.

[0242] In one embodiment, the processor 1601 is further configured to: before the generation unit determines the first logic cone to be detected in the fan-out logic cone corresponding to the target line, if the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than a first set threshold, determine the target sub-circuit in the fan-in logic cone based on the gate circuits in the fan-in logic cone, and determine the target sub-circuit in the fan-out logic cone based on the gate circuits in the fan-out logic cone.

[0243] In one implementation, the target sub-circuit is a fan-out region (FFR).

[0244] In one embodiment, the processor 1601 is further configured to: before the generation unit determines the first logic cone to be detected in the fan-out logic cone corresponding to the target line, if the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than a second set threshold, then simplify two equivalent gate circuits in the fan-in logic cone and the fan-out logic cone into a gate circuit for generating a clause of CNF; wherein, the second set threshold is less than the first set threshold, and the two equivalent gate circuits are two gate circuits with the same input and the same output.

[0245] It is understood that this application Figure 16 The memory 1602 can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0246] This application also provides an automatic test vector generation device 1700. Figure 17This is a schematic diagram of the automatic test vector generation device 1700. The device includes a generation unit 1701 and a detection unit 1702. Optionally, it may also include a circuit decomposition unit 1703 and a circuit simplification unit 1704. The functions of each unit in the automatic test vector generation device 1700 are described below.

[0247] The generation unit 1701 is used for:

[0248] The following procedure is performed on the target line in the circuit under test, wherein the circuit under test comprises multiple lines, any one of which is a connection between two connected gate circuits, and the target line is any one of the multiple lines:

[0249] In the fan-out logic cone corresponding to the target line, a first logic cone to be tested is determined; wherein, the fan-out logic cone is the region composed of gate circuits that the path from the target line to the output terminal of the circuit under test is traversed.

[0250] Based on the first logic cone, a second logic cone to be tested is determined in the fan-in logic cone corresponding to the target line; wherein, the fan-in logic cone is the region composed of gate circuits from the input terminal of the circuit under test to the target line, and the second logic cone is the region composed of gate circuits in the fan-in logic cone that affect the output value of the first logic cone;

[0251] Generate a first conjunctive expression CNF based on the first logic cone and the second logic cone;

[0252] The detection unit 1702 is used for:

[0253] The target line is detected using the first CNF to obtain a first detection result; wherein, the first detection result is used to indicate the fault type of the target line;

[0254] If the first logic cone is a portion of the fan-out logic cone, and the first detection result satisfies the first set condition corresponding to the first logic cone, then the first verification result of the target line is determined based on the first detection result.

[0255] In one embodiment, the detection unit 1702 is further configured to: if the first logic cone is the entire region in the fan-out logic cone, then determine the first verification result based on the first detection result.

[0256] In one embodiment, the generation unit 1701 is further configured to: if the first logic cone is a partial region of the fan-out logic cone, and the first detection result does not meet the first set condition, then re-determine the first logic cone to be detected in the fan-out logic cone; wherein, the first logic cone determined in different times is not completely the same.

[0257] In one embodiment, the generation unit 1701 is specifically used to: determine the first logic cone in the fan-out logic cone according to a preset initial depth value and a first step length value, wherein the initial depth value characterizes the distance between the target line and the gate circuit.

[0258] In one implementation, the first setting condition is that the fault type in the first detection result is a difficult-to-detect fault.

[0259] In one embodiment, the generation unit 1701 is specifically used to: determine the first logic cone in the fan-out logic cone according to the preset number of output terminals and the second step size value.

[0260] In one embodiment, the first detection result includes a fault type and a test vector, the test vector being used to detect circuit faults in the circuit under test; the first setting condition is that the fault type in the first detection result is a detectable fault.

[0261] In one embodiment, the generation unit 1701 is further configured to: determine a third logic cone to be detected in the fan-out logic cone; and determine a fourth logic cone to be detected in the fan-in logic cone, wherein the third logic cone is different from the first logic cone, and the fourth logic cone is a region in the fan-in logic cone composed of gate circuits that affect the output value of the third logic cone; and generate a second CNF based on the third logic cone and the fourth logic cone.

[0262] The detection unit 1702 is further configured to: detect the target line using the second CNF to obtain a second detection result; wherein the second detection result is used to indicate the fault type of the target line; when the first verification result is not determined, if the third logic cone is a part of the fan-out logic cone, and the second detection result satisfies the second setting condition corresponding to the third logic cone, then the second verification result corresponding to the target line is determined according to the second detection result, and the detection of the target line using the first CNF is stopped; when the first verification result has been determined, the detection of the target line using the second CNF is stopped.

[0263] In one implementation, the first CNF includes at least one clause, which is generated based on gate circuits in the first logic cone and the second logic cone.

[0264] In one embodiment, the detection unit 1702 is specifically used to: if the number of clauses contained in the first CNF is greater than or equal to a set threshold, perform satisfiability SAT on the at least one clause respectively, and determine the SAT solution result of each clause; and take the intersection of the SAT solution results of the at least one clause as the first detection result.

[0265] In one implementation, the first CNF includes at least one target clause corresponding to at least one target sub-circuit in the first logic cone, and at least one target clause corresponding to at least one target sub-circuit in the second logic cone, wherein the target sub-circuit and the target clause correspond one-to-one; each target sub-circuit includes at least one gate circuit.

[0266] In one embodiment, the automatic test vector generation device further includes a circuit decomposition unit 1703, which is configured to: before the generation unit determines the first logic cone to be detected in the fan-out logic cone corresponding to the target line, if the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than a first set threshold, determine the target sub-circuit in the fan-in logic cone based on the gate circuits in the fan-in logic cone, and determine the target sub-circuit in the fan-out logic cone based on the gate circuits in the fan-out logic cone.

[0267] In one implementation, the target sub-circuit is a fan-out region (FFR).

[0268] In one embodiment, the automatic test vector generation device further includes a circuit simplification element 1704, which is used to: before the generation unit determines the first logic cone to be detected in the fan-out logic cone corresponding to the target line, if the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than a second set threshold, simplify two equivalent gate circuits in the fan-in logic cone and the fan-out logic cone into a gate circuit for generating a clause of CNF; wherein the second set threshold is less than the first set threshold, and the two equivalent gate circuits are two gate circuits with the same input and the same output.

[0269] It should be noted that the division of units in the embodiments of this application is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. The functional units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units described above can be implemented in hardware or as software functional units.

[0270] Based on the above embodiments, this application also provides a chip, which is connected to a memory and is used to read and execute software programs stored in the memory to achieve... Figure 7 or Figure 14 The illustrated embodiment provides an ATPG-based circuit verification method.

[0271] Based on the above embodiments, this application provides a chip system including a processor for supporting computer devices to implement... Figure 7 or Figure 14 The illustrated embodiment provides an ATPG-based circuit verification method. In one possible design, the chip system further includes a memory for storing necessary programs and data for the computer device. The chip system may consist of chips or may include chips and other discrete components.

[0272] Based on the above embodiments, this application also provides a computer program that, when run on a computer, causes the computer to execute the ATPG-based circuit verification method provided in the above embodiments.

[0273] Based on the above embodiments, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a computer, causes the computer to perform the circuit verification method based on ATPG provided in the above embodiments.

[0274] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0275] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0276] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0277] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0278] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the scope of protection of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A circuit verification method based on automatic test vector generation, characterized by, The method includes: The first logic cone to be tested is determined in the fan-out logic cone corresponding to the target line; wherein, the fan-out logic cone is the region composed of gate circuits that pass from the target line to the output terminal of the circuit under test; Based on the first logic cone, a second logic cone to be tested is determined in the fan-in logic cone corresponding to the target line; wherein, the fan-in logic cone is the region composed of gate circuits from the input terminal of the circuit under test to the target line, and the second logic cone is the region composed of gate circuits in the fan-in logic cone that affect the output value of the first logic cone; A first conjunction expression (CNF) is generated based on the first logic cone and the second logic cone, and the target line is detected using the first CNF to obtain a first detection result; wherein, the first detection result is used to represent the fault type of the target line; If the first logic cone is a portion of the fan-out logic cone, and the first detection result satisfies the first set condition corresponding to the first logic cone, then the first verification result of the target line is determined based on the first detection result.

2. The method of claim 1, wherein, The method further includes: If the first logic cone is the entire region within the fan-out logic cone, then the first verification result is determined based on the first detection result.

3. The method of claim 1, wherein, The method further includes: If the first logic cone is a partial region of the fan-out logic cone, and the first detection result does not meet the first set condition, then the first logic cone to be detected is re-determined in the fan-out logic cone; wherein, the first logic cone determined in different times is not completely the same.

4. The method according to any one of claims 1-3, characterized in that, Determining the first logic cone to be detected in the fan-out logic cone corresponding to the target line includes: Based on the preset initial depth value and the first step length value, the first logic cone is determined in the fan-out logic cone, wherein the initial depth value represents the distance between the target line and the gate circuit.

5. The method as described in claim 4, characterized in that, The first setting condition is that the fault type in the first detection result is a difficult-to-detect fault.

6. The method according to any one of claims 1-3, characterized in that, Determining the first logic cone to be detected in the fan-out logic cone corresponding to the target line includes: The first logic cone is determined in the fan-out logic cone based on the preset number of output terminals and the second step size value.

7. The method as described in claim 6, characterized in that, The first detection result includes a fault type and a test vector, and the test vector is used to detect circuit faults in the circuit under test. The first setting condition is: the fault type in the first detection result is a detectable fault.

8. The method according to any one of claims 1-3, 5, and 7, characterized in that, The method further includes: A third logic cone to be detected is determined in the fan-out logic cone; and a fourth logic cone to be detected is determined in the fan-in logic cone, wherein the third logic cone is different from the first logic cone, and the fourth logic cone is the region of the fan-in logic cone composed of gate circuits that affect the output value of the third logic cone; A second CNF is generated based on the third logic cone and the fourth logic cone, and the target line is detected using the second CNF to obtain a second detection result; wherein the second detection result is used to indicate the fault type of the target line; If the first verification result is not determined, and if the third logic cone is a part of the fan-out logic cone, and the second detection result satisfies the second setting condition corresponding to the third logic cone, then the second verification result corresponding to the target line is determined according to the second detection result, and the detection of the target line using the first CNF is stopped. Once the first verification result has been determined, the detection of the target line using the second CNF is stopped.

9. The method according to any one of claims 1-3, 5, and 7, characterized in that, The first CNF includes at least one clause, which is generated based on the gate circuits in the first logic cone and the second logic cone.

10. The method as described in claim 9, characterized in that, The detection of the target line using the first CNF includes: If the number of clauses contained in the first CNF is greater than or equal to a set threshold, the satisfiability SAT is performed on each of the at least one clause to determine the SAT result for each clause. The intersection of the SAT solution results of the at least one clause is taken as the first detection result.

11. The method as described in claim 9, characterized in that, The first CNF includes at least one target clause corresponding to at least one target sub-circuit in the first logic cone, and at least one target clause corresponding to at least one target sub-circuit in the second logic cone, wherein the target sub-circuit and the target clause correspond one-to-one; each target sub-circuit includes at least one gate circuit.

12. The method as described in claim 11, characterized in that, Before determining the first logic cone to be detected in the fan-out logic cone corresponding to the target line, the method further includes: If the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than a first set threshold, then the target sub-circuit in the fan-in logic cone is determined based on the gate circuits in the fan-in logic cone, and the target sub-circuit in the fan-out logic cone is determined based on the gate circuits in the fan-out logic cone.

13. The method as described in claim 11 or 12, characterized in that, The target sub-circuit is a fanless region (FFR).

14. The method as described in claim 9, characterized in that, Before determining the first logic cone to be detected in the fan-out logic cone corresponding to the target line, the method further includes: If the number of gates contained in the fan-in logic cone and the fan-out logic cone is greater than the second set threshold, then the two equivalent gates in the fan-in logic cone and the fan-out logic cone are simplified into a single gate for generating a clause in CNF; wherein the second set threshold is less than the first set threshold, and the two equivalent gates are two gates with the same input and the same output.

15. An automatic test vector generation device, characterized in that, The device includes a generation unit and a detection unit; The generation unit is used for: The first logic cone to be tested is determined in the fan-out logic cone corresponding to the target line; wherein, the fan-out logic cone is the region composed of gate circuits that pass from the target line to the output terminal of the circuit under test; Based on the first logic cone, a second logic cone to be tested is determined in the fan-in logic cone corresponding to the target line; wherein, the fan-in logic cone is the region composed of gate circuits from the input terminal of the circuit under test to the target line, and the second logic cone is the region composed of gate circuits in the fan-in logic cone that affect the output value of the first logic cone; Generate a first conjunctive expression CNF based on the first logic cone and the second logic cone; The detection unit is used for: The target line is detected using the first CNF to obtain a first detection result; wherein, the first detection result is used to indicate the fault type of the target line; If the first logic cone is a portion of the fan-out logic cone, and the first detection result satisfies the first set condition corresponding to the first logic cone, then the first verification result of the target line is determined based on the first detection result.

16. The apparatus as claimed in claim 15, characterized in that, The detection unit is also used for: If the first logic cone is the entire region within the fan-out logic cone, then the first verification result is determined based on the first detection result.

17. The apparatus as claimed in claim 15, characterized in that, The generation unit is also used for: If the first logic cone is a partial region of the fan-out logic cone, and the first detection result does not meet the first set condition, then the first logic cone to be detected is re-determined in the fan-out logic cone; wherein, the first logic cone determined in different times is not completely the same.

18. The apparatus according to any one of claims 15-17, characterized in that, The generation unit is specifically used for: Based on the preset initial depth value and the first step length value, the first logic cone is determined in the fan-out logic cone, wherein the initial depth value represents the distance between the target line and the gate circuit.

19. The apparatus as claimed in claim 18, characterized in that, The first setting condition is that the fault type in the first detection result is a difficult-to-detect fault.

20. The apparatus according to any one of claims 15-17, characterized in that, The generation unit is specifically used for: The first logic cone is determined in the fan-out logic cone based on the preset number of output terminals and the second step size value.

21. The apparatus as claimed in claim 20, characterized in that, The first detection result includes a fault type and a test vector, and the test vector is used to detect circuit faults in the circuit under test. The first setting condition is: the fault type in the first detection result is a detectable fault.

22. The apparatus according to any one of claims 15-17, 19, and 21, characterized in that, The generation unit is also used for: A third logic cone to be detected is determined in the fan-out logic cone; and a fourth logic cone to be detected is determined in the fan-in logic cone, wherein the third logic cone is different from the first logic cone, and the fourth logic cone is the region of the fan-in logic cone composed of gate circuits that affect the output value of the third logic cone; A second CNF is generated based on the third logic cone and the fourth logic cone; The detection unit is also used for: The target line is detected using the second CNF to obtain a second detection result; wherein the second detection result is used to indicate the fault type of the target line; If the first verification result is not determined, and if the third logic cone is a part of the fan-out logic cone, and the second detection result satisfies the second setting condition corresponding to the third logic cone, then the second verification result corresponding to the target line is determined according to the second detection result, and the detection of the target line using the first CNF is stopped. Once the first verification result has been determined, the detection of the target line using the second CNF is stopped.

23. The apparatus according to any one of claims 15-17, 19, and 21, characterized in that, The first CNF includes at least one clause, which is generated based on the gate circuits in the first logic cone and the second logic cone.

24. The apparatus as claimed in claim 23, characterized in that, The detection unit is specifically used for: If the number of clauses contained in the first CNF is greater than or equal to a set threshold, the satisfiability SAT is performed on each of the at least one clause to determine the SAT result for each clause. The intersection of the SAT solution results of the at least one clause is taken as the first detection result.

25. The apparatus as claimed in claim 23, characterized in that, The first CNF includes at least one target clause corresponding to at least one target sub-circuit in the first logic cone, and at least one target clause corresponding to at least one target sub-circuit in the second logic cone, wherein the target sub-circuit and the target clause correspond one-to-one; each target sub-circuit includes at least one gate circuit.

26. The apparatus as claimed in claim 25, characterized in that, The automatic test vector generation device further includes a circuit decomposition unit, which is used for: Before the generation unit determines the first logic cone to be detected in the fan-out logic cone corresponding to the target line, if the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than a first set threshold, then the target sub-circuit in the fan-in logic cone is determined based on the gate circuits in the fan-in logic cone, and the target sub-circuit in the fan-out logic cone is determined based on the gate circuits in the fan-out logic cone.

27. The apparatus as claimed in claim 25 or 26, characterized in that, The target sub-circuit is a fanless region (FFR).

28. The apparatus as claimed in claim 23, characterized in that, The automatic test vector generation device further includes a circuitized simple element, which is used for: Before the generation unit determines the first logic cone to be detected in the fan-out logic cone corresponding to the target line, if the number of gate circuits contained in the fan-in logic cone and the fan-out logic cone is greater than a second set threshold, then the two equivalent gate circuits in the fan-in logic cone and the fan-out logic cone are simplified into a gate circuit for generating a clause of CNF; wherein, the second set threshold is less than the first set threshold, and the two equivalent gate circuits are two gate circuits with the same input and the same output.

29. An automatic test vector generation device, characterized in that, The method includes at least one processor coupled to at least one memory, the at least one processor being configured to read a computer program stored in the at least one memory to perform the method as described in any one of claims 1-14.

30. A chip, characterized in that, The chip is connected to a memory, and the chip is used to read and execute software programs stored in the memory to perform the method as described in any one of claims 1-14.

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