Driving module, display panel and display device

Abstract

The present disclosure provides a driving module, a display panel and a display device. The driving module comprises a first driving circuit and a first conversion circuit; n is a positive integer; the first driving circuit comprises a plurality of first driving sub-circuits; the first conversion circuit comprises a plurality of first conversion sub-circuits; an nth first driving sub-circuit outputs an nth first driving signal; an nth-1 first driving sub-circuit outputs an nth-1 first driving signal; an nth first conversion sub-circuit controls an nth second driving signal output end to output an nth second driving signal under the control of the nth-1 first driving signal and the nth first driving signal according to a first voltage signal and a second voltage signal. The present disclosure can reduce the space occupied by the driving module, narrow the width of the driving module, and facilitate the realization of narrow frame of the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a driving module, a display panel, and a display device. Background Technology

[0002] Narrow bezels are a key trend in future display technology. Currently, the GOA (Gate On Array) area is one of the main obstacles to narrowing display panel bezels. Related technologies require providing light-emitting control signals and driving signals to the pixel circuits located in the display area, and a driving module is positioned in the peripheral area of ​​the display panel. This driving module includes a driving signal generation circuit for providing driving signals and a light-emitting control signal generation circuit for generating light-emitting control signals. The driving module contains a large number of transistors and occupies a significant bezel width, which is detrimental to achieving narrow bezels. Summary of the Invention

[0003] In one aspect, embodiments of this disclosure provide a driving module, including a first driving circuit and a first conversion circuit; n is a positive integer; the first driving circuit includes multiple levels of first driving sub-circuits; the first conversion circuit includes multiple first conversion sub-circuits;

[0004] The nth-stage first driver sub-circuit is used to generate and output the nth-stage first driver signal through the nth-stage first driver signal output terminal;

[0005] The (n-1)th stage first driver sub-circuit is used to generate and output the (n-1)th stage first driver signal through the (n-1)th stage first driver signal output terminal;

[0006] The nth first conversion sub-circuit is electrically connected to the (n-1)th stage first drive signal output terminal, the nth stage first drive signal output terminal, the first voltage terminal, the second voltage terminal, and the nth stage second drive signal output terminal, respectively. It is used to control the nth stage second drive signal output terminal to output the nth stage second drive signal under the control of the (n-1)th stage first drive signal and the nth stage first drive signal, according to the first voltage signal provided by the first voltage terminal and the second voltage signal provided by the second voltage terminal.

[0007] Optionally, the driving module described in at least one embodiment of this disclosure further includes a second conversion circuit; the second conversion circuit includes a plurality of second conversion sub-circuits;

[0008] The (n-1)th second conversion sub-circuit is electrically connected to the (n-1)th stage first drive signal output terminal, the nth stage first drive signal output terminal, the nth stage second drive signal output terminal, the third voltage terminal, the fourth voltage terminal, and the (n-1)th stage third drive signal output terminal, respectively. It is used to control the (n-1)th stage third drive signal output terminal to output the (n-1)th stage third drive signal under the control of the (n-1)th stage first drive signal, the nth stage first drive signal, and the nth stage second drive signal, according to the third voltage signal provided by the third voltage terminal and the fourth voltage signal provided by the fourth voltage terminal.

[0009] Optionally, the nth first conversion sub-circuit includes an nth first conversion module and an nth second conversion module;

[0010] The nth first conversion module is electrically connected to the (n-1)th stage first drive signal output terminal, the nth stage first drive signal output terminal, the first voltage terminal, and the nth stage second drive signal output terminal, respectively. It is used to control the output of the first voltage signal provided by the first voltage terminal to the nth stage second drive signal output terminal under the control of the (n-1)th stage first drive signal, and to output the first voltage signal to the nth stage second drive signal output terminal under the control of the nth stage first drive signal.

[0011] The nth second conversion module is electrically connected to the (n-1)th stage first drive signal output terminal, the nth stage first drive signal output terminal, the second voltage terminal, and the nth stage second drive signal output terminal, respectively, and is used to output the second voltage signal provided by the second voltage terminal to the nth stage second drive signal output terminal under the control of the (n-1)th stage first drive signal and the nth stage first drive signal.

[0012] Optionally, the (n-1)th second conversion sub-circuit includes the (n-1)th third conversion module, the (n-1)th fourth conversion module, and the (n-1)th fifth conversion module;

[0013] The (n-1)th third conversion module is electrically connected to the (n-1)th stage first drive signal output terminal, the third voltage terminal and the (n-1)th stage third drive signal output terminal, respectively, and is used to output the third voltage signal provided by the third voltage terminal to the (n-1)th stage third drive signal output terminal under the control of the (n-1)th stage first drive signal.

[0014] The (n-1)th fourth conversion module is electrically connected to the nth stage first drive signal output terminal, the fourth voltage terminal and the (n-1)th stage third drive signal output terminal, respectively, and is used to output the fourth voltage signal provided by the fourth voltage terminal to the (n-1)th stage third drive signal output terminal under the control of the nth stage first drive signal.

[0015] The (n-1)th fifth conversion module is electrically connected to the nth stage second drive signal output terminal, the fourth voltage terminal, and the (n-1)th stage third drive signal output terminal, respectively, and is used to output the fourth voltage signal provided by the fourth voltage terminal to the (n-1)th stage third drive signal output terminal under the control of the nth stage second drive signal.

[0016] Optionally, the nth first conversion module includes a first transistor and a second transistor, and the nth second conversion module includes a third transistor and a fourth transistor;

[0017] The control electrode of the first transistor is electrically connected to the output terminal of the first drive signal of the (n-1)th stage, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the output terminal of the second drive signal of the nth stage.

[0018] The control electrode of the second transistor is electrically connected to the output terminal of the first drive signal of the nth stage, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the output terminal of the second drive signal of the nth stage.

[0019] The control electrode of the third transistor is electrically connected to the output terminal of the first drive signal of the (n-1)th stage, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the output terminal of the second drive signal of the nth stage.

[0020] The control electrode of the fourth transistor is electrically connected to the first drive signal output terminal of the nth stage, the first electrode of the fourth transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the fourth transistor is electrically connected to the second drive signal output terminal of the nth stage.

[0021] Optionally, the first transistor and the second transistor are both of the first type of transistor, and the third transistor and the fourth transistor are both of the second type of transistor.

[0022] Optionally, the (n-1)th third conversion module includes a fifth transistor, the (n-1)th fourth conversion module includes a sixth transistor, and the (n-1)th fifth conversion module includes a seventh transistor;

[0023] The control electrode of the fifth transistor is electrically connected to the output terminal of the first drive signal of the (n-1)th stage, the first electrode of the fifth transistor is electrically connected to the third voltage terminal, and the second electrode of the fifth transistor is electrically connected to the output terminal of the third drive signal of the (n-1)th stage.

[0024] The control electrode of the sixth transistor is electrically connected to the first drive signal output terminal of the nth stage, the first electrode of the sixth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the sixth transistor is electrically connected to the third drive signal output terminal of the (n-1)th stage.

[0025] The control electrode of the seventh transistor is electrically connected to the output terminal of the second drive signal of the nth stage, the first electrode of the seventh transistor is electrically connected to the fourth voltage terminal, and the second electrode of the seventh transistor is electrically connected to the output terminal of the third drive signal of the (n-1)th stage.

[0026] Optionally, the fifth transistor and the seventh transistor are of the first type of transistor, and the sixth transistor is of the second type of transistor.

[0027] Optionally, the nth-level first driving sub-circuit includes a first node control circuit, a control node control circuit, a second node control circuit, a first energy storage circuit, a second energy storage circuit, and an output circuit, wherein,

[0028] The first node control circuit is electrically connected to the control clock signal terminal, the sixth voltage terminal, the first node, and the control node, respectively. It is used to write the sixth voltage signal provided by the sixth voltage terminal into the first node under the control of the control clock signal provided by the control clock signal terminal, and to write the control clock signal provided by the control clock signal terminal into the first node under the control of the potential of the control node.

[0029] The control node control circuit is electrically connected to the control clock signal terminal, the input terminal, the control node, the first node, the output clock signal terminal, and the fifth voltage terminal, respectively. It is used to write the input signal provided by the input terminal into the control node under the control of the control clock signal, and to write the fifth voltage signal provided by the fifth voltage terminal into the first node under the control of the potential of the first node and the output control signal provided by the output control clock signal terminal.

[0030] The second node control circuit is electrically connected to the sixth voltage terminal, the control node, and the second node, respectively, and is used to control the connection between the control node and the second node under the control of the sixth voltage signal provided by the sixth voltage terminal;

[0031] The first terminal of the first energy storage circuit is electrically connected to the second node, and the second terminal of the first energy storage circuit is electrically connected to the output terminal of the first drive signal of the nth stage; the first energy storage circuit is used to store electrical energy.

[0032] The first end of the second energy storage circuit is electrically connected to the first node, and the second end of the second energy storage circuit is electrically connected to the fifth voltage terminal. The second energy storage circuit is used to store electrical energy.

[0033] The output circuit is electrically connected to the first node, the second node, the output clock signal terminal, the fifth voltage terminal, and the nth-stage first drive signal output terminal, respectively. It is used to output the fifth voltage signal provided by the fifth voltage terminal to the nth-stage first drive signal output terminal under the control of the potential of the first node, and to output the output clock signal to the nth-stage first drive signal output terminal under the control of the potential of the second node.

[0034] Optionally, the first node control circuit includes a first control transistor and a second control transistor;

[0035] The control electrode of the first control transistor is electrically connected to the control clock signal terminal, the first electrode of the first control transistor is electrically connected to the sixth voltage terminal, and the second electrode of the first control transistor is electrically connected to the first node.

[0036] The control electrode of the second control transistor is electrically connected to the control node, the first electrode of the second control transistor is electrically connected to the control clock signal terminal, and the second electrode of the second control transistor is electrically connected to the first node.

[0037] The control node control circuit includes a third control transistor, a fourth control transistor, and a fifth control transistor;

[0038] The control electrode of the third control transistor is electrically connected to the control clock signal terminal, the first electrode of the third control transistor is electrically connected to the input terminal, and the second electrode of the third control transistor is electrically connected to the control node.

[0039] The control electrode of the fourth control transistor is electrically connected to the first node, and the first electrode of the fourth control transistor is electrically connected to the fifth voltage terminal.

[0040] The control electrode of the fifth control transistor is electrically connected to the output clock signal terminal, the first electrode of the fifth control transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the fifth control transistor is electrically connected to the control node.

[0041] The second node control circuit includes a sixth control transistor;

[0042] The control electrode of the sixth control transistor is electrically connected to the sixth voltage terminal, the first electrode of the sixth control transistor is electrically connected to the control node, and the second electrode of the sixth control transistor is electrically connected to the second node.

[0043] The first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0044] The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the output terminal of the first drive signal of the nth stage.

[0045] The first terminal of the second capacitor is electrically connected to the first node, and the second terminal of the second capacitor is electrically connected to the fifth voltage terminal.

[0046] The output circuit includes a first output transistor and a second output transistor;

[0047] The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the fifth voltage terminal, and the second electrode of the first output transistor is electrically connected to the nth stage first drive signal output terminal.

[0048] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the output terminal of the first drive signal of the nth stage, and the second electrode of the second output transistor is electrically connected to the output clock signal terminal.

[0049] In a second aspect, embodiments of this disclosure provide a display panel, including the aforementioned driving module disposed in a peripheral area and an N-row, M-column pixel circuit disposed in a display area; N and M are positive integers;

[0050] The driving module is used to provide driving signals for the pixel circuit.

[0051] Optionally, the driving signal includes a first driving signal and a second driving signal;

[0052] The first driving circuit included in the driving module is located on the side of the first conversion circuit included in the driving module that is away from the display area.

[0053] Optionally, the drive signal further includes a third drive signal; the drive module further includes a second conversion circuit;

[0054] The second conversion circuit is located on the side of the first conversion circuit that is close to the display area.

[0055] Optionally, the pixel circuit in the nth row and mth column includes a data writing circuit in the nth row and mth column, a compensation control circuit in the nth row and mth column, a first reset circuit in the nth row and mth column, a second reset circuit in the nth row and mth column, a first light-emitting control circuit in the nth row and mth column, a second light-emitting control circuit in the nth row and mth column, a driving circuit in the nth row and mth column, a third energy storage circuit in the nth row and mth column, and a light-emitting element in the nth row and mth column; n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M;

[0056] The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth driving signal output terminal.

[0057] The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the control terminal of the driving circuit in the nth row and mth column, and the second terminal of the driving circuit in the nth row and mth column, respectively, and is used to control the connection between the control terminal of the driving circuit in the nth row and mth column and the second terminal of the driving circuit in the nth row and mth column under the control of the first driving signal of the nth stage;

[0058] The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th stage first drive signal, the control terminal of the (n-1)th row and mth column drive circuit, and the first initial voltage terminal, respectively. It is used to write the first initial voltage provided by the first initial voltage terminal into the control terminal of the (n-1)th row and mth column drive circuit under the control of the (n-1)th stage first drive signal provided by the (n-1)th stage first drive signal output terminal.

[0059] The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the first driving signal of the nth stage.

[0060] The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the nth level second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the (n+1)th second driving signal;

[0061] The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal;

[0062] The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal;

[0063] The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy;

[0064] The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage level.

[0065] Optionally, the pixel circuit in the nth row and mth column includes a data writing circuit in the nth row and mth column, an on / off control circuit in the nth row and mth column, a compensation control circuit in the nth row and mth column, a first reset circuit in the nth row and mth column, a second reset circuit in the nth row and mth column, a first light-emitting control circuit in the nth row and mth column, a second light-emitting control circuit in the nth row and mth column, a driving circuit in the nth row and mth column, a third energy storage circuit in the nth row and mth column, and a light-emitting element in the nth row and mth column; n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M;

[0066] The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth driving signal output terminal.

[0067] The on / off control circuit of the nth row and mth column is electrically connected to the output terminal of the nth level third drive signal, the control terminal of the nth row and mth column drive circuit, and the connection node of the nth row and mth column, respectively, and is used to control the connection between the control terminal of the nth row and mth column drive circuit and the connection node of the nth row and mth column under the control of the nth level third drive signal provided by the output terminal of the nth level third drive signal;

[0068] The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level first drive signal, the connection node in the nth row and mth column, and the second terminal of the drive circuit in the nth row and mth column, respectively, and is used to control the connection between the connection node in the nth row and mth column and the second terminal of the drive circuit in the nth row and mth column under the control of the nth level first drive signal;

[0069] The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th level first drive signal, the connection node in the nth row and mth column, and the first initial voltage terminal, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the connection node in the nth row and mth column under the control of the (n-1)th level first drive signal provided by the output terminal of the (n-1)th level first drive signal.

[0070] The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the first driving signal of the nth stage.

[0071] The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the nth level second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the (n+1)th second driving signal;

[0072] The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal;

[0073] The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal;

[0074] The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy;

[0075] The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage terminal;

[0076] The nth stage third drive signal output terminal and the nth stage second drive signal output terminal are connected to the same drive signal.

[0077] Optionally, the pixel circuit in the nth row and mth column includes a data writing circuit in the nth row and mth column, a compensation control circuit in the nth row and mth column, a first reset circuit in the nth row and mth column, a second reset circuit in the nth row and mth column, a first light-emitting control circuit in the nth row and mth column, a second light-emitting control circuit in the nth row and mth column, a driving circuit in the nth row and mth column, a third energy storage circuit in the nth row and mth column, and a light-emitting element in the nth row and mth column; n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M;

[0078] The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth driving signal output terminal.

[0079] The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level third drive signal, the control terminal of the nth row and mth column drive circuit, and the second terminal of the nth row and mth column drive circuit, respectively, and is used to control the connection between the control terminal of the nth row and mth column drive circuit and the second terminal of the nth row and mth column drive circuit under the control of the nth level third drive signal provided by the output terminal of the nth level third drive signal;

[0080] The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th level third drive signal, the control terminal of the (n-1)th row and mth column drive circuit, and the first initial voltage terminal, respectively. It is used to write the first initial voltage provided by the first initial voltage terminal into the control terminal of the (n-1)th row and mth column drive circuit under the control of the (n-1)th level third drive signal provided by the (n-1)th level third drive signal output terminal.

[0081] The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the first driving signal of the nth stage.

[0082] The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the nth level second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the (n+1)th second driving signal;

[0083] The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal;

[0084] The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal;

[0085] The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy;

[0086] The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage level.

[0087] Optionally, the pixel circuit in the nth row and mth column includes a data writing circuit in the nth row and mth column, a compensation control circuit in the nth row and mth column, a first reset circuit in the nth row and mth column, a second reset circuit in the nth row and mth column, a first light-emitting control circuit in the nth row and mth column, a second light-emitting control circuit in the nth row and mth column, a driving circuit in the nth row and mth column, a third energy storage circuit in the nth row and mth column, and a light-emitting element in the nth row and mth column; n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M;

[0088] The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth driving signal output terminal.

[0089] The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level third drive signal, the control terminal of the nth row and mth column drive circuit, and the second terminal of the nth row and mth column drive circuit, respectively, and is used to control the connection between the control terminal of the nth row and mth column drive circuit and the second terminal of the nth row and mth column drive circuit under the control of the nth level third drive signal provided by the output terminal of the nth level third drive signal;

[0090] The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th level third drive signal, the control terminal of the (n-1)th row and mth column drive circuit, and the first initial voltage terminal, respectively. It is used to write the first initial voltage provided by the first initial voltage terminal into the control terminal of the (n-1)th row and mth column drive circuit under the control of the (n-1)th level third drive signal provided by the (n-1)th level third drive signal output terminal.

[0091] The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the nth level second driving signal provided by the output terminal of the nth level second driving signal.

[0092] The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the (n+1)th level second driving signal or the (n+1)th second driving signal output terminal;

[0093] The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal;

[0094] The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal;

[0095] The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy;

[0096] The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage level.

[0097] In a third aspect, embodiments of this disclosure provide a display device including the display panel described above. Attached Figure Description

[0098] Figure 1 This is a schematic diagram showing the connection relationship between the nth level first driving sub-circuit, the (n-1)th level first driving sub-circuit, and the nth first conversion sub-circuit in the driving module described in this embodiment of the present disclosure;

[0099] Figure 2 Is Figure 1 Based on this, the diagram shows the nth first conversion sub-circuit including the nth level first conversion module and the nth level second conversion module;

[0100] Figure 3 This is a circuit diagram of at least one embodiment of the nth first conversion sub-circuit;

[0101] Figure 4 yes Figure 3 The timing diagram of at least one embodiment of the nth first conversion sub-circuit shown;

[0102] Figure 5This is a schematic diagram showing the positional relationship between the cutting edge and the anti-collision area 53, the first area 51, the second area 52 and the display area 50 in at least one embodiment of this disclosure;

[0103] Figure 6 yes Figure 3 A layout diagram of at least one embodiment of the nth first converter sub-circuit shown;

[0104] Figure 7A yes Figure 6 Layout diagram of the first semiconductor layer;

[0105] Figure 7B yes Figure 6 Layout diagram of the first gate metal layer in the middle;

[0106] Figure 7C for Figure 6 Layout diagram of the second semiconductor layer;

[0107] Figure 7D for Figure 6 Layout diagram of the second gate metal layer;

[0108] Figure 7E for Figure 6 Layout diagram of the first source / drain metal layer in the image;

[0109] Figure 8 yes Figure 6 A-A' section view in the middle;

[0110] Figure 9 yes Figure 6 Section B-B' in the diagram;

[0111] Figure 10 This is a structural diagram of at least one embodiment of the first driver sub-circuit of the nth stage;

[0112] Figure 11 This is a circuit diagram of at least one embodiment of the first driver sub-circuit of the nth stage;

[0113] Figure 12 This is a schematic diagram showing the connection between the nth level first driving sub-circuit 11 and the nth first conversion sub-circuit 21, and a schematic diagram showing the connection between the (n-1)th level first driving sub-circuit 12 and the (n-1)th first conversion sub-circuit 22.

[0114] Figure 13 This is a structural diagram of at least one embodiment of the (n-1)th second conversion sub-circuit;

[0115] Figure 14 This is a structural diagram of at least one embodiment of the (n-1)th second conversion sub-circuit;

[0116] Figure 15This is a circuit diagram of at least one embodiment of the (n-1)th second conversion sub-circuit;

[0117] Figure 16 yes Figure 15 The timing diagram of at least one embodiment of the (n-1)th second conversion sub-circuit shown;

[0118] Figure 17 It is a connection diagram of the nth level first driving sub-circuit 11, the nth first conversion sub-circuit 21 and the (n-1)th second conversion sub-circuit 131, and a connection diagram of the (n-1)th level first driving sub-circuit 12, the (n-1)th first conversion sub-circuit 22 and the (n-2)th second conversion sub-circuit 132;

[0119] Figure 18 This is a schematic diagram of the structure of a display panel according to at least one embodiment of the present disclosure;

[0120] Figure 19 This is a circuit diagram of at least one embodiment of the pixel circuit in the nth row and mth column;

[0121] Figure 20 yes Figure 19 The timing diagram of at least one embodiment of the pixel circuit in the nth row and mth column is shown.

[0122] Figure 21 This is a circuit diagram of at least one embodiment of the pixel circuit in the nth row and mth column;

[0123] Figure 22 yes Figure 21 The timing diagram of at least one embodiment of the pixel circuit in the nth row and mth column is shown.

[0124] Figure 23 This is a circuit diagram of at least one embodiment of the pixel circuit in the nth row and mth column;

[0125] Figure 24 yes Figure 23 The timing diagram of at least one embodiment of the pixel circuit in the nth row and mth column is shown.

[0126] Figure 25 This is a circuit diagram of at least one embodiment of the pixel circuit in the nth row and mth column;

[0127] Figure 26 yes Figure 25 The timing diagram of at least one embodiment of the pixel circuit in the nth row and mth column is shown.

[0128] Figure 27 This is a circuit diagram of at least one embodiment of the pixel circuit in the nth row and mth column;

[0129] Figure 28 yes Figure 27The timing diagram shows the operation of at least one embodiment of the pixel circuit in the nth row and mth column. Detailed Implementation

[0130] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this disclosure.

[0131] In all embodiments of this disclosure, the transistors used can be bipolar junction transistors (BJTs), thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the control terminal, one terminal is referred to as the first terminal and the other as the second terminal.

[0132] In actual operation, when the transistor is a bipolar junction transistor (BJT), the control electrode can be the base, the first electrode can be the collector, and the second electrode can be the emitter; or, the control electrode can be the base, the first electrode can be the emitter, and the second electrode can be the collector.

[0133] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the control electrode can be the gate, the first electrode can be the drain, and the second electrode can be the source; or, the control electrode can be the gate, the first electrode can be the source, and the second electrode can be the drain.

[0134] The driving module described in this embodiment includes a first driving circuit and a first conversion circuit; n is a positive integer; the first driving circuit includes multiple levels of first driving sub-circuits; the first conversion circuit includes multiple first conversion sub-circuits;

[0135] like Figure 1 As shown, the nth stage first driving sub-circuit 11 is used to generate and output the nth stage first driving signal through the nth stage first driving signal output terminal S(n);

[0136] The (n-1)th stage first driving sub-circuit 12 is used to generate and output the (n-1)th stage first driving signal through the (n-1)th stage first driving signal output terminal S(n-1);

[0137] The nth first conversion sub-circuit 21 is electrically connected to the (n-1)th stage first drive signal output terminal S(n-1), the nth stage first drive signal output terminal S(n), the first voltage terminal V1, the second voltage terminal V2, and the nth stage second drive signal output terminal E(n), respectively. It is used to control the nth stage second drive signal output terminal E(n) to output the nth stage second drive signal under the control of the (n-1)th stage first drive signal and the nth stage first drive signal, according to the first voltage signal provided by the first voltage terminal V1 and the second voltage signal provided by the second voltage terminal V2.

[0138] The driving module described in this embodiment is equipped with a first conversion circuit to generate a second driving signal under the control of a first driving signal generated by the first driving circuit, based on a first voltage signal and a second voltage signal. This reduces the space occupied by the driving module and narrows its width, which is beneficial for achieving a narrow bezel on the display panel.

[0139] In at least one embodiment of this disclosure, the first voltage signal and the second voltage signal may be DC voltage signals, but are not limited thereto.

[0140] In this embodiment of the disclosure, a first driving sub-circuit and a first conversion sub-circuit are assigned to each row of pixel circuits, thereby generating a first driving signal and a second driving signal provided to that row of pixel circuits.

[0141] In at least one embodiment of this disclosure, when the display panel is a small-sized display panel, such as a watch, the first driving circuit and the first conversion circuit can be disposed on one side of the display panel for single-sided driving; when the display panel is a medium-to-large-sized display panel, such as a mobile phone or computer screen, in order to adapt to the display image quality, the first driving circuit and the first conversion circuit can be disposed on both sides of the display panel for bilateral synchronous driving.

[0142] In at least one embodiment of this disclosure, such as Figure 2 As shown, the nth first conversion sub-circuit may include the nth first conversion module 211 and the nth second conversion module 212;

[0143] The nth first conversion module 211 is electrically connected to the (n-1)th stage first drive signal output terminal S(n-1), the nth stage first drive signal output terminal S(n), the first voltage terminal V1, and the nth stage second drive signal output terminal E(n), respectively. It is used to control the output of the first voltage signal provided by the first voltage terminal V1 to the nth stage second drive signal output terminal under the control of the (n-1)th stage first drive signal, and to output the first voltage signal to the nth stage second drive signal output terminal E(n) under the control of the nth stage first drive signal.

[0144] The nth second conversion module 212 is electrically connected to the (n-1)th stage first drive signal output terminal S(n-1), the nth stage first drive signal output terminal S(n), the second voltage terminal V2, and the nth stage second drive signal output terminal S(n), respectively, and is used to output the second voltage signal provided by the second voltage terminal V2 to the nth stage second drive signal output terminal S(n) under the control of the (n-1)th stage first drive signal and the nth stage first drive signal.

[0145] This disclosure is as follows Figure 2 At least one embodiment of the nth first conversion sub-circuit shown includes an nth first conversion module 211 and an nth second conversion module 212; the nth first conversion module, under the control of the (n-1)th level first drive signal, controls the output of a first voltage signal to the output terminal of the nth level second drive signal, and under the control of the nth level first drive signal, outputs the first voltage signal to the output terminal E(n) of the nth level second drive signal; the nth second conversion module 212, under the control of the (n-1)th level first drive signal and the nth level first drive signal, outputs a second voltage signal to the output terminal S(n) of the nth level second drive signal.

[0146] Optionally, the nth first conversion module includes a first transistor and a second transistor, and the nth second conversion module includes a third transistor and a fourth transistor;

[0147] The control electrode of the first transistor is electrically connected to the output terminal of the first drive signal of the (n-1)th stage, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the output terminal of the second drive signal of the nth stage.

[0148] The control electrode of the second transistor is electrically connected to the output terminal of the first drive signal of the nth stage, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the output terminal of the second drive signal of the nth stage.

[0149] The control electrode of the third transistor is electrically connected to the output terminal of the first drive signal of the (n-1)th stage, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the output terminal of the second drive signal of the nth stage.

[0150] The control electrode of the fourth transistor is electrically connected to the first drive signal output terminal of the nth stage, the first electrode of the fourth transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the fourth transistor is electrically connected to the second drive signal output terminal of the nth stage.

[0151] Optionally, the first transistor and the second transistor are both of the first type of transistor, and the third transistor and the fourth transistor are both of the second type of transistor.

[0152] In at least one embodiment of this disclosure, the first type of transistor may be a p-type transistor and the second type of transistor may be an n-type transistor; or, the first type of transistor may be an n-type transistor and the second type of transistor may be a p-type transistor.

[0153] like Figure 3 As shown, the nth first conversion module 211 may include a first transistor M1 and a second transistor M2, and the nth second conversion module 212 includes a third transistor M3 and a fourth transistor M4;

[0154] The gate of the first transistor M1 is electrically connected to the first drive signal output terminal S(n-1) of the (n-1)th stage, the source of the first transistor M1 is electrically connected to the first high voltage terminal Vgh1, and the drain of the first transistor M1 is electrically connected to the second drive signal output terminal E(n) of the nth stage.

[0155] The gate of the second transistor M2 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of the second transistor M2 is electrically connected to the first high voltage terminal Vgh1, and the drain of the second transistor M2 is electrically connected to the second drive signal output terminal E(n) of the nth stage.

[0156] The gate of the third transistor M3 is electrically connected to the first drive signal output terminal S(n-1) of the (n-1)th stage, the source of the third transistor M3 is electrically connected to the first low voltage terminal Vgl1, and the drain of the third transistor M3 is electrically connected to the second drive signal output terminal E(n) of the nth stage.

[0157] The gate of the fourth transistor M4 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of the fourth transistor M4 is electrically connected to the drain of the third transistor M3, and the drain of the fourth transistor M4 is electrically connected to the second drive signal output terminal E(n) of the nth stage.

[0158] exist Figure 3 In at least one embodiment of the nth first switching sub-circuit shown, M1 and M2 can be PMOS (P-type metal-oxide-semiconductor) transistors, and M3 and M4 can be NMOS (N-type metal-oxide-semiconductor) transistors, but are not limited thereto.

[0159] like Figure 3At least one embodiment of the nth first conversion sub-circuit shown can provide a corresponding second driving signal for the nth row pixel circuit disposed in the display area of ​​the display panel. The second driving signal can be a light emission control signal. The nth first driving signal can be a driving signal provided to the control electrode of the n-type transistor in the nth row pixel circuit, but is not limited thereto.

[0160] exist Figure 3 In at least one embodiment of the nth first conversion sub-circuit shown, the voltage value of the first high voltage signal provided by the first high voltage terminal Vgh1 can be 7V, and the voltage value of the first low voltage signal provided by the first low voltage terminal Vgl1 can be -9V, but is not limited thereto.

[0161] like Figure 4 As shown, this disclosure is as follows Figure 3 When at least one embodiment of the nth first conversion sub-circuit shown is in operation, the conversion period may include a first conversion time period t1, a second conversion time period t2, and a third conversion time period t3;

[0162] During the first conversion time period t1, S(n-1) provides a low voltage signal, S(n) provides a high voltage signal, M1 is turned on, M2 is turned off, M3 is turned off, and M4 is turned on, so as to output the first high voltage signal provided by the first high voltage terminal Vgh1 to E(n).

[0163] During the second conversion time period t2, S(n-1) provides a high voltage signal, S(n) provides a low voltage signal, M1 is turned off, M2 is turned on, M3 is turned on, and M4 is turned off, so as to output the first high voltage signal provided by the first high voltage terminal Vgh1 to E(n).

[0164] During the third conversion time period t3, S(n-1) provides a high voltage signal, S(n) provides a high voltage signal, M1 and M2 are both turned off, and M3 and M4 are both turned on, so as to output the first low voltage signal provided by the first low voltage terminal Vgl1 to E(n).

[0165] like Figure 5 As shown, 50 is the display area, 51 is the first area where the first driving circuit is set, 52 is the second area where the first conversion circuit is set, and 53 is the cutting edge and anti-collision area 53.

[0166] The first region 51, the second region 52, and the cutting edge and anti-collision area 53 are included in the side frame area of ​​the display panel;

[0167] The width of the second region 52 is 20um, the width of the first region 51 is 220um, and the width of the cutting edge and the anti-collision area 53 is 630um. Compared with related technologies, the width of the second region 52 is greatly reduced, which is conducive to achieving a narrow bezel.

[0168] While reducing the bezel of the display panel, this embodiment of the present disclosure can connect a second driving signal to each row of pixel circuits. Compared with the related technology in which two rows of pixel circuits share a second driving signal, this embodiment of the present disclosure can output the second driving signal row by row and delay it by one pulse in sequence.

[0169] Figure 6 yes Figure 3 The layout diagram shown is of at least one embodiment of the nth first conversion sub-circuit. Figure 7A yes Figure 6 The layout diagram of the first semiconductor layer in the middle. Figure 7B yes Figure 6 Layout diagram of the first gate metal layer in the middle. Figure 7C for Figure 6 The layout diagram of the second semiconductor layer in the middle. Figure 7D for Figure 6 The layout diagram of the second gate metal layer in the middle, Figure 7E for Figure 6 The layout diagram of the first source / drain metal layer in the image.

[0170] Figure 8 yes Figure 6 A-A' section diagram in the middle, Figure 9 yes Figure 6 The B-B' section diagram.

[0171] exist Figure 7A In the diagram, S1 is the source of M1, D1 is the drain of M1, S2 is the source of M2, and D2 is the drain of M2.

[0172] exist Figure 7C In the diagram, S3 is the source of M1, S3 is the source of M3, D3 is the drain of M3, S4 is the source of M4, and D4 is the drain of M4.

[0173] In at least one embodiment of this disclosure, the first semiconductor layer may be an LTPS semiconductor layer and the second semiconductor layer may be an IGZO (indium gallium zinc oxide) semiconductor layer, but is not limited thereto.

[0174] exist Figure 8In the diagram, 80 is the substrate, 81 is the first semiconductor layer, 82 is the first gate insulating layer, 83 is the first gate metal layer, 84 is the second gate insulating layer, 85 is the insulating layer, and 86 is the source / drain metal layer.

[0175] exist Figure 9 In the diagram, 80 is the substrate, 82 is the first gate insulating layer, 83 is the first gate metal layer, 84 is the second gate insulating layer, 87 is the second semiconductor layer, 85 is the insulating layer, and 86 is the source / drain metal layer.

[0176] In at least one embodiment of this disclosure, the insulating layer 85 may include a third gate insulating layer and an interlayer dielectric layer, but is not limited thereto.

[0177] In at least one embodiment of this disclosure, such as Figure 10 As shown, the first driving sub-circuit of the nth stage may include a first node control circuit 61, a control node control circuit 62, a second node control circuit 63, a first energy storage circuit 64, a second energy storage circuit 65, and an output circuit 66, wherein,

[0178] The first node control circuit 61 is electrically connected to the control clock signal terminal Gc, the sixth voltage terminal V6, the first node N1 and the control node N0 respectively. It is used to write the sixth voltage signal provided by the sixth voltage terminal V6 into the first node N1 under the control of the control clock signal provided by the control clock signal terminal Gc, and to write the control clock signal provided by the control clock signal terminal Gc into the first node N1 under the control of the potential of the control node N0.

[0179] The control node control circuit 62 is electrically connected to the control clock signal terminal Gc, the input terminal I1, the control node N0, the first node N1, the output clock signal terminal Go, and the fifth voltage terminal V5, respectively. It is used to write the input signal provided by the input terminal I1 into the control node N0 under the control of the control clock signal, and to write the fifth voltage signal provided by the fifth voltage terminal V5 into the first node under the control of the potential of the first node N1 and the output control signal provided by the output control clock signal terminal Go.

[0180] The second node control circuit 63 is electrically connected to the sixth voltage terminal V6, the control node N0, and the second node N2, respectively, and is used to control the connection between the control node N0 and the second node N2 under the control of the sixth voltage signal provided by the sixth voltage terminal V6.

[0181] The first terminal of the first energy storage circuit 64 is electrically connected to the second node N2, and the second terminal of the first energy storage circuit 64 is electrically connected to the output terminal S(n) of the first drive signal of the nth stage; the first energy storage circuit 64 is used to store electrical energy.

[0182] The first end of the second energy storage circuit 65 is electrically connected to the first node N1, and the second end of the second energy storage circuit 65 is electrically connected to the fifth voltage terminal V5. The second energy storage circuit 65 is used to store electrical energy.

[0183] The output circuit 66 is electrically connected to the first node N1, the second node N2, the output clock signal terminal Go, the fifth voltage terminal V5, and the nth stage first drive signal output terminal S(n), respectively. It is used to output the fifth voltage signal provided by the fifth voltage terminal V5 to the nth stage first drive signal output terminal S(n) under the control of the potential of the first node N1, and to output the output clock signal to the nth stage first drive signal output terminal S(n) under the control of the potential of the second node N2.

[0184] In at least one embodiment of this disclosure, the fifth voltage terminal V5 may be a second high voltage terminal and the sixth voltage terminal V6 may be a second low voltage terminal, but this is not a limitation.

[0185] Optionally, the first node control circuit includes a first control transistor and a second control transistor;

[0186] The control electrode of the first control transistor is electrically connected to the control clock signal terminal, the first electrode of the first control transistor is electrically connected to the sixth voltage terminal, and the second electrode of the first control transistor is electrically connected to the first node.

[0187] The control electrode of the second control transistor is electrically connected to the control node, the first electrode of the second control transistor is electrically connected to the control clock signal terminal, and the second electrode of the second control transistor is electrically connected to the first node.

[0188] The control node control circuit includes a third control transistor, a fourth control transistor, and a fifth control transistor;

[0189] The control electrode of the third control transistor is electrically connected to the control clock signal terminal, the first electrode of the third control transistor is electrically connected to the input terminal, and the second electrode of the third control transistor is electrically connected to the control node.

[0190] The control electrode of the fourth control transistor is electrically connected to the first node, and the first electrode of the fourth control transistor is electrically connected to the fifth voltage terminal.

[0191] The control electrode of the fifth control transistor is electrically connected to the output clock signal terminal, the first electrode of the fifth control transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the fifth control transistor is electrically connected to the control node.

[0192] The second node control circuit includes a sixth control transistor;

[0193] The control electrode of the sixth control transistor is electrically connected to the sixth voltage terminal, the first electrode of the sixth control transistor is electrically connected to the control node, and the second electrode of the sixth control transistor is electrically connected to the second node.

[0194] The first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0195] The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the output terminal of the first drive signal of the nth stage.

[0196] The first terminal of the second capacitor is electrically connected to the first node, and the second terminal of the second capacitor is electrically connected to the fifth voltage terminal.

[0197] The output circuit includes a first output transistor and a second output transistor;

[0198] The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the fifth voltage terminal, and the second electrode of the first output transistor is electrically connected to the nth stage first drive signal output terminal.

[0199] The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the output terminal of the first drive signal of the nth stage, and the second electrode of the second output transistor is electrically connected to the output clock signal terminal.

[0200] like Figure 11 As shown, in Figure 10 Based on at least one embodiment of the nth first driving sub-circuit shown,

[0201] The first node control circuit 61 includes a first control transistor Mc1 and a second control transistor Mc2;

[0202] The gate of the first control transistor Mc1 is electrically connected to the control clock signal terminal Gc, the source of the first control transistor Mc1 is electrically connected to the second low voltage terminal Vgl2, and the drain of the first control transistor Mc1 is electrically connected to the first node N1.

[0203] The gate of the second control transistor Mc2 is electrically connected to the control node N0, the source of the second control transistor Mc2 is electrically connected to the control clock signal terminal Gc, and the drain of the second control transistor Mc2 is electrically connected to the first node N1.

[0204] The control node control circuit 62 includes a third control transistor Mc3, a fourth control transistor Mc4, and a fifth control transistor Mc5.

[0205] The gate of the third control transistor Mc3 is electrically connected to the control clock signal terminal Gc, the source of the third control transistor Mc3 is electrically connected to the input terminal I1, and the drain of the third control transistor Mc3 is electrically connected to the control node N0.

[0206] The gate of the fourth control transistor Mc4 is electrically connected to the first node N1, and the drain of the fourth control transistor Mc4 is electrically connected to the second high voltage terminal Vgh2.

[0207] The gate of the fifth control transistor Mc5 is electrically connected to the output clock signal terminal Go, the source of the fifth control transistor Mc5 is electrically connected to the drain of the fourth control transistor Mc4, and the drain of the fifth control transistor Mc5 is electrically connected to the control node N0.

[0208] The second node control circuit 63 includes a sixth control transistor Mc6;

[0209] The gate of the sixth control transistor Mc6 is electrically connected to the second low voltage terminal Vgl2, the source of the sixth control transistor Mc6 is electrically connected to the control node N0, and the drain of the sixth control transistor Mc6 is electrically connected to the second node N2.

[0210] The first energy storage circuit 64 includes a first capacitor C1, and the second energy storage circuit 65 includes a second capacitor C2;

[0211] The first terminal of the first capacitor C1 is electrically connected to the second node N2, and the second terminal of the first capacitor C1 is electrically connected to the first drive signal output terminal S(n) of the nth stage.

[0212] The first terminal of the second capacitor C2 is electrically connected to the first node N1, and the second terminal of the second capacitor C2 is electrically connected to the second high voltage terminal Vgh2.

[0213] The output circuit 66 includes a first output transistor Mo1 and a second output transistor Mo2;

[0214] The gate of the first output transistor Mo1 is electrically connected to the first node N1, the source of the first output transistor Mo1 is electrically connected to the second high voltage terminal Vgh2, and the drain of the first output transistor Mo2 is electrically connected to the nth stage first drive signal output terminal S(n).

[0215] The gate of the second output transistor Mo2 is electrically connected to the second node N2, the source of the second output transistor Mo2 is electrically connected to the nth stage first drive signal output terminal S(n), and the drain of the second output transistor Mo2 is electrically connected to the output clock signal terminal Go.

[0216] exist Figure 11 In at least one embodiment of the nth-stage first driving sub-circuit shown, the fifth voltage terminal can be the second high voltage terminal Vgh2, and the sixth voltage terminal can be the second low voltage terminal Vgl2, but is not limited thereto.

[0217] exist Figure 11 In at least one embodiment of the nth-stage first driver sub-circuit shown, all transistors are p-type transistors, but this is not a limitation.

[0218] Figure 12 This is a schematic diagram showing the connection between the nth level first driving sub-circuit 11 and the nth first conversion sub-circuit 21, and a schematic diagram showing the connection between the (n-1)th level first driving sub-circuit 12 and the (n-1)th first conversion sub-circuit 22.

[0219] exist Figure 12 In the diagram, S(n-1) is the first drive signal output terminal of the (n-1)th stage, S(n) is the first drive signal output terminal of the nth stage, and S(n-2) is the first drive signal output terminal of the (n-2)th stage; E(n-1) is the second drive signal output terminal of the (n-1)th stage, and E(n) is the second drive signal output terminal of the nth stage.

[0220] exist Figure 12 In at least one embodiment shown, the input terminal of the (n-1)th stage first driving sub-circuit 12 is electrically connected to the starting voltage terminal GSTV, and the input terminal of the nth stage first driving sub-circuit 11 is electrically connected to S(n-1).

[0221] In the (n-1)th stage first driver sub-circuit, the control clock signal terminal is electrically connected to the first clock signal terminal Gck, and the output clock signal terminal is electrically connected to the second clock signal terminal Gcb.

[0222] In the first driver sub-circuit of the nth stage, the control clock signal terminal is electrically connected to the second clock signal terminal Gcb, and the output clock signal terminal is electrically connected to the first clock signal terminal Gck.

[0223] In practice, pixel circuit design has begun to integrate the advantages of PMOS and NMOS transistors (e.g., combining LTPS (Low Temperature Polycrystalline Silicon) and IGZO (Indium Gallium Zinc Oxide) technologies to form LTPO (Low Temperature Oxide) 7T1C or 8T1C pixel circuits), placing both types of transistors in the same pixel circuit. This design trend requires two switching signals, one for the PMOS transistor and one for the NMOS transistor, which are asynchronous. Therefore, embodiments of this disclosure can employ a second conversion circuit to generate a third driving signal, which is a switching signal provided to the p-type transistor in the pixel circuit.

[0224] The driving module described in at least one embodiment of this disclosure further includes a second conversion circuit; the second conversion circuit includes a plurality of second conversion sub-circuits;

[0225] like Figure 13 As shown, the (n-1)th second conversion sub-circuit 131 is electrically connected to the (n-1)th stage first drive signal output terminal S(n), the nth stage first drive signal output terminal S(n), the nth stage second drive signal output terminal E(n), the third voltage terminal V3, the fourth voltage terminal V4, and the (n-1)th stage third drive signal output terminal NS(n-1), respectively. It is used to control the (n-1)th stage third drive signal output terminal NS(n-1) to output the (n-1)th stage third drive signal under the control of the (n-1)th stage first drive signal, the nth stage first drive signal, and the nth stage second drive signal, according to the third voltage signal provided by the third voltage terminal V3 and the fourth voltage signal provided by the fourth voltage terminal V4.

[0226] In at least one embodiment of this disclosure, such as Figure 14 As shown, the (n-1)th second conversion sub-circuit may include the (n-1)th third conversion module 143, the (n-1)th fourth conversion module 144, and the (n-1)th fifth conversion module 145;

[0227] The (n-1)th third conversion module 143 is electrically connected to the (n-1)th stage first drive signal output terminal S(n-1), the third voltage terminal V3 and the (n-1)th stage third drive signal output terminal NS(n-1), respectively, and is used to output the third voltage signal provided by the third voltage terminal V3 to the (n-1)th stage third drive signal output terminal NS(n-1) under the control of the (n-1)th stage first drive signal;

[0228] The (n-1)th fourth conversion module 144 is electrically connected to the nth stage first drive signal output terminal S(n), the fourth voltage terminal V4, and the (n-1)th stage third drive signal output terminal NS(n-1), respectively, and is used to output the fourth voltage signal provided by the fourth voltage terminal V4 to the (n-1)th stage third drive signal output terminal NS(n-1) under the control of the nth stage first drive signal;

[0229] The (n-1)th fifth conversion module 145 is electrically connected to the nth stage second drive signal output terminal E(n), the fourth voltage terminal V4, and the (n-1)th stage third drive signal output terminal NS(n-1), respectively, and is used to output the fourth voltage signal provided by the fourth voltage terminal V4 to the (n-1)th stage third drive signal output terminal NS(n-1) under the control of the nth stage second drive signal.

[0230] In at least one embodiment of this disclosure, the fourth voltage terminal may be a third low voltage terminal, and the third voltage terminal may be a third high voltage terminal, but is not limited thereto.

[0231] like Figure 14 In at least one embodiment of the (n-1)th second conversion sub-circuit shown, the (n-1)th third conversion module 143, under the control of the (n-1)th stage first drive signal, outputs a third voltage signal to the (n-1)th stage third drive signal output terminal NS(n-1); the (n-1)th fourth conversion module 144, under the control of the nth stage first drive signal, outputs a fourth voltage signal to the (n-1)th stage third drive signal output terminal NS(n-1); and the (n-1)th fifth conversion module 145, under the control of the nth stage second drive signal, outputs a fourth voltage signal to the (n-1)th stage third drive signal output terminal NS(n-1).

[0232] Optionally, the (n-1)th third conversion module includes a fifth transistor, the (n-1)th fourth conversion module includes a sixth transistor, and the (n-1)th fifth conversion module includes a seventh transistor;

[0233] The control electrode of the fifth transistor is electrically connected to the output terminal of the first drive signal of the (n-1)th stage, the first electrode of the fifth transistor is electrically connected to the third voltage terminal, and the second electrode of the fifth transistor is electrically connected to the output terminal of the third drive signal of the (n-1)th stage.

[0234] The control electrode of the sixth transistor is electrically connected to the first drive signal output terminal of the nth stage, the first electrode of the sixth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the sixth transistor is electrically connected to the third drive signal output terminal of the (n-1)th stage.

[0235] The control electrode of the seventh transistor is electrically connected to the output terminal of the second drive signal of the nth stage, the first electrode of the seventh transistor is electrically connected to the fourth voltage terminal, and the second electrode of the seventh transistor is electrically connected to the output terminal of the third drive signal of the (n-1)th stage.

[0236] Optionally, the fifth transistor, the sixth transistor, and the seventh transistor are all of the first type of transistor.

[0237] like Figure 15 As shown, in Figure 14 Based on at least one embodiment of the (n-1)th second conversion sub-circuit shown, the (n-1)th third conversion module 143 includes a fifth transistor M5, the (n-1)th fourth conversion module 144 includes a sixth transistor M6, and the (n-1)th fifth conversion module 145 includes a seventh transistor M7;

[0238] The gate of the fifth transistor M5 is electrically connected to the first drive signal output terminal S(n) of the (n-1)th stage, the source of the fifth transistor M5 is electrically connected to the third high voltage terminal Vgh3, and the drain of the fifth transistor M5 is electrically connected to the third drive signal output terminal NS(n-1) of the (n-1)th stage.

[0239] The gate of the sixth transistor M6 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of the sixth transistor M6 is electrically connected to the third low voltage terminal Vgl3, and the drain of the sixth transistor M6 is electrically connected to the third drive signal output terminal NS(n-1) of the (n-1)th stage.

[0240] The gate of the seventh transistor M7 is electrically connected to the second drive signal output terminal E(n) of the nth stage, the source of the seventh transistor M7 is electrically connected to the third low voltage terminal Vgl3, and the drain of the seventh transistor M7 is electrically connected to the third drive signal output terminal NS(n-1) of the (n-1)th stage.

[0241] In at least one embodiment of the (n-1)th second converter circuit as shown in Figure 15, M5, M6, and M7 are all PMOS transistors, but not limited thereto.

[0242] In at least one embodiment of the (n-1)th second conversion sub-circuit as shown in Figure 15, the voltage value of the third high voltage signal provided by the third high voltage terminal Vgh3 can be 7V, and the voltage value of the third low voltage signal provided by the third low voltage terminal Vgl3 can be -9V, but is not limited thereto.

[0243] The embodiments disclosed herein can generate a third driving signal under the control of the first and second driving signals by adding only three transistors, which is beneficial for achieving a narrow bezel.

[0244] like Figure 16 As shown in Figure 15, at least one embodiment of the (n-1)th second conversion sub-circuit, when in operation, includes a conversion period t1, a second conversion period t2, and a third conversion period t3;

[0245] During the first conversion time period t1, S(n-1) provides a low voltage signal, S(n) provides a high voltage signal, E(n) provides a high voltage signal, M4 is turned on, and M5 and M6 are both turned off, outputting the third high voltage signal to NS(n-1);

[0246] During the second conversion time period t2, S(n-1) provides a high voltage signal, S(n) provides a low voltage signal, E(n) provides a high voltage signal, M5 is turned off, M6 is turned on, M7 is turned off, and the third low voltage signal is output to NS(n-1).

[0247] During the third transition time period t3, S(n-1) provides a high voltage signal, S(n) provides a high voltage signal, E(n) provides a low voltage signal, M5 and M6 are both turned off, M7 is turned on, and the third low voltage signal is output to NS(n-1).

[0248] Figure 17 It is a connection diagram of the nth level first driving sub-circuit 11, the nth first conversion sub-circuit 21 and the (n-1)th second conversion sub-circuit 131, and a connection diagram of the (n-1)th level first driving sub-circuit 12, the (n-1)th first conversion sub-circuit 22 and the (n-2)th second conversion sub-circuit 132;

[0249] exist Figure 17 In the diagram, S(n-1) is the first drive signal output terminal of the (n-1)th stage, S(n) is the first drive signal output terminal of the nth stage, S(n-2) is the first drive signal output terminal of the (n-2)th stage; E(n-1) is the second drive signal output terminal of the (n-1)th stage, E(n) is the second drive signal output terminal of the nth stage; NS(n-2) is the third drive signal output terminal of the (n-2)th stage; and NS(n-1) is the third drive signal output terminal of the (n-1)th stage.

[0250] exist Figure 17 In at least one embodiment shown, the input terminal of the (n-1)th stage first driving sub-circuit 12 is electrically connected to the starting voltage terminal GSTV, and the input terminal of the nth stage first driving sub-circuit 11 is electrically connected to S(n-1).

[0251] In the (n-1)th stage first driver sub-circuit, the control clock signal terminal is electrically connected to the first clock signal terminal Gck, and the output clock signal terminal is electrically connected to the second clock signal terminal Gcb.

[0252] In the first driver sub-circuit of the nth stage, the control clock signal terminal is electrically connected to the second clock signal terminal Gcb, and the output clock signal terminal is electrically connected to the first clock signal terminal Gck.

[0253] In at least one embodiment of this disclosure, the voltage values ​​of the first high-voltage signal, the second high-voltage signal, and the third high-voltage signal may be the same or different.

[0254] The voltage values ​​of the first low voltage signal, the second low voltage signal, and the third low voltage signal can be the same or different.

[0255] The display panel described in this embodiment includes the aforementioned driving module disposed in the peripheral area and an N-row, M-column pixel circuit disposed in the display area; N and M are positive integers;

[0256] The driving module is used to provide driving signals for the pixel circuit.

[0257] In at least one embodiment of this disclosure, the driving signal includes a first driving signal and a second driving signal;

[0258] The first driving circuit included in the driving module is located on the side of the first conversion circuit included in the driving module that is away from the display area.

[0259] like Figure 18 As shown, in at least one embodiment of this disclosure, the circuit 181 is the first first driving circuit, and the circuit 182 is the second first driving circuit. The first first driving circuit 181 is disposed on the left side of the display area A0, and the second first driving circuit 182 is disposed on the right side of the display area A0.

[0260] The first conversion circuit 183 is disposed between the first driving circuit 181 and the display area A0, and the second conversion circuit 184 is disposed between the second driving circuit 182 and the display area A0.

[0261] exist Figure 18 In the diagram, P1 is the red pixel circuit, P2 is the green pixel circuit, P3 is the blue pixel circuit, and P0 is the display panel.

[0262] In at least one embodiment of this disclosure, the driving signal further includes a third driving signal; the driving module further includes a second conversion circuit.

[0263] The second conversion circuit is located on the side of the first conversion circuit that is close to the display area.

[0264] In specific implementation, when the driving module further includes a second conversion circuit, the second conversion circuit may be located between the first conversion circuit and the display area, but is not limited thereto; in actual operation, the second conversion circuit may also be located between the first conversion circuit and the first driving circuit.

[0265] Optionally, the pixel circuit in the nth row and mth column includes a data writing circuit in the nth row and mth column, a compensation control circuit in the nth row and mth column, a first reset circuit in the nth row and mth column, a second reset circuit in the nth row and mth column, a first light-emitting control circuit in the nth row and mth column, a second light-emitting control circuit in the nth row and mth column, a driving circuit in the nth row and mth column, a third energy storage circuit in the nth row and mth column, and a light-emitting element in the nth row and mth column; n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M;

[0266] The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth driving signal output terminal.

[0267] The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the control terminal of the driving circuit in the nth row and mth column, and the second terminal of the driving circuit in the nth row and mth column, respectively, and is used to control the connection between the control terminal of the driving circuit in the nth row and mth column and the second terminal of the driving circuit in the nth row and mth column under the control of the first driving signal of the nth stage;

[0268] The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th stage first drive signal, the control terminal of the (n-1)th row and mth column drive circuit, and the first initial voltage terminal, respectively. It is used to write the first initial voltage provided by the first initial voltage terminal into the control terminal of the (n-1)th row and mth column drive circuit under the control of the (n-1)th stage first drive signal provided by the (n-1)th stage first drive signal output terminal.

[0269] The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the first driving signal of the nth stage.

[0270] The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the nth level second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the (n+1)th second driving signal;

[0271] The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal;

[0272] The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal;

[0273] The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy;

[0274] The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage level.

[0275] In at least one embodiment of this disclosure, the first initial voltage terminal and the second initial voltage terminal may be the same initial voltage terminal or different initial voltage terminals.

[0276] In at least one embodiment of this disclosure, the first level terminal may be a high level terminal and the second level terminal may be a low level terminal, but this is not a limitation.

[0277] like Figure 19 As shown, the first reset circuit 191 in the nth row and mth column includes a first display control transistor Md1; the compensation control circuit 192 in the nth row and mth column includes a second display control transistor Md2; the driving circuit 193 in the nth row and mth column includes a driving transistor Md3; the data writing circuit 194 in the nth row and mth column includes a fourth display control transistor Md4; the first light-emitting control circuit 195 in the nth row and mth column includes a fifth display control transistor Md5; the second light-emitting control circuit 196 in the nth row and mth column includes a sixth display control transistor Md6; and the second reset circuit 197 in the nth row and mth column includes a seventh display control transistor Md7. The light-emitting element in the nth row and mth column is an organic light-emitting diode O0 in the nth row and mth column. The third energy storage circuit 198 in the nth row and mth column includes a storage capacitor C0.

[0278] The gate of Md1 is electrically connected to the output terminal S(n-1) of the first drive signal of the (n-1)th stage, the source of Md1 is electrically connected to the initial voltage terminal I0, and the drain of Md1 is electrically connected to the gate of Md3.

[0279] The gate of Md2 is electrically connected to the output terminal S(n) of the first drive signal of the nth stage, the source of Md2 is electrically connected to the gate of Md3, and the drain of Md2 is electrically connected to the drain of Md3.

[0280] The gate of Md4 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of Md4 is electrically connected to the data line Dm of the mth column, and the drain of Md4 is electrically connected to the source of Md3.

[0281] The gate of Md5 is electrically connected to the output terminal E(n) of the second drive signal of the nth stage, the source of Md5 is electrically connected to the high-level terminal Vdd, and the drain of Md5 is electrically connected to the source of Md3.

[0282] The gate of Md6 is electrically connected to the output terminal E(n) of the second drive signal of the nth stage, the source of Md6 is electrically connected to the drain of Md3, the drain of Md6 is electrically connected to the anode of O0, and the cathode of O0 is electrically connected to the low-level terminal Vss.

[0283] The gate of Md7 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of Md7 is electrically connected to the initial voltage terminal I0, and the drain of Md7 is electrically connected to the drain of Md6.

[0284] The first terminal of C0 is electrically connected to the high-level terminal Vdd, and the second terminal of C0 is electrically connected to the gate of Md3.

[0285] exist Figure 19 In at least one embodiment of the pixel circuit shown, all transistors are PMOS transistors. Therefore, only a first driving circuit and a first conversion circuit are needed, and a second conversion circuit is not required to control the operation of the pixel circuit, which is beneficial for achieving a narrow bezel.

[0286] like Figure 20 As shown, Figure 19 In at least one embodiment of the pixel circuit shown, the display cycle includes an initialization phase ST1, a data writing phase ST2, and a light emission phase ST3, which are set sequentially.

[0287] During the initialization phase ST1, S(n-1) provides a low voltage signal, S(n) provides a high voltage signal, E(n) provides a high voltage signal, Md1 is turned on, and I0 provides an initial voltage Vinit to write Vinit into the gate of Md3 so that Md3 can be turned on when the data writing phase ST2 begins.

[0288] During the initialization phase ST1, Md2, Md3, Md4, Md5, Md6 and Md7 are all turned off;

[0289] During the data writing phase ST2, S(n-1) provides a high voltage signal, S(n) provides a low voltage signal, and E(n) provides a high voltage signal. Md2 and Md4 are both turned on. Dm provides the data voltage Vdata to write Vdata to the source of Md3 and controls the connection between the gate and drain of Md3. Md7 is turned on, and I0 provides the initial voltage Vinit to write Vinit to the anode of O0 to control O0 from emitting light and to eliminate the charge remaining on the anode of O0.

[0290] When the data writing stage ST2 begins, Md3 is turned on, charging C0 through Vdata to increase the potential of the gate of Md3 until Md3 is turned off. At this time, the potential of the gate of Md3 is Vdata + Vth, where Vth is the threshold voltage of Md3.

[0291] During the data writing phase ST2, Md1, Md5, and Md6 are all turned off.

[0292] During the light-emitting stage ST3, S(n-1) provides a high voltage signal, S(n) provides a high voltage signal, E(n) provides a low voltage signal, Md3, Md5 and Md6 are all turned on, and Md3 drives O0 to emit light;

[0293] During the light-emitting stage ST3, Md1, Md2, Md4 and Md7 are all turned off.

[0294] like Figure 21 As shown, the first reset circuit 191 in the nth row and mth column includes a first display control transistor Md1; the compensation control circuit 192 in the nth row and mth column includes a second display control transistor Md2; the driving circuit 193 in the nth row and mth column includes a driving transistor Md3; the data writing circuit 194 in the nth row and mth column includes a fourth display control transistor Md4; the first light-emitting control circuit 195 in the nth row and mth column includes a fifth display control transistor Md5; the second light-emitting control circuit 196 in the nth row and mth column includes a sixth display control transistor Md6; and the second reset circuit 197 in the nth row and mth column includes a seventh display control transistor Md7. The light-emitting element in the nth row and mth column is an organic light-emitting diode O0 in the nth row and mth column. The third energy storage circuit 198 in the nth row and mth column includes a storage capacitor C0.

[0295] The gate of Md1 is electrically connected to the output terminal S(n-1) of the first drive signal of the (n-1)th stage, the source of Md1 is electrically connected to the initial voltage terminal I0, and the drain of Md1 is electrically connected to the gate of Md3.

[0296] The gate of Md2 is electrically connected to the output terminal S(n) of the first drive signal of the nth stage, the source of Md2 is electrically connected to the gate of Md3, and the drain of Md2 is electrically connected to the drain of Md3.

[0297] The gate of Md4 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of Md4 is electrically connected to the data line Dm of the mth column, and the drain of Md4 is electrically connected to the source of Md3.

[0298] The gate of Md5 is electrically connected to the output terminal E(n+1) of the second drive signal of the (n+1)th stage, the source of Md5 is electrically connected to the high-level terminal Vdd, and the drain of Md5 is electrically connected to the source of Md3.

[0299] The gate of Md6 is electrically connected to the output terminal E(n) of the second drive signal of the nth stage, the source of Md6 is electrically connected to the drain of Md3, the drain of Md6 is electrically connected to the anode of O0, and the cathode of O0 is electrically connected to the low-level terminal Vss.

[0300] The gate of Md7 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of Md7 is electrically connected to the initial voltage terminal I0, and the drain of Md7 is electrically connected to the drain of Md6.

[0301] The first terminal of C0 is electrically connected to the high-level terminal Vdd, and the second terminal of C0 is electrically connected to the gate of Md3.

[0302] exist Figure 21 In at least one embodiment of the pixel circuit shown, all transistors are PMOS transistors. Therefore, only a first driving circuit and a first conversion circuit are needed, and a second conversion circuit is not required to control the operation of the pixel circuit, which is beneficial for achieving a narrow bezel.

[0303] exist Figure 21 In at least one embodiment of the pixel circuit shown, the gate of Md5 is electrically connected to E(n+1), and the gate of Md6 is electrically connected to E(n) to improve short-term image retention.

[0304] like Figure 22 As shown, Figure 21 When at least one embodiment of the pixel circuit shown is in operation, the display cycle includes an initialization phase ST1, a data writing phase ST2, a light emission preparation phase ST0, and a light emission phase ST3, which are set sequentially.

[0305] During the initialization phase ST1, S(n-1) provides a low voltage signal, S(n) provides a high voltage signal, E(n) provides a high voltage signal, E(n+1) provides a low voltage signal, Md1 is turned on, and I0 provides an initial voltage Vinit to write Vinit into the gate of Md3 so that Md3 can be turned on when the data writing phase ST2 begins.

[0306] During the initialization phase ST1, Md2, Md3, Md4, Md5, Md6 and Md7 are all turned off;

[0307] During the data writing phase ST2, S(n-1) provides a high voltage signal, S(n) provides a low voltage signal, E(n) provides a high voltage signal, and E(n+1) provides a high voltage signal. Md2 and Md4 are both turned on. Dm provides the data voltage Vdata to write Vdata to the source of Md3 and controls the connection between the gate and drain of Md3. Md7 is turned on, and I0 provides the initial voltage Vinit to write Vinit to the anode of O0, thereby controlling O0 to not emit light and eliminating the charge remaining on the anode of O0.

[0308] When the data writing stage ST2 begins, Md3 is turned on, charging C0 through Vdata to increase the potential of the gate of Md3 until Md3 is turned off. At this time, the potential of the gate of Md3 is Vdata + Vth, where Vth is the threshold voltage of Md3.

[0309] During the data writing phase ST2, Md1, Md5, and Md6 are all turned off.

[0310] During the light emission preparation stage ST0, S(n-1) provides a high voltage signal, S(n) provides a high voltage signal, E(n) provides a low voltage signal, E(n+1) provides a high voltage signal, Md6 is turned on, and Md1, Md2, Md4, Md5 and Md7 are all turned off.

[0311] During the light-emitting stage ST3, S(n-1) provides a high voltage signal, S(n) provides a high voltage signal, E(n) provides a low voltage signal, E(n+1) provides a low voltage signal, Md3, Md5 and Md6 are all turned on, and Md3 drives O0 to emit light;

[0312] During the light-emitting stage ST3, Md1, Md2, Md4 and Md7 are all turned off.

[0313] Optionally, the pixel circuit in the nth row and mth column includes a data writing circuit in the nth row and mth column, an on / off control circuit in the nth row and mth column, a compensation control circuit in the nth row and mth column, a first reset circuit in the nth row and mth column, a second reset circuit in the nth row and mth column, a first light-emitting control circuit in the nth row and mth column, a second light-emitting control circuit in the nth row and mth column, a driving circuit in the nth row and mth column, a third energy storage circuit in the nth row and mth column, and a light-emitting element in the nth row and mth column; n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M;

[0314] The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth driving signal output terminal.

[0315] The on / off control circuit of the nth row and mth column is electrically connected to the output terminal of the nth level third drive signal, the control terminal of the nth row and mth column drive circuit, and the connection node of the nth row and mth column, respectively, and is used to control the connection between the control terminal of the nth row and mth column drive circuit and the connection node of the nth row and mth column under the control of the nth level third drive signal provided by the output terminal of the nth level third drive signal;

[0316] The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level first drive signal, the connection node in the nth row and mth column, and the second terminal of the drive circuit in the nth row and mth column, respectively, and is used to control the connection between the connection node in the nth row and mth column and the second terminal of the drive circuit in the nth row and mth column under the control of the nth level first drive signal;

[0317] The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th level first drive signal, the connection node in the nth row and mth column, and the first initial voltage terminal, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the connection node in the nth row and mth column under the control of the (n-1)th level first drive signal provided by the output terminal of the (n-1)th level first drive signal.

[0318] The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the first driving signal of the nth stage.

[0319] The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the nth level second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the (n+1)th second driving signal;

[0320] The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal;

[0321] The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal;

[0322] The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy;

[0323] The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage terminal;

[0324] The nth stage third drive signal output terminal and the nth stage second drive signal output terminal are connected to the same drive signal.

[0325] like Figure 23 As shown, the first reset circuit 191 in the nth row and mth column includes a first display control transistor Md1; the compensation control circuit 192 in the nth row and mth column includes a second display control transistor Md2; the driving circuit 193 in the nth row and mth column includes a driving transistor Md3; the data writing circuit 194 in the nth row and mth column includes a fourth display control transistor Md4; the first light-emitting control circuit 195 in the nth row and mth column includes a fifth display control transistor Md5; the second light-emitting control circuit 196 in the nth row and mth column includes a sixth display control transistor Md6; and the second reset circuit 197 in the nth row and mth column includes a seventh display control transistor Md7. The light-emitting element in the nth row and mth column is an organic light-emitting diode O0 in the nth row and mth column. The third energy storage circuit 198 in the nth row and mth column includes a storage capacitor C0; and the on / off control circuit 199 in the nth row and mth column includes an eighth display control transistor Md8.

[0326] The gate of Md1 is electrically connected to the output terminal S(n-1) of the first drive signal of the (n-1)th stage, the source of Md1 is electrically connected to the initial voltage terminal I0, and the drain of Md1 is electrically connected to the connection node Nj in the nth row and mth column.

[0327] The gate of Md2 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of Md2 is electrically connected to the connection node Nj in the nth row and mth column, and the drain of Md2 is electrically connected to the drain of Md3.

[0328] The gate of Md4 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of Md4 is electrically connected to the data line Dm of the mth column, and the drain of Md4 is electrically connected to the source of Md3.

[0329] The gate of Md5 is electrically connected to the output terminal E(n) of the second drive signal of the nth stage, the source of Md5 is electrically connected to the high-level terminal Vdd, and the drain of Md5 is electrically connected to the source of Md3.

[0330] The gate of Md6 is electrically connected to the output terminal E(n) of the second drive signal of the nth stage, the source of Md6 is electrically connected to the drain of Md3, the drain of Md6 is electrically connected to the anode of O0, and the cathode of O0 is electrically connected to the low-level terminal Vss.

[0331] The gate of Md7 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of Md7 is electrically connected to the initial voltage terminal I0, and the drain of Md7 is electrically connected to the drain of Md6.

[0332] The gate of Md8 is electrically connected to the output terminal NS(n) of the third drive signal of the nth stage, the source of Md8 is electrically connected to the gate of Md3, and the drain of Md8 is electrically connected to the connection node Nj in the nth row and mth column.

[0333] The first terminal of C0 is electrically connected to the high-level terminal Vdd, and the second terminal of C0 is electrically connected to the gate of Md3.

[0334] exist Figure 23 In at least one embodiment of the pixel circuit in the nth row and mth column shown, Md1, Md2, Md3, Md4, Md5, Md6 and Md7 are all PMOS transistors, and Md8 is an NMOS transistor, but this is not a limitation.

[0335] exist Figure 23 In at least one embodiment of the pixel circuit in the nth row and mth column shown, the first level terminal is a high level terminal Vdd, and the second level terminal is a low level terminal Vss;

[0336] The first initial voltage terminal and the second initial voltage terminal are the same initial voltage terminal;

[0337] However, this is not the only limit.

[0338] like Figure 24 As shown, Figure 23 In at least one embodiment of the pixel circuit in the nth row and mth column shown, the display cycle includes an initialization phase ST1, a data writing phase ST2, and a light emission phase ST3 that are set sequentially during operation.

[0339] During the initialization phase ST1, S(n) provides a high voltage signal, S(n-1) provides a low voltage signal, NS(n) provides a high voltage signal, E(n) provides a high voltage signal, Md1 and Md8 are turned on, and I0 provides the initial voltage Vinit to write Vinit into the gate of Md3 so that Md3 can be turned on when the data writing phase ST2 begins.

[0340] During the data writing phase ST2, S(n) provides a low voltage signal, S(n-1) provides a high voltage signal, NS(n) provides a high voltage signal, E(n) provides a high voltage signal, Md8 is turned on, Md2 is turned on, Md4 is turned on, Dm provides the data voltage Vdata; Md7 is turned on, and I0 provides the initial voltage Vinit to write Vinit to the anode of O0, thereby controlling O0 to not emit light and clearing the residual charge on the anode of O0.

[0341] When the data writing phase ST2 begins, Md3 is turned on to charge C0 through the data voltage Vdata, thereby increasing the potential of the gate of Md3 until Md3 is turned off. At this time, the potential of the gate of Md3 is Vdata + Vth, where Vth is the threshold voltage of Md3.

[0342] During the light-emitting stage ST3, S(n) and S(n-1) both provide high voltage signals, NS(n) and E(n) both provide low voltage signals, Md5, Md3 and Md6 are all turned on, and Md6 drives O0 to emit light.

[0343] like Figure 24 As shown, the signal provided by NS(n) is the same as the signal provided by E(n), which can reduce the second conversion circuit. Only the first driving circuit and the first conversion circuit are needed to control the display, which is beneficial for achieving a narrow bezel.

[0344] exist Figure 23 In at least one embodiment of the pixel circuit in the nth row and mth column shown, the gate of Md5 can also be replaced by being electrically connected to the output terminal E(n+1) of the second drive signal of the (n+1)th stage.

[0345] Optionally, the pixel circuit in the nth row and mth column includes a data writing circuit in the nth row and mth column, a compensation control circuit in the nth row and mth column, a first reset circuit in the nth row and mth column, a second reset circuit in the nth row and mth column, a first light-emitting control circuit in the nth row and mth column, a second light-emitting control circuit in the nth row and mth column, a driving circuit in the nth row and mth column, a third energy storage circuit in the nth row and mth column, and a light-emitting element in the nth row and mth column; n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M;

[0346] The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth driving signal output terminal.

[0347] The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level third drive signal, the control terminal of the nth row and mth column drive circuit, and the second terminal of the nth row and mth column drive circuit, respectively, and is used to control the connection between the control terminal of the nth row and mth column drive circuit and the second terminal of the nth row and mth column drive circuit under the control of the nth level third drive signal provided by the output terminal of the nth level third drive signal;

[0348] The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th level third drive signal, the control terminal of the (n-1)th row and mth column drive circuit, and the first initial voltage terminal, respectively. It is used to write the first initial voltage provided by the first initial voltage terminal into the control terminal of the (n-1)th row and mth column drive circuit under the control of the (n-1)th level third drive signal provided by the (n-1)th level third drive signal output terminal.

[0349] The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the first driving signal of the nth stage.

[0350] The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the nth level second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the (n+1)th second driving signal;

[0351] The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal;

[0352] The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal;

[0353] The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy;

[0354] The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage level.

[0355] like Figure 25 As shown, the first reset circuit 191 in the nth row and mth column includes a first display control transistor Md1; the compensation control circuit 192 in the nth row and mth column includes a second display control transistor Md2; the driving circuit 193 in the nth row and mth column includes a driving transistor Md3; the data writing circuit 194 in the nth row and mth column includes a fourth display control transistor Md4; the first light-emitting control circuit 195 in the nth row and mth column includes a fifth display control transistor Md5; the second light-emitting control circuit 196 in the nth row and mth column includes a sixth display control transistor Md6; and the second reset circuit 197 in the nth row and mth column includes a seventh display control transistor Md7. The light-emitting element in the nth row and mth column is an organic light-emitting diode O0 in the nth row and mth column. The third energy storage circuit 198 in the nth row and mth column includes a storage capacitor C0.

[0356] The gate of Md1 is electrically connected to the output terminal NS(n-1) of the third drive signal of the (n-1)th stage, the source of Md1 is electrically connected to the initial voltage terminal I0, and the drain of Md1 is electrically connected to the gate of Md3.

[0357] The gate of Md2 is electrically connected to the output terminal NS(n) of the third drive signal of the nth stage, the source of Md2 is electrically connected to the gate of Md3, and the drain of Md2 is electrically connected to the drain of Md3.

[0358] The gate of Md4 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of Md4 is electrically connected to the data line Dm of the mth column, and the drain of Md4 is electrically connected to the source of Md3.

[0359] The gate of Md5 is electrically connected to the output terminal E(n) of the second drive signal of the nth stage, the source of Md5 is electrically connected to the high-level terminal Vdd, and the drain of Md5 is electrically connected to the source of Md3.

[0360] The gate of Md6 is electrically connected to the output terminal E(n) of the second drive signal of the nth stage, the source of Md6 is electrically connected to the drain of Md3, the drain of Md6 is electrically connected to the anode of O0, and the cathode of O0 is electrically connected to the low-level terminal Vss.

[0361] The gate of Md7 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of Md7 is electrically connected to the initial voltage terminal I0, and the drain of Md7 is electrically connected to the drain of Md6.

[0362] The first terminal of C0 is electrically connected to the high-level terminal Vdd, and the second terminal of C0 is electrically connected to the gate of Md3.

[0363] exist Figure 25In at least one embodiment of the pixel circuit in the nth row and mth column shown, Md1 and Md2 are both NMOS transistors, and Md3, Md4, Md5, Md6 and Md7 are all PMOS transistors, but not limited thereto.

[0364] exist Figure 25 In at least one embodiment of the pixel circuit in the nth row and mth column shown, the gate of Md5 can also be replaced by being electrically connected to the output terminal E(n+1) of the second drive signal of the (n+1)th stage.

[0365] like Figure 26 As shown, Figure 25 In at least one embodiment of the pixel circuit in the nth row and mth column shown, the display cycle includes an initialization phase ST1, a data writing phase ST2, and a light emission phase ST3 that are set sequentially during operation.

[0366] During the initialization phase ST1, S(n) provides a high voltage signal, NS(n-1) provides a high voltage signal, NS(n) provides a low voltage signal, E(n) provides a high voltage signal, Md1 is turned on, and I0 provides the initial voltage Vinit to write Vinit into the gate of Md3 so that Md3 can be turned on when the data writing phase ST2 begins.

[0367] During the data writing phase ST2, S(n) provides a low voltage signal, NS(n-1) provides a low voltage signal, NS(n) provides a high voltage signal, E(n) provides a high voltage signal, M2 and M4 are turned on, Dm provides the data voltage Vdata, and controls the connection between the gate and drain of Md3.

[0368] When the data writing phase ST2 begins, Md3 is turned on to charge C0 through Vdata, thereby increasing the potential of the gate of Md3 until Md3 is turned off. At this time, the potential of the gate of Md3 is Vdata + Vth, where Vth is the threshold voltage of Md3.

[0369] During the light-emitting stage ST3, S(n) provides a high voltage signal, NS(n-1) provides a low voltage signal, NS(n) provides a low voltage signal, E(n) provides a low voltage signal, Md5, Md3 and Md6 are turned on, and Md3 drives O0 to emit light.

[0370] The driving module described in at least one embodiment of this disclosure includes a first driving circuit, a first conversion circuit, and a second conversion circuit, which can generate a first driving signal, a second driving signal, and a third driving signal. It eliminates the need for a driving circuit to generate the second driving signal and a driving circuit to generate the third driving signal, and can reduce the number of transistors used, which is beneficial for achieving a narrow bezel.

[0371] Optionally, the pixel circuit in the nth row and mth column includes a data writing circuit in the nth row and mth column, a compensation control circuit in the nth row and mth column, a first reset circuit in the nth row and mth column, a second reset circuit in the nth row and mth column, a first light-emitting control circuit in the nth row and mth column, a second light-emitting control circuit in the nth row and mth column, a driving circuit in the nth row and mth column, a third energy storage circuit in the nth row and mth column, and a light-emitting element in the nth row and mth column; n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M;

[0372] The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth driving signal output terminal.

[0373] The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level third drive signal, the control terminal of the nth row and mth column drive circuit, and the second terminal of the nth row and mth column drive circuit, respectively, and is used to control the connection between the control terminal of the nth row and mth column drive circuit and the second terminal of the nth row and mth column drive circuit under the control of the nth level third drive signal provided by the output terminal of the nth level third drive signal;

[0374] The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th level third drive signal, the control terminal of the (n-1)th row and mth column drive circuit, and the first initial voltage terminal, respectively. It is used to write the first initial voltage provided by the first initial voltage terminal into the control terminal of the (n-1)th row and mth column drive circuit under the control of the (n-1)th level third drive signal provided by the (n-1)th level third drive signal output terminal.

[0375] The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the nth level second driving signal provided by the output terminal of the nth level second driving signal.

[0376] The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the (n+1)th level second driving signal or the (n+1)th second driving signal output terminal;

[0377] The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal;

[0378] The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal;

[0379] The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy;

[0380] The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage level.

[0381] like Figure 27 As shown, the first reset circuit 191 in the nth row and mth column includes a first display control transistor Md1; the compensation control circuit 192 in the nth row and mth column includes a second display control transistor Md2; the driving circuit 193 in the nth row and mth column includes a driving transistor Md3; the data writing circuit 194 in the nth row and mth column includes a fourth display control transistor Md4; the first light-emitting control circuit 195 in the nth row and mth column includes a fifth display control transistor Md5; the second light-emitting control circuit 196 in the nth row and mth column includes a sixth display control transistor Md6; and the second reset circuit 197 in the nth row and mth column includes a seventh display control transistor Md7. The light-emitting element in the nth row and mth column is an organic light-emitting diode O0 in the nth row and mth column. The third energy storage circuit 198 in the nth row and mth column includes a storage capacitor C0.

[0382] The gate of Md1 is electrically connected to the output terminal NS(n-1) of the third drive signal of the (n-1)th stage, the source of Md1 is electrically connected to the initial voltage terminal I0, and the drain of Md1 is electrically connected to the gate of Md3.

[0383] The gate of Md2 is electrically connected to the output terminal NS(n) of the third drive signal of the nth stage, the source of Md2 is electrically connected to the gate of Md3, and the drain of Md2 is electrically connected to the drain of Md3.

[0384] The gate of Md4 is electrically connected to the first drive signal output terminal S(n) of the nth stage, the source of Md4 is electrically connected to the data line Dm of the mth column, and the drain of Md4 is electrically connected to the source of Md3.

[0385] The gate of Md5 is electrically connected to the output terminal E(n) of the second drive signal of the nth stage, the source of Md5 is electrically connected to the high-level terminal Vdd, and the drain of Md5 is electrically connected to the source of Md3.

[0386] The gate of Md6 is electrically connected to the output terminal E(n) of the second drive signal of the nth stage, the source of Md6 is electrically connected to the drain of Md3, the drain of Md6 is electrically connected to the anode of O0, and the cathode of O0 is electrically connected to the low-level terminal Vss.

[0387] The gate of Md7 is electrically connected to the output terminal E(n) of the second drive signal of the nth stage, the source of Md7 is electrically connected to the initial voltage terminal I0, and the drain of Md7 is electrically connected to the drain of Md6.

[0388] The first terminal of C0 is electrically connected to the high-level terminal Vdd, and the second terminal of C0 is electrically connected to the gate of Md3.

[0389] exist Figure 27 In at least one embodiment of the pixel circuit in the nth row and mth column shown, Md1, Md2 and Md7 are all NMOS transistors, and Md3, Md4, Md5 and Md6 are all PMOS transistors, but not limited thereto.

[0390] exist Figure 27 In at least one embodiment of the pixel circuit in the nth row and mth column shown, the gate of Md5 can also be replaced by being electrically connected to the output terminal E(n+1) of the second drive signal of the (n+1)th stage.

[0391] The driving module described in at least one embodiment of this disclosure includes a first driving circuit, a first conversion circuit, and a second conversion circuit, which can generate a first driving signal, a second driving signal, and a third driving signal. It eliminates the need for a driving circuit to generate the second driving signal and a driving circuit to generate the third driving signal, and can reduce the number of transistors used, which is beneficial for achieving a narrow bezel.

[0392] like Figure 28 As shown, Figure 27 In at least one embodiment of the pixel circuit in the nth row and mth column shown, the display cycle includes an initialization phase ST1, a data writing phase ST2, and a light emission phase ST3 that are set sequentially during operation.

[0393] During the initialization phase ST1, S(n) provides a high voltage signal, NS(n-1) provides a high voltage signal, NS(n) provides a low voltage signal, E(n) provides a high voltage signal, Md1 is turned on, and I0 provides the initial voltage Vinit to write Vinit into the gate of Md3 so that Md3 can be turned on when the data writing phase ST2 begins.

[0394] During the data writing phase ST2, S(n) provides a low voltage signal, NS(n-1) provides a low voltage signal, NS(n) provides a high voltage signal, E(n) provides a high voltage signal, M2 and M4 are turned on, Dm provides the data voltage Vdata, and controls the connection between the gate and drain of Md3.

[0395] When the data writing phase ST2 begins, Md3 is turned on to charge C0 through Vdata, thereby increasing the potential of the gate of Md3 until Md3 is turned off. At this time, the potential of the gate of Md3 is Vdata + Vth, where Vth is the threshold voltage of Md3.

[0396] During the light-emitting stage ST3, S(n) provides a high voltage signal, NS(n-1) provides a low voltage signal, NS(n) provides a low voltage signal, E(n) provides a low voltage signal, Md5, Md3 and Md6 are turned on, and Md3 drives O0 to emit light.

[0397] The display device described in this disclosure includes the display panel described above.

[0398] The display device provided in this disclosure can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0399] The above description represents the preferred embodiments of this disclosure. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles described herein, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A drive module, characterized in that, It includes a first driving circuit and a first conversion circuit; n is a positive integer; the first driving circuit includes multiple levels of first driving sub-circuits; the first conversion circuit includes multiple first conversion sub-circuits; The nth-stage first driver sub-circuit is used to generate and output the nth-stage first driver signal through the nth-stage first driver signal output terminal; The (n-1)th stage first driver sub-circuit is used to generate and output the (n-1)th stage first driver signal through the (n-1)th stage first driver signal output terminal; The nth first conversion sub-circuit is electrically connected to the (n-1)th stage first drive signal output terminal, the nth stage first drive signal output terminal, the first voltage terminal, the second voltage terminal, and the nth stage second drive signal output terminal, respectively, and is used to control the nth stage second drive signal output terminal to output the nth stage second drive signal under the control of the (n-1)th stage first drive signal and the nth stage first drive signal, according to the first voltage signal provided by the first voltage terminal and the second voltage signal provided by the second voltage terminal; The drive module further includes a second conversion circuit; the second conversion circuit includes a plurality of second conversion sub-circuits; The (n-1)th second conversion sub-circuit is electrically connected to the (n-1)th stage first drive signal output terminal, the nth stage first drive signal output terminal, the nth stage second drive signal output terminal, the third voltage terminal, the fourth voltage terminal, and the (n-1)th stage third drive signal output terminal, respectively. It is used to control the (n-1)th stage third drive signal output terminal to output the (n-1)th stage third drive signal under the control of the (n-1)th stage first drive signal, the nth stage first drive signal, and the nth stage second drive signal, according to the third voltage signal provided by the third voltage terminal and the fourth voltage signal provided by the fourth voltage terminal.

2. The drive module as described in claim 1, characterized in that, The nth first conversion sub-circuit includes the nth first conversion module and the nth second conversion module; The nth first conversion module is electrically connected to the (n-1)th stage first drive signal output terminal, the nth stage first drive signal output terminal, the first voltage terminal, and the nth stage second drive signal output terminal, respectively. It is used to control the output of the first voltage signal provided by the first voltage terminal to the nth stage second drive signal output terminal under the control of the (n-1)th stage first drive signal, and to output the first voltage signal to the nth stage second drive signal output terminal under the control of the nth stage first drive signal. The nth second conversion module is electrically connected to the (n-1)th stage first drive signal output terminal, the nth stage first drive signal output terminal, the second voltage terminal, and the nth stage second drive signal output terminal, respectively, and is used to output the second voltage signal provided by the second voltage terminal to the nth stage second drive signal output terminal under the control of the (n-1)th stage first drive signal and the nth stage first drive signal.

3. The drive module as described in claim 1, characterized in that, The (n-1)th second conversion sub-circuit includes the (n-1)th third conversion module, the (n-1)th fourth conversion module, and the (n-1)th fifth conversion module; The (n-1)th third conversion module is electrically connected to the (n-1)th stage first drive signal output terminal, the third voltage terminal and the (n-1)th stage third drive signal output terminal, respectively, and is used to output the third voltage signal provided by the third voltage terminal to the (n-1)th stage third drive signal output terminal under the control of the (n-1)th stage first drive signal. The (n-1)th fourth conversion module is electrically connected to the nth stage first drive signal output terminal, the fourth voltage terminal and the (n-1)th stage third drive signal output terminal, respectively, and is used to output the fourth voltage signal provided by the fourth voltage terminal to the (n-1)th stage third drive signal output terminal under the control of the nth stage first drive signal. The (n-1)th fifth conversion module is electrically connected to the nth stage second drive signal output terminal, the fourth voltage terminal, and the (n-1)th stage third drive signal output terminal, respectively, and is used to output the fourth voltage signal provided by the fourth voltage terminal to the (n-1)th stage third drive signal output terminal under the control of the nth stage second drive signal.

4. The drive module as described in claim 2, characterized in that, The nth first conversion module includes a first transistor and a second transistor, and the nth second conversion module includes a third transistor and a fourth transistor; The control electrode of the first transistor is electrically connected to the output terminal of the first drive signal of the (n-1)th stage, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the output terminal of the second drive signal of the nth stage. The control electrode of the second transistor is electrically connected to the output terminal of the first drive signal of the nth stage, the first electrode of the second transistor is electrically connected to the first voltage terminal, and the second electrode of the second transistor is electrically connected to the output terminal of the second drive signal of the nth stage. The control electrode of the third transistor is electrically connected to the output terminal of the first drive signal of the (n-1)th stage, the first electrode of the third transistor is electrically connected to the second voltage terminal, and the second electrode of the third transistor is electrically connected to the output terminal of the second drive signal of the nth stage. The control electrode of the fourth transistor is electrically connected to the first drive signal output terminal of the nth stage, the first electrode of the fourth transistor is electrically connected to the second electrode of the third transistor, and the second electrode of the fourth transistor is electrically connected to the second drive signal output terminal of the nth stage.

5. The drive module as described in claim 4, characterized in that, The first transistor and the second transistor are both of the first type of transistor, and the third transistor and the fourth transistor are both of the second type of transistor.

6. The drive module as described in claim 3, characterized in that, The (n-1)th third conversion module includes a fifth transistor, the (n-1)th fourth conversion module includes a sixth transistor, and the (n-1)th fifth conversion module includes a seventh transistor; The control electrode of the fifth transistor is electrically connected to the output terminal of the first drive signal of the (n-1)th stage, the first electrode of the fifth transistor is electrically connected to the third voltage terminal, and the second electrode of the fifth transistor is electrically connected to the output terminal of the third drive signal of the (n-1)th stage. The control electrode of the sixth transistor is electrically connected to the first drive signal output terminal of the nth stage, the first electrode of the sixth transistor is electrically connected to the fourth voltage terminal, and the second electrode of the sixth transistor is electrically connected to the third drive signal output terminal of the (n-1)th stage. The control electrode of the seventh transistor is electrically connected to the output terminal of the second drive signal of the nth stage, the first electrode of the seventh transistor is electrically connected to the fourth voltage terminal, and the second electrode of the seventh transistor is electrically connected to the output terminal of the third drive signal of the (n-1)th stage.

7. The drive module as described in claim 6, characterized in that, The fifth transistor and the seventh transistor are of the first type of transistor, and the sixth transistor is of the second type of transistor.

8. The drive module according to any one of claims 1 to 7, characterized in that, The first driving sub-circuit of the nth stage includes a first node control circuit, a control node control circuit, a second node control circuit, a first energy storage circuit, a second energy storage circuit, and an output circuit, wherein, The first node control circuit is electrically connected to the control clock signal terminal, the sixth voltage terminal, the first node, and the control node, respectively. It is used to write the sixth voltage signal provided by the sixth voltage terminal into the first node under the control of the control clock signal provided by the control clock signal terminal, and to write the control clock signal provided by the control clock signal terminal into the first node under the control of the potential of the control node. The control node control circuit is electrically connected to the control clock signal terminal, the input terminal, the control node, the first node, the output clock signal terminal, and the fifth voltage terminal, respectively. It is used to write the input signal provided by the input terminal into the control node under the control of the control clock signal, and to write the fifth voltage signal provided by the fifth voltage terminal into the first node under the control of the potential of the first node and the output control signal provided by the output clock signal terminal. The second node control circuit is electrically connected to the sixth voltage terminal, the control node, and the second node, respectively, and is used to control the connection between the control node and the second node under the control of the sixth voltage signal provided by the sixth voltage terminal; The first terminal of the first energy storage circuit is electrically connected to the second node, and the second terminal of the first energy storage circuit is electrically connected to the output terminal of the first drive signal of the nth stage; the first energy storage circuit is used to store electrical energy. The first end of the second energy storage circuit is electrically connected to the first node, and the second end of the second energy storage circuit is electrically connected to the fifth voltage terminal. The second energy storage circuit is used to store electrical energy. The output circuit is electrically connected to the first node, the second node, the output clock signal terminal, the fifth voltage terminal, and the nth-stage first drive signal output terminal, respectively. It is used to output the fifth voltage signal provided by the fifth voltage terminal to the nth-stage first drive signal output terminal under the control of the potential of the first node, and to output the output clock signal to the nth-stage first drive signal output terminal under the control of the potential of the second node.

9. The drive module as described in claim 8, characterized in that, The first node control circuit includes a first control transistor and a second control transistor; The control electrode of the first control transistor is electrically connected to the control clock signal terminal, the first electrode of the first control transistor is electrically connected to the sixth voltage terminal, and the second electrode of the first control transistor is electrically connected to the first node. The control electrode of the second control transistor is electrically connected to the control node, the first electrode of the second control transistor is electrically connected to the control clock signal terminal, and the second electrode of the second control transistor is electrically connected to the first node. The control node control circuit includes a third control transistor, a fourth control transistor, and a fifth control transistor; The control electrode of the third control transistor is electrically connected to the control clock signal terminal, the first electrode of the third control transistor is electrically connected to the input terminal, and the second electrode of the third control transistor is electrically connected to the control node. The control electrode of the fourth control transistor is electrically connected to the first node, and the first electrode of the fourth control transistor is electrically connected to the fifth voltage terminal. The control electrode of the fifth control transistor is electrically connected to the output clock signal terminal, the first electrode of the fifth control transistor is electrically connected to the second electrode of the fourth control transistor, and the second electrode of the fifth control transistor is electrically connected to the control node. The second node control circuit includes a sixth control transistor; The control electrode of the sixth control transistor is electrically connected to the sixth voltage terminal, the first electrode of the sixth control transistor is electrically connected to the control node, and the second electrode of the sixth control transistor is electrically connected to the second node. The first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; The first terminal of the first capacitor is electrically connected to the second node, and the second terminal of the first capacitor is electrically connected to the output terminal of the first drive signal of the nth stage. The first terminal of the second capacitor is electrically connected to the first node, and the second terminal of the second capacitor is electrically connected to the fifth voltage terminal. The output circuit includes a first output transistor and a second output transistor; The control electrode of the first output transistor is electrically connected to the first node, the first electrode of the first output transistor is electrically connected to the fifth voltage terminal, and the second electrode of the first output transistor is electrically connected to the nth stage first drive signal output terminal. The control electrode of the second output transistor is electrically connected to the second node, the first electrode of the second output transistor is electrically connected to the output terminal of the first drive signal of the nth stage, and the second electrode of the second output transistor is electrically connected to the output clock signal terminal.

10. A display panel, comprising a driving module as described in any one of claims 1 to 9 disposed in a peripheral area and an N-row, M-column pixel circuit disposed in the display area; where N and M are positive integers; The driving module is used to provide driving signals for the pixel circuit.

11. The display panel as claimed in claim 10, characterized in that, The driving signal includes a first driving signal and a second driving signal; The first driving circuit included in the driving module is located on the side of the first conversion circuit included in the driving module that is away from the display area.

12. The display panel as claimed in claim 11, characterized in that, The driving signal further includes a third driving signal; the driving module further includes a second conversion circuit; The second conversion circuit is located on the side of the first conversion circuit that is close to the display area.

13. The display panel according to any one of claims 10 to 12, characterized in that, The pixel circuit in row n and column m includes a data writing circuit in row n and column m, a compensation control circuit in row n and column m, a first reset circuit in row n and column m, a second reset circuit in row n and column m, a first light emission control circuit in row n and column m, a second light emission control circuit in row n and column m, a driving circuit in row n and column m, a third energy storage circuit in row n and column m, and a light emission element in row n and column m. n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M; The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth level first driving signal output terminal. The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the control terminal of the driving circuit in the nth row and mth column, and the second terminal of the driving circuit in the nth row and mth column, respectively, and is used to control the connection between the control terminal of the driving circuit in the nth row and mth column and the second terminal of the driving circuit in the nth row and mth column under the control of the first driving signal of the nth stage; The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th stage first drive signal, the control terminal of the (n-1)th row and mth column drive circuit, and the first initial voltage terminal, respectively. It is used to write the first initial voltage provided by the first initial voltage terminal into the control terminal of the (n-1)th row and mth column drive circuit under the control of the (n-1)th stage first drive signal provided by the (n-1)th stage first drive signal output terminal. The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the first driving signal of the nth stage. The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the nth level second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the (n+1)th second driving signal; The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal; The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal; The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy; The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage level.

14. The display panel according to any one of claims 10 to 12, characterized in that, The pixel circuit in row n and column m includes a data writing circuit in row n and column m, an on / off control circuit in row n and column m, a compensation control circuit in row n and column m, a first reset circuit in row n and column m, a second reset circuit in row n and column m, a first light emission control circuit in row n and column m, a second light emission control circuit in row n and column m, a driving circuit in row n and column m, a third energy storage circuit in row n and column m, and a light emission element in row n and column m. n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M; The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth level first driving signal output terminal. The on / off control circuit of the nth row and mth column is electrically connected to the output terminal of the nth level third drive signal, the control terminal of the nth row and mth column drive circuit, and the connection node of the nth row and mth column, respectively, and is used to control the connection between the control terminal of the nth row and mth column drive circuit and the connection node of the nth row and mth column under the control of the nth level third drive signal provided by the output terminal of the nth level third drive signal; The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level first drive signal, the connection node in the nth row and mth column, and the second terminal of the drive circuit in the nth row and mth column, respectively, and is used to control the connection between the connection node in the nth row and mth column and the second terminal of the drive circuit in the nth row and mth column under the control of the nth level first drive signal; The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th level first drive signal, the connection node in the nth row and mth column, and the first initial voltage terminal, respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the connection node in the nth row and mth column under the control of the (n-1)th level first drive signal provided by the output terminal of the (n-1)th level first drive signal. The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the first driving signal of the nth stage. The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the nth level second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the (n+1)th second driving signal; The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal; The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal; The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy; The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage terminal; The nth stage third drive signal output terminal and the nth stage second drive signal output terminal are connected to the same drive signal.

15. The display panel according to any one of claims 10 to 12, characterized in that, The pixel circuit in row n and column m includes a data writing circuit in row n and column m, a compensation control circuit in row n and column m, a first reset circuit in row n and column m, a second reset circuit in row n and column m, a first light emission control circuit in row n and column m, a second light emission control circuit in row n and column m, a driving circuit in row n and column m, a third energy storage circuit in row n and column m, and a light emission element in row n and column m. n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M; The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth level first driving signal output terminal. The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level third drive signal, the control terminal of the nth row and mth column drive circuit, and the second terminal of the nth row and mth column drive circuit, respectively, and is used to control the connection between the control terminal of the nth row and mth column drive circuit and the second terminal of the nth row and mth column drive circuit under the control of the nth level third drive signal provided by the output terminal of the nth level third drive signal; The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th level third drive signal, the control terminal of the (n-1)th row and mth column drive circuit, and the first initial voltage terminal, respectively. It is used to write the first initial voltage provided by the first initial voltage terminal into the control terminal of the (n-1)th row and mth column drive circuit under the control of the (n-1)th level third drive signal provided by the (n-1)th level third drive signal output terminal. The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the first driving signal of the nth stage, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the first driving signal of the nth stage. The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the nth level second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the second driving signal provided by the (n+1)th second driving signal; The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal; The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal; The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy; The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage level.

16. The display panel according to any one of claims 10 to 12, characterized in that, The pixel circuit in row n and column m includes a data writing circuit in row n and column m, a compensation control circuit in row n and column m, a first reset circuit in row n and column m, a second reset circuit in row n and column m, a first light emission control circuit in row n and column m, a second light emission control circuit in row n and column m, a driving circuit in row n and column m, a third energy storage circuit in row n and column m, and a light emission element in row n and column m. n is a positive integer less than or equal to N, and m is a positive integer less than or equal to M; The nth row and mth column data writing circuit is electrically connected to the nth level first driving signal output terminal, the mth column data line and the first terminal of the nth row and mth column driving circuit, respectively, and is used to write the data voltage provided by the mth column data line into the first terminal of the nth row and mth column pixel circuit under the control of the nth level first driving signal provided by the nth level first driving signal output terminal. The compensation control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level third drive signal, the control terminal of the nth row and mth column drive circuit, and the second terminal of the nth row and mth column drive circuit, respectively, and is used to control the connection between the control terminal of the nth row and mth column drive circuit and the second terminal of the nth row and mth column drive circuit under the control of the nth level third drive signal provided by the output terminal of the nth level third drive signal; The first reset circuit in the nth row and mth column is electrically connected to the output terminal of the (n-1)th level third drive signal, the control terminal of the (n-1)th row and mth column drive circuit, and the first initial voltage terminal, respectively. It is used to write the first initial voltage provided by the first initial voltage terminal into the control terminal of the (n-1)th row and mth column drive circuit under the control of the (n-1)th level third drive signal provided by the (n-1)th level third drive signal output terminal. The second reset circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the first electrode of the light-emitting element in the nth row and mth column, and the second initial voltage terminal, respectively. It is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element in the nth row and mth column under the control of the nth level second driving signal provided by the output terminal of the nth level second driving signal. The control terminal of the first light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal or the (n+1)th second driving signal; the first light-emitting control circuit in the nth row and mth column is also electrically connected to the first level terminal and the first terminal of the driving circuit in the nth row and mth column, respectively, for controlling the first level terminal to connect with the first terminal of the driving circuit in the nth row and mth column under the control of the (n+1)th level second driving signal or the (n+1)th second driving signal output terminal; The second light-emitting control circuit in the nth row and mth column is electrically connected to the output terminal of the nth level second driving signal, the second terminal of the nth row and mth column driving circuit, and the first electrode of the nth row and mth column light-emitting element, respectively, and is used to control the connection between the second terminal of the nth row and mth column driving circuit and the first electrode of the nth row and mth column light-emitting element under the control of the nth level second driving signal; The driving circuit in the nth row and mth column is used to generate a driving current under the control of the potential at its control terminal; The third energy storage circuit in the nth row and mth column is electrically connected to the control terminal and the first level terminal of the driving circuit in the nth row and mth column, respectively, for storing electrical energy; The second electrode of the light-emitting element in the nth row and mth column is electrically connected to the second voltage level.

17. A display device, characterized in that, Includes the display panel as described in any one of claims 10 to 16.

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