A method for isolating a fluctuation source of a tunneling field effect transistor

Abstract

The application discloses a method for separating fluctuation sources of a tunneling field effect transistor, and belongs to the technical field of semiconductors. The application separates the influence of two fluctuation sources which have the greatest influence on the tunneling probability of the tunneling junction of the drain, i.e. the impurity doping concentration gradient (DG) fluctuation and the length (L und ) fluctuation of the underlap region of the drain, and further extracts the impurity doping concentration gradient (DG) fluctuation and the length (L und ) fluctuation of the underlap region of the drain. All work can be completed by means of a semiconductor analyzer and MATLAB, and has the advantages of rapidness and low cost.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a method for separating fluctuation sources in tunneling field-effect transistors. Background Technology

[0002] The development of AIoT (Artificial Intelligence of Things) technology has placed higher demands on semiconductor power consumption, and tunneling field-effect transistors (TFETs) are considered one of the most promising low-power devices. Both the source and drain terminals of a TFET contain tunneling junctions. The tunneling junction at the source provides the on-state current for device conduction, while the tunneling junction at the drain increases the off-state current. The fluctuations in tunneling current caused by the drain tunneling junction directly affect the fluctuations in the off-state current of the TFET, thus influencing its ability to effectively reduce circuit power consumption.

[0003] Generally, a method of fabricating an undercovered drain region is used to increase the tunneling width of the drain tunnel junction and reduce the tunneling current of the drain tunnel junction in a tunneling field-effect transistor (TFTE). The undercovered drain region refers to the electrical length from the gate edge near the drain to the drain tunnel junction in a TFTE. For fabricating the undercovered drain region, the drain doping concentration gradient and the length of the undercovered drain region are two main factors affecting the tunneling probability of the drain tunnel junction. It is necessary to separate the effects of their fluctuations on the drain tunneling current fluctuations for further reduction of TFTE fluctuations and to comprehensively evaluate the TFTE's ability to reduce circuit power consumption.

[0004] Therefore, a method is needed to separate the fluctuation sources of tunneling field-effect transistors (DLund-TFETs). Specifically, for DLund-TFETs with undercovered drain regions, this method aims to separate the effects of the two fluctuation sources that have the greatest impact on the tunneling probability of the drain tunnel junction: the impurity doping concentration gradient (DG) fluctuation and the length of the undercovered drain region (L). und Fluctuations – separation. Summary of the Invention

[0005] The purpose of this invention is to propose a method for separating fluctuation sources in tunneling field-effect transistors (DLund-TFETs). This method addresses the impact of two fluctuation sources that have the greatest influence on the tunneling probability of the drain tunnel junction: the doping concentration gradient (DG) fluctuation and the length of the drain undercover region (L). und Fluctuations – separation.

[0006] A method for isolating fluctuation sources in a tunneling field-effect transistor (DLund-TFET) with an undercovered drain region, characterized in that:

[0007] Step 1: Test the transfer characteristic curves of N N-type and P-type DLund-TFET devices with the same size, structure and materials;

[0008] Step 2: Obtain the fluctuation source separation coefficient k of the N-type (or P-type) DLund-TFET device based on the transfer characteristic curve from Step 1. Specifically, this includes extracting the average drain undercover region length L of the N-type (or P-type) DLund-TFET device. und Extract the average source tunneling junction minimum tunneling width λ of a P-type (or N-type) DLund-TFET device. ON Extract the band-to-band tunneling generation rate coefficient B of P-type (or N-type) DLund-TFET devices. kane According to the formula Calculate the fluctuation source separation coefficient k of an N-type (or P-type) DLund-TFET device; where E G It refers to the band gap width of the channel material, and q refers to the amount of electron charge.

[0009] Step 3: Calculate the impurity doping concentration gradient DG fluctuations and the length L of the drain undercover region. und Fluctuations in the current I of the DLund-TFET device DS The impact of fluctuations, specifically, is as follows:

[0010] 3-1) Obtain the gate voltage V of the P-type (or N-type) DLund-TFET device through experimental test data. G = (-1*VDD)(or V G The current I when =VDD) DS average value ON > and standard deviation σI ON ;

[0011] 3-2) Obtain the gate voltage of the N-type (or P-type) DLund-TFET device at V through experimental test data. G = (-1*VDD)(or V G The current I when =VDD) DS average value AMI > and standard deviation σI AMI ;

[0012] 3-3) Impurity doping concentration gradient DG fluctuations affect N-type (or P-type) DLund-TFET devices at a gate voltage of V G = (-1*VDD)(or V G The current I when =VDD) DS The impact of fluctuations Calculated using the following formula

[0013] ​​3-4) Length L of the undercovered area at the leak end und Fluctuations affect N-type (or P-type) DLUnd-TFET devices at a gate voltage of V. G = (-1*VDD)(or V G The current I when =VDD) DS The impact of fluctuations Calculated using the following formula

[0014] Step 4: Extract the impurity doping concentration gradient (DG) fluctuations and the drain undercover length (L) in the DLund-TFET device. und Fluctuations specifically include: the average source-tunneling junction minimum tunneling width λ of a P-type (or N-type) DLUnd-TFET device. ON The scaling factor Q relative to the source-end impurity doping concentration gradient (DG) is, according to the formula, Obtain the drain undercoverage length fluctuation σL of an N-type (or P-type) DLund-TFET device. und ; and according to the formula Obtain the drain impurity doping concentration gradient fluctuation σDDG of an N-type (or P-type) DLund-TFET device.

[0015] Furthermore, in step 1, the source-drain voltage V of the DLund-TFET device DS The gate voltage (V) is set according to the requirements of device and circuit analysis. G The scan range is from (-1*VDD) to VDD. VDD is the power supply voltage corresponding to the circuit composed of DLund-TFET devices. When V G When VDD is present, the DLund-TFET device exhibits strong inversion at the channel surface. G When N is (-1*VDD), there is strong accumulation at the channel surface of the DLund-TFET device. The value of N can be a positive integer greater than or equal to 1.

[0016] Furthermore, in step 2, the methods for extracting and calculating each parameter are as follows:

[0017] The average drain undercoverage length L of N-type (or P-type) DLund-TFET devices und The gate capacitance can be extracted by testing the gate capacitance of multiple DLund-TFET devices with different gate lengths.

[0018] The average source tunnel junction minimum tunneling width λ of P-type (or N-type) DLund-TFET devices ON and the tunneling generation rate coefficient B kane The average current I obtained from the experiment can be used to... DS Obtained by verification with the formula. The formula is:

[0019]

[0020] Among them, W G E represents the gate width of the device. G For the band gap of the channel material, T Sieff To adjust the parameters, A kane and B kane This is the tunneling generation rate coefficient. For N-type devices, W... t,min Gate voltage (V) G The minimum tunnel width λ when VDD is used ON If it is a P-type device, W t,min Gate voltage (V) G The minimum tunnel width λ when is (-1*VDD) ON .

[0021] Furthermore, in step 4, the minimum tunneling width λ of the average source-tunneling junction of the P-type (or N-type) DLund-TFET device is extracted. ON The scaling factor Q relative to the source-end impurity doping concentration gradient (DG) can be obtained through Sentaurus Sprocess simulation.

[0022] The beneficial effects of this invention are as follows:

[0023] The method proposed in this invention can address the effects of two fluctuation sources that have the greatest impact on the tunneling probability of the drain tunneling junction in tunneling field-effect transistors (DLund-TFETs) with undercovered drain regions: impurity doping concentration gradient (DG) fluctuations and drain undercover length (L). und Fluctuations – Separate and further extract impurity doping concentration gradient (DG) fluctuations and drain undercover length (L) region. und Fluctuations. All work can be done using only a semiconductor analyzer and MATLAB, offering advantages such as speed and low cost. Attached Figure Description

[0024] Figure 1 This is a flowchart of the method for separating the drain tunneling current fluctuation source of the DLund-TFET device proposed in this invention;

[0025] Figure 2 shows intermediate results of separating the drain tunneling current fluctuation source of a certain DLund-TFET device using the method proposed according to the present invention.

[0026] (1) The transfer characteristic curve of the N-type DLund-TFET device;

[0027] (2) The transfer characteristic curve of the P-type DLund-TFET device;

[0028] Figure 3 Figure 2 shows a schematic diagram of the structure and geometric parameters of a certain DLund-TFET device studied.

[0029] In the picture:

[0030] 1—High-resistivity silicon substrate; 2—Shallow trench isolation;

[0031] 3—Gate dielectric layer; 4—Gate conductive layer;

[0032] 5—Source end sidewall; 6—Drain end sidewall;

[0033] 7—Source end impurity doping region; 8—Drain end impurity doping region;

[0034] 9 – Source metal layer; 10 – Drain metal layer. Detailed Implementation

[0035] An exemplary embodiment of the present invention will now be further described with reference to the accompanying drawings. It should be noted that the purpose of disclosing the embodiments is to aid in further understanding the present invention; however, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

[0036] Figure 1 A flowchart illustrating the proposed method for separating the drain tunneling current fluctuation sources in DLund-TFET devices is presented. Based on... Figure 1 The steps in Figure 3 The diagram shows the separation of drain tunneling current fluctuation sources in a certain type of DLund-TFET device. This device is an N-type TFET device.

[0037] First, the transfer characteristic curve of the N-type device was tested using a semiconductor parameter analyzer, specifically the gate voltage (V). G The scan range is -2.5V to 2.5V, and the source voltage V... S 0V, leakage voltage V D The voltage is 2.5V. The transfer characteristic curve of the P-type device is then tested using a semiconductor parameter analyzer, and the gate voltage (V) is... G The scan range is 0V to -2.5V, and the source voltage is V. S 0V, leakage voltage V D The voltage was -2.5V. Fifty-five N-type devices and 55 P-type devices were tested respectively, and the transfer characteristic curves are shown in Figure 2(1) and Figure 2(2).

[0038] Next, the gate-source capacitance and gate-drain capacitance of five N-type devices with different gate lengths were tested, with five devices of each type tested. The average drain undercoverage length L of the N-type devices was then extracted. und It is 19nm;

[0039] Next, based on the transfer characteristic curves obtained from the above tests, the V-type DLund-TFET device is calculated. G =V D =The average current at -2.5V, and compared with the formula

[0040] Proofreading, including W G E represents the gate width of the device. G For the band gap of the channel material, T Sieff To adjust the parameters, A kane and B kane This is the tunneling generation rate coefficient. W for P-type devices t,min Gate voltage (V) G The minimum tunnel width λ when is (-1*VDD) ON The minimum tunneling width λ of the average source tunnel junction is obtained based on this formula. ON =2.8nm, band tunneling generation rate coefficient B kane It is 0.6nm;

[0041] Next, according to the formula The calculated fluctuation source separation coefficient k = 0.6;

[0042] Next, the experimental test data were used to obtain the P-type device at a gate voltage of V. G Current I at -2.5V DS average value ON >=3.1x10 -4 A / μm and standard deviation σI ON =1.7x10 -5 A / μm;

[0043] Next, the experimental test data were used to obtain the N-type device at a gate voltage of V. G Current I at -2.5V DS average value AMI >=5.8x10 -9 A / μm and standard deviation σI AMI =5.1x10 -9 A / μm;

[0044] Next, according to the formula Calculate the effect of impurity doping concentration gradient (DG) fluctuations on N-type devices at gate voltage V. G Current I at -2.5V DS The impact of fluctuations​​

[0045] Next, according to the formula Calculate the length of the undercovered area at the leak end (L) und Fluctuations affect N-type devices at gate voltage V G Current I at -2.5V DS The impact of fluctuations

[0046] Next, based on the actual process conditions, a device geometry and physical model was constructed in Sentaurus Sprocess for simulation to obtain the minimum tunneling width λ of the average source-tunneling junction of the P-type device. ON The ratio Q relative to the source-end impurity doping concentration gradient (DG) is 0.2dec;

[0047] Next, according to the formula Calculate the drain undercoverage length fluctuation σL of an N-type device. und It is 4.7nm;

[0048] Next, according to the formula Calculate the drain impurity doping concentration gradient fluctuation σDDG = 0.28 nm / dec for the N-type device.

[0049] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method for separating fluctuation sources in a tunneling field-effect transistor with an undercovered drain region, characterized in that, Includes the following steps: Step 1: Test the transfer characteristic curves of N N-type and P-type DLund-TFET devices with the same size, structure and materials; Step 2: Obtain the fluctuation source separation coefficient k of the N-type or P-type DLund-TFET device based on the transfer characteristic curve in Step 1. Specifically, this includes extracting the average drain undercover region length L of the N-type or P-type DLund-TFET device. und Extract the average source tunneling junction minimum tunneling width λ of the P-type or N-type DLund-TFET device. ON Extract the band-to-band tunneling generation rate coefficient B of P-type or N-type DLund-TFET devices. kane According to the formula Calculate the fluctuation source separation coefficient k of an N-type or P-type DLund-TFET device, where E G This refers to the band gap width of the channel material, and q refers to the electron charge. Among them, the average source tunnel junction minimum tunneling width λ of P-type or N-type DLund-TFET devices ON and the tunneling generation rate coefficient B kane The average current I obtained through experimental testing DS The formula was obtained after verification. Among them, W G E represents the gate width of the device. G For the band gap of the channel material, T Sieff To adjust the parameters, A kane and B kane W is the tunneling generation rate coefficient. For N-type devices, W... t,min Gate voltage V G Minimum tunnel width λ when VDD ON If it is a P-type device, W t,min Gate voltage V G Minimum tunnel width λ when it is -1*VDD ON ; Step 3: Calculate the impurity doping concentration gradient DG fluctuations and the length L of the drain undercover region. und Fluctuations in the current I of the DLund-TFET device DS The effects of fluctuations, specifically, are explained as follows: 3-1) Obtain the gate voltage of a P-type or N-type DLund-TFET device at V through experimental test data. G =-1*VDD or V G Current I at =VDD DS average value ON > and standard deviation ;​ 3-2) Obtain the gate voltage of an N-type or P-type DLund-TFET device at V through experimental test data. G =-1*VDD or V G Current I at =VDD DS average value AMI > and standard deviation ;​ 3-3) Impurity doping concentration gradient (DG) fluctuations affect N-type or P-type DLund-TFET devices at a gate voltage of V G =-1*VDD or V G Current I at =VDD DS The impact of fluctuations The following formula is used to calculate the result. ; 3-4) Length L of the undercovered area at the leak end und Fluctuations affect N-type or P-type DLund-TFET devices at a gate voltage of V G =-1*VDD or V G Current I at =VDD DS The impact of fluctuations The following formula is used to calculate the result. ; Step 4: Utilize the minimum tunneling width λ of the average source tunneling junction of a P-type or N-type DLund-TFET device. ON The scaling factor Q relative to the source-end impurity doping concentration gradient (DG) is calculated according to the formula... Obtain the drain undercoverage length fluctuation of N-type or P-type DLund-TFET devices ; and according to the formula Obtain the drain impurity doping concentration gradient fluctuation of N-type or P-type DLund-TFET devices .

2. The method for separating fluctuation sources of a tunneling field-effect transistor with an undercovered drain region as described in claim 1, characterized in that, In step 1, the source-drain voltage V of the DLund-TFET device DS The gate voltage V is set according to the requirements of device and circuit analysis. G The scan range is from -1*VDD to VDD, where VDD is the power supply voltage corresponding to the circuit composed of DLund-TFET devices. G When VDD is present, the DLund-TFET device exhibits strong inversion at the channel surface. G When the value is -1*VDD, strong accumulation occurs on the channel surface of the DLund-TFET device.

3. The method for separating fluctuation sources of a tunneling field-effect transistor with an undercovered drain region as described in claim 1, characterized in that, In step 2, the average drain undercoverage length L of the N-type or P-type DLund-TFET device und The gate capacitance was extracted by testing the gate capacitance of DLund-TFET devices with different gate lengths.

4. The method for separating fluctuation sources of a tunneling field-effect transistor with an undercovered drain region as described in claim 1, characterized in that, In step 4, the minimum tunneling width λ of the average source-tunneling junction of the P-type or N-type DLund-TFET device is extracted. ON The scaling factor Q relative to the source-end impurity doping concentration gradient (DG), The results were obtained through Sentaurus Sprocess simulation.

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