Method for testing a sip chip for speech signal processing

Abstract

The application discloses a test method of SiP chip for voice signal processing. The method of the application firstly burns a test program containing two sub-programs in an upper computer chip; the upper computer chip communicates with a tested chip for the first time, confirms the type of the tested chip, and sends the first sub-program to the tested chip; the tested chip executes the first sub-program after successful verification, including calibrating an OSC, testing a PLL, a Flash, an SRAM and a PMU; then the second communication is carried out, the second sub-program is sent to the tested chip, the tested chip executes the second sub-program after successful verification, including testing an audio path and an audio signal processor of the tested chip; and finally, a test result is output. The method of the application avoids developing an additional communication protocol and a test tool based on a PC end, improves the test efficiency and test coverage, and guarantees the stability of the test process.

Description

Technical Field

[0001] This invention belongs to the field of chip technology, especially the field of chip testing technology, and is a testing method for SiP chips used for voice signal processing. Background Technology

[0002] Packaging: The process of assembling bare dies cut from a wafer into a final chip product. Simply put, it involves placing the bare integrated circuit dies produced by the manufacturer onto a substrate that serves as a support, bringing out the pins, and then fixing and packaging them into a whole.

[0003] System-in-Package (SiP): A packaging solution that integrates multiple functional wafers, including processor and memory wafers, into a single package based on factors such as application scenario and number of packaging substrate layers, thereby achieving a basic and complete functional package.

[0004] Printed circuit board (PCB): It is the support structure for electronic components, which contains metal conductors as lines to connect electronic components.

[0005] Universal Asynchronous Receiver / Transmitter (UART): A hardware interface that transmits data via serial communication.

[0006] Cyclic redundancy check (CRC): A hash function that generates a short, fixed-length checksum based on data such as network data packets or computer files. It is mainly used to detect or verify errors that may occur after data transmission or storage.

[0007] According to Moore's Law, the feature size of transistors on silicon-based semiconductors is halved every 18 months, while performance doubles. This performance improvement, coupled with cost reduction, provides semiconductor manufacturers with a strong incentive to further shrink semiconductor feature sizes. Processor chips and memory chips are the two types of chips that most closely adhere to Moore's Law.

[0008] However, PCB boards do not follow Moore's Law, making them a bottleneck for overall system performance improvement. While chip sizes have continuously shrunk, PCB board design has remained largely unchanged over the years. This limitation of the PCB board restricts overall system performance. For example, with relatively stable processor and memory package sizes, the number of interconnects between the processor and memory does not change significantly. Memory bandwidth equals the memory interface width multiplied by the memory interface operating frequency. The memory output width equals the number of interconnects between the processor and memory. Therefore, increasing memory bandwidth requires increasing the memory interface operating frequency. This limits overall system performance improvement.

[0009] System-on-Package (SiP) is the key to overcoming system bottlenecks. By packaging multiple semiconductor chips and passive components within a single chip to form a system-on-a-chip (SoC), it eliminates the need for a PCB (Printed Circuit Board) to support chip connections, thus resolving system performance bottlenecks caused by the inherent limitations of PCBs. For example, the internal trace density of a SiP can be significantly higher than that of a PCB, overcoming the bottleneck imposed by PCB trace width. Furthermore, memory and processor chips can be connected via vias, no longer limited by PCB trace width, thereby increasing data bandwidth through interface bandwidth. SiP also offers advantages such as shorter development cycles, more functionality, lower power consumption, superior performance, and smaller size.

[0010] Due to the packaging characteristics of SiP (System-in-Package) memory, executing preset test programs during the instrumentation testing phase becomes difficult. Testing traditional chips with external memory often requires reading test programs from external memory and transferring them into memory for execution. SiP memory chips are typically embedded in complex embedded systems, therefore compatibility with other devices must be considered during testing. Furthermore, existing testing methods often struggle to comprehensively cover all the functions of SiP memory chips and may fail to effectively detect some hidden defects, potentially leading to serious stability and performance issues in embedded systems. With the widespread application of SiP memory chips in various embedded devices, addressing these issues becomes crucial. Summary of the Invention

[0011] The purpose of this invention is to provide a testing method for SiP chips used in voice signal processing.

[0012] The method of this invention is specifically as follows:

[0013] Step (1) The test program is burned into the host computer chip, and the host computer chip enters the waiting handshake mode; the host computer executes the test master control of the chip under test; the test program contains two subroutines;

[0014] Step (2) The chip under test is installed in the chip fixture. After power-on, the host computer chip performs the first communication handshake with the chip under test through its own universal asynchronous transceiver UART. The chip under test is a SiP chip for voice signal processing.

[0015] After the handshake is successful in step (3), the host computer chip and the chip under test agree on the baud rate for the first communication; the baud rate for the first communication is the maximum baud rate that the host computer chip and the chip under test can accept in the current state.

[0016] Step (4) The host computer chip and the chip under test communicate for the first time at the agreed baud rate. The host computer chip confirms the model of the chip under test and informs the chip under test that the test program will be transmitted.

[0017] Step (5) The host computer chip transmits the first subroutine in the test program to the memory of the chip under test; after receiving the first subroutine, the chip under test performs verification. If the verification is successful, the host computer chip waits to transmit the second subroutine, and the chip under test executes step (6); if the verification fails, the host computer chip is notified and asked to retransmit; if the verification still fails after retransmitting twice, the chip under test is considered to be malfunctioning and directly proceeds to step (12).

[0018] Step (6) The chip under test executes the first subroutine, which specifically includes:

[0019] (6-1) Calibrate the built-in crystal oscillator (OSC) of the chip under test: Adjust the calibration coefficient of the built-in crystal oscillator (OSC) of the chip under test to successively approximate the clock frequency provided by the host computer chip until it is consistent with the clock frequency provided by the host computer chip. Write the final calibration coefficient into the one-time programmable memory (OTP) of the chip under test and display the OSC calibration success flag; if it is not consistent with the clock frequency provided by the host computer chip, display the OSC calibration failure flag.

[0020] (6-2) Based on the preset multiple output clock frequencies of the PLL of the chip under test, set a set of coefficients corresponding to each output clock frequency; query the status register of the PLL of the chip under test after setting each set of coefficients, check the locking status corresponding to each set of coefficients, if the locking status corresponding to all sets of coefficients is locked, display the PLL locking success flag, otherwise display the PLL locking failure flag.

[0021] (6-3) Write the fixed data set in the first subroutine into the Flash of the chip under test, then read the data in the Flash and compare it with the fixed data set in the first subroutine. If they match, erase all the data in the Flash and verify whether the erasure is successful. If successful, display the Flash read / write / erase success flag; if they do not match, or the erasure verification fails, display the Flash read / write / erase failure flag.

[0022] (6-4) The chip under test requests available memory space from its own SRAM through the first subroutine, writes the fixed data set in the first subroutine into the available memory space, then reads the data in the memory space and compares it with the fixed data set in the first subroutine. If they match, the SRAM read / write success flag is displayed; otherwise, the SRAM read / write failure flag is displayed.

[0023] (6-5) The chip under test controls the internal power management module (PMU) through the first subroutine to put the chip under test into standby mode and wait for a set time before exiting standby mode. If the entry and exit from standby mode are executed correctly, the PMU correct flag is displayed; otherwise, the PMU error flag is displayed.

[0024] Step (7) The host computer chip performs a second handshake with the chip under test through its own Universal Asynchronous Receiver / Transmitter (UART);

[0025] After the handshake is successful in step (8), the host computer chip and the chip under test agree on the baud rate for the second communication, which is the maximum baud rate that the host computer chip and the chip under test can accept in the current state.

[0026] Step (9) The host computer chip transfers the second subroutine in the test program to the memory of the chip under test and replaces the first subroutine.

[0027] Step (10) After receiving the second subroutine, the chip under test performs verification. If the verification is successful, the host computer chip waits to test the next chip under test and returns to step (2). The chip under test executes step (11). If the verification fails, the host computer chip is notified to retransmit. If the verification still fails after retransmitting twice, the chip under test is considered to be malfunctioning and directly enters step (12).

[0028] Step (11) The chip under test executes the second subroutine, which specifically includes:

[0029] (11-1) Connect the output pin of the digital-to-analog converter (DAC) of the chip under test to the input pin of the analog-to-digital converter (ADC);

[0030] (11-2) The chip under test outputs a sine wave signal with a set sampling rate and signal frequency through the DAC output pin via the second subroutine. The ADC of the chip under test samples the sine wave signal, downsamples it to the set sampling rate through a digital filter, and stores the downsampled sine wave signal in memory. The signal-to-noise ratio, total harmonic distortion ratio, and signal characteristics of the downsampled sine wave signal are calculated and compared with preset signal-to-noise ratio thresholds, total harmonic distortion ratio thresholds, and signal characteristic thresholds. If all are greater than or equal to the thresholds, an audio path correct flag is displayed; otherwise, an audio path error flag is displayed.

[0031] (11-3) The chip under test outputs a specific voice signal through the DAC output pin via the second subroutine. The ADC of the chip under test samples the specific voice signal, downsamples it to the set sampling rate through a digital filter, and stores the downsampled specific voice signal in memory. The ADSP is used to extract acoustic features and detect wake words on the specific voice signal. If the extracted acoustic features match the preset features and the wake word is detected correctly, the ADSP displays a correct ADSP flag; otherwise, the ADSP displays an incorrect ADSP flag.

[0032] Step (12) outputs the test results, including whether the tested chip is functioning normally or abnormally, and all flags.

[0033] This invention introduces a host computer chip with a universal asynchronous transceiver (UART) as the test controller for the chip under test. By utilizing the serial port of the host computer chip, the test program is transmitted in segments to the memory of the test chip during testing, achieving the effect of controlling the test chip. This invention breaks away from the traditional method of using a computer as the host computer, avoiding the development of additional communication protocols and test tools based on the PC, and enabling parallel testing of multiple chips. Simultaneously, the segmented transmission of the test program by the host computer chip overcomes the memory space limitations of the test chip and circumvents the problem of the test chip's inability to use external Flash memory, improving testing efficiency and coverage, ensuring the stability of the testing process, and enhancing the compatibility of the test chip. This invention provides a novel solution for the reliability testing of SiP chips. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the method flow of the present invention. Detailed Implementation

[0035] The following uses the test of the applicant's (Hangzhou Guoxin Technology Co., Ltd.) voice signal processing chip GX8002B as an example to further illustrate the method of the present invention.

[0036] The testing method has the following hardware resources:

[0037] The host computer chip with a universal asynchronous transceiver is GX8008C.

[0038] The voice signal processing chip under test: GX8002B;

[0039] The chip under test has the following internal hardware resources;

[0040] Crystal Oscillator OSC, 24MHz: Provides a clock frequency of 24MHz;

[0041] One-time programmable memory (OTP);

[0042] Static Random Access Memory (SRAM);

[0043] Flash memory integrated inside the chip;

[0044] Audio signal processor (ADSP);

[0045] A phase-locked loop (PLL) is used to integrate the clock signal and output a stable clock frequency;

[0046] Power Management Module (PMU);

[0047] Universal Asynchronous Transmitter (UART).

[0048] like Figure 1 As shown, the specific process for testing SiP chips used for voice signal processing is as follows:

[0049] Step (1) The test program is burned into the host computer chip GX8008C. GX8008C enters the handshake waiting mode. GX8008C executes the test master control of the chip under test GX8002B. The test program includes two subroutines.

[0050] Step (2) Install the chip under test GX8002B in the chip fixture. After power-on, GX8008C performs the first communication handshake with the chip under test GX8002B through its own universal asynchronous transceiver.

[0051] After the handshake is successful in step (3), the host computer chip GX8008C and the tested chip GX8002B agree on a baud rate of 576000 for the first communication.

[0052] Step (4) The host computer chip GX8008C and the chip under test GX8002B communicate for the first time at the agreed baud rate of 576000. After the host computer chip GX8008C confirms that the chip under test is GX8002B, it informs the chip under test GX8002B that it will transmit the test program.

[0053] Step (5): The host computer chip GX8008C transmits the first subroutine in the test program to the memory address 0x10000000 of the chip under test GX8002B. After receiving the first subroutine, the chip under test GX8002B performs CRC verification. If the CRC verification is successful, the host computer chip GX8008C waits to transmit the second subroutine, and the chip under test executes step (6). If the CRC verification fails, the host computer chip GX8008C is notified to retransmit. If the CRC verification still fails after two retransmissions, the chip under test GX8002B is considered to be malfunctioning and directly proceeds to step (12).

[0054] Step (6) The tested chip GX8002B executes the first subroutine, which specifically includes:

[0055] (6-1) Calibrate the built-in crystal oscillator (OSC) of the tested chip GX8002B: Adjust the calibration coefficient of the crystal oscillator (OSC) to successively approximate the clock frequency provided by the host computer chip GX8008C until it is consistent with the clock frequency provided by the host computer chip GX8008C. Write the final calibration coefficient into the one-time programmable memory (OTP) of GX8002B and output the OSC calibration success flag through the UART of GX8002B; if it is not possible to achieve consistency with the clock frequency provided by the host computer chip GX8008C, output the OSC calibration failure flag.

[0056] (6-2) Based on the output clock frequencies of the GX8002B PLL under test chip: 25MHz, 36MHz, 50MHz, set a set of coefficients corresponding to each output clock frequency; query the status register of the GX8002B PLL under test chip after setting each set of coefficients, check the locking status corresponding to each set of coefficients, if the locking status corresponding to all sets of coefficients is locked, output a PLL locking success flag through the UART of GX8002B, otherwise output a PLL locking failure flag.

[0057] (6-3) Write the fixed data 0x12345678 into all addresses of the Flash memory of the GX8002B chip under test. Then read all the data in the Flash memory and compare it with the set fixed data 0x12345678. If they match, erase all the data in the Flash memory and verify whether the erasure is successful. If successful, output the Flash read / write / erase success flag through the UART of GX8002B. If they do not match, or the erasure verification fails, output the Flash read / write / erase failure flag.

[0058] (6-4) The tested chip GX8002B requests available memory space from its own SRAM, writes the set fixed data 0x55 into the available memory space, then reads the data in the memory space and compares it with the set fixed data 0x55. If they match, the SRAM read / write success flag is output through the UART of GX8002B; otherwise, the SRAM read / write failure flag is output.

[0059] (6-5) The tested chip GX8002B controls the internal power management module PMU to put the tested chip GX8002B into standby mode and waits for 100 milliseconds before exiting standby mode; if the entry and exit from standby mode are executed correctly, the PMU correct flag is output through the GX8002B serial port; otherwise, the PMU error flag is output.

[0060] Step (7) The host computer chip GX8008C performs a second handshake with the tested chip GX8002B through its own Universal Asynchronous Receiver / Transmitter (UART).

[0061] After the handshake is successful in step (8), the host computer chip GX8008C and the tested chip GX8002B agree on a baud rate of 1500000 for the second communication.

[0062] Step (9) The host computer chip GX8008C transmits the second subroutine in the test program to the memory address 0x10000000 of the chip under test GX8002B at a baud rate of 1500000, replacing the first subroutine.

[0063] Step (10): After receiving the second subroutine, the chip under test GX8002B performs CRC verification. If the verification is successful, the host computer chip GX8008C waits to test the next chip under test and returns to step (2). The chip under test GX8002B executes step (11). If the verification fails, GX8008C is notified to retransmit. If the verification still fails after two retransmissions, the chip under test GX8002B is considered to be malfunctioning and directly enters step (12).

[0064] Step (11) GX8002B executes the second subroutine, which specifically includes:

[0065] (11-1) Connect the output pin of the digital-to-analog converter (DAC) of the chip under test, GX8002B, to the input pin of the analog-to-digital converter (ADC);

[0066] (11-2) The tested chip GX8002B outputs a sine wave signal with a sampling rate of 48KHz and a signal frequency of 1KHz through the DAC output pin via the second subroutine. The tested chip GX8002B analog-to-digital converter (ADC) samples the sine wave signal, downsamples it to a sampling rate of 16KHz through a digital filter, and stores the downsampled sine wave signal in memory. The signal-to-noise ratio (SNR), total harmonic distortion (THD), and signal characteristics of the downsampled sine wave signal are calculated and compared with preset SNR thresholds of 60dB, THD thresholds of -70dB, and signal characteristic thresholds. If all are greater than or equal to the thresholds, the audio path is correctly marked by outputting the audio path error flag through the UART of GX8002B; otherwise, the audio path error flag is output.

[0067] (11-3) The tested chip GX8002B outputs a voice signal containing "Hello Xiaoxin, Hello Xiaoxin" through the DAC output pin via the second subroutine. The GX8002B analog-to-digital converter (ADC) samples the voice signal, downsamples it to a sampling rate of 16kHz through a digital filter, and stores the downsampled voice signal in memory. The audio signal processor (ADSP) extracts acoustic features and detects wake words for the specific voice signal. If the extracted acoustic features match the preset features and the wake word "Hello Xiaoxin" is detected correctly, the audio signal processor outputs a correct flag through the UART of the GX8002B; otherwise, it outputs an incorrect flag.

[0068] Step (12) Calculate all test results and light up the LEDs used to display the results according to the normal or abnormal status; green light corresponds to the GX8002B chip being tested and functioning normally, and red light corresponds to the GX8002B chip being abnormal.

[0069] The above embodiments are merely preferred embodiments of the present invention. It should be understood that those skilled in the art can design many other modifications and embodiments. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A test method for a SiP chip used for voice signal processing, characterized in that, The method is as follows: Step (1) The test program is burned into the host computer chip, and the host computer chip enters the waiting handshake mode; the test program contains two subroutines, and the host computer executes the test master control of the chip under test; Step (2) Install the chip under test in the chip fixture; after power-on, the host computer chip performs the first communication handshake with the chip under test through its own universal asynchronous transceiver UART; the chip under test is a SiP chip for voice signal processing; After the initial communication handshake is successful in step (3), the host computer chip and the chip under test agree on the baud rate for the first communication; Step (4) The host computer chip and the chip under test communicate for the first time at the agreed baud rate. The host computer chip confirms the model of the chip under test and informs the chip under test that the test program will be transmitted. Step (5) The host computer chip transmits the first subroutine in the test program to the memory of the chip under test; after receiving the first subroutine, the chip under test performs verification. If the verification is successful, the host computer chip waits to transmit the second subroutine, and the chip under test executes step (6); if the verification fails, the host computer chip is notified and asked to retransmit; if the verification still fails after retransmitting twice, the chip under test is considered to be malfunctioning and directly proceeds to step (12). Step (6) The chip under test executes the first subroutine, including: calibrating the built-in crystal oscillator OSC of the chip under test, testing the phase-locked loop PLL of the chip under test, testing the Flash read / write erase of the chip under test, testing the SRAM read / write of the chip under test, and testing the power management module PMU of the chip under test. Step (7) The host computer chip performs a second communication handshake with the chip under test through its own Universal Asynchronous Receiver / Transmitter (UART); Step (8) After the second communication handshake is successful, the host computer chip and the chip under test agree on the baud rate for the second communication; Step (9) The host computer chip transfers the second subroutine in the test program to the memory of the chip under test and replaces the first subroutine; Step (10) After receiving the second subroutine, the chip under test performs verification. If the verification is successful, the host computer chip waits to test the next chip under test and returns to step (2). The chip under test executes step (11). If the verification fails, the host computer chip is notified to retransmit. If the verification still fails after retransmitting twice, the chip under test is considered to be malfunctioning and directly enters step (12). Step (11) The chip under test executes the second subroutine, which includes testing the audio path and audio signal processor of the chip under test; Step (12) outputs the test results, including whether the tested chip is functioning normally or abnormally, as well as the test results of steps (6) and (11).

2. The testing method for a SiP chip for voice signal processing as described in claim 1, characterized in that: In steps (3) and (8), the baud rate agreed upon by the host computer chip and the chip under test is the maximum baud rate that the host computer chip and the chip under test can accept together in the current state.

3. The testing method for a SiP chip for voice signal processing as described in claim 1, characterized in that: Step (6) The chip under test executes the first subroutine, as follows: (6-1) Calibrate the built-in crystal oscillator (OSC) of the chip under test: Adjust the calibration coefficient of the built-in crystal oscillator (OSC) of the chip under test to successively approximate the clock frequency provided by the host computer chip until it is consistent with the clock frequency provided by the host computer chip. Write the final calibration coefficient into the one-time programmable memory (OTP) of the chip under test and display the OSC calibration success flag; if it is not consistent with the clock frequency provided by the host computer chip, display the OSC calibration failure flag. (6-2) Based on the preset multiple output clock frequencies of the PLL of the chip under test, set a set of coefficients corresponding to each output clock frequency; query the status register of the PLL of the chip under test after setting each set of coefficients, check the locking status corresponding to each set of coefficients, if the locking status corresponding to all sets of coefficients is locked, display the PLL locking success flag, otherwise display the PLL locking failure flag. (6-3) Write the fixed data set in the first subroutine into the Flash of the chip under test, then read the data in the Flash and compare it with the fixed data set in the first subroutine. If they match, erase all the data in the Flash and verify whether the erasure is successful. If successful, display the Flash read / write / erase success flag; if they do not match, or the erasure verification fails, display the Flash read / write / erase failure flag. (6-4) The chip under test requests available memory space from its own SRAM through the first subroutine, writes the fixed data set in the first subroutine into the available memory space, then reads the data in the memory space and compares it with the fixed data set in the first subroutine. If they match, the SRAM read / write success flag is displayed; otherwise, the SRAM read / write failure flag is displayed. (6-5) The chip under test controls the internal power management module PMU through the first subroutine to put the chip under test into standby mode and exit standby mode after waiting for a set time. If entering and exiting standby mode is performed correctly, the PMU correct flag will be displayed; otherwise, the PMU error flag will be displayed.

4. The testing method for a SiP chip for voice signal processing as described in claim 1, characterized in that: Step (11) The chip under test executes the second subroutine, as follows: (11-1) Connect the output pin of the digital-to-analog converter (DAC) of the chip under test to the input pin of the analog-to-digital converter (ADC); (11-2) The chip under test outputs a sine wave signal with a set sampling rate and signal frequency through the DAC output pin via the second subroutine. The ADC of the chip under test samples the sine wave signal, downsamples it to the set sampling rate through a digital filter, and stores the downsampled sine wave signal in memory. The signal-to-noise ratio, total harmonic distortion ratio, and signal characteristics of the downsampled sine wave signal are calculated and compared with preset signal-to-noise ratio thresholds, total harmonic distortion ratio thresholds, and signal characteristic thresholds. If all are greater than or equal to the thresholds, an audio path correct flag is displayed; otherwise, an audio path error flag is displayed. (11-3) The chip under test outputs a specific voice signal set by the DAC output pin through the second subroutine. The ADC of the chip under test samples the specific voice signal, and the signal is downsampled to the set sampling rate by a digital filter. The downsampled specific voice signal is stored in memory. The ADSP is used to extract acoustic features and detect wake words on the specific voice signal. If the extracted acoustic features match the preset features and the wake word is detected correctly, the ADSP displays the correct ADSP flag; otherwise, the ADSP displays the incorrect ADSP flag.

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