An input detection and hibernate wake-up method and system suitable for SOC
By using discrete component design and isolated wake-up circuits, the problem of high SOC wake-up cost is solved, achieving low-cost and high-reliability wake-up function, which is suitable for electronic controllers such as body controllers and smart cockpits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- DONGFENG MOTOR GRP
- Filing Date
- 2023-10-26
- Publication Date
- 2026-07-21
AI Technical Summary
The current SOC is costly to implement the wake-up requirement in automotive electronic controllers and relies on dedicated chips, resulting in low cost-effectiveness and a risk of chip shortage.
It adopts a discrete component design, increases the diversity of wake-up methods through isolated wake-up channels, uses rising edge and falling edge wake-up circuits, flexibly sets circuit characteristics, and wakes up the SOC according to the wake-up control strategy when the SOC is in sleep mode. It has EMC, electrostatic discharge, and reverse current protection measures.
It reduces the hardware cost and software complexity of the SOC, improves reliability and flexibility, reduces the failure rate, and achieves low power consumption and highly reliable wake-up functionality.
Smart Images
Figure CN117591185B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of circuit controller technology, specifically relating to an input detection and sleep / wake-up method and system suitable for SOC. Background Technology
[0002] With the continuous penetration and upgrading of intelligent vehicles, the core competitive area of automobiles has shifted from mechanical components to controllers. Controllers have evolved from traditional distributed single-function controllers to today's integrated multi-functional domain controllers, and the processors of controllers have also shifted from MCUs to SOCs.
[0003] In the current field of automotive electronic controllers, SoCs have more powerful computing capabilities than MCUs, while MCUs have better automotive electronic control performance than SoCs. For example, many SoCs only have two wake-up ports and only support level wake-up, not edge wake-up. Most MCUs support 15 to 30 wake-up channels and can select level, edge, or both level and edge wake-up. Most automotive electronic controllers require 8 to 25 wake-up sources. Therefore, SoCs need external wake-up source expansion circuits to meet the wake-up requirements of automotive electronic controllers.
[0004] Currently, most domain controllers use two or more processors: an MCU processor and a SOC processor. The MCU processor is used for control functions such as wake-up, while the SOC processor is used for computation. A small number of domain controllers use only one SOC processor. Wake-up is handled by dedicated chips, and the results of each dedicated chip are connected to the SOC's wake-up port via a multi-input OR gate. For example, switch wake-up is handled by the TIC12400 integrated circuit, and CAN wake-up is handled by the TJA1043 integrated circuit. The two results are ORed by the 74LS32 integrated circuit and then connected to the SOC's wake-up port.
[0005] However, both of these solutions are costly to implement and heavily reliant on dedicated chips, resulting in low cost-effectiveness. In the highly competitive automotive electronic controller market, cost-effectiveness is a key factor in determining whether a controller can gain market share. The strong reliance on dedicated chips also carries a significant risk of chip shortages. Summary of the Invention
[0006] To address the aforementioned problems, this invention provides an input detection and sleep / wake-up method and system suitable for SOCs, thereby resolving the issues in the prior art.
[0007] To achieve the aforementioned objectives, this invention proposes an input detection and sleep / wake-up method suitable for SOCs, comprising:
[0008] Step S1: Obtain the sleep conditions of the first chip;
[0009] Step S2: Set a first delay period. When the first chip meets the sleep conditions, the first chip is in a first state. The first circuit power supply and the second circuit power supply are turned off. Wait for the first delay period to acquire the first wake-up input and the second wake-up input. If the first wake-up input and the second wake-up input are a preset first threshold, the first circuit power supply and the second circuit power supply are turned on. The first chip changes from the first state to the second state. If the first wake-up input and the second wake-up input are a preset second threshold and the third circuit power supply is turned off, the first chip re-enters the first state.
[0010] Step S3: When the first chip is in the first state, obtain the state change of the first switch set. If the state change is the first form, set the first wake-up input and the second wake-up input to the first threshold, the first chip enters the third state, and the power supply of the third circuit is turned on.
[0011] Step S4: Set a detection cycle threshold. The first chip detects the state change based on the detection cycle threshold and enters the second state from the third state.
[0012] Furthermore, step S1 includes the following step of obtaining the hibernation conditions:
[0013] A detection cycle is set to determine the attribute status of the first chip. Based on the detection cycle and the attribute status, the working mode of the first chip is obtained, and the sleep conditions are set based on the working mode.
[0014] Furthermore, in step S2, the first wake-up input and the second wake-up input are obtained based on the following steps:
[0015] The first low-side switch input, the first high-side switch input, the first analog switch input, and the first combination switch input are acquired respectively. A first voltage range, a second voltage range, and a first pulse width threshold are set. If the first low-side switch input and the first high-side switch input are within the second voltage range, the first wake-up input and the second wake-up input output a first type of wake-up signal; otherwise, a second type of wake-up signal is output. If the first analog switch input and the first combination switch input are within the first voltage range, the first wake-up input and the second wake-up input output the first type of wake-up signal; otherwise, a second type of wake-up signal is output.
[0016] Furthermore, in step S3, the state change is set by detecting the change values of the first condition and the second condition in the first switch set.
[0017] Furthermore, in step S4, the first chip transitioning from the third state to the second state includes the following steps:
[0018] When the first chip enters the third state, the power supply of the first circuit and the power supply of the second circuit are turned on. The detection cycle threshold includes a first detection time and a second detection time. If the first chip detects the first wake-up input and the second wake-up input within the first detection time, the first chip enters the second state from the third state. Otherwise, the first chip performs detection within the second detection time and enters the second state from the third state.
[0019] This invention also provides an input detection and sleep / wake-up system suitable for SOCs. This system is used to implement the aforementioned input detection and sleep / wake-up method for SOCs. The system mainly includes:
[0020] The data acquisition module is used to acquire the sleep conditions of the first chip;
[0021] The control and determination module is used to set a first delay period. When the first chip meets the sleep conditions, the first chip is in a first state, the first circuit power supply and the second circuit power supply are turned off, and the first wake-up input and the second wake-up input are obtained based on the first delay period. If the first wake-up input and the second wake-up input are a preset first threshold, the first circuit power supply and the second circuit power supply are turned on, and the first chip enters a second state from the first state. If the first wake-up input and the second wake-up input are a preset second threshold, and the third circuit power supply is turned off, the first chip re-enters the first state.
[0022] The sleep-wake module is used to acquire the state change of the first switch set when the first chip is in the first state. If the state change is a first mode, the first wake-up input and the second wake-up input are set to the first threshold, the first chip enters the third state, and the power supply of the third circuit is turned on.
[0023] The circuit detection module is used to set a detection cycle threshold. The first chip detects the state change based on the detection cycle threshold and enters the second state from the third state.
[0024] Compared with the prior art, the beneficial effects of the present invention are at least as follows:
[0025] This invention utilizes discrete components to achieve the operating performance of each circuit module, isolates the wake-up channels of each circuit module to reduce crosstalk between them, and uses both rising and falling edges to wake up the same signal in the circuit module, while separating the rising and falling edge wake-up circuits to increase the diversity of wake-up methods and the reliability of the wake-up circuit. By modifying the RC parameters in the circuit, the threshold values for wake-up voltage and wake-up time, as well as the high and low voltage thresholds, can be changed, enabling flexible setting of circuit characteristics. In this invention, the circuit modules completely isolate the SOC port from the peripheral ports. When the SOC is working, they are used to detect analog and digital input signals and generate interrupts according to the interrupt control strategy. When the SOC is in sleep mode, it can be woken up according to the wake-up control strategy. It has protection measures such as EMC, electrostatic discharge, reverse current protection, voltage clamping, current limiting, and isolation buffering, which improves the reliability of the SOC.
[0026] This invention features a dedicated low-power power supply, low-power control circuit, and edge wake-up circuit, resulting in low dark current and low static power consumption. The circuit modules in this invention can be applied to various types of electronic controllers such as body controllers, smart cockpits, and intelligent driving controllers. Moreover, the circuit modules can not only be used in a customized manner but also replicated, connected in parallel, and recombined for use. Therefore, this invention has the characteristics of strong versatility, good customizability, excellent scalability, high reconfigurability, low cost, simple control, high reliability, long service life, low static power consumption, and low SOC load rate. Attached Figure Description
[0027] Figure 1 This is a flowchart illustrating the steps of an input detection and sleep / wake-up method for a System-on-a-Chip (SOC) according to the present invention.
[0028] Figure 2 This is a circuit block diagram of modules M1-M13 in the first chip of the present invention;
[0029] Figure 3 This is a circuit schematic diagram of module M1 of the present invention;
[0030] Figure 4 This is a circuit schematic diagram of module M2 of the present invention.
[0031] Figure 5 This is a circuit schematic diagram of module M12 of the present invention;
[0032] Figure 6 This is a circuit schematic diagram of module M8 of the present invention;
[0033] Figure 7 This is a circuit schematic diagram of module M10 of the present invention;
[0034] Figure 8 This is a circuit schematic diagram of module M7 of the present invention;
[0035] Figure 9 This is a structural diagram of an input detection and sleep / wake-up system suitable for SOC according to the present invention. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0037] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but unless otherwise specified, these elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first script may be referred to as a second script, and similarly, a second script may be referred to as a first script.
[0038] like Figure 1 As shown, an input detection and sleep / wake-up method suitable for SOC includes:
[0039] Step S1: Obtain the sleep conditions of the first chip.
[0040] Specifically, in this embodiment, the first chip refers to a system-level SoC chip, which is capable of supporting complex systems that run multiple tasks. The sleep condition is set based on the working status of each circuit module obtained by the first chip when it is in sleep mode.
[0041] Step S2: Set a first delay period. When the first chip meets the sleep conditions, the first chip is in the first state. Turn off the first circuit power supply and the second circuit power supply, and wait for the first delay period to obtain the first wake-up input and the second wake-up input. If the first wake-up input and the second wake-up input are the preset first threshold, then turn on the first circuit power supply and the second circuit power supply, and the first chip changes from the first state to the second state. If the first wake-up input and the second wake-up input are the preset second threshold, and the third circuit power supply is turned off, then the first chip re-enters the first state.
[0042] Specifically, in this embodiment, the first delay period is set to 20ms, the first state is set to sleep state, and the circuit block diagram of the first chip is as follows. Figure 2 As shown, Figure 2In the diagram: Module M1 is the power supply for the combination switch wake-up circuit; Module M2 is the output circuit for the combination switch detection; Module M3 is the input circuit for the combination switch detection; Module M4 is the automotive combination switch; Module M5 is the low-side switch detection circuit; Module M6 is the low-side switch; Module M7 is the high-side switch detection circuit; Module M8 is the low-level wake-up circuit triggered by a positive edge; Module M9 is the high-side switch; Module M10 is the low-level wake-up circuit triggered by a negative edge; Module M11 is the analog switch; Module M12 is the analog switch detection circuit; and Module M13 is the power supply for the analog wake-up circuit. The first circuit power supply refers to the power supply BAT_SW for the combination switch wake-up circuit in module M1, whose detailed circuit diagram is shown below. Figure 3 As shown, the power supply output of the first circuit is detected through circuit module M2, and its detailed circuit schematic is as follows. Figure 4 As shown, the second circuit power supply refers to the analog wake-up circuit power supply 5V0_SW in module M12, and its detailed circuit schematic is as follows. Figure 5 As shown, the first wake-up input refers to the input result of the low-level wake-up circuit triggered by the positive edge in module M8. Its detailed circuit schematic is shown below. Figure 6 As shown, the second wake-up input refers to the input result of the low-level wake-up circuit triggered by the negative edge in module M10. Its detailed circuit schematic is shown below. Figure 7 As shown, the first threshold is set to a valid low level with a range of (0~0.6)V, the second threshold is set to a valid high level with a range of (1.2~2.0)V, the second state is set to the running state, and the third circuit power supply refers to part of the power supply of the first chip SOC, including 0V8_SW, 1V8_SW and 3V3_SW power supplies.
[0043] In circuit module M2, Q4 is a BC817-25 NPN transistor, which amplifies the input signal current and inversely amplifies the input signal voltage. R14 is a 10kΩ base shunt resistor for Q4, and R13 is a 10kΩ base limiting resistor for Q4. R13 and R14 determine the conduction voltage threshold of Q4. Q5 is a BC807-25 PNP transistor, which amplifies the input signal current and inversely amplifies the input signal voltage. R18 is a 10kΩ base shunt resistor for Q5, and R1... R7 is the base current-limiting resistor for Q5 with a resistance of 10kΩ. R17 and R18 determine the on-voltage threshold of Q5. R16 is the input current-limiting resistor for Power_ArraySW0_WK with a resistance of 4.7kΩ. C7 is the first-stage filter capacitor for Output_ArraySW0 with a resistance of 47nF. C8 is the second-stage filter capacitor for Output_ArraySW0 with a resistance of 47nF. R21 is the output current-limiting resistor for Output_ArraySW0 with a resistance of 680Ω. When Power_Ar When the Power_ArraySW0_WK input is open and the DO0_SOC input is high (3.3V), the Output_ArraySW0 output voltage is 12.7V, and the Output_ArraySW0 output current capability is 18mA. When the Power_ArraySW0_WK input is open and the DO0_SOC input is low (0V), the Output_ArraySW0 output is open, and the Output_ArraySW0 output leakage current is 5uA. When the Power_ArraySW0_WK input is 12V and the DO0_SOC input is low (0V), the Output_ArraySW0 output voltage is 12V, the Output_ArraySW0 output resistance is 5.38kΩ, and the Output_ArraySW0 output current capability is 2.2mA. The Output_ArraySW0 output delay relative to the DO0_SOC input is 95µs, and the Output_ArraySW0 output delay relative to the Power_ArraySW0_WK input is 750µs.
[0044] Step S3: When the first chip is in the first state, obtain the state change of the first switch set. If the state change is the first form, set the first wake-up input and the second wake-up input as the first threshold, the first chip enters the third state, and the third circuit power is turned on.
[0045] Specifically, in this embodiment, such as Figure 2As shown, the first switch set refers to the set of the first circuit power supply, the second circuit power supply, and the third circuit power supply. The state change refers to whether the switch corresponding to each circuit power supply changes from open to closed. Among them, the externally input low-level pulse PIL0 appears as a valid low-level pulse or waveform, and the externally input high-level pulse PIH0 appears as a valid high-level pulse or waveform. The first state refers to the circuit state corresponding to the appearance of a valid low level, and the third state refers to the wake-up state.
[0046] Step S4: Set the detection cycle threshold. The first chip detects state changes based on the detection cycle threshold and enters the second state from the third state.
[0047] Specifically, the detection cycle threshold is set according to different detection cycles. The first chip detects the state changes of each circuit module according to different detection cycle thresholds, and enters the running state from the wake-up state according to the detection results.
[0048] This invention utilizes discrete components to achieve the operating performance of each circuit module, isolates the wake-up channels of each circuit module to reduce crosstalk between them, and uses both rising and falling edges to wake up the same signal in the circuit module, while separating the rising and falling edge wake-up circuits to increase the diversity of wake-up methods and the reliability of the wake-up circuit. By modifying the RC parameters in the circuit, the threshold values for wake-up voltage and wake-up time, as well as the high and low voltage thresholds, can be changed, enabling flexible setting of circuit characteristics. In this invention, the circuit modules completely isolate the SOC port from the peripheral ports. When the SOC is working, they are used to detect analog and digital input signals and generate interrupts according to the interrupt control strategy. When the SOC is in sleep mode, it can be woken up according to the wake-up control strategy. It has protection measures such as EMC, electrostatic discharge, reverse current protection, voltage clamping, current limiting, and isolation buffering, which improves the reliability of the SOC.
[0049] This invention features a dedicated low-power power supply, low-power control circuit, and edge wake-up circuit, resulting in low dark current and low static power consumption. The circuit modules in this invention can be applied to various types of electronic controllers such as body controllers, smart cockpits, and intelligent driving controllers. Moreover, the circuit modules can not only be used in a customized manner but also replicated, connected in parallel, and recombined for use. Therefore, this invention has the characteristics of strong versatility, good customizability, excellent scalability, high reconfigurability, low cost, simple control, high reliability, long service life, low static power consumption, and low SOC load rate.
[0050] Of particular note is that the design of each circuit module in this invention can reduce the hardware cost of the controller, reduce the complexity of the controller software, and thus reduce the failure rate of the controller.
[0051] Step S1 includes the following steps to obtain the hibernation conditions:
[0052] Set a detection cycle, determine the attribute status of the first chip, obtain the working mode of the first chip based on the detection cycle and attribute status, and set sleep conditions based on the working mode.
[0053] Specifically, the attribute state refers to the on / off state of all circuit power supplies in the first chip. The working pattern of the first chip is determined by setting the detection cycle and attribute state, and the on / off state of each circuit power supply is set as the sleep condition when the first chip enters the sleep state.
[0054] In step S2, the first wake-up input and the second wake-up input are obtained based on the following steps:
[0055] The first low-side switch input, the first high-side switch input, the first analog switch input, and the first combination switch input are acquired respectively. A first voltage range, a second voltage range, and a first pulse width threshold are set. If the first low-side switch input and the first high-side switch input are within the second voltage range, the first wake-up input and the second wake-up input output a first type of wake-up signal; otherwise, a second type of wake-up signal is output. If the first analog switch input and the first combination switch input are within the first voltage range, the first wake-up input and the second wake-up input output a first type of wake-up signal; otherwise, a second type of wake-up signal is output.
[0056] Specifically, in this embodiment, such as Figure 5As shown, Q7 is an NPN transistor of model BC817-25, which amplifies the current of the input signal and inversely amplifies the voltage of the input signal. It is also the discharge transistor of C17. R33 is a 20kΩ charging resistor for C17. C17 is a 100nF charging, discharging, and filtering capacitor for WU0_SOC. C13 is a 10nF input filtering capacitor for DIL0_SW and DIH0_SW. R29 is a 10kΩ base shunt resistor for Q7. R25 is a 2kΩ base current limiting resistor for Q7. R25 and R29 determine the conduction voltage threshold of Q2. D7 is a BAS321 base-emitter protection diode for Q7. D4 is a BAS321 base-emitter protection diode for Q7. The BAS321 anti-crosstalk diode is used. R23 is a 30kΩ discharge capacitor (C9), C9 is a 1µF DC blocking capacitor (DIH0_SW). D5 is a BAS321 anti-crosstalk diode. R24 is a 30kΩ discharge capacitor (C10), C10 is a 1µF DC blocking capacitor (DIH0_SW). Q8 is a BC817-25 NPN transistor, amplifying the input signal current and inversely amplifying the input signal voltage. C14 is a 10nF input filter capacitor (DIH0_ArraySW). R30 is a 10kΩ base shunt resistor for Q8. R26 is a 1kΩ base current limiting resistor for Q8. R26 and... R30 determines the turn-on voltage threshold of Q8. D8 is a BAS321 base-emitter protection diode for Q8. C11 is a 1uF DC blocking capacitor for DIH0_ArraySW. Q9 is a BC817-25 NPN transistor, which amplifies the input signal current and inversely amplifies the input signal voltage. C15 is a 10nF input filter capacitor for AIL0_ASW. R31 is a 10kΩ base shunt resistor for Q9. R27 is a 1kΩ base current limiting resistor for Q9. R27 and R31 determine the turn-on voltage threshold of Q9. D9 is a BAS321 base-emitter protection diode for Q9. C12 is a 1uF capacitor for AIL0_ArraySW. The IL0_ASW is a DC blocking capacitor; Q10 is a BC817-25 NPN transistor, which amplifies the input signal current and inversely amplifies the input signal voltage; C16 is a 51pF PIH0 input filter capacitor; R32 is a 10kΩ base shunt resistor for Q10; R28 is a 2kΩ base current limiting resistor for Q10; R28 and R32 determine the conduction voltage threshold of Q10; D6 is a BAS321 base reverse protection diode for Q10; when SW4 switches from closed to open, WU0_SOC outputs a 0.3ms low-level pulse, which can wake up the SOC; when SW1 switches from open to closed, WU0_SOC outputs 0.A 3ms low-level pulse can wake up the SOC; when CSW1 switches from open to closed, WU0_SOC outputs a 0.3ms low-level pulse to wake up the SOC; when SW2 or SW3, or both SW2 and SW3, switch from closed to open, WU0_SOC outputs a 0.06ms low-level pulse to wake up the SOC; PIH0 is connected to the RX or INH of CAN, CANFD, or LIN. When CAN, CANFD, or LIN receives a wake-up frame signal, WU0_SOC outputs a valid low-level wake-up signal to wake up the SOC.
[0057] In this embodiment, as Figure 6As shown, Q11 is a BC807-25 PNP transistor, which amplifies the input signal current and inversely amplifies the input signal voltage. C22 is the 10nF input filter capacitor for DIL0_SW and DIH0_SW. R40 is a 10kΩ base shunt resistor for Q11. R36 is a 2kΩ base current limiting resistor for Q11. R36 and R40 determine the conduction voltage threshold of Q11. D13 is a BAS321 base-emitter protection diode for Q11. D10 is a BAS321 anti-crosstalk diode. R34 is a 30kΩ discharge capacitor for C18. C18 is a 1µF DC blocking capacitor for DIL0_SW. In this circuit, D11 is a BAS321 anti-crosstalk diode; R35 is a 30kΩ discharge capacitor (C19); C19 is a 1µF DC blocking capacitor (DIH0_SW); C27 is a 100nF 3V3_C filter capacitor; Q12 is a BC807-25 PNP transistor, which amplifies the input signal current and inversely amplifies the input signal voltage; C23 is a 10nF DIH0_ArraySW input filter capacitor; R41 is a 10kΩ base shunt resistor for Q12; R37 is a 1kΩ base current limiting resistor for Q12; R37 and R41 determine the turn-on voltage threshold of Q12; and D14 is a type... Q12, designated BAS321, is a base-emitter protection diode. C20 is a 1uF DC blocking capacitor (DIH0_ArraySW); C28 is a 100nF 3V3_C filter capacitor; Q13 is a BC807-25 PNP transistor, amplifying the input signal current and inversely amplifying the input signal voltage; C24 is a 10nF input filter capacitor (AIL0_ASW); R42 is a 10kΩ base shunt resistor for Q13; R38 is a 1kΩ base current limiting resistor for Q13; R38 and R42 determine the conduction voltage threshold of Q13; D15 is the base-emitter protection diode for Q13 (designated BAS321). The transistor configuration is as follows: C21 is a 1uF AIL0_ASW DC blocking capacitor; C29 is a 100nF 3V3_C filter capacitor; Q14 is a BC807-25 PNP transistor, which amplifies the input signal current and reverses the input signal voltage; C25 is a 51pF PIL0 input filter capacitor; R43 is a 10kΩ base shunt resistor for Q14; R39 is a 2kΩ base current limiting resistor for Q14; R39 and R43 determine the conduction voltage threshold of Q14; D12 is a BAS321 base reverse protection diode for Q14; and C26 is a 100nF 3V3_C filter capacitor.Q15 is an NPN transistor, model BC817-25, which amplifies the input signal current and inversely amplifies the input signal voltage. It is also the discharge transistor of C31. R46 is a 20kΩ charging resistor for C31. C31 is a 100nF charging, discharging, and filtering capacitor for WU1_SOC. C30 is a 10nF collector output filter capacitor for Q11, Q12, Q13, and Q14. R45 is a 10kΩ base shunt resistor for Q15. R44 is a 2kΩ base current limiting resistor for Q15. R44 and R45 determine the conduction voltage threshold of Q15. When SW4 switches from open to closed, the output of WU1_SOC is 0. A 3ms low-level pulse can wake up the SOC; when SW1 switches from closed to open, WU1_SOC outputs a 0.3ms low-level pulse to wake up the SOC; when CSW1 switches from open to closed, WU1_SOC outputs a 0.3ms low-level pulse to wake up the SOC; when SW2 or SW3, or both SW2 and SW3, switches from open to closed, WU1_SOC outputs a 0.06ms low-level pulse to wake up the SOC; PIL0 is connected to the RX or INH of CAN, CANFD, or LIN. When CAN, CANFD, or LIN receives a wake-up frame signal, WU1_SOC outputs a valid low-level wake-up signal to wake up the SOC.
[0058] In step S3, the state change is set by detecting the change values of the first condition and the second condition in the first switch set.
[0059] Specifically, the first set of switches includes a first circuit power supply, a second circuit power supply, and a third circuit power supply. The first condition refers to a pulse or waveform with a valid low level, and the second condition refers to a pulse or waveform with a valid high level.
[0060] In step S4, the first chip transitions from the third state to the second state, which includes the following steps:
[0061] When the first chip enters the third state, the first circuit power supply and the second circuit power supply are turned on. The detection cycle threshold includes the first detection time and the second detection time. If the first chip detects the first wake-up input and the second wake-up input within the first detection time, the first chip enters the second state from the third state. Otherwise, the first chip performs the detection within the second detection time and enters the second state from the third state.
[0062] Specifically, in this embodiment, when the first chip enters the wake-up state, the SOC power supplies 0V8_SW, 1V8_SW, and 3V3_SW in the third circuit power supply are turned on, and the first chip SOC is powered on and restarted. After restarting, the BAT_SW and 5V0_SW power supplies are turned on. After a 20ms delay, the SOC checks all wake-up sources. If a valid wake-up source is detected, the SOC performs the corresponding processing and enters the normal working state. If no valid wake-up source is detected, the SOC continues to detect for 1 minute. If no valid wake-up source is detected, the SOC enters the normal working state. The schematic diagram of circuit module M7 is shown below. Figure 8 As shown, high-side switching detection can be performed on the power supply of the third circuit. For example, Q2 is an NPN transistor of model BC817-25, which amplifies the current of the input signal and inversely amplifies the voltage of the input signal. R3 is the input load resistor of DIH0_SW with a resistance of 4.7kΩ. C1 is the input filter capacitor of DIH0_SW with a capacitance of 47nF. R7 is the base shunt resistor of Q2 with a resistance of 12kΩ. R6 is the base current limiting resistor of Q2 with a resistance of 68kΩ. R6 and R7 determine the conduction voltage threshold of Q2. C3 is the base filter capacitor of Q2 with a capacitance of 10nF. R11 is the base filter capacitor of Q2 with a resistance of 4.7kΩ. The collector current limiting resistor is 2. When 3V3_SW is turned on, if the high-side switch SW1 is closed, DIH0_SW receives a high voltage of 12.7V, DI1_SOC outputs a low level of 0V, and the input current of DIH0_SW is 2.7mA. If the high-side switch SW1 is turned off, DIH0_SW receives a low voltage of 0V, and DI1_SOC outputs a high level of 3.3V. The delay of DI1_SOC output relative to the input of DIH0_SW is 600us, and the delay of DI1_SOC output relative to the input of 3V3_SW is 10ns. When 3V3_SW is turned off, DI1_SOC outputs a low level of 0V.
[0063] like Figure 9 As shown, the present invention also provides an input detection and sleep / wake-up system suitable for SOCs. This system is used to implement the aforementioned input detection and sleep / wake-up method suitable for SOCs. The system mainly includes:
[0064] The data acquisition module is used to acquire the sleep conditions of the first chip;
[0065] The control and determination module is used to set a first delay period. When the first chip meets the sleep conditions, the first chip is in the first state, the first circuit power supply and the second circuit power supply are turned off, and the first wake-up input and the second wake-up input are obtained based on the first delay period. If the first wake-up input and the second wake-up input are a preset first threshold, the first circuit power supply and the second circuit power supply are turned on, and the first chip enters the second state from the first state. If the first wake-up input and the second wake-up input are a preset second threshold, and the third circuit power supply is turned off, the first chip re-enters the first state.
[0066] The sleep-wake module is used to obtain the state change of the first switch set when the first chip is in the first state. If the state change is the first mode, the first wake-up input and the second wake-up input are set as the first threshold, the first chip enters the third state, and the third circuit power is turned on.
[0067] The circuit detection module is used to set the detection cycle threshold. The first chip detects state changes based on the detection cycle threshold and enters the second state from the third state.
[0068] It should be understood that although the steps in the flowcharts of the various embodiments of the present invention are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the various embodiments may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.
[0069] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.
[0070] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0071] The above embodiments merely illustrate several implementation methods of the present invention, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.
[0072] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. An input detection and sleep / wake-up method suitable for SOC, characterized in that, The method includes the following steps: Step S1: Obtain the sleep conditions of the first chip; Step S2: Set a first delay period. When the first chip meets the sleep conditions, the first chip is in a first state. The first circuit power supply and the second circuit power supply are turned off. Wait for the first delay period to acquire the first wake-up input and the second wake-up input. If the first wake-up input and the second wake-up input are a preset first threshold, the first circuit power supply and the second circuit power supply are turned on. The first chip changes from the first state to the second state. If the first wake-up input and the second wake-up input are a preset second threshold and the third circuit power supply is turned off, the first chip re-enters the first state. The first wake-up input and the second wake-up input are obtained based on the following steps: The first low-side switch input, the first high-side switch input, the first analog switch input, and the first combination switch input are acquired respectively. A first voltage range, a second voltage range, and a first pulse width threshold are set. If the first low-side switch input and the first high-side switch input are within the second voltage range, the first wake-up input and the second wake-up input output a first type of wake-up signal; otherwise, a second type of wake-up signal is output. If the first analog switch input and the first combination switch input are within the first voltage range, the first wake-up input and the second wake-up input output the first type of wake-up signal; otherwise, a second type of wake-up signal is output. Step S3: When the first chip is in the first state, obtain the state change of the first switch set. If the state change is the first form, set the first wake-up input and the second wake-up input to the first threshold, the first chip enters the third state, and the power supply of the third circuit is turned on. Step S4: Set a detection cycle threshold. The first chip detects the state change based on the detection cycle threshold and transitions from the third state to the second state. The transition of the first chip from the third state to the second state includes the following steps: When the first chip enters the third state, the power supply of the first circuit and the power supply of the second circuit are turned on. The detection cycle threshold includes a first detection time and a second detection time. If the first chip detects the first wake-up input and the second wake-up input within the first detection time, the first chip enters the second state from the third state. Otherwise, the first chip performs detection within the second detection time and enters the second state from the third state.
2. The input detection and sleep / wake-up method suitable for SOC according to claim 1, characterized in that, In step S1 The hibernation conditions are obtained by including the following steps: A detection cycle is set to determine the attribute status of the first chip. Based on the detection cycle and the attribute status, the working mode of the first chip is obtained, and the sleep conditions are set based on the working mode.
3. The input detection and sleep / wake-up method suitable for SOC according to claim 1, characterized in that, In step S3, the state change is set by detecting the change values of the first condition and the second condition in the first switch set.
4. An input detection and sleep / wake-up system suitable for SOC, used to implement the input detection and sleep / wake-up method suitable for SOC as described in any one of claims 1-3, characterized in that, The system includes the following modules: The data acquisition module is used to acquire the sleep conditions of the first chip; The control and determination module is used to set a first delay period. When the first chip meets the sleep conditions, the first chip is in a first state, the first circuit power supply and the second circuit power supply are turned off, and a first wake-up input and a second wake-up input are obtained based on the first delay period. If the first wake-up input and the second wake-up input are a preset first threshold, the first circuit power supply and the second circuit power supply are turned on, and the first chip enters a second state from the first state. If the first wake-up input and the second wake-up input are a preset second threshold, and the third circuit power supply is turned off, the first chip re-enters the first state. The first wake-up input and the second wake-up input are obtained based on the following steps: obtaining a first low-side switch input, a first high-side switch input, a first analog switch input and a first combination switch input respectively; setting a first voltage range, a second voltage range and a first pulse width threshold; if the first low-side switch input and the first high-side switch input are within the second voltage range, the first wake-up input and the second wake-up input output a first type of wake-up signal; otherwise, output a second type of wake-up signal. If the first analog switch input and the first combination switch input are within the first voltage range, the first wake-up input and the second wake-up input output the first type of wake-up signal; otherwise, output a second type of wake-up signal. The sleep-wake module is used to acquire the state change of the first switch set when the first chip is in the first state. If the state change is a first mode, the first wake-up input and the second wake-up input are set to the first threshold, the first chip enters the third state, and the power supply of the third circuit is turned on. A circuit detection module is used to set a detection cycle threshold. The first chip detects the state change based on the detection cycle threshold and enters the second state from the third state. The process of the first chip entering the second state from the third state includes the following steps: when the first chip enters the third state, the power supply of the first circuit and the power supply of the second circuit are turned on. The detection cycle threshold includes a first detection time and a second detection time. If the first chip detects the first wake-up input and the second wake-up input within the first detection time, the first chip enters the second state from the third state. Otherwise, the first chip performs detection within the second detection time and enters the second state from the third state.