Pixel driving circuit and display device for digitally controlling initialization of pixel internal memory and register

Abstract

The present disclosure relates to a pixel driving circuit included in a display device and a display device. The pixel driving circuit according to the present disclosure includes a memory section including a pixel built-in memory and a register and for storing data related to driving of a light emitting element, a driving section for supplying power to the light emitting element based on the data stored in the memory section, and a reset section for controlling initialization of the memory section; the reset section generates a pixel built-in memory reset signal for controlling initialization of the pixel built-in memory and a register reset signal for controlling initialization of the register.

Description

Technical Field

[0001] This disclosure relates to a pixel included in a display device, and more particularly, to a pixel and display device that digitally controls the initialization of the pixel’s built-in memory and registers. Background Technology

[0002] A typical display device comprises multiple pixels arranged in an M*N array. Each pixel may include more than one light-emitting element, and is typically composed of three light-emitting elements (red, green, and blue (R, G, B)). Each light-emitting element is called a subpixel.

[0003] Among the various methods for controlling driven sub-pixels, there is a pulse width modulation (PWM) control method. This method stores the video data of the sub-frame to be controlled in its built-in memory during a single frame and controls the grayscale (gradation) using a PWM signal. For PWM control, the pixel driving circuit for each pixel can be implemented using transistors, but these can be categorized as digital circuits or analog circuits based on their operating region.

[0004] Digital circuits operate in the cutoff region, corresponding to on-off states, and in the non-saturated region to represent "0" and "1". Conversely, analog circuits (excluding analog switches), such as amplifier (AMP) circuits or bias (BIAS) circuits, operate in the saturation region, and therefore must continuously consume a specified current throughout the circuit's operating time. Since the power required may not always be the same depending on the display driving mode or the screen, a method is needed to reduce static power consumption in pixel driving circuits.

[0005] On the other hand, to initialize the memory, an analog element called Power On Reset (POR) is typically configured in the driver circuit, which poses a significant obstacle to the miniaturization of pixel circuits and the reduction of static power consumption. Furthermore, if registers need to be initialized every time the memory is initialized, the data 1-bit time is reduced accordingly, thus increasing dynamic current consumption and limiting the achievement of high resolution. Therefore, a method for digitally controlling the initialization of memory and registers is needed.

[0006] The background technology described above is technical information that the inventors possessed or obtained during the derivation of this invention, and is not necessarily publicly known technology disclosed to the general public before the application for this invention. Summary of the Invention

[0007] The problem the invention aims to solve

[0008] The purpose of this disclosure is to provide a pixel and display device that digitally controls the initialization of the pixel's built-in memory and registers. The problems to be solved by this disclosure are not limited to those mentioned above; other problems and advantages of this disclosure not mentioned above can be understood through the following description and will become clearer through embodiments of this disclosure. Furthermore, it will be understood that the problems and advantages to be solved by this disclosure can be achieved through the solutions and combinations thereof described in the claims.

[0009] means for solving problems

[0010] According to a pixel driving circuit of a first aspect of this disclosure, the circuit includes: a memory section including a pixel-built-in memory and a register for storing data related to driving a light-emitting element; a driving section for supplying power to the light-emitting element based on the data stored in the memory section; and a reset section for controlling the initialization of the memory section; the reset section generates a pixel-built-in memory reset signal for controlling the initialization of the pixel-built-in memory and a register reset signal for controlling the initialization of the register.

[0011] The display device according to a second aspect of this disclosure includes: a display panel including an arrangement of a plurality of pixel driving circuits forming rows and columns; a scan driving circuit that sequentially outputs row signals to the pixel driving circuits arranged in the row direction in the arrangement of the display panel; and a data driving circuit that outputs column signals related to the driving of light-emitting elements corresponding to each of the plurality of pixel driving circuits to the pixel driving circuits arranged in the column direction in the arrangement of the display panel; each of the plurality of pixel driving circuits is a pixel driving circuit according to the first aspect.

[0012] Invention Effects

[0013] By digitally controlling the initialization of each of the pixel's built-in memory and registers, dynamic current consumption can be reduced and high resolution can be achieved.

[0014] Furthermore, the clock signal used to store data in memory is the same as the data signal, so no additional hardware pins are required, and the initialization of each of the pixel’s built-in memory and registers can be controlled individually without significantly increasing the chip size. Attached Figure Description

[0015] Figure 1 This is a display device including a plurality of pixel driving circuits according to an embodiment of the present disclosure.

[0016] Figure 2This is a block diagram schematically illustrating the configuration of a pixel driving circuit according to an embodiment of the present disclosure.

[0017] Figure 3 This is a circuit diagram of an electric power generation unit according to an embodiment of the present disclosure.

[0018] Figure 4 This is a timing diagram related to the output reference voltage of the power generation unit using row and column signals, based on the specifications in this manual.

[0019] Figure 5 This is a block diagram schematically illustrating the configuration of a trigger that may be included in a register or pixel-embedded memory for storing input data.

[0020] Figure 6 This is a diagram illustrating the operation of the reset section according to an embodiment of the present disclosure.

[0021] Figure 7 This is a block diagram illustrating a typical scheme for outputting a separate reset signal.

[0022] Figure 8 The configuration of the reset section according to an embodiment of the present disclosure is shown.

[0023] Figure 9 This is a timing diagram illustrating the operation of the reset unit according to an embodiment of the present disclosure.

[0024] Figure 10 The configuration of the reset section according to another embodiment of the present disclosure is shown.

[0025] Figure 11 This is a timing diagram illustrating the operation of the reset unit according to another embodiment of the present disclosure. Detailed Implementation

[0026] The advantages and features of this disclosure, as well as methods for implementing them, will become apparent from the accompanying drawings and detailed description of the embodiments. However, it should be understood that this disclosure is not limited to the embodiments described below, but can be implemented in many different forms and includes all variations, equivalents, or substitutions falling within the spirit and technical scope of this disclosure. The embodiments described below are intended to complete this disclosure, and this disclosure is provided to fully inform those skilled in the art of the scope of the invention. In describing this disclosure, detailed descriptions of specific known techniques will be omitted if it is determined that such descriptions might obscure the gist of the disclosure.

[0027] The terminology used in the embodiments is selected as widely used and common as possible; however, these may be changed based on the intent or case of those skilled in the art, the emergence of new technologies, etc. Furthermore, in certain cases, terms may be arbitrarily chosen by the applicant; in such cases, their meanings will be detailed in the corresponding specification. Therefore, the terms used in this specification should be defined according to their meanings and the entirety of this specification, rather than based on their simple names.

[0028] The terminology used in this application is for illustrative purposes only and is not intended to limit this disclosure. Unless the context clearly specifies otherwise, singular expressions include plural expressions. In this application, terms such as "comprising" or "having" should be understood to specify the presence of features, numbers, steps, actions, elements, components, or combinations thereof as described in the specification, without precluding the presence or additional possibilities of one or more other features or numbers, steps, actions, elements, components, or combinations thereof.

[0029] Furthermore, the terms used in the specification, including ordinal numbers such as "first" or "second," may be used to describe various components, but the components should not be limited by these terms. The terms may be used to distinguish one component from another.

[0030] In the following embodiments, "ON" used in conjunction with a component state can refer to the active state of the component, and "OFF" can refer to the inactive state of the component. When used in association with a signal received by the component, "ON" can refer to a signal that activates the component, and "OFF" can refer to a signal that deactivates the component. Components can be activated by high or low voltages. For example, a P-type transistor can be activated by a low voltage. An N-type transistor is activated by a high voltage. Therefore, it should be understood that the "ON" voltages of P-type and N-type transistors are opposite (low to high) voltage levels.

[0031] When an element is referred to as being "connected to" another element, it includes all cases where it is directly connected to the other element or intervenes in the other element. Embodiments of the invention will be described in detail below with reference to the accompanying drawings.

[0032] Figure 1 This is a display device including a plurality of pixel driving circuits according to an embodiment of the present disclosure.

[0033] Reference Figure 1 According to an embodiment of the present disclosure, a display device 100 may include a display panel 110, a scanning drive circuit 120, a data drive circuit 130, and a control unit 140.

[0034] In this disclosure, the display panel 110 may include a plurality of pixels PX. In one embodiment, the plurality of pixels PX may be configured as M*N (M and N are natural numbers) pixels arranged in a matrix, but the arrangement of the plurality of pixels PX may be arranged in various patterns such as a "Z" shape, depending on other embodiments.

[0035] In this disclosure, the display panel 110 can be implemented as one of the following: liquid crystal display (LCD), light emitting diode (LED) display, organic light emitting diode (OLED) display, active-matrix organic light emitting diode (AMOLED) display, electrochromic display (ECD), digital micromirror device (DMD), actuated mirror device (AMD), grating light valve (GLV), plasma display panel (PDP), electroluminescent display (ELD), or vacuum fluorescent display (VFD). Furthermore, it can be implemented as other types of flat panel displays or flexible displays. As an example, this disclosure will illustrate the display panel 110 as an LED display.

[0036] In this disclosure, each of a plurality of pixels PX may include more than one light-emitting element. In one embodiment, the light-emitting element may be a light-emitting diode (LED). The light-emitting diode may be a micro LED having a size of less than 80 μm. In one embodiment, a pixel PX may output multiple colors by using multiple light-emitting elements of different colors. As an example, a pixel PX may include red, green, and blue light-emitting elements. As another example, a pixel PX may also include a white light-emitting element, which may replace any one of the red, green, and blue light-emitting elements. As yet another example, a pixel PX may also consist of a single white light-emitting element. In embodiments where a pixel PX includes multiple light-emitting elements, each light-emitting element included in a pixel PX is referred to as a "subpixel".

[0037] In this disclosure, each pixel PX may include a pixel driving circuit for driving the light-emitting elements (i.e., sub-pixels) included in the pixel. In this disclosure, the pixel driving circuit can drive the sub-pixels to turn on or off using signals output from the scan driving circuit 120 and / or the data driving circuit 130. In one embodiment, the pixel driving circuit may include at least one thin-film transistor and at least one capacitor, etc. In one embodiment, the pixel driving circuit may be implemented using a stacked structure on a semiconductor wafer.

[0038] In this disclosure, the display panel 110 may include one or more scan lines SL1 to SL2 arranged along the row direction. m and one or more data lines DL1 to DL1 arranged along the column direction. n In this disclosure, pixel PX can be located on more than one scan line SL1 to SL2. m With one or more data lines DL1 to DL n At the intersection. Each pixel PX can be connected to any scan line SL. k and any data cable DL k More than one scan line SL1~SL m It can be connected to the scan drive circuit 120, and has more than one data line DL1 to DL2. n It can be connected to the data drive circuit 130.

[0039] In this disclosure, the scan drive circuit 120 can output an output for driving one or more scan lines SL1 to SL2. m The signal of one or more pixels of any scan line (hereinafter referred to as the row signal). Preferably, the scan drive circuit 120 can sequentially select one or more scan lines SL1 to SL2. m For example, pixels connected to the first scan line SL1 can be driven during the first scan drive, and pixels connected to the second scan line SL2 can be driven during the second scan drive. That is, the row signal can correspond to a clock signal used to control the driving of the light-emitting element.

[0040] In this disclosure, the data drive circuit 130 can be driven by one or more data lines DL1 to DL2. n Each pixel outputs a grayscale-related signal (hereinafter referred to as a column signal). That is, the column signal can correspond to the bit value of the image data. A data line is connected to more than one pixel in the vertical direction, but the grayscale-related signal can be input only to pixels connected to the scan line selected by the scan drive circuit 120.

[0041] In this disclosure, the control unit 140 can output control signals to execute the operation of the scan drive circuit 120 and the data drive circuit 130. The control unit 140 can output control signals corresponding to image data equivalent to an image frame to the scan drive circuit 120 or the data drive circuit 130.

[0042] Figure 2 This is a block diagram schematically illustrating the configuration of a pixel driving circuit according to an embodiment of the present disclosure.

[0043] refer to Figure 2 According to one embodiment of this specification, a pixel driving circuit 200 may include a pixel-embedded memory 211 and a driving unit 220. Furthermore, the pixel driving circuit 200 may include: terminals VCC and GND for receiving power; terminals R, G, and B for outputting light-emitting control signals to the light-emitting element; a terminal ROW for receiving row signals output from the scan driving circuit; and a terminal COL for receiving column signals output from the data driving circuit. The electrical connections may be configured to allow power and signals to be input and output through the aforementioned terminals.

[0044] In this disclosure, the memory unit 210 may store data related to driving the light-emitting element. In one embodiment, the memory unit 210 may include a pixel-in-memory memory 211 and a register 212. The pixel-in-memory memory 211 may store data related to driving the light-emitting element (e.g., an LED), that is, it may store video data. Video data refers to data related to the grayscale of light emitted by the light-emitting element within one frame or one PWM cycle. In one embodiment, the pixel-in-memory memory 211 may store data related to charging of a capacitor unit (not shown) included in the driving unit 220.

[0045] In this disclosure, the driving unit 220 can supply power to the light-emitting element based on data stored in the memory unit 210. Specifically, the driving unit 220 can supply power to the light-emitting element based on data stored in the pixel built-in memory 211. In one embodiment, the driving unit 220 can be configured to control the power supply to the light-emitting element according to a PWM driving method, and since the PWM driving method is a technology known to those skilled in the art, its detailed description will be omitted.

[0046] In one embodiment, the biasing unit may provide bias power to the driving unit 220. To provide bias power, the biasing unit may be connected to a terminal VCC for receiving power.

[0047] The pixel driving circuit 200 disclosed herein may further include a power generation unit 230. The power generation unit 230 can output a reference voltage VDD to the memory unit 210 using row signals output from the scan driving circuit and column signals output from the data driving circuit. The configuration and operation of the power generation unit 230 will be described later.

[0048] The pixel driving circuit 200 disclosed herein may include a reset unit 240 for controlling the initialization of the memory unit 210. Specifically, the reset unit 240 may generate a reset signal RSTB and output it to the memory unit 210. The configuration and operation of the reset unit 240 will be described later.

[0049] Figure 3 This is a circuit diagram of an electric power generation unit according to an embodiment of the present disclosure.

[0050] As described above, a pixel driving circuit according to an embodiment of the present disclosure may include a power generation unit. The power generation unit may output a reference voltage to a memory using a row signal output from a scan driving circuit and a column signal output from a data driving circuit. Hereinafter, "memory" may refer to a memory unit or a pixel-embedded memory.

[0051] Reference Figure 3 According to one embodiment of this specification, the power generation unit 300 may include a transistor 310, a NAND gate 320, and a delay element 330. The power generation unit 300 may be connected to the row signal input terminal ROW and the column signal input terminal COL and receive the row signal and column signal. Furthermore, the power generation unit 300 may include a reference voltage output terminal for outputting a reference voltage VDD_INT to a memory.

[0052] Transistor 310 can be configured between the input terminal of the row signal and the output terminal of the reference voltage. According to one embodiment, transistor 310 can be a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET). The drain and source terminals of the PMOSFET can be connected to the input terminal of the row signal and the output terminal of the reference voltage, and the gate terminal of the PMOSFET can be connected to the signal output terminal of a NAND gate. For reference, the PMOSFET is off when the signal input to the gate terminal is logic high ("1"), and on when the signal input to the gate terminal is logic low ("0").

[0053] NAND gate 320 can be configured between the middle terminal (gate terminal) of transistor 310 and the input terminal of the column signal. As a logic circuit element, NAND gate 320 can have two input terminals and one output terminal. The column signal can be input to one of the two input terminals of NAND gate 320, while the delayed row signal is input to the other input terminal. For reference, NAND gate 320 outputs a logic low level only when all inputs are logic high ([1, 1]), and outputs a logic high level in all other cases ([0, 0], [1, 0], [0, 1]).

[0054] The delay element 330 can be configured between the input of the row signal and the NAND gate. The delay element 330 can receive the row signal, delay it for a predetermined time, and output the delayed row signal to any one of the inputs of the NAND gate 320. As an example, the delay time can be 0.5ns to 1ns.

[0055] Figure 4 This is a timing diagram related to the output reference voltage of the power generation unit using row and column signals, based on the specifications in this manual.

[0056] Reference Figure 4 "ROW" indicates that the row signal is input through the row signal input terminal, and "ROW_D" indicates that the row signal is input via a delay element (e.g., Figure 3 The delay element 330) delays the row signal, "COL" indicates the column signal input through the column signal input terminal, and "CTRL" indicates the signal from the NAND gate (e.g., Figure 3 The signal output by the NAND gate 320.

[0057] First, the row signal can transition from logic high to logic low, remain at logic low for a predetermined time, and then transition back to logic high. The column signal can also transition from logic high to logic low, remain at logic low for a predetermined time, and then transition back to logic high. In this case, the column signal can transition from logic high to logic low slightly earlier than the row signal. Furthermore, the column signal can maintain a logic low level for a time difference between when the data to be input into memory is logic low and when it is logic high. When corresponding to logic low data, the column signal can transition from logic low to logic high after the row signal becomes logic high (see reference). Figure 4 (a)). When corresponding to logic high-level data, the column signal can change from logic low to logic high before the row signal changes to logic high (see (a)). Figure 4 (b)

[0058] Based on the timing of the delayed row and column signals, a NAND gate can transition from logic low to logic high and then back to logic low. As described above, a transistor (e.g., Figure 3 The transistor 310 (PMOSFET) can be turned on (On) by a logic low-level signal and turned off (Off) by a logic high-level signal, and then turned on (On) again by a logic low-level signal.

[0059] refer to Figure 4 (c) When the row signal ROW is at a logic high level, the transistor is in the On state, thus the reference voltage VDD_INT can be output to the reference voltage output terminal. Conversely, when the row signal ROW is at a logic low level, the transistor is in the Off state, thus maintaining the reference voltage VDD_INT at the reference voltage output terminal. For this purpose, the power generation unit (e.g., Figure 3 The power generation unit 300 may also include a capacitor disposed between the output terminal of the reference voltage and the circuit ground (e.g., Figure 3 (Capacitor 340). Since the transistor is in the off state, the capacitor can serve to maintain the reference voltage VDD_INT at the output of the reference voltage.

[0060] Figure 5 This is a block diagram schematically illustrating the configuration of a trigger that may be included in a register or pixel-embedded memory for storing input data.

[0061] Reference Figure 5 The column signal can be input to the data signal input terminal D of the flip-flop FF, and the row signal can be input to the clock signal input terminal CLK. (Reference) Figure 4 (a) When the column signal is at a logic low level at the instant the row signal changes from logic low to logic high (rising edge), logic low-level data can be input to the flip-flop FF. Furthermore, refer to... Figure 4 (b) When the column signal is at a logic high level at the instant the row signal changes from logic low to logic high, logic high-level data can be input to the flip-flop FF. That is, in this disclosure, while outputting reference power from the power generation unit through the timing of the row and column signals, capacitor data or video data can be simultaneously input using the same signal. In this disclosure, the memory can be illustrated by an example consisting of multiple flip-flops, but is not limited thereto.

[0062] On the other hand, as described above, the pixel driving circuit of this disclosure may also include a reset unit that outputs a reset signal RSTB for initializing the memory unit to the memory unit.

[0063] Figure 6This is a diagram illustrating the operation of the reset section according to an embodiment of the present disclosure.

[0064] Reference Figure 6 The reset unit 600 may include a data signal input terminal D, a clock signal input terminal CLK, and a signal output terminal Q. In one embodiment, a row signal may be input to the data signal input terminal, and as described above, the row signal, as a clock signal for controlling the driving of the light-emitting element, may correspond to a clock signal for storing data in the memory unit. In one embodiment, a column signal may be input to the clock signal input terminal, and as described above, the column signal, as a data signal related to the grayscale of the light-emitting element stored in the memory unit, may correspond to the bit value of the image data. In this case, the column signal input to the clock signal input terminal, as shown in "COL_B" in the figure, can be input in an inverted state from the column signal output from the data driving circuit. Therefore, the reset unit 600 may also include a signal inverter (not shown) located at the clock signal input terminal for inverting the column signal. In one embodiment, a reset signal RSTB may be output from the signal output terminal.

[0065] In one embodiment, during the data reset interval RESET, the scan drive circuit can output a row signal that remains at a logic low level for a longer period than the reference interval. During the data reset interval RESET, the data drive circuit can output a column signal that transitions from a logic high level to a logic low level while the row signal is at a logic low level. In this disclosure, the memory section can be initialized when the reset signal RSTB is at a logic low level (“0”).

[0066] On the other hand, as mentioned above, the memory section may include pixel-built-in memory and registers. Figure 6 The reset unit 600 shown cannot independently control the initialization of the pixel-built-in memory and registers. The reset unit proposed in this disclosure can output separate reset signals to the pixel-built-in memory and registers respectively. The reset unit for outputting separate reset signals to the pixel-built-in memory and registers will be described below.

[0067] Figure 7 This is a block diagram illustrating a typical scheme for outputting a separate reset signal.

[0068] Reference Figure 7 The pixel driving circuit 700 serves as a component for controlling the initialization of the memory section, and may further include a buffer memory 710 and a power-on reset (POR) circuit 720. For example... Figure 7 As shown, a buffer memory 710 and a power-on reset (POR) circuit are usually required to output separate reset signals to the pixel's built-in memory and registers, respectively.

[0069] However, as Figure 7 As shown, to implement a separate reset signal for each of the pixel's built-in memory and registers, an external hardware pin RSTB is needed to accommodate a single reset signal. Furthermore, the POR 720 is implemented as an analog circuit, thus increasing power consumption. Therefore, Figure 7 The proposed solution may be disadvantageous in terms of circuit size and power consumption.

[0070] Replacement Figure 7 The pixel driving circuit 700 shown below will be described in terms of a scheme of the present disclosure for outputting a separate reset signal while using the signals already in use.

[0071] Figure 8 The configuration of the reset section according to an embodiment of the present disclosure is shown.

[0072] Reference Figure 8 The reset unit 800 may include multiple D flip-flops. Although... Figure 8 The example shown includes three D flip-flops, but the reset section 800 can include any suitable number of D flip-flops.

[0073] In this embodiment, the row signal can be input to the data signal input terminal of the first D flip-flop 810, while the column signal can be input to the clock signal input terminal of the first D flip-flop 810. As described above, the row signal can correspond to the clock signal used to store data in the memory section, while the column signal can correspond to the data signal related to the grayscale of the light-emitting element stored in the memory section.

[0074] In this embodiment, the pixel-in-memory reset signal RSTB_MiP can be output from the signal output terminal of the first D flip-flop 810. The pixel-in-memory reset signal RSTB_MiP is a signal used to control the initialization of the pixel-in-memory included in the memory section. The pixel-in-memory reset signal RSTB_MiP can be output to the pixel-in-memory.

[0075] In this embodiment, the pixel built-in memory reset signal RSTB_MiP output from the signal output terminal of the first D flip-flop 810 can be input to the data signal input terminal of the second D flip-flop 820. The column signal can be input to the clock signal input terminal of the second D flip-flop 820.

[0076] In this embodiment, the temporary signal T1 can be output from the signal output terminal of the second D flip-flop 820.

[0077] In this embodiment, the temporary signal T1 output from the signal output terminal of the second D flip-flop 820 can be input to the data signal input terminal of the third D flip-flop 830. The column signal can be input to the clock signal input terminal of the third D flip-flop 830.

[0078] In this embodiment, the register reset signal RSTB_REG can be output from the signal output terminal of the third D flip-flop 830. The register reset signal RSTB_REG is a signal used to control the initialization of registers included in the memory section. The register reset signal RSTB_REG can be output to the register.

[0079] According to the reset unit 800 of this embodiment, the pixel built-in memory reset signal RSTB_MiP and the register reset signal RSTB_REG can be generated separately by using signals used in existing pixel driving circuits, that is, by using row signals and column signals, without the need for additional hardware pins or analog components.

[0080] In this embodiment, the column signal output from the data driving circuit can be input in an inverted state to the clock signal input of each of the first D flip-flop 810, the second D flip-flop 820, and the third D flip-flop 830. Therefore, the reset unit 800 may also include a signal inverter (not shown) to invert the column signal.

[0081] Figure 9 This is a timing diagram illustrating the operation of the reset unit according to an embodiment of the present disclosure.

[0082] Figure 9 The timing diagram shown is related to... Figure 8 The diagram shows the signals generated by the operation of the reset unit 800.

[0083] exist Figure 9 In this context, the pixel-embedded memory reset signal RSTB_MiP can correspond to... Figure 8 The pixel built-in memory reset signal RSTB_MiP, output by the first D flip-flop 810, and the temporary signal T1 can be corresponding to... Figure 8 The temporary signal T1 is the output of the second D flip-flop 820, and the register reset signal RSTB_REG can correspond to it as... Figure 8 The register reset signal RSTB_REG is the output of the third D flip-flop 830.

[0084] According to this embodiment, the reset unit can generate the pixel built-in memory reset signal and the register reset signal in such a way that the pixel built-in memory reset signal and the register reset signal are kept at a logic low level for the same time period.

[0085] Specifically, in this embodiment, for data reset, the scan drive circuit can output a row signal ROW that remains low for a longer time than the reference interval. When the row signal ROW is low, at the first falling edge 1st of the edge from the logic high level to the logic low level of the column signal COL (hereinafter referred to as the falling edge), the pixel built-in memory reset signal RSTB_MiP can become low.

[0086] In response to the pixel built-in memory reset signal RSTB_MiP going low, the temporary signal T1 can go low at the second falling edge 2nd, which is the next falling edge after the first falling edge 1st of the column signal COL.

[0087] In response to the temporary signal T1 going low, the register reset signal RSTB_REG can go low at the third falling edge (3rd), which is the next falling edge after the second falling edge (2nd) of the column signal COL. That is, compared to the pixel built-in memory reset signal RSTB_MiP, the register reset signal RSTB_REG can go low after the interval between two repeated falling edges of the column signal COL. This can be based on... Figure 8 The result of the configuration of the reset part 800.

[0088] On the other hand, in this embodiment, the row signal ROW can change from a logic low level to a logic high level after a specified time. When the row signal ROW is at a logic high level, at the fourth falling edge 4th, the pixel built-in memory reset signal RSTB_MiP can change to a logic high level, where the fourth falling edge 4th is the next falling edge after the third falling edge 3rd of the column signal COL.

[0089] In response to the pixel built-in memory reset signal RSTB_MiP becoming a logic high level, the temporary signal T1 can become a logic high level at the fifth falling edge 5th, which is the next falling edge after the fourth falling edge 4th of the column signal COL.

[0090] In response to the temporary signal T1 going high, the register reset signal RSTB_REG can go high at the sixth falling edge 6th, which is the next falling edge after the fifth falling edge 5th of the column signal COL.

[0091] In this disclosure, the pixel-in-memory memory and registers can be initialized when both the pixel-in-memory reset signal RSTB_MiP and the register reset signal RSTB_REG are logic low. That is, the pixel-in-memory memory can be initialized during the period when the pixel-in-memory reset signal RSTB_MiP is logic low, i.e., the pixel-in-memory reset (MiP Reset) period. Similarly, the registers can be initialized during the period when the register reset signal RSTB_REG is logic low, i.e., the register reset (Register Reset) period.

[0092] Therefore, the pixel built-in memory reset signal and register reset signal generated by the reset unit according to this embodiment have different starting points (i.e., the time points when the pixel built-in memory and register are initialized respectively) but can remain at a logic low level within the same time period.

[0093] The above is for reference only. Figure 8 and Figure 9 According to an embodiment of the present disclosure, the reset unit can output separate reset signals to the pixel built-in memory and the register, respectively.

[0094] Figure 10 The configuration of the reset section according to another embodiment of the present disclosure is shown.

[0095] Reference Figure 10 The reset unit 1000 may include multiple D flip-flops and logic elements. Although... Figure 10 The example shown includes three D flip-flops, but the reset unit 1000 can include any suitable number of D flip-flops.

[0096] In this embodiment, the row signal can be input to the data signal input terminal of the first D flip-flop 1010, while the column signal can be input to the clock signal input terminal of the first D flip-flop 1010. As described above, the row signal can correspond to the clock signal used to store data in the memory section, while the column signal can correspond to the data signal related to the grayscale of the light-emitting element stored in the memory section.

[0097] In this embodiment, the pixel-in-memory reset signal RSTB_MiP can be output from the signal output terminal of the first D flip-flop 1010. The pixel-in-memory reset signal RSTB_MiP is a signal used to control the initialization of the pixel-in-memory included in the memory section. The pixel-in-memory reset signal RSTB_MiP can be output to the pixel-in-memory.

[0098] In this embodiment, the pixel built-in memory reset signal RSTB_MiP output from the signal output terminal of the first D flip-flop 1010 can be input to the data signal input terminal of the second D flip-flop 1020. The column signal can be input to the clock signal input terminal of the second D flip-flop 1020.

[0099] In this embodiment, the first temporary signal T1 can be output from the signal output terminal of the second D flip-flop 1020.

[0100] In this embodiment, the first temporary signal T1 output from the signal output terminal of the second D flip-flop 1020 can be input to the data signal input terminal of the third D flip-flop 1030. The column signal can be input to the clock signal input terminal of the third D flip-flop 1030.

[0101] In this embodiment, the second temporary signal T2 can be output from the signal output terminal of the third D flip-flop 1030.

[0102] In this embodiment, the pixel built-in memory reset signal RSTB_MiP and the second temporary signal T2 output from the first D flip-flop 1010 can be input to the OR gate 1040.

[0103] OR gate 1040, as a logic circuit element, can have two inputs and one output. When either of the signals input to the two inputs of OR gate 1040 is logic high, OR gate 1040 outputs a logic high signal. That is, in this embodiment, when either the pixel internal memory reset signal RSTB_MiP or the second temporary signal T2 is logic high, OR gate 1040 outputs a logic high signal. Conversely, when both the pixel internal memory reset signal RSTB_MiP and the second temporary signal T2 are logic low, OR gate 1040 outputs a logic low signal.

[0104] In this embodiment, a register reset signal RSTB_REG can be output from the output of OR gate 1040. The register reset signal RSTB_REG is a signal used to control the initialization of registers included in the memory section. The register reset signal RSTB_REG can be output to a register.

[0105] According to the reset unit 1000 of this embodiment, the pixel built-in memory reset signal RSTB_MiP and the register reset signal RSTB_REG can be generated separately by using signals used in existing pixel driving circuits, that is, by using row signals and column signals, without the need for additional hardware pins or analog components.

[0106] In this embodiment, the column signal output from the data driving circuit can be input in an inverted state to the clock signal input terminal of each of the first D flip-flop 1010, the second D flip-flop 1020, and the third D flip-flop 1030. Therefore, the reset unit 1000 may also include a signal inverter (not shown) to invert the column signal.

[0107] Figure 11 This is a timing diagram illustrating the operation of the reset unit according to another embodiment of the present disclosure.

[0108] Figure 11 The timing diagram shown is related to... Figure 10 A diagram showing the signals generated by the operation of the reset unit 1000.

[0109] exist Figure 11 In this context, the pixel-embedded memory reset signal RSTB_MiP can correspond to... Figure 10 The pixel built-in memory reset signal RSTB_MiP,T1 output of the first D flip-flop 1010 can be corresponding to... Figure 10 The first temporary signals T1 and T2 of the output of the second D flip-flop 1020 can correspond to as Figure 10 The second temporary signal T2, output of the third D flip-flop 1030, and the register reset signal RSTB_REG can be corresponding to... Figure 10 The register reset signal RSTB_REG is output by OR gate 1040.

[0110] According to this embodiment, the reset unit can generate the pixel built-in memory reset signal and the register reset signal by simultaneously changing the pixel built-in memory reset signal and the register reset signal from logic low level to logic high level.

[0111] Specifically, in this embodiment, for data reset, the scan drive circuit can output a row signal ROW that remains low for a longer time than the reference interval. When the row signal ROW is low, the pixel built-in memory reset signal RSTB_MiP can become low at the first falling edge 1st of the falling edge of the column signal COL.

[0112] In response to the pixel built-in memory reset signal RSTB_MiP going low, the first temporary signal T1 can go low at the second falling edge 2nd, which is the next falling edge after the first falling edge 1st of the column signal COL.

[0113] In response to the first temporary signal T1 becoming a logic low level, the second temporary signal T2 can become a logic low level at the third falling edge 3rd, which is the next falling edge after the second falling edge 2nd of the column signal COL.

[0114] Reference Figure 10 As described above, when the register reset signal RSTB_REG is the output of the OR gate, and thus the input of the OR gate, i.e., either the pixel internal memory reset signal RSTB_MiP or the second temporary signal T2, is at a logic high level, the register reset signal RSTB_REG is at a logic high level; and when both the pixel internal memory reset signal RSTB_MiP and the second temporary signal T2 are at a logic low level, the register reset signal RSTB_REG is at a logic low level.

[0115] Therefore, in response to the second temporary signal T2 becoming logic low at the third falling edge of the column signal COL, and since the pixel built-in memory reset signal RSTB_MiP is logic low, the register reset signal RSTB_REG becomes logic low.

[0116] On the other hand, in this embodiment, the row signal ROW can change from a logic low level to a logic high level after a specified time. When the row signal ROW is at a logic high level, at the fourth falling edge 4th, the pixel built-in memory reset signal RSTB_MiP can change to a logic high level, where the fourth falling edge 4th is the next falling edge after the third falling edge 3rd of the column signal COL.

[0117] At this point, in response to the pixel built-in memory reset signal RSTB_MiP becoming logic high, the output of the OR gate can also change. That is, at the fourth falling edge, the second temporary signal T2, one of the inputs of the OR gate, is still logic low, but since the pixel built-in memory reset signal RSTB_MiP becomes logic high, the register reset signal RSTB_REG, which is the output of the OR gate, can also become logic high.

[0118] In this disclosure, the pixel-in-memory memory can be initialized in the interval where the pixel-in-memory reset signal RSTB_MiP is at a logic low level, i.e., the pixel-in-memory reset (MiP Reset) interval, and the register can be initialized in the interval where the register reset signal RSTB_REG is at a logic low level, i.e., the register reset (Register Reset) interval.

[0119] As described above, in this embodiment, in response to the pixel built-in memory reset signal RSTB_MiP becoming a logic high level, the register reset signal RSTB_REG becomes a logic high level, which means that the pixel built-in memory initialization release and the register initialization release are performed simultaneously.

[0120] Therefore, the pixel built-in memory reset signal and register reset signal generated by the reset unit according to this embodiment have different starting points (i.e., the time points when the pixel built-in memory and register are initialized respectively) but the pixel built-in memory and register have the same ending point (i.e., the initialization release time point, which is when the pixel built-in memory and register are initialized respectively) and the same initialization release time point (i.e., the time points when the pixel built-in memory and register are initialized respectively).

[0121] The above is for reference only. Figure 10 and Figure 11 According to another embodiment of this disclosure, the reset unit can output separate reset signals to the pixel's built-in memory and the register, and can simultaneously deinitialize.

[0122] The aforementioned scan drive circuit and data drive circuit may include processors, application-specific integrated circuits (ASICs), other chipsets, logic circuits, registers, communication modems, data processing devices, etc., known in the art to which this invention pertains, to execute the various control logics described above. Furthermore, when the control logic is implemented in software, the scan drive circuit and data drive circuit can be implemented through a collection of program modules. In this case, the program modules can be stored in a storage device and executed by the processor.

[0123] The program may include code encoded in computer languages ​​such as C / C++, C#, JAVA, Python, and machine language, which can be read by the computer's processor (CPU) through a computer device interface, allowing the computer to read and execute the methods implemented by the program. Such code may include functional code related to functions that define the necessary functionality for executing methods, and control code related to the executable program required by the computer processor to perform functions according to the prescribed program. Furthermore, this code may also include memory reference-related code regarding the location (address number) of additional information or media required by the computer processor to perform functions in the computer's internal or external memory. Additionally, if the computer processor needs to communicate with any other remote computer or server to perform functions, the code may also include communication-related code regarding how to use the computer's communication module to communicate with any other remote computer or server, and what information or media to send / receive during communication.

[0124] The storage medium for a stored program is not a short-term data storage medium such as registers or cache memory, but rather a medium that stores data semi-permanently and can be read by a device. Specifically, examples of storage media include, but are not limited to, read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disks, and optical data storage devices. That is, the program can be stored on multiple recording media on various servers accessible to the computer, or on multiple recording media on the user's computer. Furthermore, the storage media can be distributed across computer systems connected via a network, and computer-readable code can be stored in a distributed manner.

[0125] Those skilled in the art related to this embodiment will understand that it can be implemented in modified forms without departing from the essential characteristics described above. Therefore, the spirit of the invention should not be limited to the embodiments described above, and all scopes, not only the claims, but also those equivalent to or modified from those claims, fall within the spirit of the invention.

Claims

1. A pixel driving circuit, wherein, include: The memory section includes pixel-in-pixel memory and registers, and is used to store data related to driving the light-emitting elements. The driving unit supplies power to the light-emitting element based on the data stored in the memory unit, and The reset unit is configured to generate a pixel-in-memory reset signal for controlling the initialization of the pixel-in-memory memory and a register reset signal for controlling the initialization of the register, based on the timing of at least one edge occurrence included in a first signal for controlling the driving of the light-emitting element and the timing of at least one edge occurrence included in a second signal related to the grayscale of the light-emitting element.

2. The pixel driving circuit according to claim 1, wherein, The memory unit stores the data by using the first signal as a clock signal. The reset unit generates the pixel built-in memory reset signal and the register reset signal by using the second signal as a clock signal.

3. The pixel driving circuit according to claim 1, wherein, The reset unit generates the pixel built-in memory reset signal and the register reset signal in such a way that the pixel built-in memory reset signal and the register reset signal are kept at a logic low level for the same time period.

4. The pixel driving circuit according to claim 1, wherein, The reset unit generates the pixel built-in memory reset signal and the register reset signal by simultaneously changing the pixel built-in memory reset signal and the register reset signal from logic low level to logic high level.

5. The pixel driving circuit according to claim 2, wherein, The reset unit includes multiple D flip-flops connected in series. The inverted signal of the second signal is input to the clock signal input terminal CLK of each of the plurality of D flip-flops. The first signal is input to the data signal input terminal D of the first D flip-flop among the plurality of D flip-flops. The outputs of adjacent D flip-flops are input to the data signal input terminal D of the D flip-flop that is not at the front of the plurality of D flip-flops.

6. The pixel driving circuit according to claim 5, wherein, The reset unit further includes: The OR gate takes the output of the first D flip-flop and the output of the last D flip-flop as inputs.

7. A display device, wherein, include: The display panel includes an arrangement of multiple pixel driving circuits forming rows and columns. The scan drive circuit sequentially outputs the row signals to the pixel drive circuits arranged along the row direction in the display panel, and... The data driving circuit outputs a column signal related to the driving of the light-emitting element corresponding to each of the plurality of pixel driving circuits to the pixel driving circuits arranged in the column direction in the arrangement in the display panel. Each of the plurality of pixel driving circuits is a pixel driving circuit according to any one of claims 1 to 6.

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