Array substrate row drive circuit

Abstract

The application provides an array substrate row driving circuit, comprising a plurality of cascade light-emitting driving modules, wherein the nth light-emitting driving module comprises a first control unit, a second control unit, a pull-up unit and a pull-down unit; the first control unit is electrically connected with a first reference signal end, a first stage transmission signal output end and a first node; the second control unit is electrically connected with a second stage transmission signal output end, a second reference signal end, the first reference signal end and the first node; the first control unit pulls up the potential of the first node based on the first stage transmission signal; and the second control unit pulls down the potential of the first node based on the second stage transmission signal; thus, the first node is prevented from being in a high-voltage state for a long time, and the problem of poor working stability of the array substrate row driving circuit caused by the first node being in a high-voltage state for a long time is avoided.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to an array substrate row driving circuit. Background Technology

[0002] Gate-driver-on-Array (GOA) technology has become a key development focus for display panel manufacturers due to its advantages in manufacturing cost and functionality. Mid-sized Organic Light Emitting Diode (OLED) display panels require GOAs to meet the threshold voltage compensation function during pixel circuit operation. Figure 1 The 5T1C (5 transistors and 1 capacitor) pixel circuit 200 shown provides a light emission control signal S1, a data signal write control signal S2, a compensation control signal S3, and an initialization control signal S4. For the pixel circuit 200 based on five N-type metal-oxide-semiconductor (NMOS) transistors, this is the light emission circuit of the pixel circuit 200 (the light emission circuit refers to...). Figure 1 The line between the first power supply terminal VDD and the second power supply terminal VSS in Figure 2 The compensation phase t2 shown is disconnected to improve the compensation capability.

[0003] according to Figure 2 It is known that the light emission control signal S1 is a low-level signal during the compensation phase t2, and a high-level signal during the initialization phase t1 and the light emission phase t3. Therefore, the fifteenth transistor T15 is turned off during the compensation phase t2 and turned on during the initialization phase t1 and the light emission phase t3. Since the light emission control signal S1 is a high-level signal for a long time, the GOA that provides the light emission control signal S1 needs to output a high-level light emission control signal S1 to the pixel circuit 200 for a long time. Therefore, the pull-up unit in the GOA configured to provide the light emission control signal S1 to the corresponding pixel row needs to be in the working state for a long time. As a result, the pull-up node electrically connected to the pull-up unit is in a high-voltage state for a long time, which causes the transistor in the pull-up unit to have a threshold voltage negative bias problem, resulting in poor working stability of the GOA. Summary of the Invention

[0004] This application provides an array substrate row driving circuit, which aims to solve the problem of poor working stability of the array substrate row driving circuit due to the pull-up node being in a high voltage state for a long time.

[0005] An array substrate row driving circuit includes cascaded multi-stage light-emitting driving modules, wherein the nth stage light-emitting driving module includes: The first control unit is electrically connected to the first reference signal terminal of the array substrate row driving circuit, the first level signal output terminal of the np-th level light-emitting driving module, and the first node of the n-th level light-emitting driving module. The first control unit is used to output a reference high-level signal from the first reference signal terminal to the first node under the control of the first level signal output terminal. The second control unit is electrically connected to the second-stage signal output terminal, the second reference signal terminal of the array substrate row driving circuit, the first reference signal terminal, and the first node. The second control unit is used to output the first reference low-level signal of the second reference signal terminal to the first node under the control of the second-stage signal output terminal and the reference high-level signal. A pull-up unit is electrically connected to the first node, the first reference signal terminal, and the nth-level light-emitting drive signal output terminal of the nth-level light-emitting drive module. The pull-up unit is used to output the reference high-level signal to the nth-level light-emitting drive signal output terminal based on the potential of the first node. A pull-down unit is electrically connected to the first reference signal terminal, the third reference signal terminal of the array substrate row driving circuit, the nth stage light-emitting driving signal output terminal, the second node of the nth stage light-emitting driving module, and the first stage signal transmission output terminal. The pull-down unit is used to output a second reference low-level signal from the third reference signal terminal to the second node and the nth stage light-emitting driving signal output terminal under the control of the first stage signal transmission and the reference high-level signal. A sustaining unit is electrically connected to the first node, the second node, and the first reference signal terminal. The sustaining unit is used to output the reference high-level signal to the second node based on the potential of the first node. Where n and p are both integers greater than 0, and n is greater than p.

[0006] In the array substrate row driving circuit provided in this application, the sustaining unit includes a second transistor, the gate of the second transistor is electrically connected to the first node, the source of the second transistor is electrically connected to the first reference signal terminal, and the drain of the second transistor is electrically connected to the second node, wherein the second transistor is a P-type transistor.

[0007] In the array substrate row driving circuit provided in this application, the pull-up unit includes a first transistor, the gate of the first transistor is electrically connected to the first node, the source of the first transistor is electrically connected to the first reference signal terminal, and the drain of the first transistor is electrically connected to the nth stage light-emitting driving signal output terminal, wherein the first transistor is a P-type transistor.

[0008] In the array substrate row driving circuit provided in this application, the first control unit includes a third transistor, the gate of the third transistor is electrically connected to the first stage signal output terminal, the source of the third transistor is electrically connected to the first reference signal terminal, and the drain of the third transistor is electrically connected to the first node.

[0009] In the array substrate row driving circuit provided in this application, the second control unit includes a fourth transistor and a fifth transistor; The gate of the fourth transistor is electrically connected to the signal output terminal of the second stage, the source of the fourth transistor is electrically connected to the first reference signal terminal, and the drain of the fourth transistor is electrically connected to the second node. The gate of the fifth transistor is electrically connected to the second node, the source of the fifth transistor is electrically connected to the second reference signal terminal, and the drain of the fifth transistor is electrically connected to the first node.

[0010] In the array substrate row driving circuit provided in this application, the pull-down unit includes a sixth transistor, a seventh transistor, and an eighth transistor; The gate of the sixth transistor is electrically connected to the third node of the nth stage light-emitting driving module, the source of the sixth transistor is electrically connected to the third reference signal terminal, and the drain of the sixth transistor is electrically connected to the nth stage light-emitting driving signal output terminal. The gate of the seventh transistor is electrically connected to the third node, the source of the seventh transistor is electrically connected to the third reference signal terminal, and the drain of the seventh transistor is electrically connected to the second node. The gate of the eighth transistor is electrically connected to the first stage signal output terminal, the source of the eighth transistor is electrically connected to the first reference signal terminal, and the drain of the eighth transistor is electrically connected to the third node.

[0011] In the array substrate row driving circuit provided in this application, the sixth transistor, the seventh transistor, and the eighth transistor are all N-type transistors.

[0012] In the array substrate row driving circuit provided in this application, the nth level light-emitting driving module further includes a first pull-down control unit. The first pull-down control unit is electrically connected to the second node, the third node, and the third reference signal terminal. The first pull-down control unit is used to output the second reference low-level signal to the third node according to the potential of the second node. And / or, the nth level light-emitting driving module further includes a second pull-down control unit, which is electrically connected to the second level signal output terminal, the third node, and the third reference signal. The second pull-down control unit is used to output the second reference low-level signal to the third node according to the second level signal.

[0013] In the array substrate row driving circuit provided in this application, the third reference signal terminal includes a first sub-reference signal terminal and a second sub-reference signal terminal; The source of the sixth transistor is electrically connected to the second sub-reference signal terminal, and the source of the seventh transistor is electrically connected to the first sub-reference signal terminal. The first pull-down control unit is electrically connected to the first sub-reference signal terminal, and / or the second pull-down control unit is electrically connected to the first sub-reference signal terminal; Wherein, the voltage value of the third reference low-level signal provided by the first sub-reference signal terminal is less than the voltage value of the fourth reference low-level signal provided by the second sub-reference signal terminal.

[0014] The array substrate row driving circuit provided in this application, by setting a first control unit electrically connected to the first reference signal terminal, the first stage transmission signal output terminal and the first node, and a second control unit electrically connected to the second stage transmission signal output terminal, the second reference signal terminal, the first reference signal terminal and the first node, the first control unit pulls up the potential of the first node (the first node is the pull-up node) based on the first stage transmission signal and the second control unit pulls down the potential of the first node based on the second stage transmission signal, thereby avoiding the first node being in a high voltage state for a long time, and thus avoiding the problem of poor working stability caused by the first node being in a high voltage state for a long time. Attached Figure Description

[0015] Figure 1 This is a circuit diagram of a 5T1C pixel circuit with compensation function in related technologies; Figure 2 for Figure 1 The driving timing diagram of the pixel circuit is shown. Figure 3 A block diagram of an array substrate row driving circuit provided for an embodiment of this application; Figure 4 for Figure 3The diagram shows a block diagram in which the array substrate row driving circuit is electrically connected to the first-stage signal output terminal and the second-stage signal output terminal, respectively. Figure 5 for Figure 3 The diagram shows a first block diagram of the nth stage light-emitting driving module of the array substrate row driving circuit. Figure 6 for Figure 3 The second block diagram of the nth stage light-emitting driving module of the array substrate row driving circuit is shown. Figure 7 for Figure 6 The diagram shows the first type of circuit for the nth-level light-emitting driver module. Figure 8 for Figure 6 The diagram shows the second type of circuit for the nth-level light-emitting driving module. Figure 9 for Figure 7 as well as Figure 8 The driving timing diagram of the circuit shown is shown. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. The described embodiments are only used to explain the ideas of the present invention and should not be regarded as limiting the scope of protection of this application.

[0017] The transistors used in the embodiments of this application can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Since the source and drain of the transistors are interchangeable, in this embodiment, to distinguish the two terminals of the transistor other than the gate, one terminal is called the source and the other the drain. According to the configuration shown in the accompanying drawings, the middle terminal of the transistor is the gate, the signal input terminal is the source, and the signal output terminal is the drain. Furthermore, the P-type transistors used in the embodiments of this application conduct when the gate is low and are cut off when the gate is high, while the N-type transistors conduct when the gate is high and are cut off when the gate is low.

[0018] like Figure 1 As shown, the pixel circuit 200 with compensation function provided by the related technology includes an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a storage capacitor Cst.

[0019] Among them, the gate of the twelfth transistor T12 is connected to the data writing control signal S2, the source of the twelfth transistor T12 is connected to the data signal Vdata, and the drain of the twelfth transistor T12 is electrically connected to the gate of the eleventh transistor T11.

[0020] The gate of the fifteenth transistor T15 is electrically connected to the light-emitting control signal S1, the source of the fifteenth transistor T15 is electrically connected to the first power supply terminal VDD, and the drain of the fifteenth transistor T15 is electrically connected to the drain of the eleventh transistor T11.

[0021] The eleventh transistor T11 is the driving transistor of the pixel circuit 200. The drain of the eleventh transistor T11 is electrically connected to the drain of the fifteenth transistor T15, and the source of the eleventh transistor T11 is electrically connected to the anode of the light-emitting device L.

[0022] The first plate of the storage capacitor Cst is electrically connected to the gate of the eleventh transistor T11, and the second plate of the storage capacitor Cst is electrically connected to the source of the eleventh transistor T11.

[0023] The gate of the thirteenth transistor T13 is connected to the compensation control signal S3, the source of the thirteenth transistor T13 is connected to the compensation signal Vref, and the drain of the thirteenth transistor T13 is electrically connected to the gate of the eleventh transistor T11.

[0024] The gate of the fourteenth transistor T14 is connected to the reset control signal S4, the source of the fourteenth transistor T14 is connected to the reset signal Vini, and the drain of the fourteenth transistor T14 is electrically connected to the source of the eleventh transistor T11.

[0025] The cathode of the light-emitting device L is also electrically connected to the second power supply terminal VSS. After the potential at the anode of the light-emitting device L rises to the preset potential, the light-emitting device L emits light.

[0026] like Figure 2 as well as Figure 1 As shown, a driving cycle of the pixel circuit 200 sequentially includes a data writing stage t1, a compensation stage t2, and a light emission stage t3.

[0027] During the data writing phase t1, the reset control signal S4 rises from a low level to a high level, the fourteenth transistor T14 turns on, and the fourteenth transistor T14 outputs the reset signal Vini to the source of the eleventh transistor T11 to reset the source of the eleventh transistor T11.

[0028] During the data writing phase t1, the compensation control signal S3 rises from a low level to a high level, turning on the thirteenth transistor T13. The thirteenth transistor T13 then outputs the compensation signal Vref to the gate of the eleventh transistor T11. The voltage values ​​Vr of the compensation signal Vref and Vi of the reset signal Vini must satisfy Vr - Vi > Vth, where Vth is the threshold voltage value of the eleventh transistor T11. After the eleventh transistor T11 turns on, the reset control signal S4 drops to a low level, causing the fourteenth transistor T14 to turn off. During the data writing phase t1, the light emission control signal S1 remains at a high level. The fifteenth transistor T15 is continuously turned on during the data writing phase t1, outputting the first power supply signal VDD from the first power supply terminal to the drain of the eleventh transistor T11. At the same time, since the eleventh transistor T11 is in the on state, it charges the storage capacitor Cst based on the first power supply signal. When the voltage difference between the first and second plates of the storage capacitor Cst is Vth, the eleventh transistor T11 turns off. At this time, the voltage at the source of the eleventh transistor T11 is Vr-Vth.

[0029] During compensation phase t2, the data write control signal S2 rises to a high level, turning on the twelfth transistor T12 and outputting the data signal Vdata to the gate of the eleventh transistor T11. During compensation phase t2, the voltage at the gate of the eleventh transistor T11 is the voltage Vd of the data signal Vdata; at this time, the voltage at the source of the eleventh transistor T11 remains Vr-Vth. During compensation phase t2, the light emission control signal S1 is low, the fifteenth transistor T15 is off, the reset control signal S4 remains low, the fourteenth transistor T14 is off, the compensation control signal S3 remains low, and the thirteenth transistor T13 is off.

[0030] During the light-emitting stage t3, the light-emitting control signal S3 rises to a high level, and the fifteenth transistor T15 turns on. The first power supply signal is output from the fifteenth transistor T15 to the drain of the eleventh transistor T11. The eleventh transistor T11 is in saturation. According to the current characteristics in saturation, the working current I flowing through the eleventh transistor T11 and used to drive the light-emitting device L satisfies formula (1): I=K (Vgs-Vth) 2 =K (Vd-Vr+Vth-Vth) 2 =K (Vd-Vr) 2Where K is a structural parameter, which can be regarded as a constant. It can be seen from formula (1) that the driving current I output by the eleventh transistor T11 is not affected by the threshold voltage Vth, the voltage drop between the first power supply signal terminal VDD and the second power supply signal terminal VSS, but is related to the voltage value Vd of the data signal Vdta and the voltage value Vr of the compensation signal Vref, so that the pixel circuit 200 realizes the threshold voltage compensation of the eleventh transistor T11.

[0031] In related technologies, the GOA required for medium-sized OLED display panels is to meet the following requirements: Figure 1 The threshold voltage compensation function of the pixel circuit 200 shown requires GOA to... Figure 1 The pixel circuit 200 shown provides an initialization control signal S4 to the gate of the fourteenth transistor T14, a compensation control signal S3 to the gate of the thirteenth transistor T13, a data signal write control signal S3 to the gate of the twelfth transistor T12, and a light emission control signal S1 to the gate of the fifteenth transistor T15.

[0032] When the eleventh transistor T11, twelfth transistor T12, thirteenth transistor T13, fourteenth transistor T14, and fifteenth transistor T15 are in operation, in order to control the light-emitting circuit in the pixel circuit 200 to disconnect during the compensation phase t2 to improve the compensation capability of the pixel circuit 200, the gate of the fifteenth transistor T15 needs to receive a high-level light-emitting control signal S1 during the data writing phase t1 and the light-emitting phase t3 to turn the fifteenth transistor T15 on. Conversely, the gate of the fifteenth transistor T15 needs to receive a low-level light-emitting control signal S1 during the compensation phase t2 to turn the fifteenth transistor T15 off. Therefore, the display panel needs to have an independent GOA to provide the required light-emitting control signal S1 separately for the pixel circuit 200 of each row of pixel units.

[0033] Based on this, embodiments of this application propose an array substrate row driving circuit to drive, for example... Figure 1 The gate of the fifteenth transistor T15 in the pixel circuit 200 shown provides, as Figure 2 The light emission control signal S1 shown is used to improve the working stability of the array substrate row driving circuit.

[0034] like Figure 3 As shown, the array substrate row driving circuit 1000 provided in the embodiments of this application includes cascaded multi-level light-emitting driving modules 100. Each level of light-emitting driving module 100 is electrically connected to the first reference signal terminal VGH, the second reference signal terminal GND, and the third reference signal terminal VGL of the array substrate row driving circuit 1000. Furthermore, one light-emitting driving signal output terminal of each level of light-emitting driving module 100 is connected to a row of pixel units as shown in the diagram. Figure 1The gate electrical connection of the fifteenth transistor T15 is shown.

[0035] For example, the np-th level light-emitting drive signal output terminal En(np) of the np-th level light-emitting drive module 100 is electrically connected to the gate of the fifteenth transistor T15 of the pixel circuit 200 of the np-th row pixel unit, the n-th level light-emitting drive signal output terminal En(n) of the n-th level light-emitting drive module 100 is electrically connected to the gate of the fifteenth transistor T15 of the pixel circuit 200 of the n-th row pixel unit, and the n+p-th level light-emitting drive signal terminal En(n+p) of the n+p-th level light-emitting drive module 100 is electrically connected to the gate of the fifteenth transistor T15 of the pixel circuit 200 of the n+p-th row pixel unit.

[0036] like Figure 3 As shown, each stage of the light-emitting driving module 100 is also electrically connected to the corresponding first-stage signal output terminal and the second-stage signal output terminal. For example, the nth stage light-emitting driving module 100 is electrically connected to the corresponding first-stage signal output terminal Count(np) and the second-stage signal output terminal Count(n+p), the npth stage light-emitting driving module 100 is electrically connected to the corresponding first-stage signal output terminal Count(n-2p) and the second-stage signal output terminal Count(n), and the n+pth stage light-emitting driving module 100 is electrically connected to the corresponding first-stage signal output terminal Count(n) and the second-stage signal output terminal Count(n+2p).

[0037] It should be noted that in this embodiment, the first-level signal output terminals of any two adjacent and cascaded light-emitting driving modules 100 are different, and the second-level signal output terminals of any two adjacent and cascaded light-emitting driving modules 100 are different.

[0038] Specifically, such as Figure 4 As shown, the first-stage signal output terminal and the second-stage signal output terminal, which are electrically connected to each stage light-emitting driving module 100 of the array substrate row driving circuit 1000, are the stage signal output terminals of the corresponding stage gate driving module 300 of another conventional array substrate row driving circuit 3000.

[0039] The conventional array substrate row driving circuit 3000 includes cascaded multi-stage gate driving modules 300, and each stage gate driving module 300 is electrically connected to the first control signal terminal VGH2, the second control signal terminal VSS, the first clock signal terminal CKa, and the second clock signal terminal CKb, respectively.

[0040] Each gate drive module 300 outputs a stage transmission signal according to the first clock signal of the first clock signal terminal CKa, and outputs a gate drive signal according to the second clock signal of the second clock signal terminal CKb.

[0041] The second clock signal terminal CKb may include multiple second sub-clock signal terminals CKb_1, CKb_2, and CKb_3, so that each gate driving module 300 outputs a compensation control signal to the first gate signal output terminal, a data write control signal to the second gate signal output terminal, and a reset control signal to the third gate signal output terminal of each gate driving module 300 according to the second sub-clock signals provided by the multiple second sub-clock signal terminals CKb_1, CKb_2, and CKb_3.

[0042] For example, such as Figure 1 as well as Figure 4 As shown, the first gate signal output terminal REF(n) of the nth-level gate driving module 300 outputs a compensation control signal S3 to the gate of the thirteenth transistor T13 of the nth row pixel unit; the second gate signal output terminal Gn(n) of the nth-level gate driving module 300 outputs a data write control signal S2 to the gate of the twelfth transistor T12 of the nth row pixel unit; and the third gate signal output terminal INI(n) of the nth-level gate driving module 300 outputs a reset control signal S4 to the fourteenth transistor T14 of the nth row pixel unit.

[0043] Furthermore, the stage transmission signal output terminal Count(n) of the nth stage gate driver module 300 is electrically connected to the npth stage gate driver module 300, the (n+p)th stage gate driver module 300, the npth stage light-emitting driver module 100, and the (n+p)th stage light-emitting driver module 100, respectively. Therefore, the second stage transmission signal output terminal electrically connected to the npth stage light-emitting driver module 100 is the stage transmission signal output terminal Count(n) of the nth stage gate driver module 300, and the first stage transmission signal output terminal electrically connected to the (n+p)th stage light-emitting driver module 100 is the stage transmission signal output terminal Count(n) of the nth stage gate driver module 300.

[0044] Similarly, the first-level signal output terminal electrically connected to the nth-level light-emitting driving module 100 is the stage signal output terminal Count(np) of the np-level gate driving module 300, and the second-level signal output terminal electrically connected to the nth-level light-emitting driving module 100 is the stage signal output terminal Count(n+p) of the n+p-level gate driving module 300.

[0045] like Figure 5 As shown, the nth-level light-emitting driving module 100 includes a first control unit 10, a second control unit 20, a pull-up unit 30, and a pull-down unit 40.

[0046] The first control unit 10 is electrically connected to the first reference signal terminal VGH of the array substrate row driving circuit 1000, the first stage signal output terminal Count(np), and the first node Q1(n) of the nth stage light-emitting driving module 100. n and p are both integers greater than 0, and n is greater than p. The first node Q1(n) is the node of the line between the first control unit 10 and the pull-up unit 30. In this embodiment, the first stage signal output terminal Count(np), electrically connected to the nth stage light-emitting control module 100, is the stage signal output terminal of the npth stage gate driving module 300.

[0047] In the array substrate row driving circuit 1000, a start signal can be set to replace the stage transmission signal of the pn-th stage in the first-stage light-emitting driving module 100 to the p-th stage gate module; similarly, a start signal or another signal can be set to replace the stage transmission signal of the p+n-th stage light-emitting driving module 100 in the last-stage light-emitting driving module 100 to the p-th-last stage light-emitting driving module 100. Apart from the above differences, the circuit structure and signal connections of the first p-th stage light-emitting driving module 100 and the last p-th stage light-emitting driving module 100 are the same as those of the other stage light-emitting driving modules 100.

[0048] The first control unit 10 is used to output the reference high-level signal provided by the first reference signal terminal VGH to the first node Q1(n) under the control of the first-stage transmission signal provided by the first-stage transmission signal output terminal Count(np), and pull up the potential of the first node Q1(n).

[0049] The second control unit 20 is electrically connected to the second-level signal output terminal Count(n+p) of the n+p-th level light-emitting driving module 100, the second reference signal terminal GND of the array substrate row driving circuit 1000, the first reference signal terminal VGH and the first node Q1(n).

[0050] The second control unit 20, under the control of the second-stage transmission signal provided by the second-stage transmission signal output terminal Count(n+p) and the reference high-level signal provided by the first reference signal terminal VGH, outputs the first reference low-level signal provided by the second reference signal terminal GND to the first node Q1(n), thereby pulling down the potential of the first node Q1(n). In this embodiment, the second-stage transmission signal terminal Count(n+p), which is electrically connected to the nth-stage light-emitting control module 100, is the stage transmission signal output terminal of the (n+p)th-stage gate driving module 300.

[0051] The pull-up unit 30 is electrically connected to the first node Q1(n), the first reference signal terminal VGH, and the nth stage light-emitting drive signal output terminal En(n) of the nth stage light-emitting drive module 100.

[0052] The pull-up unit 30 is used to output the reference high-level signal provided by the first reference signal terminal VGH to the nth stage light-emitting drive signal output terminal En(n) based on the potential of the first node Q1(n), thereby pulling up the potential of the nth stage light-emitting drive signal output terminal En(n). Thus, when the pull-up unit 30 is turned on, the light-emitting control signal output by the nth stage light-emitting drive signal output terminal En(n) is a reference high-level signal.

[0053] The pull-down unit 40 is electrically connected to the first reference signal terminal VGH, the third reference signal terminal VGL of the array substrate row driving circuit 1000, the nth stage light-emitting driving signal output terminal En(n), the second node Q2(n) of the nth stage light-emitting driving module 100, and the first stage signal output terminal Count(np). The second node Q2(n) is the node of the line between the second control unit 20 and the pull-down unit 40.

[0054] The pull-down unit 40, under the control of the first-stage transmission signal provided by the first-stage transmission signal output terminal Count(np) and the reference high-level signal provided by the first reference signal terminal VGH, outputs the second constant low-voltage signal provided by the third reference signal terminal VGL to the second node Q2(n) and the nth-stage light-emitting drive signal output terminal En(n), thereby pulling down the potential of the second node Q2(n) and the potential of the nth-stage light-emitting drive signal output terminal En(n). When the pull-down unit 40 is turned on, the potential of the second node Q2(n) is pulled down to the potential of the third reference signal terminal VGL, and the second control unit 20 is not working. When the pull-down unit 40 is turned on, the light-emitting control signal output by the nth-stage light-emitting drive signal output terminal En(n) is the second reference low-level signal.

[0055] In this embodiment, the first control unit 10 is electrically connected to the first-stage signal output terminal Count(np), and the second control unit 20 is electrically connected to the second-stage signal output terminal Count(n+p). The first control unit 10 pulls up the potential of the first node Q1(n) based on the first-stage signal output terminal Count(np), and the second control unit 20 pulls down the potential of the first node Q1(n) based on the second-stage signal output terminal Count(n+p). This avoids the first node Q1(n) being in a high-voltage state for a long time, thereby avoiding the problem of poor working stability of the array substrate row driving circuit 1000 due to the first node Q1(n) being in a high-voltage state for a long time.

[0056] Meanwhile, in this embodiment, the pulse width of the light-emitting control signal provided by the nth light-emitting drive signal output terminal En(n), which is a low-level signal, is also controlled based on the waveform of the first-level signal output terminal Count(np) and the waveform of the second-level signal output terminal Count(n+p).

[0057] like Figure 6 As shown, in some embodiments provided in this application, compared to Figure 5 , Figure 6 The nth-level light-emitting driving module 100 shown also includes a sustaining unit 50. The sustaining unit 50 is electrically connected to the first node Q1(n), the second node Q2(n), and the first reference signal terminal VGH. The sustaining unit 50 is used to output a reference high-level signal of the first reference signal terminal VGH to the second node Q2(n) based on the potential of the first node Q1(n).

[0058] When the sustaining unit 50 operates according to the potential of the first node Q1(n), it outputs a reference high-level signal to the second node Q2(n) to maintain the potential of the second node Q2(n) at a high level.

[0059] Specifically, when the second control unit 20 outputs a first reference low-level signal provided by the second reference signal terminal GND to the first node Q1(n) based on the high potential of the second node Q2(n), the low potential of the first node Q1(n) is maintained. While the potential of the first node Q1(n) remains low, if the pull-up unit 30 is in an operating state based on the low first potential, the pull-up unit 30 continuously outputs a reference high-level signal to the nth stage light-emitting drive signal output terminal En(n), ensuring that the light-emitting control signal remains a reference high-level signal.

[0060] When the second control unit 20 stops working due to the high potential of the second node Q2(n), the potential of the first node Q1(n) is maintained at a different potential than that of the second reference signal terminal GND.

[0061] like Figure 7 As shown, in some embodiments provided in this application, the pull-up unit 30 includes a first transistor T1. The gate of the first transistor T1 is electrically connected to the first node Q1(n), the source of the first transistor T1 is electrically connected to the first reference signal terminal VGH, and the drain of the first transistor T1 is electrically connected to the nth stage light-emitting drive signal output terminal En(n). The first transistor T1 is a P-type transistor.

[0062] Since the first transistor T1 is a P-type transistor, the first transistor T1 is turned on when its gate is at a low level. That is, when the second control unit 20 is working, the first transistor T1 is turned on according to the low potential of the first node Q1(n). Thus, the first transistor T1 outputs a reference high-level signal to the nth stage light-emitting drive signal output terminal En(n), so that the light-emitting control signal output by the nth stage light-emitting drive signal output terminal En(n) is a reference high-level signal during the operation of the second control unit 20.

[0063] Since the first transistor T1 is a P-type transistor, the first transistor T1 is cut off when the gate is at a high level. That is, when the first control unit 10 is working, the first transistor T1 is turned off according to the high potential of the first node Q1(n), so the first transistor T1 does not work. This ensures that during the operation of the first control unit 10, the light-emitting control signal output by the nth stage light-emitting drive signal output terminal En(n) is not a reference high-level signal.

[0064] Combination Figure 1 and Figure 2 It is known that the light emission control signal S1 only needs to be a low-level signal during the compensation phase t2 of the pixel circuit 200. That is, the first transistor T1 of the nth-level light emission driving module 100 needs to be in a conducting state for a long time to output a reference high-level signal to the nth-level light emission driving signal output terminal En(n). Since the first transistor T1 is a P-type transistor, which has high mobility, its ability to prevent threshold voltage negative drift is improved. Therefore, the nth-level light emission driving module does not need to add a transistor with leakage protection function to improve the first transistor T1's ability to prevent threshold voltage negative bias. The configuration based on the first transistor T1 saves the need for a transistor with leakage protection function, thus reducing the display panel space occupied by the array substrate row driving circuit.

[0065] Furthermore, since the first transistor T1 is a P-type transistor, the gate of the first transistor T1 does not need to be in a high voltage state, that is, the first node Q1(n) does not need to be in a high voltage state, so the first transistor T1 can be turned on and output a light-emitting control signal as a reference high-level signal to the nth stage light-emitting drive signal output terminal En(n).

[0066] like Figure 7 As shown, in some embodiments provided in this application, the sustaining unit 50 includes a second transistor T2. The gate of the second transistor T2 is electrically connected to the first node Q1(n), the source of the second transistor T2 is electrically connected to the first reference signal terminal VGH, the drain of the second transistor T2 is electrically connected to the second node Q2(n), and the second transistor T2 is a P-type transistor.

[0067] Since the second transistor T2 is a P-type transistor, it is in a conducting state when the potential of the first node Q1(n) is low, thereby outputting a reference high-level signal to the second node Q2(n) to maintain the potential of the second node Q2(n) at a high level. As long as the second control unit 20 outputs the first reference low-level signal to the first node Q1(n) based on the high potential of the second node Q2(n), it can achieve the following: maintaining the second transistor T2 in a conducting state while keeping the potential of the first node Q1(n) low; maintaining the second transistor T2 in a conducting state while keeping the potential of the second node Q2(n) high; and maintaining the potential of the second node Q2(n) at a high level while keeping the potential of the first node Q1(n) low. In this way, the potential of the first node Q1(n) and the potential of the second node Q2(n) can be mutually preserved through the second control unit 20 and the maintenance unit 50. The first transistor T1 can be kept in working state without adding a capacitor in the pull-up unit 30. As a result, the array substrate of the display panel can save the design of a large area of ​​capacitor plate and realize a narrower bezel of the display panel.

[0068] In some embodiments provided in this application, such as Figure 7 As shown, the first control unit 10 includes a third transistor T3. The gate of the third transistor T3 is electrically connected to the first stage signal output terminal Count(np), the source of the third transistor T3 is electrically connected to the first reference signal terminal VGH, and the drain of the third transistor T3 is electrically connected to the first node Q1(n).

[0069] The on / off state of the third transistor T3 depends on whether the first-stage transmission signal is a high-level signal or a low-level signal. Since the third transistor T3 is an N-type transistor, it turns on when its gate receives a high-level first-stage transmission signal and turns off when its gate receives a low-level first-stage transmission signal.

[0070] In some embodiments provided in this application, such as Figure 7 As shown, the second control unit 20 includes a fourth transistor T4 and a fifth transistor T5.

[0071] The gate of the fourth transistor T4 is electrically connected to the second-stage signal output terminal Count(n+p), the source of the fourth transistor T4 is electrically connected to the first reference signal terminal VGH, and the drain of the fourth transistor T4 is electrically connected to the second node Q2(n). When the fourth transistor T4 is turned on according to the second-stage signal, it outputs a reference high-level signal to the second node Q2(n), pulling up the potential of the second node Q2(n).

[0072] The gate of the fifth transistor T5 is electrically connected to the second node Q2(n), the source of the fifth transistor T5 is electrically connected to the second reference signal terminal GND, and the drain of the fifth transistor T5 is electrically connected to the first node Q1(n). When the fifth transistor T5 is in the on state according to the potential of the second node Q2(n), it outputs the first reference low-level signal to the first node Q1(n), thus pulling down the potential of the first node Q1(n).

[0073] The fourth transistor T4 and the fifth transistor T5 can both be N-type transistors. When the fourth transistor T4 is turned on based on the second stage transmission signal of the high electrical signal, the fifth transistor T5 is also turned on accordingly, thereby pulling down the potential of the first node Q1(n).

[0074] In some embodiments provided in this application, such as Figure 7 As shown, the pull-down unit 40 includes a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0075] The gate of the sixth transistor T6 is electrically connected to the third node Q3(n) of the nth stage light-emitting driving module 100, the source of the sixth transistor T6 is electrically connected to the third reference signal terminal VGL, and the drain of the sixth transistor T6 is electrically connected to the signal output terminal En(n). When the sixth transistor T6 is turned on based on the potential of the third node Q3(n), it outputs the second reference low-level signal provided by the third reference signal terminal VGL to the second node Q2(n), thus pulling down the potential of the second node Q2(n).

[0076] The gate of the seventh transistor T7 is electrically connected to the third node Q3(n) of the nth-stage light-emitting drive module 100, the source of the seventh transistor T7 is electrically connected to the third reference signal terminal VGL, and the drain of the seventh transistor T7 is electrically connected to the second node Q2(n). When the seventh transistor T7 is turned on based on the potential of the third node Q3(n), it outputs the second reference low-level signal provided by the third reference signal terminal VGL to the nth-stage light-emitting drive signal output terminal En(n), pulling down the potential of the nth-stage light-emitting drive signal output terminal En(n), so that the light-emitting control signal output by the nth-stage light-emitting drive signal output terminal En(n) is the second reference low-level signal. The third node Q3(n) is the node of the line between the gate of the sixth transistor T6 and the gate of the seventh transistor T7 in the pull-down unit 40.

[0077] The gate of the eighth transistor T8 is electrically connected to the first-stage signal output terminal Count(np), the source of the eighth transistor T8 is electrically connected to the first reference signal terminal VGH, and the drain of the eighth transistor T8 is electrically connected to the third node Q3(n). The eighth transistor T8 is in the conducting state according to the first-stage signal, outputting the reference high-level signal of the first reference signal terminal VGH to the third node Q3(n), thus pulling up the potential of the third node Q3(n).

[0078] In some embodiments provided in this application, the sixth transistor T6 and the seventh transistor T7 are both N-type transistors or both P-type transistors, so that the sixth transistor T6 and the seventh transistor T7 can be in the on state or in the off state at the same time.

[0079] In some embodiments provided in this application, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the third transistor T3 are all N-type transistors. Since the third transistor T3 and the eighth transistor T8 are both N-type transistors, when the first-stage transmission signal is a high-level signal, both the third transistor T3 and the eighth transistor T8 are turned on, and the potentials of the first node Q1(n) and the third node Q3(n) are both raised. Simultaneously, since the sixth transistor T6 and the seventh transistor T7 are both N-type transistors, they are both turned on, thereby pulling down the potential of the second node Q2(n) and the potential of the nth-stage light-emitting drive signal output terminal En(n). If the second control unit 20 stops outputting the first reference low-level signal to the first node Q1(n) based on the low potential of the second node Q2(n), then while the first control unit 10 pulls up the potential of the first node Q1(n), it can prevent the second control unit 20 from mistakenly turning on and pulling down the potential of the first node Q1(n).

[0080] In the embodiments provided in this application, such as Figure 8 As shown, the voltage value of the first reference low-level signal provided by the second reference signal terminal GND is less than the voltage value of the reference high-level signal provided by the first reference signal terminal VGH, so that the first node Q1(n) is not in a high-voltage state for a long period of time. Furthermore, since both the first transistor T1 and the second transistor T2 are P-type crystals, even if the first node Q1(n) is not in a high-voltage state, the potential of the first node Q1(n) can still ensure that the nth-stage light-emitting driver module 100 stably outputs a constant-voltage high-level signal, and can also reduce the power consumption of the nth-stage light-emitting driver module 100.

[0081] In some embodiments provided in this application, such as Figure 8 As shown, compared to Figure 7 , Figure 8The nth-level light-emitting driver module 100 also includes a first pull-down control unit 60. The first pull-down control unit 60 is electrically connected to the second node Q2(n), the third node Q3(n), and the third reference signal terminal VGL. The first pull-down control unit 60 is used to output a second reference low-level signal to the third node Q3(n) according to the potential of the second node Q2(n).

[0082] Furthermore, in some embodiments provided in this application, the first pull-down control unit 60 includes a ninth transistor T9. The gate of the ninth transistor T9 is electrically connected to the second node Q2(n), the source of the ninth transistor T9 is electrically connected to the third reference signal terminal VGL, and the drain of the ninth transistor T9 is electrically connected to the third node Q3(n).

[0083] When the ninth transistor T9 is in the on state based on the potential of the second node Q2(n), it outputs the second reference low-level signal provided by the third reference signal terminal VGL to the third node Q3(n), thereby pulling down the potential of the third node Q3(n), that is, pulling down the potential of the gate of the sixth transistor T6 and the potential of the gate of the seventh transistor T7.

[0084] In some embodiments provided in this application, such as Figure 8 As shown, compared to Figure 7 , Figure 8 The nth-level light-emitting driver module 100 shown also includes a second pull-down control unit 70. The second pull-down control unit 70 is electrically connected to the second-level signal output terminal Count(n+p), the third node Q3(n), and the third reference signal terminal VGL. The second pull-down control unit 70 is used to output a second reference low-level signal to the third node Q3(n) according to the second-level signal output terminal Count(n+p).

[0085] Furthermore, in some embodiments provided in this application, the second pull-down control unit 70 includes a tenth transistor T10. The gate of the tenth transistor T10 is electrically connected to the second-stage signal output terminal Count(n+p), the source of the tenth transistor T10 is electrically connected to the third reference signal terminal VGL, and the drain of the tenth transistor T10 is electrically connected to the third node Q3(n).

[0086] When the tenth transistor T10 is in the conducting state based on the second stage transmission signal, it outputs the second reference low-level signal provided by the third reference signal terminal VGL to the third node Q3(n), thereby pulling down the potential of the third node Q3(n).

[0087] In some embodiments provided in this application, such as Figure 8 As shown, compared to Figure 7 , Figure 8The nth-level light-emitting driving module 100 also includes a first pull-down control unit 60 and a second pull-down control unit 70. The first pull-down control unit 60 includes a ninth transistor T9, and the second pull-down control unit 70 includes a tenth transistor T10.

[0088] When both the fourth transistor T4 and the tenth transistor T10 are N-type transistors or both are P-type transistors, the fourth transistor T4 and the tenth transistor T10 are turned on based on the second stage signal transmission. The fourth transistor T4 pulls up the potential of the second node Q2(n), and the tenth transistor T10 pulls down the potential of the third node Q3(n).

[0089] Meanwhile, when the sixth transistor T6 is an N-type transistor, the sixth transistor T6 is turned off based on the low potential of the third node Q3(n), avoiding the fourth transistor T4 from pulling up the potential of the second node Q2(n). At the same time, the sixth transistor T6 is mis-turned on and pulls down the potential of the second node Q2(n).

[0090] Meanwhile, when the fifth transistor T5 is an N-type transistor, it is turned on based on the high potential of the second node Q2(n). The fifth transistor T5 pulls down the potential of the first node Q1(n), turning on the first transistor T1, which is a P-type transistor. Thus, the light-emitting control signal of the nth stage light-emitting drive signal output terminal En(n) is a reference high-level signal. At this time, when the seventh transistor T7 is an N-type transistor, it is turned off based on the low potential of the third node Q3(n). This prevents the first transistor T1 from pulling up the potential of the nth stage light-emitting drive signal output terminal En(n). At the same time, the seventh transistor T7 is mis-turned on and pulls down the potential of the nth stage light-emitting drive signal output terminal En(n).

[0091] It is important to note that, such as Figure 8 As shown, the third reference signal terminal VGL includes a first sub-reference signal terminal VGL1 and a second sub-reference signal terminal VGL2. The source of the ninth transistor T9 is electrically connected to the first sub-reference signal terminal VGL1. The source of the fifth transistor T5 is electrically connected to the second sub-reference signal terminal VGL2. Furthermore, the voltage value of the third reference low-level signal provided by the first sub-reference signal terminal VGL1 is less than the voltage value of the fourth reference low-level signal provided by the second sub-reference signal terminal VGL2. Therefore, based on the potential of the third node Q3(n), the voltage difference between the gate and source of the seventh transistor T7 is less than 0 volts, and the seventh transistor T7 is turned off more completely.

[0092] Similarly, such as Figure 8As shown, the source first reference signal terminal VGH of the tenth transistor T10 is electrically connected, so based on the potential of the third node Q3(n), the voltage difference between the gate and source of the seventh transistor T7 is less than 0 volts, and the seventh transistor T7 is turned off more completely.

[0093] Similarly, such as Figure 7 As shown, the voltage value of the second reference low-level signal provided by the third reference signal terminal VGL is less than the voltage value of the first reference low-level signal provided by the second reference signal terminal GND. Therefore, when the sixth transistor T6 pulls down the potential of the second node Q2(n) to the potential of the third reference signal terminal VGL, the voltage difference between the gate and source of the fifth transistor T5 is less than 0 volts, and the fifth transistor T5 is turned off more completely.

[0094] like Figure 9 As shown below, in conjunction with Figure 8 and Figure 9 This section describes the driving timing of the nth-level light-emitting driver module 100. For ease of explanation, the following uses... Figure 8 The first transistor T1 and the second transistor T2 shown are P-type transistors, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are N-type transistors.

[0095] In the first stage M1, since the first-stage transmission signal is a high-level signal, the third transistor T3 and the eighth transistor T8 are turned on. The third transistor T3 provides a reference high-level signal to the first node Q1(n), pulling up the potential of the first node Q1(n). The first transistor T1 and the second transistor T2 are both turned off. At the same time, the eighth transistor T8 provides a reference high-level signal to the third node Q3(n), pulling up the potential of the third node Q3(n), and the sixth transistor T6 and the seventh transistor T7 are turned on. The sixth transistor T6 outputs a third reference low-level signal to the second node Q2(n), pulling down the potential of the second node Q2(n), and the fifth transistor T5 is turned off based on the low potential of the second node Q2(n). The seventh transistor T7 outputs a fourth constant low-level voltage to the nth-stage light-emitting drive signal output terminal En(n). In this stage, the light-emitting control signal output from the nth-stage light-emitting drive signal output terminal En(n) is the fourth reference low-level signal.

[0096] In the second stage M2, since the first-stage transmission signal is a low-level signal, both the third transistor T3 and the eighth transistor T8 are turned off. And since the second-stage transmission signal is a high-level signal, the fourth transistor T4 and the tenth transistor T10 are turned on. The fourth transistor T4 provides a reference high-level signal to the second node Q2(n), pulling up the potential of the second node Q2(n). The fifth transistor T5 is turned on based on the high potential of the second node Q2(n), and outputs the first reference low-level signal to the first node Q1(n), pulling down the potential of the first node Q1(n). Thus, the first transistor T1 and the second transistor T2 are turned on based on the low potential of the first node Q1(n). The first transistor T1 outputs a reference high-level signal to the nth-stage light-emitting drive signal output terminal En(n), so in this stage, the light-emitting control signal output from the nth-stage light-emitting drive signal output terminal En(n) is a reference high-level signal. The tenth transistor T10 outputs the third reference low-level signal to the third node Q3(n), pulling down the potential of the third node Q3(n). Simultaneously, the sixth transistor T6 and the seventh transistor T7 are both turned off. Meanwhile, since the potential of the second node Q2(n) is high, the ninth transistor T9 is turned on, outputting the third reference low-level signal to the third node Q3(n). This keeps the potential of the third node Q3(n) low while the potential of the second node Q2(n) remains high.

[0097] Of course, this application may have other various embodiments. Without departing from the spirit and essential points of this application, those skilled in the art can make various corresponding changes and modifications based on this application, but these corresponding changes and modifications should all fall within the protection scope of the appended claims.

Claims

1. A row driving circuit for an array substrate, characterized in that, This includes cascaded multi-stage light-emitting driver modules, where the nth stage light-emitting driver module includes: The first control unit is electrically connected to the first reference signal terminal, the first level signal output terminal, and the first node of the nth level light-emitting driving module of the array substrate row driving circuit. The first control unit is used to output the reference high-level signal of the first reference signal terminal to the first node under the control of the first level signal output terminal. The second control unit is electrically connected to the second-stage signal output terminal, the second reference signal terminal of the array substrate row driving circuit, the first reference signal terminal, and the first node. The second control unit is used to output the first reference low-level signal of the second reference signal terminal to the first node under the control of the second-stage signal output terminal and the reference high-level signal. A pull-up unit is electrically connected to the first node, the first reference signal terminal, and the nth-level light-emitting drive signal output terminal of the nth-level light-emitting drive module. The pull-up unit is used to output the reference high-level signal to the nth-level light-emitting drive signal output terminal based on the potential of the first node. A pull-down unit is electrically connected to the first reference signal terminal, the third reference signal terminal of the array substrate row driving circuit, the nth stage light-emitting driving signal output terminal, the second node of the nth stage light-emitting driving module, and the first stage signal transmission output terminal. The pull-down unit is used to output a second reference low-level signal from the third reference signal terminal to the second node and the nth stage light-emitting driving signal output terminal under the control of the first stage signal transmission and the reference high-level signal. A sustaining unit is electrically connected to the first node, the second node, and the first reference signal terminal. The sustaining unit is used to output the reference high-level signal to the second node based on the potential of the first node. Where n and p are both integers greater than 0, and n is greater than p.

2. The array substrate row driving circuit according to claim 1, characterized in that, The sustaining unit includes a second transistor, the gate of which is electrically connected to the first node, the source of which is electrically connected to the first reference signal terminal, and the drain of which is electrically connected to the second node, wherein the second transistor is a P-type transistor.

3. The array substrate row driving circuit according to claim 1, characterized in that, The pull-up unit includes a first transistor, the gate of which is electrically connected to the first node, the source of which is electrically connected to the first reference signal terminal, and the drain of which is electrically connected to the nth stage light-emitting drive signal output terminal. The first transistor is a P-type transistor.

4. The array substrate row driving circuit according to claim 1, characterized in that, The first control unit includes a third transistor, the gate of which is electrically connected to the first stage signal output terminal, the source of which is electrically connected to the first reference signal terminal, and the drain of which is electrically connected to the first node.

5. The array substrate row driving circuit according to claim 1, characterized in that, The second control unit includes a fourth transistor and a fifth transistor; The gate of the fourth transistor is electrically connected to the signal output terminal of the second stage, the source of the fourth transistor is electrically connected to the first reference signal terminal, and the drain of the fourth transistor is electrically connected to the second node. The gate of the fifth transistor is electrically connected to the second node, the source of the fifth transistor is electrically connected to the second reference signal terminal, and the drain of the fifth transistor is electrically connected to the first node.

6. The array substrate row driving circuit according to claim 1, characterized in that, The pull-down unit includes a sixth transistor, a seventh transistor, and an eighth transistor; The gate of the sixth transistor is electrically connected to the third node of the nth stage light-emitting driving module, the source of the sixth transistor is electrically connected to the third reference signal terminal, and the drain of the sixth transistor is electrically connected to the nth stage light-emitting driving signal output terminal. The gate of the seventh transistor is electrically connected to the third node, the source of the seventh transistor is electrically connected to the third reference signal terminal, and the drain of the seventh transistor is electrically connected to the second node. The gate of the eighth transistor is electrically connected to the first stage signal output terminal, the source of the eighth transistor is electrically connected to the first reference signal terminal, and the drain of the eighth transistor is electrically connected to the third node.

7. The array substrate row driving circuit according to claim 6, characterized in that, The sixth transistor, the seventh transistor, and the eighth transistor are all N-type transistors.

8. The array substrate row driving circuit according to claim 6, characterized in that, The nth level light-emitting driving module further includes a first pull-down control unit, which is electrically connected to the second node, the third node, and the third reference signal terminal. The first pull-down control unit is used to output the second reference low-level signal to the third node according to the potential of the second node. And / or, the nth level light-emitting driving module further includes a second pull-down control unit, which is electrically connected to the second level signal output terminal, the third node, and the third reference signal terminal. The second pull-down control unit is used to output the second reference low-level signal to the third node according to the second level signal.

9. The array substrate row driving circuit according to claim 8, characterized in that, The third reference signal terminal includes a first sub-reference signal terminal and a second sub-reference signal terminal; The source of the sixth transistor is electrically connected to the second sub-reference signal terminal, and the source of the seventh transistor is electrically connected to the first sub-reference signal terminal. The first pull-down control unit is electrically connected to the first sub-reference signal terminal, and / or the second pull-down control unit is electrically connected to the first sub-reference signal terminal; Wherein, the voltage value of the third reference low-level signal provided by the first sub-reference signal terminal is less than the voltage value of the fourth reference low-level signal provided by the second sub-reference signal terminal.

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