Semiconductor device for memory device

Abstract

A semiconductor device for a memory device is provided. The semiconductor device of the present disclosure includes a voltage sensor, a converter, and a command / address on-die termination (CA_ODT) circuit. The voltage sensor receives a voltage set command and senses a voltage level of the voltage set command to generate a sense signal. The converter generates a set signal in response to the sense signal. The CA_ODT circuit generates a supply voltage for the memory device in response to the set signal. A voltage level of the supply voltage corresponds to the voltage level of the voltage set command.

Description

Technical Field

[0001] This disclosure generally relates to a semiconductor device, and more specifically, to a semiconductor device for a memory device. Background Technology

[0002] As memory devices become smaller, some functions and pins are integrated. Some on-die termination (ODT) pins are removed. Some functions must be designed onto other pins.

[0003] Some operations of memory devices (such as power-up operations) are performed at different times by at least two supply voltages. However, JEDEC does not explicitly define these operations when some ODT pins are removed. Therefore, it is necessary to provide more efficient operations for switching between at least two supply voltages. Summary of the Invention

[0004] This disclosure provides a semiconductor device capable of providing at least two power sources immediately and sequentially to a memory device.

[0005] The disclosed semiconductor device includes a voltage sensor, a converter, and a command / address on-die-termination (CA_ODT) circuit. The voltage sensor receives a voltage setting command and senses the voltage level of the voltage setting command to generate a sensing signal. The converter is coupled to the voltage sensor. The converter generates a setting signal in response to the sensing signal. The CA_ODT circuit is coupled between the converter and a memory device. The CA_ODT circuit generates a power supply voltage for the memory device in response to the setting signal. The voltage level of the power supply voltage corresponds to the voltage level of the voltage setting command.

[0006] Based on the above description, the voltage sensor senses the voltage level of the voltage setting command to generate a sensing signal. The converter responds to the sensing signal to set the CA_ODT circuit, thereby the CA_ODT circuit generates a power supply voltage for the memory device. The voltage level of the power supply voltage corresponds to the voltage level of the voltage setting command. Therefore, the semiconductor device immediately and sequentially supplies at least two power supplies to the memory device based on the voltage level of the voltage setting command.

[0007] To make the foregoing easier to understand, several embodiments accompanied by accompanying drawings are described in detail below. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the present disclosure and, together with the implementation methods, are used to explain the principles of the disclosure.

[0009] Figure 1 A schematic diagram of a semiconductor device according to a first embodiment of the present disclosure is shown;

[0010] Figure 2 A timing diagram of a voltage setting command, a sensing signal, a setting signal, and a power supply voltage according to an embodiment of this disclosure is shown.

[0011] Figure 3 A schematic diagram of a semiconductor device according to a second embodiment of the present disclosure is shown;

[0012] Figure 4 A schematic diagram of a semiconductor device according to a third embodiment of the present disclosure is shown;

[0013] Figure 5 A timing diagram showing the voltage setting command and sensing signal according to an embodiment of the present disclosure is provided.

[0014] Figure 6 A schematic diagram of a CA_ODT circuit according to an embodiment of this disclosure is shown.

[0015] Explanation of icon numbers

[0016] 100, 200, 300: Semiconductor devices;

[0017] 110, 210, 310: Voltage sensors;

[0018] 120: Converter;

[0019] 130, 230: Command / Address die-mounted terminal block (CA_ODT) circuit;

[0020] 212, 312: Comparators;

[0021] MD: Memory device;

[0022] NDC: Power Input Node;

[0023] R1, R2: Resistors;

[0024] SSEN: Sensing signal;

[0025] SST: Set signal;

[0026] SW1: First switch;

[0027] SW2: Second switch;

[0028] t: time;

[0029] tp: point in time;

[0030] VDD, VDDQ: High reference voltage;

[0031] VL1: First voltage level;

[0032] VL2: Second voltage level;

[0033] VPWR: Power supply voltage;

[0034] VREF, VREF1, VREF2: Reference voltages;

[0035] VSCMD: Voltage setting command;

[0036] VSE1: First sensed value;

[0037] VSE2: Second sensing value;

[0038] VSS: Low reference voltage;

[0039] VST1: First setting value;

[0040] VST2: Second setting value. Detailed Implementation

[0041] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings described below. It should be noted that, for the purposes of clarity of illustration and ease of understanding, the various drawings of this disclosure show a portion of an electronic device, and some elements in the various drawings may not be drawn to scale. Furthermore, the number and dimensions of each device shown in the drawings are illustrative only and are not intended to limit the scope of this disclosure.

[0042] Certain terms are used throughout the description and claims to refer to specific components. As those skilled in the art will understand, electronic device manufacturers may use different names to refer to components. This document is not intended to distinguish between components with different names rather than different functions. In the following description and claims, the terms “comprising,” “including,” and “having” are used in an open-ended manner and should therefore be interpreted as meaning “including but not limited to…”. Thus, when the terms “comprising,” “including,” and / or “having” are used in the description of this disclosure, it indicates the presence, but is not limited to, of a corresponding feature, area, step, operation, and / or component, but is not limited to the presence of one or more corresponding features, areas, steps, operations, and / or components.

[0043] It should be understood that when an element is described as "coupled to," "connected to," or "conducted to" another element, it can be directly connected to the other element and establish a direct electrical connection, or an intervening element can be present therein for relay electrical connection (indirect electrical connection). In contrast, when an element is described as "directly coupled to," "directly conducted to," or "directly connected to" another element, no intervening element is present.

[0044] Although terms such as first, second, third, etc., may be used to describe different constituent elements, such constituent elements are not limited by these terms. The terms are used only to distinguish constituent elements in the specification from other constituent elements. The claims may not use the same terms, but may use terms such as first, second, third, etc., relative to the required order of the elements. Therefore, in the following description, a first constituent element may be a second constituent element in a claim.

[0045] Please refer to Figure 1 , Figure 1 A schematic diagram of a semiconductor device according to a first embodiment of the present disclosure is shown. In this embodiment, the semiconductor device 100 is adapted to drive a memory device MD. The semiconductor device 100 includes a voltage sensor 110, a converter 120, and a command / address on-die-termination (CA_ODT) circuit 130. The voltage sensor 110 receives a voltage setting command VSCMD and senses the voltage level of the voltage setting command VSCMD to generate a sensing signal SSEN. The converter 120 is coupled to the voltage sensor 110. The converter 120 generates a setting signal SST in response to the sensing signal SSEN. The CA_ODT circuit 130 is coupled between the converter 120 and the memory device MD. The CA_ODT circuit 130 generates a power supply voltage VPWR in response to the setting signal SST. The CA_ODT circuit 130 provides the power supply voltage VPWR to the memory device MD. For example, the power supply voltage VPWR is used to drive a memory controller and / or at least one memory array of the memory device MD. In this embodiment, the voltage level of the power supply voltage VPWR corresponds to the voltage level of the voltage setting command VSCMD.

[0046] It should be noted that voltage sensor 110 senses the voltage level of voltage setting command VSCMD to generate a sensing signal SSEN. Converter 120 sets CA_ODT circuit 130 in response to sensing signal SSEN. CA_ODT circuit 130 provides power supply voltage VPWR to memory device MD. The voltage level of power supply voltage VPWR corresponds to the voltage level of voltage setting command VSCMD. Therefore, semiconductor device 100 provides at least two different power supplies immediately and sequentially to memory device based on the voltage level of voltage setting command VSCMD.

[0047] Furthermore, the semiconductor device 100 supplies the power supply voltage VPWR to the memory device MD via the CA_ODT circuit 130. Therefore, no changes are required to the design and process of the memory device MD. The semiconductor device 100 performs some operations (such as power-on operations) on the memory device MD at different times via the CA_ODT circuit 130 based on at least two power supply voltages.

[0048] For ease of description, this embodiment uses two different voltage levels of the voltage setting command VSCMD as an example. The number of different voltage levels disclosed herein can be multiple, and is not limited to this embodiment.

[0049] For example, the memory device MD can be any type of dynamic random access memory (DRAM) module or any type of DRAM chip.

[0050] In this embodiment, the CA_ODT circuit 130 can be configured as a CA_ODT pin to reduce reflected signals during write operations.

[0051] For example, please also refer to Figure 1 and Figure 2 , Figure 2 A timing diagram of a voltage setting command, a sensing signal, a setting signal, and a power supply voltage according to an embodiment of this disclosure is shown. In this embodiment, when the voltage setting command VSCMD has a first voltage level VL1, the voltage sensor 110 generates a sensing signal SSEN with a first sensing value VSE1 in response to the first voltage level VL1. The converter 120 converts the sensing signal SSEN with the first sensing value VSE1 into a setting signal SST with a first setting value VST1. The CA_ODT circuit 130 generates a power supply voltage VPWR as a high power supply voltage (e.g., a high reference voltage VDD or a high reference voltage VDDQ) in response to the setting signal SST with the first setting value VST1.

[0052] At time point tp, the voltage setting command VSCMD has a second voltage level VL2. Voltage sensor 110, in response to the second voltage level VL2, generates a sensing signal SSEN with a second sensed value VSE2. Converter 120 converts the sensing signal SSEN with the second sensed value VSE2 into a setting signal SST with a second set value VST2. CA_ODT circuit 130, in response to the setting signal SST with the second set value VST2, generates a power supply voltage VPWR as a low power supply voltage (e.g., a low reference voltage VSS).

[0053] In this embodiment, each of the first sensing value VSE1, the second sensing value VSE2, the first set value VST1, and the second set value VST2 can be a voltage level, a digital value, or a logic value.

[0054] In this embodiment, the converter 120 may be implemented by any type of signal conversion circuit (such as an analog-to-digital converter), voltage shifter, encoder, decoder or buffer.

[0055] When the voltage level of the voltage setting command VSCMD changes, the voltage level of the power supply voltage VPWR changes accordingly. In other words, when the voltage level of the voltage setting command VSCMD is the first voltage level VL1, the CA_ODT circuit 130 generates the power supply voltage VPWR as a high power supply voltage. When the voltage level of the voltage setting command VSCMD is the second voltage level VL2, the CA_ODT circuit 130 generates the power supply voltage VPWR as a low power supply voltage.

[0056] Please refer to Figure 3 , Figure 3 A schematic diagram of a semiconductor device according to a second embodiment of the present disclosure is shown. In this embodiment, the semiconductor device 200 includes a voltage sensor 210, a converter 120, and a CA_ODT circuit 130. (See reference...) Figure 1 and Figure 2 The relevant descriptions are used to infer converter 120 and CA_ODT circuit 130, which will not be repeated below.

[0057] In this embodiment, the voltage sensor 210 includes a comparator 212. The comparator 212 receives a voltage setting command VSCMD and a reference voltage VREF. The comparator 212 compares the voltage setting command VSCMD with the reference voltage VREF to generate a sensing signal SSEN. The comparator 212 provides the sensing signal SSEN to the converter 120. For example, when the voltage level of the voltage setting command VSCMD is higher than the voltage level of the reference voltage VREF, the comparator 212 may generate a value with a first sensed value (such as...). Figure 2 The sensing signal SSEN is the first sensing value (VSE1) shown. On the other hand, when the voltage level of the voltage setting command VSCMD is lower than the voltage level of the reference voltage VREF, the comparator 212 generates a sensing signal SSEN with a second sensing value (e.g., VSE1). Figure 2 The second sensing value (VSE2) shown is the sensing signal SSEN.

[0058] Please refer to Figure 4 , Figure 4 A schematic diagram of a semiconductor device according to a third embodiment of the present disclosure is shown. In this embodiment, the semiconductor device 300 includes a voltage sensor 310, a converter 120, and a CA_ODT circuit 130. (See reference...) Figure 1 and Figure 2 The relevant descriptions are used to infer converter 120 and CA_ODT circuit 130, which will not be repeated below.

[0059] In this embodiment, the voltage sensor 310 includes a comparator 312. The comparator 313 receives a voltage setting command VSCMD and reference voltages VREF1 and VREF2. The comparator 312 compares the voltage setting command VSCMD with the reference voltages VREF1 and VREF2 to generate a sensing signal SSEN.

[0060] For example, please also refer to Figure 4 and Figure 5 , Figure 5 A timing diagram of a voltage setting command VSCMD and a sensing signal SSEN according to an embodiment of the present disclosure is shown. In this embodiment, the voltage level of a reference voltage VREF1 is higher than the voltage level of a reference voltage VREF2. When the voltage level VL1 of the voltage setting command VSCMD is higher than the voltage level of the reference voltage VREF1, comparator 312 generates a sensing signal SSEN having a first sensing value VSE1.

[0061] On the other hand, when the voltage level VL2 of the voltage setting command VSCMD is lower than the voltage level of the reference voltage VREF2, the comparator 312 generates a sensing signal SSEN with a second sensing value VSE2.

[0062] Furthermore, when the voltage level of the voltage setting command VSCMD is lower than or higher than the voltage level of the reference voltage VREF1, comparator 312 can maintain the sensed value of the sensing signal SSEN. Therefore, when the voltage level of the voltage setting command VSCMD transitions between voltage levels VL1 and VL2, comparator 312 can reduce the fluctuation of the sensed value of the sensing signal SSEN.

[0063] Please also refer to Figure 2 and Figure 6 , Figure 6 A schematic diagram of a CA_ODT circuit according to an embodiment of the present disclosure is shown. In this embodiment, when the setting signal SST has a first setting value VST1, the CA_ODT circuit 230 provides a first configuration and generates a power supply voltage VPWR having a first voltage level based on the first configuration. When the setting signal SST has a second setting value VST2, the CA_ODT circuit 230 provides a second configuration and generates a power supply voltage VPWR having a second voltage level based on the second configuration.

[0064] In this embodiment, the CA_ODT circuit includes a first switch SW1 and a second switch SW2. The first terminal of the first switch SW1 is coupled to a high reference voltage VDDQ. The second terminal of the first switch SW1 is coupled to a power input node NDC, which is coupled to a memory device MD. The control terminal of the first switch SW1 receives a setting signal SST. The first terminal of the second switch SW2 is coupled to the power input node NDC. The second terminal of the second switch SW2 is coupled to a low reference voltage VSS. The control terminal of the second switch SW2 also receives the setting signal SST.

[0065] In detail, the CA_ODT circuit further includes resistors R1 and R2. A first switch SW1 and resistor R1 are connected in series between the high reference voltage VDDQ and the power input node NDC. A second switch SW2 and resistor R2 are connected in series between the low reference voltage VSS and the power input node NDC. For example, resistor R1 is connected between the high reference voltage VDDQ and the first terminal of the first switch SW1. Resistor R2 is connected between the low reference voltage VSS and the second terminal of the second switch SW2.

[0066] In this embodiment, when the setting signal SST has a first setting value VST1, the CA_ODT circuit 230 turns on the first switch SW1 and turns off the second switch SW2. Therefore, the CA_ODT circuit 230 provides a first configuration. Based on this first configuration, the voltage level of the power input node NDC is substantially equal to the voltage level of the high reference voltage VDDQ. Therefore, when the setting signal SST has the first setting value VST1, the CA_ODT circuit 230 generates a power supply voltage VPWR based on the high reference voltage VDDQ.

[0067] When the setting signal SST has a second setting value VST2, the CA_ODT circuit 230 turns on the second switch SW2 and turns off the first switch SW1. Therefore, the CA_ODT circuit 230 provides a second configuration. Based on this second configuration, the voltage level of the power input node NDC is substantially equal to the voltage level of the low reference voltage VSS. Therefore, when the setting signal SST has the second setting value VST2, the CA_ODT circuit 230 generates a power supply voltage VPWR based on the low reference voltage VSS.

[0068] In some embodiments, the CA_ODT circuit 230 may provide a third configuration when the first switch SW1 and the second switch SW2 are turned on in response to other set values ​​of the setting signal SST. Resistors R1 and R2 may divide the high reference voltage VDDQ to generate a power supply voltage VPWR having a voltage level different from the voltage level of the high reference voltage VDDQ and the voltage level of the low reference voltage VSS. In other words, based on the third configuration, the CA_ODT circuit 230 generates a power supply voltage VPWR having a voltage level lower than the voltage level of the high reference voltage VDDQ and higher than the voltage level of the low reference voltage VSS.

[0069] In this embodiment, each of the first switch SW1 and the second switch SW2 can be implemented by any type of transistor or transfer gate.

[0070] Given the foregoing, the voltage sensor senses the voltage level of the voltage setting command to generate a sensing signal. The converter 120 sets the CA_ODT circuit in response to the sensing signal SSEN. The CA_ODT circuit provides the power supply voltage VPWR to the memory device. The voltage level of the power supply voltage corresponds to the voltage level of the voltage setting command. Therefore, the semiconductor device immediately and sequentially provides at least two different power supplies to the memory device based on the voltage level of the voltage setting command. Furthermore, the semiconductor device provides the power supply voltage to the memory device via the CA_ODT circuit. Therefore, no changes to the design and process of the memory device are required. The semiconductor device performs some operations of the memory device at different times based on at least two power supply voltages via the CA_ODT circuit.

[0071] It will be apparent to those skilled in the art that various modifications and changes can be made to the disclosed embodiments without departing from the scope or spirit of this disclosure. In view of the foregoing, it is intended that this disclosure cover modifications and variations, provided that such modifications and variations fall within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device for a memory device, comprising: A voltage sensor is configured to receive a voltage setting command and sense the voltage level of the voltage setting command to generate a sensing signal; A converter, coupled to the voltage sensor, is configured to generate a set signal in response to the sensed signal; as well as A command / address die-on termination circuit, coupled between the converter and the memory device, is configured to generate a power supply voltage for the memory device in response to the setting signal, wherein the voltage level of the power supply voltage corresponds to the voltage level of the voltage setting command.

2. The semiconductor device according to claim 1, wherein: When the voltage level of the voltage setting command is the first voltage level, the on-chip termination circuit of the command / address transistor generates the power supply voltage as a high power supply voltage, and When the voltage level of the voltage setting command is the second voltage level, the on-chip termination circuit of the command / address transistor generates the power supply voltage as a low power supply voltage.

3. The semiconductor device of claim 1, wherein the voltage sensor comprises: A comparator is configured to receive the voltage setting command and a reference voltage, and compare the voltage setting command with the reference voltage to generate the sensing signal.

4. The semiconductor device according to claim 3, wherein: When the voltage level of the voltage setting command is higher than the voltage level of the reference voltage, the comparator generates a sensing signal having a first sensing value, and When the voltage level of the voltage setting command is lower than the voltage level of the reference voltage, the comparator generates the sensing signal with a second sensing value.

5. The semiconductor device of claim 1, wherein the voltage sensor comprises: A comparator is configured to receive the voltage setting command, a first reference voltage, and a second reference voltage, and to compare the voltage setting command with the first reference voltage and the second reference voltage and generate the sensing signal.

6. The semiconductor device according to claim 5, wherein: The voltage level of the first reference voltage is higher than the voltage level of the second reference voltage. When the voltage level of the voltage setting command is higher than the voltage level of the first reference voltage, the comparator generates a sensing signal having a first sensing value, and When the voltage level of the voltage setting command is lower than the voltage level of the second reference voltage, the comparator generates the sensing signal with a second sensing value.

7. The semiconductor device according to claim 1, wherein: The converter converts the sensing signal having a first sensing value into the setting signal having a first set value, and The converter converts the sensing signal having a second sensing value into the setting signal having a second setting value.

8. The semiconductor device of claim 1, wherein the command / address die-on termination circuit is configured to: When the setting signal has a first setting value, a first configuration is provided and a power supply voltage having a first voltage level is generated based on the first configuration. When the setting signal has a second setting value, a second configuration is provided and a power supply voltage with a second voltage level is generated based on the second configuration.

9. The semiconductor device of claim 1, wherein the command / address die-on termination circuit comprises: A first switch, wherein a first terminal of the first switch is coupled to a high reference voltage, a second terminal of the first switch is coupled to a power input node, the power input node is coupled to the memory device, and a control terminal of the first switch receives the setting signal; as well as The second switch, wherein the first terminal of the second switch is coupled to the power input node, the second terminal of the second switch is coupled to the low reference voltage, and the control terminal of the second switch receives the setting signal.

10. The semiconductor device according to claim 9, wherein: When the setting signal has a first set value, the on-chip termination circuit of the command / address transistor generates the power supply voltage based on the high reference voltage, and When the setting signal has a second setting value, the on-die termination circuit of the command / address transistor generates the power supply voltage based on the low reference voltage.

11. The semiconductor device according to claim 9, wherein: When the setting signal has a first set value, the terminal circuit on the command / address die connects the first switch and disconnects the second switch, and When the setting signal has a second setting value, the terminal circuit on the command / address die turns on the second switch and turns off the first switch.

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