Method and device for improving ssd firmware error correction test coverage
By setting the read level of the NAND flash die and adjusting the LDPC error correction process in SSD firmware testing, the problem of low test coverage in existing technologies is solved, achieving more efficient error correction test coverage and test flexibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUZHOU UNIONMEMORY INFORMATION SYST LTD
- Filing Date
- 2023-11-30
- Publication Date
- 2026-07-31
AI Technical Summary
Existing SSD firmware testing does not cover high-pressure and multi-module mixed scenarios, resulting in low test coverage. Furthermore, grinding tests can easily cause irreversible damage to SSDs.
By entering cmdline commands during solid-state drive read/write operations to set the read level of the NAND flash die, it checks whether the read retry table has been modified. If it has been modified, it reports a failure and enters the LDPC error correction process, using the default or fail level for error correction. Finally, it enters the RAID recovery process to recover the data.
It improves the coverage of SSD firmware error correction testing, covering different test scenarios under multi-module stress testing, avoiding damage to the SSD disk caused by grinding tests, and improving the flexibility and controllability of testing.
Smart Images
Figure CN117594113B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of solid-state drive testing technology, and in particular to a method, apparatus, computer device, and storage medium for improving the coverage of SSD firmware error correction testing. Background Technology
[0002] Due to certain characteristics of the physical structure of NAND flash and external environmental factors, existing storage devices are prone to errors during the reading process of NAND flash data. Common error correction methods include: NAND flash controller ECC error correction (LDPC hard); adjusting the read threshold voltage for read retry; adjusting the read threshold voltage offset for LDPC soft decoding; and using RAID striping to recover data.
[0003] Currently, traditional chip testing often involves separate testing of error correction modules, failing to cover high-stress and multi-module mixed testing scenarios. In SSD firmware testing, because the initial flash memory is in relatively good condition, it's difficult for read failures to trigger the error correction module. A grinding test is required to bring the flash memory to an error-prone state, but this grinding process can easily cause irreversible damage to the SSD. Clearly, in traditional testing processes, each testing stage is uncontrollable and inflexible, resulting in low overall test coverage. Summary of the Invention
[0004] Therefore, it is necessary to provide a method, apparatus, computer equipment, and storage medium for improving the coverage of SSD firmware error correction tests to address the aforementioned technical problems.
[0005] A method for improving SSD firmware error correction test coverage, the method comprising:
[0006] During solid-state drive read / write operations, the read level of the NAND flash die is set by inputting the cmdline command;
[0007] Enter the read retry process and determine whether the firmware's read retry table has been modified in the current scenario;
[0008] If the read retry table has not been modified in the current scenario, the read retry will report success; if the read retry table has been modified in the current scenario, the read retry will report failure.
[0009] After a read retry fails, the LDPC error correction process is initiated. LDPC uses the default read level to perform error correction and succeeds.
[0010] In one embodiment, the step of reporting a readretry failure if the read retry table has been modified in the current scenario further includes:
[0011] Modify the read level of LDPC error correction to all fail level in the firmware;
[0012] After a read retry fails, the LDPC error correction process begins. When LDPC attempts to correct errors using the fail level, it reports an error correction failure.
[0013] In one embodiment, after the read retry fails and the LDPC error correction process is initiated, following the step of LDPC using the fail level to report an error correction failure, the process further includes:
[0014] After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated.
[0015] In the RAID recovery process, all reads are performed at the default read level, and all reads are successful, resulting in successful data recovery.
[0016] In one embodiment, after the read retry fails and the LDPC error correction process is initiated, following the step of LDPC using the fail level to report an error correction failure, the process further includes:
[0017] After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated.
[0018] By randomly setting the read level of other NAND flash dies to the failure level using cmdline, data recovery failures will occur during the RAID recovery process.
[0019] An apparatus for improving SSD firmware error correction test coverage, the apparatus comprising:
[0020] The setting module is used to set the read level of the NAND flash die by inputting cmdline commands during the read and write process of the solid-state drive;
[0021] The judgment module is used to enter the read retry process and determine whether the read retry table of the firmware has been modified in the current scenario.
[0022] The reread module is used to report readretry success if the read retry table has not been modified in the current scenario, and readretry failure if the read retry table has been modified in the current scenario.
[0023] The error correction module is used to enter the LDPC error correction process after a read retry fails. LDPC uses the default read level to perform error correction and the error correction is successful.
[0024] In one embodiment, the error correction module is further configured to:
[0025] Modify the read level of LDPC error correction to all fail level in the firmware;
[0026] After a read retry fails, the LDPC error correction process begins. When LDPC attempts to correct errors using the fail level, it reports an error correction failure.
[0027] In one embodiment, the device further includes a recovery module, the recovery module being used for:
[0028] After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated.
[0029] In the RAID recovery process, all reads are performed at the default read level, and all reads are successful, resulting in successful data recovery.
[0030] In one embodiment, the recovery module is further configured to:
[0031] After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated.
[0032] By randomly setting the read level of other NAND flash dies to the failure level using cmdline, data recovery failures will occur during the RAID recovery process.
[0033] A computer device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of any of the methods described above.
[0034] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.
[0035] The aforementioned method, apparatus, computer equipment, and storage medium for improving SSD firmware error correction test coverage involve setting the NAND flash die's read level during SSD read / write operations by inputting cmdline commands; entering the readretry process to determine if the firmware's read retry table has been modified in the current scenario; if the readretry table has not been modified, the read retry reports success; if the read retry table has been modified, the read retry reports failure; if the read retry fails, the LDPC error correction process is initiated, where LDPC performs error correction using the default read level and succeeds. This invention, by using flexible error injection scenarios, can cover different test scenarios under multi-module stress testing, thereby effectively improving the coverage of SSD firmware error correction tests. Attached Figure Description
[0036] Figure 1 This is a schematic diagram of the firmware error correction process commonly used in current storage devices;
[0037] Figure 2 This is a flowchart illustrating a method for improving SSD firmware error correction test coverage in one embodiment.
[0038] Figure 3 This is a schematic diagram of an error correction testing method covering multiple scenarios in one embodiment;
[0039] Figure 4 This is a structural block diagram of an implementation device for improving SSD firmware error correction test coverage in one embodiment;
[0040] Figure 5 This is a structural block diagram of an apparatus for improving SSD firmware error correction test coverage in another embodiment;
[0041] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0043] In existing storage devices, due to some characteristics of the physical structure of NAND flash and external environmental factors, errors are prone to occur during the reading process of NAND flash data. Common error correction methods include: NAND flash controller ECC error correction (LDPC hard); adjusting the read threshold voltage to perform read retry; adjusting the read threshold voltage offset value to perform LDPC softdecode; and using RAID striping to recover data.
[0044] Specifically, such as Figure 1 The diagram illustrates a common firmware error correction process for current storage devices. In chip testing, error correction module testing is often done independently, failing to cover high-stress scenarios and involving multiple modules. In SSD firmware testing, because the initial flash memory is in good condition, it's difficult for read failures to trigger the error correction module. A grinding test is required to bring the flash memory to an error-prone state, but this grinding process can easily cause irreversible damage to the SSD. Both approaches lack control and flexibility in their testing processes, resulting in low overall test coverage.
[0045] Based on this, the present invention provides a method for improving the test coverage of SSD firmware error correction, which aims to improve the test coverage of the error correction process.
[0046] In one embodiment, such as Figure 2 As shown, a method for improving SSD firmware error correction test coverage is provided, the method including:
[0047] Step 202: During the read / write process of the solid-state drive, the read level of the NAND flash die is set by inputting the cmdline command;
[0048] Step 204: Enter the read retry process and determine whether the firmware's read retry table has been modified in the current scenario;
[0049] Step 206: If the read retry table has not been modified in the current scenario, read retry will report success; if the read retry table has been modified in the current scenario, read retry will report failure.
[0050] Step 208: After a read retry fails, the LDPC error correction process begins. LDPC uses the default read level to perform error correction and succeeds.
[0051] This embodiment provides a method to improve the coverage of SSD firmware error correction tests. During firmware operation, the read level of a specific NAND flash die is set via cmdline. Then, the read retry table in the firmware is modified to make the read retry process result controllable, resulting in either a pass or a fail. Furthermore, the LDPC soft decoder read voltage offset in the firmware is modified to make the LDPC error correction result controllable, resulting in either a pass or a fail.
[0052] For specific details, please refer to Figure 3 The diagram shown illustrates a multi-scenario error correction testing method, which can be flexibly adjusted according to different scenarios.
[0053] In scenario 1, the read retry test was successful, and the implementation method is as follows:
[0054] First, during SSD read / write operations, use cmdline to input commands to set the read voltage level for a specific NAND flash die (this is the level that was previously selected to prevent read failures). Figure 3 (1. Error in annotation);
[0055] Then, the read retry process begins. In this scenario, the read retry table has not been modified and is a valid table; therefore, the read retry will report success.
[0056] In scenario 2, the read retry test fails, and the implementation method is as follows:
[0057] First, modify the read retry table in the firmware so that the entire table contains entries that will cause read errors.
[0058] Then, during SSD read / write operations, commands are input via cmdline to set the read threshold voltage for a specific NAND flash die (selected earlier to prevent read failures). Figure 3 (1. Error in annotation);
[0059] Finally, the read retry process begins. Overriding the read retry in this scenario will result in a failure.
[0060] In scenario 3, the read retry test failed, but the LDPC soft decode process was successfully completed and corrected. The implementation method is as follows:
[0061] If the read retry fails, the LDPC soft decode process begins. LDPC uses the default level for error correction, which will succeed at this point.
[0062] In one embodiment, after the step of reporting read retry failure if the read retry table has been modified in the current scenario, the method further includes: modifying the read level of LDPC error correction to a full fail level in the firmware; after read retry fails, entering the LDPC error correction process, and reporting error correction failure when LDPC uses the fail level for error correction.
[0063] In scenario 4, the read retry test fails, the LDPC soft decode process fails to correct the error, and the implementation method is as follows:
[0064] First, modify the read voltage level of LDPC soft decode to the all-fail level in the firmware;
[0065] Then, if the read retry fails, the LDPC soft decode process begins.
[0066] Finally, LDPC uses fail level for error correction, which will fail at this point.
[0067] In the above embodiment, during the read / write process of the solid-state drive, the read level of the NAND flashdie is set by inputting a cmdline command; the read retry process is then initiated, determining whether the firmware's read retry table has been modified in the current scenario; if the read retry table has not been modified in the current scenario, the read retry reports success; if the read retry table has been modified in the current scenario, the read retry reports failure; after a read retry failure, the LDPC error correction process is initiated, and LDPC performs error correction using the default read level, which is successful. This solution, by using flexible error injection scenarios, can cover different test scenarios under multi-module stress testing, thereby effectively improving the coverage of SSD firmware testing.
[0068] In one embodiment, after a read retry fails and the LDPC error correction process is initiated, the step following the step of LDPC using faillevel to perform error correction and reporting an error correction failure also includes:
[0069] After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated.
[0070] In the RAID recovery process, all reads are performed at the default read level, and all reads are successful, resulting in successful data recovery.
[0071] In one embodiment, after a read retry fails and the LDPC error correction process is initiated, the step following the step of LDPC using faillevel to perform error correction and reporting an error correction failure also includes:
[0072] After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated.
[0073] By randomly setting the read level of other NAND flash dies to the failure level using cmdline, data recovery failures will occur during the RAID recovery process.
[0074] Specifically, refer to Figure 3 The diagram shown illustrates a multi-scenario error correction testing method. Specific application scenarios also include:
[0075] In scenario 5, the read retry test fails, the LDPC soft decode process fails to correct, and the RAID recovery process is initiated, successfully recovering the data. The implementation method is as follows:
[0076] First, after LDPC fails, the firmware is set to the default read voltage level, and the RAID recovery process begins.
[0077] Then, during the RAID recovery process, all reads were performed at the default read level, all reads were successful, and the data was successfully recovered.
[0078] In scenario 6, the read retry test fails, the LDPC soft decode process fails to correct errors, and the RAID recovery process fails. Error injection causes data recovery to fail. The implementation method is as follows:
[0079] First, after LDPC failure, the firmware is set to the default read voltage level, and the RAID recovery process begins.
[0080] Then, the read voltage level of other dies is randomly set to the failure level using cmdline;
[0081] Finally, some dies may fail during the RAID recovery process, causing data recovery to fail.
[0082] In this embodiment, the software enters the RAID recovery process. At this time, other dies can be marked as faulty by using cmdline to achieve a RAID recovery result of PASS or FAIL.
[0083] It should be understood that, although Figures 1-3 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 1-3 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0084] In one embodiment, such as Figure 4 As shown, an apparatus 400 for improving SSD firmware error correction test coverage is provided, the apparatus comprising:
[0085] Setting module 401 is used to set the read level of NAND flash die by inputting cmdline command during solid-state drive read and write operations;
[0086] Judgment module 402 is used to enter the read retry process and determine whether the read retry table of the firmware has been modified in the current scenario;
[0087] The reread module 403 is used to report a success if the read retry table has not been modified in the current scenario, and to report a failure if the read retry table has been modified in the current scenario.
[0088] Error correction module 404 is used to enter the LDPC error correction process after a read retry fails. LDPC uses the default read level to perform error correction and the error correction is successful.
[0089] In one embodiment, the error correction module 404 is further configured to:
[0090] Modify the read level of LDPC error correction to all fail level in the firmware;
[0091] After a read retry fails, the LDPC error correction process begins. When LDPC attempts to correct errors using the fail level, it reports an error correction failure.
[0092] In one embodiment, such as Figure 5 As shown, an implementation device 400 for improving SSD firmware error correction test coverage is provided. The device further includes a recovery module 405 for:
[0093] After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated.
[0094] In the RAID recovery process, all reads are performed at the default read level, and all reads are successful, resulting in successful data recovery.
[0095] In one embodiment, the recovery module 405 is further configured to:
[0096] After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated.
[0097] By randomly setting the read level of other NAND flash dies to the failure level using cmdline, data recovery failures will occur during the RAID recovery process.
[0098] For specific limitations on the implementation device for improving SSD firmware error correction test coverage, please refer to the limitations on the implementation method for improving SSD firmware error correction test coverage mentioned above, which will not be repeated here.
[0099] In one embodiment, a computer device is provided, the internal structure of which can be shown as follows: Figure 6 As shown, the computer device includes a processor, memory, and a network interface connected via a device bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores operating devices, computer programs, and databases. The internal memory provides an environment for the operation of the operating devices and computer programs stored in the non-volatile storage media. The network interface is used for communication with external terminals via a network connection. When the computer program is executed by the processor, it implements a method for improving SSD firmware error correction test coverage.
[0100] Those skilled in the art will understand that Figure 6The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.
[0101] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the various method embodiments described above.
[0102] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the various method embodiments described above.
[0103] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.
[0104] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0105] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for improving SSD firmware error correction test coverage, the method comprising: During solid-state drive read / write operations, the read level of the NAND flash die is set by inputting the cmdline command; Enter the read retry process and determine whether the firmware's read retry table has been modified in the current scenario; If the read retry table has not been modified in the current scenario, the read retry will report success; if the read retry table has been modified in the current scenario, the read retry will report failure. After a read retry fails, the LDPC error correction process is initiated. LDPC uses the default read level to perform error correction and succeeds. The step following the statement that read retry fails if the read retry table has been modified in the current scenario also includes: Modify the read level of LDPC error correction to all fail level in the firmware; After the read retry fails, the LDPC error correction process begins. When LDPC attempts to correct errors using the fail level, it reports an error correction failure. The process of entering the LDPC error correction procedure after the read retry fails, and the step of reporting an error correction failure when LDPC uses the fail level, further includes: After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated. In the RAID recovery process, all reads are performed at the default read level, and all reads are successful, resulting in successful data recovery. The process, which involves entering the LDPC error correction procedure after the read retry fails and then reporting an error correction failure when LDPC uses the fail level, also includes the following steps: After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated. By randomly setting the read level of other NAND flash dies to the failure level using cmdline, data recovery failures will occur during the RAID recovery process.
2. An apparatus for improving SSD firmware error correction test coverage, characterized in that, The device includes: The setting module is used to set the read level of the NAND flash die by inputting cmdline commands during the read and write process of the solid-state drive; The judgment module is used to enter the read retry process and determine whether the read retry table of the firmware has been modified in the current scenario. The reread module is used to report a success if the read retry table has not been modified in the current scenario, and to report a failure if the read retry table has been modified in the current scenario. The error correction module is used to enter the LDPC error correction process after a read retry fails. LDPC uses the default read level to perform error correction and the error correction is successful. The error correction module is also used for: Modify the read level of LDPC error correction to all fail level in the firmware; After the read retry fails, the LDPC error correction process begins. When LDPC attempts to correct errors using the fail level, it reports an error correction failure. The device further includes a recovery module, which is used for: After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated. In the RAID recovery process, all reads are performed at the default read level, and all reads are successful, resulting in successful data recovery. The recovery module is further used for: After LDPC error correction fails, the read level of the NAND flash die is set to the default value in the firmware and the RAID recovery process is initiated. By randomly setting the read level of other NAND flash dies to the failure level using cmdline, data recovery failures will occur during the RAID recovery process.
3. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 1.
4. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method of claim 1.