一种低衬底漏电的RFSOI晶圆及其制备方法
By introducing polycrystalline silicon or porous silicon layers as defect enrichment layers into RFSOI wafers, and combining them with specific bonding and stripping processes, the back gate leakage problem was solved, resulting in lower back gate leakage and substrate coupling effects, thus improving the performance of RFSOI wafers.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2023-12-25
- Publication Date
- 2026-07-17
AI Technical Summary
Existing RFSOI wafers exhibit significant back-gate leakage current when a bias voltage is applied to the back gate, which affects the back-gate control capability.
A polycrystalline silicon layer or a porous silicon layer is used as a defect enrichment layer, and a top-to-bottom structure of a first silicon layer, a first buried oxide layer, a first defect enrichment layer, a second buried oxide layer, a second defect enrichment layer, and a wafer substrate is formed through specific bonding and peeling processes, which effectively blocks the electrical signal interference of the substrate layer to the back gate region.
This achieves lower back gate leakage current and isolation substrate coupling effect, improving the performance stability and integration of RFSOI wafers.
Smart Images
Figure CN117594521B_ABST