High voltage metal-oxide-semiconductor transistors

Abstract

This invention discloses a high-voltage metal-oxide-semiconductor transistor, comprising a semiconductor substrate, a plurality of active regions, a gate insulating layer, and a gate. The active regions are defined by an isolation structure, wherein each active region includes a channel portion and two side portions. The channel portion has a first pair of sides and a second pair of sides, and the two side portions are located on the first pair of sides of the channel portion. The gate insulating layer is disposed on the surface of the channel portion. The gate is disposed on the gate insulating layer and extends over a portion of the isolation structure, wherein the gate includes a pair of channel edge openings and a plurality of slits. The channel edge openings are located on the second pair of sides of the channel portion to expose a portion of the gate insulating layer, while the plurality of slits are disposed above the channel portion.

Description

Technical Field

[0001] This invention relates to a metal oxide semiconductor (MOS) transistor, and more particularly to a high voltage metal oxide semiconductor transistor. Background Technology

[0002] High-voltage (HV) devices are used in many applications, such as RF and power devices. However, the small width of the parasitic edge transistors in HV MOS transistors can produce a hump effect, which refers to the peak in the Id-Vg curve, leading to a lower critical voltage and increased sensitivity to bulk polarization. Furthermore, during the metal gate formation process, large-area metal gates in HV MOS transistors may exhibit dish-shaped depressions, resulting in excessive variations in gate thickness that fail to meet device performance requirements. Summary of the Invention

[0003] This invention provides a high-voltage metal-oxide-semiconductor transistor to suppress the peaks in Id-Vg of HV elements and solve the problem of dips during the metal gate formation process.

[0004] The high-voltage metal-oxide-semiconductor transistor of the present invention includes a semiconductor substrate, a plurality of active regions, a gate insulating layer, and a gate. The plurality of active regions are defined by an isolation structure in the semiconductor substrate, wherein each active region includes a channel portion and two side portions, the channel portion having a first pair of sides and a second pair of sides, the side portions being located on the first pair of sides of the channel portion, and the isolation structure having divots near the plurality of active regions. The gate insulating layer is disposed on the surface of the channel portion, and the gate is disposed on the gate insulating layer and extends over a portion of the isolation structure. The gate includes a pair of channel edge openings and a plurality of slits, the pair of channel edge openings being located on the second pair of sides of the channel portion to expose the divots and a portion of the gate insulating layer, and the plurality of slits being disposed above the channel portion.

[0005] In one embodiment of the invention, the pair of channel edge openings divide the gate into three parts, and the high voltage metal-oxide-semiconductor transistor further includes interconnects for connecting the three parts.

[0006] In one embodiment of the invention, the pair of channel edge openings and the plurality of slits divide the gate into a plurality of portions, and the high voltage metal-oxide-semiconductor transistor further includes interconnects for connecting the plurality of portions.

[0007] In one embodiment of the present invention, the plurality of slits divide the gate into a plurality of portions, and the high voltage metal-oxide-semiconductor transistor further includes interconnects for connecting the plurality of portions.

[0008] In one embodiment of the present invention, the high-voltage metal-oxide-semiconductor transistor further includes a dielectric material filling the pair of channel edge openings and the plurality of slits.

[0009] In one embodiment of the present invention, the high voltage metal-oxide-semiconductor transistor further includes a dielectric layer disposed on the pair of channel edge openings to form an air gap in the pair of channel edge openings.

[0010] In one embodiment of the present invention, the extension direction of the plurality of slits is parallel to the first opposite side of the channel portion.

[0011] In one embodiment of the present invention, the extension direction of the plurality of slits is perpendicular to the first opposite side of the channel portion.

[0012] In one embodiment of the present invention, the first opposite sides of the channel portion are at an angle to the extension direction of the plurality of slits.

[0013] In one embodiment of the present invention, the plurality of slits are straight lines or broken lines.

[0014] In one embodiment of the present invention, the high voltage metal-oxide-semiconductor transistor further includes a plurality of high voltage lightly doped drain (LDD) regions located in the semiconductor substrate, and each high voltage LDD region is distributed from one side of the first pair of sides of the channel portion to the side portion close to the side.

[0015] In one embodiment of the present invention, the doping concentration of the plurality of high-voltage LDD regions is less than the doping concentration of the two sides of the plurality of active regions.

[0016] In one embodiment of the present invention, the two sides of the plurality of high-voltage LDD regions and the plurality of active regions are N-type doped regions.

[0017] In one embodiment of the present invention, the two sides of the plurality of high-voltage LDD regions and the plurality of active regions are P-type doped regions.

[0018] Based on the above, in the aforementioned high-voltage MOS transistor, the hump phenomenon can be suppressed by providing a channel edge opening at the edge of the channel. Furthermore, the formation of a dish-shaped metal gate can be prevented by forming multiple slits above the active region. Since the channel edge opening and the multiple slits can be formed in the same fabrication process, manufacturing time and costs can be saved.

[0019] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0020] Figure 1 This is a plan view of a high-voltage metal-oxide-semiconductor transistor according to the first embodiment of the present invention;

[0021] Figure 2 It is along Figure 1 A cross-sectional schematic diagram of a high-voltage metal-oxide-semiconductor transistor in segment II-II'.

[0022] Figure 3 It is along Figure 1 A cross-sectional schematic diagram of a high-voltage metal-oxide-semiconductor transistor with segment III-III'.

[0023] Figure 4 It is along Figure 1 A cross-sectional schematic diagram of another example of a high-voltage metal-oxide-semiconductor transistor with line segment II-II'.

[0024] Figure 5 This is a plan view of a high-voltage metal-oxide-semiconductor transistor according to a second embodiment of the present invention;

[0025] Figure 6 This is a plan view of a high-voltage metal-oxide-semiconductor transistor according to a third embodiment of the present invention;

[0026] Figure 7 This is a plan view of a high-voltage metal-oxide-semiconductor transistor according to the fourth embodiment of the present invention.

[0027] Symbol Explanation

[0028] 100: Semiconductor substrate

[0029] 100a: Surface

[0030] 102: Gate insulating layer

[0031] 104: Gate

[0032] 1041, 1042, 1043, 1044, 1045: Partial

[0033] 106: Isolation Structure

[0034] 110: Opening at the edge of the channel

[0035] 112: Slit

[0036] 114a, 114b: High-voltage lightly doped drain (LDD) regions

[0037] 116: Dielectric materials

[0038] 200: Dent

[0039] 400: Dielectric layer

[0040] 402: Air gap

[0041] AA: Active (Active) Region

[0042] Ch: Channel Section

[0043] In01, In02, In03: Internal Connections

[0044] O1a, O1b: First pair of edges

[0045] O2a, O2b: Second pair of edges

[0046] S1, S2: Side

[0047] W1, W3: Width

[0048] W2, W5: Distance

[0049] W4: Interval Detailed Implementation

[0050] The following description provides several embodiments for implementing different features of the invention. Furthermore, these embodiments are merely exemplary and are not intended to limit the scope and application of the invention. Moreover, for clarity, the relative dimensions (e.g., length, thickness, spacing, etc.) and relative positions of regions or structural components may be reduced or enlarged. Additionally, similar or identical element symbols are used in different figures to represent similar or identical components or features.

[0051] Figure 1 This is a plan view of a high-voltage metal-oxide-semiconductor transistor according to the first embodiment of the present invention. Figure 2 It is along Figure 1 A cross-sectional schematic diagram of a high-voltage metal-oxide-semiconductor transistor with line segment II-II'. Figure 3 It is along Figure 1 A cross-sectional schematic diagram of a high-voltage metal-oxide-semiconductor transistor with segment III-III'.

[0052] Please refer to Figures 1 to 3The high-voltage metal-oxide-semiconductor transistor of the first embodiment includes a semiconductor substrate 100, a plurality of active regions AA, a gate insulating layer 102, and a gate 104. The active regions AA are defined by an isolation structure 106 in the semiconductor substrate 100, wherein the plurality of active regions AA include a channel portion Ch and two side portions S1, S2. The channel portion Ch has a first pair of opposite sides O1a-O1b and a second pair of opposite sides O2a-O2b. The two side portions S1, S2 are located on the first pair of opposite sides O1a-O1b of the channel portion Ch and serve as the source / drain of the high-voltage metal-oxide-semiconductor transistor.

[0053] Since semiconductor fabrication processes typically include one or more cleaning and / or stripping steps to remove residual components, such as oxides (not shown), from the semiconductor substrate 100, the isolation structure 106 may be etched during these cleaning or stripping steps, thus forming divots 200 on the surface of the isolation structure 106 near the active region AA, such as... Figure 2 and Figure 3 As shown, the pit 200 is formed by etching with a chemical etching solution. The pit 200 is caused because the etching rate of the isolation structure 106 near the active region AA is faster than that of the isolation structure 106 far from the active region AA. This difference in etching rate is due to various phenomena such as localized changes in the concentration of the chemical solution during the etching process.

[0054] Please continue to refer to Figure 1 and Figure 2The gate insulating layer 102 is disposed on the surface 100a of the channel portion Ch, and the gate 104 is disposed on the gate insulating layer 102 and extends on a portion of the isolation structure 106. The gate insulating layer 102 comprises silicon oxide or a high-k dielectric material. The high-k dielectric material includes, for example, HfO2, HfSiO4, HfSiON, AlN, Al2O3, La2O3, Ta2O5, Y2O3, ZrO2, SrTiO3, ZrSiO4, HfZrO4, SBT (SrBi2Ta2O9), PZT (PbZrTiO3), BST (BaSrTiO3), or combinations thereof. The gate 104 includes a pair of channel edge openings 110 and a plurality of slits 112. The pair of channel edge openings 110 are located on the second opposite sides O2a to O2b of the channel portion Ch to expose the pit 200 and a portion of the gate insulating layer 102. In one embodiment, the length of each of the pair of channel edge openings 110 is equal to the length of each of the second pair of sides O2a to O2b. In some embodiments, each channel edge opening 110 has a width W1 along the II-II' segment, and the width W1 is, for example, 0.3 μm to 0.4 μm. In this case, the distance W2 along the II-II' segment from the edge of the gate 104 to the nearest edge of the channel edge opening 110 is, for example, less than 2 μm. Since the gate 104 is located outside the channel edge (i.e., the second pair of sides O2a and O2b of the channel portion Ch), no parasitic MOS is generated at the channel edge, thereby suppressing the hump phenomenon of the Id-Vg curve of the high-voltage MOS transistor.

[0055] The plurality of slits 112 are provided above the channel portion Ch. Although in Figure 1 Only two slits 112 are shown in the diagram, but the invention is not limited thereto. In other embodiments, the number of slits 112 can be adjusted as needed, for example, three or four. In a first embodiment, the extension direction of the slits 112 is parallel to the first opposite sides O1a and O1b of the channel portion Ch, but the invention is not limited thereto. In another embodiment, the extension direction of the slits 112 may be perpendicular to the first opposite sides O1a and O1b of the channel portion Ch. In yet another embodiment, the first opposite sides O1a and O1b of the channel portion Ch may form an angle with the extension direction of the slits 112, wherein the angle is, for example, an acute angle or an obtuse angle. Furthermore, the slits 112 may be as follows: Figure 1The straight line shown, or in some embodiments of the invention, a broken line. The gate 104 may include a metal gate, wherein the metal gate includes a metal layer and a work function layer. The metal layer includes Al, Ti, Ta, W, Nb, Mo, Cu, TiN, TiC, TaN, Ti / W, or Ti / TiN; the work function layer may be a P-type work function layer or an N-type work function layer. In one embodiment, the P-type work function layer includes TiN, TiC, TaN, TaC, WC, or TiAlN. In one embodiment, the N-type work function layer includes TiAl, ZrAl, WAl, or HfAl.

[0056] Please continue to refer to Figure 1 and Figure 3 Each slit 112 has a width W3 along the III-III' segment, and the width W3 is, for example, less than 0.1 μm. In this case, the spacing W4 between two slits 112 is, for example, less than 2 μm, and the distance W5 along the III-III' segment from the edge of the gate 104 to the nearest edge of the slit 112 is, for example, less than 2 μm. The high-voltage metal-oxide-semiconductor transistor of the first embodiment may further include a plurality of high-voltage lightly doped drain (LDD) regions 114a to 114b located in the semiconductor substrate 100. The high-voltage LDD region 114a is distributed from the first opposite side O1a of the channel portion Ch to the side portion S1, and the high-voltage LDD region 114b is distributed from the first opposite side O1b of the channel portion Ch to the side portion S2. That is, the side portion S1 is located within the high-voltage LDD region 114a, and the side portion S2 is located within the high-voltage LDD region 114b. The high-voltage LDD region 114a may further extend below the gate insulating layer 102 near the first opposite side O1a, and the high-voltage LDD region 114b may further extend below the gate insulating layer 102 near the first opposite side O1b. The doping concentration of the high-voltage LDD regions 114a and 114b is, for example, less than the doping concentration of the two side portions S1 and S2 of the active region AA. The high-voltage LDD regions 114a and 114b, as well as the two side portions S1 and S2 of the active region AA, may be N-type doped regions; or, P-type doped regions.

[0057] Please continue to refer to Figure 2 and Figure 3The high-voltage metal-oxide-semiconductor transistor may further include a dielectric material 116 filling the pair of channel edge openings 110 and the plurality of slits 112. The dielectric material 116 includes silicon oxide, silicon oxynitride, phosphosilicate glass, borosilicate, fluorinated silicate glass, organosilicon glass, silicon carbide, spin-coated glass, spin-coated polymer, silicon carbide, or combinations thereof. In some embodiments, the method of forming the gate 104 may include forming a monolayer of dielectric material 116 on a semiconductor substrate 100, a gate insulating layer 102, an active region AA, and an isolation structure 106; patterning the monolayer to form openings other than the channel edge openings 110 and slits 112; re-depositing a metal gate to fill the openings; and then performing a planarization process (e.g., CMP) on the metal gate until the dielectric material 116 is exposed. Because the large-area gate 104 has the pair of channel edge openings 110 and the plurality of slits 112 filled with dielectric material 116, the dishing problem during the metal gate formation process can be solved.

[0058] However, the present invention is not limited thereto. In other embodiments of the present invention, the method of forming the gate 104 may include first forming a whole layer of sacrificial material (not shown) on the semiconductor substrate 100, the active region AA, and the isolation structure 106; then patterning the aforementioned whole layer to form a dummy gate with the same shape as the gate 104; then depositing a whole layer of dielectric material 116 covering the dummy gate; and performing a planarization process (e.g., CMP) on the dielectric material 116 until the dummy gate is exposed; and then replacing the dummy gate with a high-k dielectric material and a metal gate, wherein the high-k dielectric material serves as the gate insulating layer 102 and the metal gate serves as the gate 104. Since the metal gate must be fabricated through a planarization process, the dielectric material 116 filling the plurality of slits 112 can prevent the gate 104 from being recessed.

[0059] Figure 4 It is along Figure 1 A cross-sectional schematic diagram of another example of a high-voltage metal-oxide-semiconductor transistor, using the II-II' segment, where... Figure 2 The same component symbol is used to represent the same component.

[0060] Please refer to Figure 4 The high-voltage metal-oxide-semiconductor transistor may further include a dielectric layer 400 disposed on the pair of channel edge openings 110 to form an air gap 402 in the pair of channel edge openings 110. The dielectric layer 400 may cover the gate 104, the isolation structure 106, and the two sides S1 and S2 of the active region AA. The dielectric layer 400 may be selected from the same group of materials as the dielectric material 116.

[0061] Figure 5This is a plan view of a high-voltage metal-oxide-semiconductor transistor according to a second embodiment of the present invention, wherein the same element symbols as in the first embodiment are used to represent the same components.

[0062] exist Figure 5 In this configuration, the pair of channel edge openings 110 divide the gate into three portions 1041, 1042, and 1043. Therefore, the high-voltage metal-oxide-semiconductor transistor of the second embodiment includes an interconnect In01 to electrically connect these three portions 1041, 1042, and 1043.

[0063] Figure 6 This is a plan view of a high-voltage metal-oxide-semiconductor transistor according to a third embodiment of the present invention, wherein the same element symbols as in the first embodiment are used to represent the same components.

[0064] exist Figure 6 In this configuration, the pair of channel edge openings 110 and the plurality of slits 112 divide the gate into multiple portions 104. 1～5 Therefore, the high-voltage metal-oxide-semiconductor transistor of the third embodiment further includes an internal interconnect InO2 for connecting the plurality of portions 104. 1～5 .

[0065] Figure 7 This is a plan view of a high-voltage metal-oxide-semiconductor transistor according to a fourth embodiment of the present invention, wherein the same element symbols as in the first embodiment are used to represent the same components.

[0066] exist Figure 7 In the transistor, multiple slits 112 divide the gate into multiple portions 1041 and 1042. Therefore, the high-voltage metal-oxide-semiconductor transistor of the fourth embodiment also includes an interconnect InO3 for connecting portions 1041 and 1042.

[0067] In summary, because the gate is designed with a channel edge opening at the channel edge, the hump phenomenon in high-voltage MOS transistors can be suppressed. The hump phenomenon in medium-voltage MOS transistors can also be suppressed using the same method. Furthermore, the slit above the channel region and the aforementioned channel edge opening on the gate can solve the gate dishing problem.

[0068] Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A high-voltage metal-oxide-semiconductor transistor, comprising: Semiconductor substrate; Multiple active regions are defined by an isolation structure in the semiconductor substrate, wherein the multiple active regions include a channel portion and two side portions, the channel portion has a first pair of sides and a second pair of sides, the two side portions are located at the first pair of sides of the channel portion, and the isolation structure has a recess near the multiple active regions; A gate insulating layer is disposed on the surface of the channel portion; as well as A gate is disposed on the gate insulating layer and extends over a portion of the isolation structure, wherein the gate includes a pair of channel edge openings and a plurality of slits, the pair of channel edge openings being located on the second opposite sides of the channel portion to expose the pit and a portion of the gate insulating layer, and the plurality of slits being disposed above the channel portion. Wherein, the length of each of the pair of channel edge openings is equal to the length of each of the second pair of sides.

2. The high-voltage metal-oxide-semiconductor transistor of claim 1, wherein the pair of channel edge openings divide the gate into three parts, and further includes interconnects connecting the three parts.

3. The high-voltage metal-oxide-semiconductor transistor of claim 1, wherein the pair of channel edge openings and the plurality of slits divide the gate into a plurality of portions, and further includes interconnects connecting the plurality of portions.

4. The high-voltage metal-oxide-semiconductor transistor of claim 1, wherein the plurality of slits divide the gate into a plurality of portions, and further includes interconnects connecting the plurality of portions.

5. The high-voltage metal-oxide-semiconductor transistor of claim 1, further comprising a dielectric material filling the pair of channel edge openings and the plurality of slits.

6. The high-voltage metal-oxide-semiconductor transistor of claim 1 further comprises a dielectric layer disposed on the pair of channel edge openings to form an air gap in the pair of channel edge openings.

7. The high-voltage metal-oxide-semiconductor transistor of claim 1, wherein the extension direction of the plurality of slits is parallel to the first opposite sides of the channel portion.

8. The high-voltage metal-oxide-semiconductor transistor of claim 1, wherein the extension direction of the plurality of slits is perpendicular to the first opposite sides of the channel portion.

9. The high-voltage metal-oxide-semiconductor transistor of claim 1, wherein the first opposite sides of the channel portion form an angle with the extension direction of the plurality of slits.

10. The high-voltage metal-oxide-semiconductor transistor of claim 1, wherein the plurality of slits are straight lines or broken lines.

11. The high-voltage metal-oxide-semiconductor transistor of claim 1, further comprising a plurality of high-voltage lightly doped drain (LDD) regions located in the semiconductor substrate, wherein each of the high-voltage lightly doped drain regions is distributed from one side of the first opposite edge of the channel portion to one side of the channel portion near the edge.

12. The high-voltage metal-oxide-semiconductor transistor of claim 11, wherein the doping concentration of the plurality of high-voltage lightly doped drain regions is less than the doping concentration of the two sides of the plurality of active regions.

13. The high-voltage metal-oxide-semiconductor transistor of claim 11, wherein the plurality of high-voltage lightly doped drain regions and the two sides of the plurality of active regions are N-type doped regions.

14. The high-voltage metal-oxide-semiconductor transistor of claim 11, wherein the plurality of high-voltage lightly doped drain regions and the two sides of the plurality of active regions are P-type doped regions.

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