A semiconductor device and a manufacturing process thereof

Abstract

The application discloses a semiconductor device and a preparation process thereof, and relates to the technical field of semiconductors, and aims to inhibit the parasitic channel leakage of a ring gate transistor and improve the working performance of the ring gate transistor. The semiconductor device comprises a semiconductor substrate, an active structure, a gate stack structure, a first inner sidewall, a semiconductor material structure and a second inner sidewall. The active structure comprises a source region, a drain region and a channel region. The gate stack structure surrounds the outer periphery of the channel region. The first inner sidewall is formed between the gate stack structure and the source region and between the gate stack structure and the drain region. The semiconductor material structure is located below the active structure; the height of the semiconductor material structure located below the source region, the drain region and part of the first inner sidewall is smaller than the height of the remaining part of the semiconductor material structure. In the length direction of the gate stack structure, the second inner sidewall is located between the semiconductor material structure and the source region and between the semiconductor material structure and the drain region; and the thickness of the second inner sidewall is smaller than the thickness of the first inner sidewall.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication process. Background Technology

[0002] Compared to fin field-effect transistors, gate-around transistors have a gate stacking structure that is formed not only on the top and sidewalls of the channel, but also on the bottom of the channel, thereby suppressing short-channel effects and enhancing the gate control capability of gate-around transistors.

[0003] However, in existing gate-around transistors, the parasitic channel effect caused by the sub-fins leads to the degradation of electrical characteristics, which is not conducive to improving the operating performance of gate-around transistors. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication process for suppressing parasitic channel leakage current in gate-around transistors, thereby improving the operating performance of gate-around transistors.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising: a semiconductor substrate, an active structure, a gate stack structure, a first inner sidewall, a semiconductor material structure, and a second inner sidewall. The active structure is formed on the semiconductor substrate; the active structure includes a source region, a drain region, and a channel region located between the source and drain regions. The channel region contacts both the source and drain regions. The gate stack structure is formed on the semiconductor substrate and surrounds the outer periphery of the channel region. The first inner sidewall is formed between the gate stack structure and the source region, and between the gate stack structure and the drain region. The semiconductor material structure is formed on the semiconductor substrate and below the active structure; a gap exists between the semiconductor material structure and the channel region, and the semiconductor material structure and the channel region are made of different materials; the height of the portion of the semiconductor material structure located below the source region, drain region, and part of the first inner sidewall is less than the height of the remaining portion of the semiconductor material structure. The second inner wall is formed below the first inner wall; along the length of the gate stack structure, the second inner wall is located between the semiconductor material structure and the source region, and between the semiconductor material structure and the drain region; along the length of the gate stack structure, the thickness of the second inner wall is less than the thickness of the first inner wall.

[0006] With the above technical solution, the gate stack structure surrounds the outer periphery of the channel region, thus the semiconductor device provided by the present invention includes a gate-to-ring transistor. Secondly, the semiconductor device provided by the present invention includes a first inner wall formed between the gate stack structure and the source region, and between the gate stack structure and the drain region, to limit the length of the gate stack structure and reduce the parasitic capacitance between the source region and the drain region and the gate stack structure, thereby improving the operating performance of the semiconductor device.

[0007] Furthermore, the semiconductor device provided by this invention also includes a semiconductor material structure formed on a semiconductor substrate and located below the active structure. The height of the portion of the semiconductor material structure located below the source region, drain region, and a portion of the first inner wall is less than the height of the remaining portion (the remaining portion of the semiconductor material structure is located below a portion of the channel region). At this time, there is a gap between the bottom of the first inner wall and the portion of the semiconductor material structure corresponding to the portion below the first inner wall. Based on this, the semiconductor device also includes second inner walls formed on both sides of the semiconductor material structure along the length direction of the gate stack structure, the second inner walls filling the aforementioned gap. Furthermore, since the second inner walls are located between the semiconductor material structure and the source region, and between the semiconductor material structure and the drain region, while the channel region is located between the source and drain regions included in the active structure, the length of the semiconductor material structure located between the second inner walls along the length direction of the gate stack structure is less than the length of the channel region. Simultaneously, the aforementioned second inner walls are non-conductive structures. Based on this, under the same dimensional conditions, compared to the parasitic channel contact between the bottom of the gate stack structure and the portion below the corresponding channel region of the semiconductor material structure in the semiconductor device provided by the present invention, the bottom of the gate stack structure is less effective in contact with the parasitic channel region of the semiconductor material structure, while the bottom of the gate stack structure in the prior art is in contact with the parasitic channel with a length equal to the width of the channel region. In this case, when the semiconductor device is in operation, the path width of the carriers that can be formed in the semiconductor material structure under the gate control effect of the gate stack structure is smaller, thereby significantly reducing the leakage current conducted through the semiconductor material structure in the source and drain regions, thus improving the leakage current of the parasitic channel in the semiconductor device. Simultaneously, the presence of the second inner wall can also prevent source-drain punch-through, improving the electrical performance of the semiconductor device.

[0008] Furthermore, the semiconductor material structure and the channel region are made of different materials. Based on this, during the fabrication of the semiconductor device provided by this invention, by utilizing the difference between the semiconductor material structure and the channel region, an etchant with an etching effect on the semiconductor material structure can be selected. This allows for selective lateral etching only on both sides of the pre-formed semiconductor material structure used to prepare the semiconductor material structure along the length of the gate stack structure, without affecting or minimally affecting the channel layer used to prepare the channel region. This improves the yield of the semiconductor device while reducing the fabrication difficulty. Moreover, the semiconductor device provided by this invention can suppress parasitic channel leakage by selectively etching the pre-formed semiconductor material structure and forming the second inner sidewall. It eliminates the need for expensive semiconductor substrates with buried oxide layers, such as silicon-on-insulator (SiI), thereby reducing the manufacturing cost of semiconductor devices including gate-around transistors.

[0009] In a second aspect, the present invention provides a process for fabricating a semiconductor device, the process comprising: first, providing a semiconductor substrate; next, forming a fin structure on the semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure includes a semiconductor material preform structure and at least one stacked layer on the semiconductor material preform structure; each stacked layer includes a sacrificial layer and a channel layer on the sacrificial layer; the material of the semiconductor material preform structure is different from the materials of the sacrificial layer and the channel layer; along the length direction of the fin structure, at least one stacked layer has a source formation region, a drain formation region, and a channel formation region located between the source formation region and the drain formation region. Next, selectively removing portions of the at least one stacked layer corresponding to the source formation region and the drain formation region. Next, along the length direction of the fin structure, etching the two side edges of the remaining sacrificial layer so that the sidewalls of the remaining portion of each sacrificial layer are recessed inward relative to the sidewalls of the remaining channel layer; and making the height of the portion of the remaining semiconductor material preform structure corresponding to the source formation region, the drain formation region, and part of the channel formation region less than the height of the remaining portion; the remaining portion of the semiconductor material preform structure forms a semiconductor material structure. Next, along the length of the channel layer, first inner sidewalls are formed on both sides of the remaining portion of each sacrificial layer, and a second inner sidewall is formed below the first inner sidewall. The thickness of the second inner sidewall is less than the thickness of the first inner sidewall. Next, source and drain regions are formed, respectively, at least on portions of the semiconductor material structure corresponding to the source and drain formation regions. Next, the remaining portion of each sacrificial layer is selectively removed to form a channel region in the channel layer above the semiconductor material structure, thereby obtaining an active structure. The active structure includes a channel region, a source region, and a drain region. Next, a gate stack structure surrounding the outer periphery of the channel region is formed on the semiconductor substrate.

[0010] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0012] Figure 1 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 1 ;

[0013] Figure 2 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 2 ;

[0014] Figure 3A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 3 ;

[0015] Figure 4 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 4 ;

[0016] Figure 5 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 5 ;

[0017] Figure 6 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 6 ;

[0018] Figure 7 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 7 ;

[0019] Figure 8 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 8 ;

[0020] Figure 9 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 9 ;

[0021] Figure 10 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 10 ;

[0022] Figure 11 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 10 one;

[0023] Figure 12 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 10 two;

[0024] Figure 13 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 10 three;

[0025] Figure 14 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 10 Four;

[0026] Figure 15 A schematic diagram of the semiconductor device fabrication process provided in the embodiments of the present invention. Figure 10 five.

[0027] Reference numerals: 11 Semiconductor substrate, 12 Source region, 13 Drain region, 14 Channel region, 15 Gate stack structure, 16 First inner sidewall, 17 Semiconductor material structure, 18 Second inner sidewall, 19 Shallow trench isolation structure, 20 Interlayer dielectric layer, 21 Fin structure, 22 Semiconductor material preform structure, 23 Stacked layer, 24 Sacrificial layer, 25 Channel layer, 26 Source formation region, 27 Drain formation region, 28 Channel formation region, 29 Semiconductor material layer, 30 Stacked material layer, 31 Fin, 32 Sacrificial gate, 33 Gate sidewall. Detailed Implementation

[0028] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0029] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0030] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0031] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0032] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0033] With the development of semiconductor technology, gate-around transistors (GMT-A) have emerged. Compared with fin field-effect transistors, GMT-A features a gate stacking structure that is formed not only on the top and sidewalls of the channel but also on the bottom of the channel. This enhances the gate control capability of GMT-A and suppresses short-channel effects, resulting in higher operating performance.

[0034] In existing gate-around transistors (GOTMTs), the parasitic channel effect caused by the sub-fins leads to degradation of electrical characteristics, which is detrimental to improving the operating performance of GOTMTs. To address this problem, those skilled in the art often use the following two methods: First, using a semiconductor substrate with a buried oxide layer, such as a silicon-on-insulator (SiI) substrate. Because the buried oxide layer is a non-conductive insulating layer, it can prevent parasitic channel leakage. Second, using a punch-through injection process to suppress parasitic channel leakage. Specifically, during the fabrication of the GOTMT, after forming the fin structure and shallow trench isolation structure on the substrate, a punch-through injection process is used to inject at least some impurity ions with a conductivity type opposite to the impurities doped in the source and drain regions into the fin structure. This forms a barrier layer in the lower middle part of the fin structure, thereby using the highly doped barrier layer to suppress parasitic channels.

[0035] However, the semiconductor substrates with buried oxide layers, such as silicon-on-insulator (SiI), used in the first method have high manufacturing costs, while the process fluctuations (e.g., implantation depth, source / drain etching depth) of the punch-through injection process in the second method have a significant impact, resulting in poor suppression of parasitic channel leakage. Furthermore, high doping concentrations can easily lead to problems such as interband tunneling, thereby reducing the operating performance of gate-around transistors.

[0036] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and its fabrication process. The semiconductor device provided in these embodiments further includes a semiconductor material structure formed on a semiconductor substrate and located below the active structure. The height of the portion of the semiconductor material structure located below the source region, drain region, and a portion of the first inner sidewall is less than the height of the remaining portion. Furthermore, the semiconductor device includes second inner sidewalls formed on both sides of the semiconductor material structure along the length of the gate stack structure. Because these second inner sidewalls are located between the semiconductor material structure and the source region, and between the semiconductor material structure and the drain region, and because the second inner sidewalls are non-conductive, the effective contact length between the bottom of the gate stack structure and the portion below the corresponding channel region of the semiconductor material structure is reduced, improving leakage current in the parasitic channel of the semiconductor device and enhancing its electrical performance.

[0037] Firstly, such as Figure 15 As shown, the semiconductor device provided in this embodiment of the invention includes: a semiconductor substrate 11, an active structure, a gate stack structure 15, a first inner sidewall 16, a semiconductor material structure 17, and a second inner sidewall 18. The active structure is formed on the semiconductor substrate 11; the active structure includes a source region 12, a drain region 13, and a channel region 14 located between the source region 12 and the drain region 13. The channel region 14 contacts both the source region 12 and the drain region 13. The gate stack structure 15 is formed on the semiconductor substrate 11 and surrounds the outer periphery of the channel region 14. The first inner sidewall 16 is formed between the gate stack structure 15 and the source region 12, and between the gate stack structure 15 and the drain region 13. A semiconductor material structure 17 is formed on a semiconductor substrate 11 and located below the active structure; there is a gap between the semiconductor material structure 17 and the channel region 14, and the semiconductor material structure 17 and the channel region 14 are made of different materials; the height of the portion of the semiconductor material structure 17 located below the source region 12, the drain region 13, and part of the first inner sidewall 16 is less than the height of the rest of its portion. A second inner sidewall 18 is formed below the first inner sidewall 16; along the length direction of the gate stack structure 15, the second inner sidewall 18 is located between the semiconductor material structure 17 and the source region 12, and between the semiconductor material structure 17 and the drain region 13; along the length direction of the gate stack structure 15, the thickness of the second inner sidewall 18 is less than the thickness of the first inner sidewall 16.

[0038] Specifically, the aforementioned semiconductor substrate can be any semiconductor material such as a silicon substrate or a germanium-silicon substrate, and it should be a semiconductor substrate with low manufacturing costs. Secondly, as... Figure 15 As shown, in the semiconductor device provided by this embodiment of the invention, the gate stack structure 15 surrounds the outer periphery of the channel region 14, therefore the semiconductor device provided by this embodiment of the invention includes a gate-to-ring transistor. Additionally, in some cases, the semiconductor substrate 11 may have an isolation region and an active region. For example... Figure 10 and Figure 15 As shown, the aforementioned semiconductor material structure 17 and active structure are formed on the active region of the semiconductor substrate 11. Furthermore, the semiconductor device provided in this embodiment of the invention also includes a shallow trench isolation structure 19 formed on the isolation region to isolate different active regions and prevent leakage. The top height of the shallow trench isolation structure 19 is less than or equal to the top height of the portion of the semiconductor material structure 17 located between the second inner sidewalls 18.

[0039] In this embodiment of the invention, the semiconductor device does not specifically limit the range of the isolation region and the active region, which can be determined according to the actual application scenario. As for the shallow trench isolation structure, the top height of the shallow trench isolation structure can be any value less than or equal to the top height of the portion of the semiconductor material structure located between the second inner sidewalls, as long as it can be applied to the semiconductor device provided in this embodiment of the invention. Furthermore, the material of the shallow trench isolation structure can be insulating materials such as SiN, Si3N4, SiO2, or SiCO.

[0040] For the aforementioned active structure, the source and drain regions can be made of any semiconductor material such as silicon, silicon-germanium, or germanium. The source and drain regions can be made of the same or different materials. For example, both the source and drain regions can be made of silicon, silicon-germanium, or germanium. Another example is that the source region can be made of silicon, and the drain region can be made of silicon-germanium.

[0041] The active structure described above includes a channel region having at least one nanostructure. Along the thickness direction of the semiconductor substrate, each nanostructure has a gap between itself and the semiconductor material structure. Furthermore, when the channel region includes at least two nanostructures, there are also gaps between adjacent nanostructures. Different nanostructures can be spaced apart along the thickness direction of the semiconductor substrate or spaced apart along the width direction of the gate stack structure. The specifications, number, and specific distribution of the nanostructures can be set according to actual needs and are not specifically limited here. For example, the channel region may include two layers of nanostructures spaced apart along the thickness direction of the semiconductor substrate. In addition, the material of the channel region can be silicon, germanium-silicon, or group III-V semiconductor materials, etc. For example, the material of the channel region can be silicon.

[0042] For the above-mentioned gate stack structure, such as Figure 15As shown, the gate stack structure 15 may include a gate dielectric layer and a gate formed at least on the outer periphery of each nanostructure through gaps. The gate dielectric layer may also be formed above the portion of the semiconductor substrate 11 and the semiconductor material structure 17 exposed in the gate formation region. Specifically, the gate dielectric layer may be made of insulating materials with low dielectric constants, such as silicon oxide or silicon nitride, or insulating materials with high dielectric constants, such as HfO2, ZrO2, TiO2, or Al2O3. The gate may be made of conductive materials such as doped polycrystalline silicon, TiN, TaN, or TiSiN. The thickness of the gate dielectric layer and the gate can be set according to actual needs and is not specifically limited here.

[0043] For the aforementioned first inner wall, the first inner wall is located between the gate stack structure and the source region, and between the gate stack structure and the drain region, and its material can be an insulating material such as silicon nitride or silicon oxynitride. In this embodiment of the invention, the thickness of the first inner wall along the length of the gate stack structure is not specifically limited.

[0044] From a material perspective, the semiconductor material structure described above can be made of any semiconductor material different from that of the channel region. For example, when the channel region is made of silicon, the semiconductor material structure can be made of non-silicon semiconductor materials such as germanium-silicon.

[0045] When the semiconductor material structure is made of germanium-silicon, the germanium content in the semiconductor material structure can be determined based on the thickness of the second inner wall and the thickness difference between the first and second inner walls in the actual application scenario, without specific limitations here.

[0046] For example, when the semiconductor material structure is made of germanium-silicon, the germanium content in the semiconductor material structure can be greater than 0 and less than or equal to 40%. For example, the germanium content in the semiconductor material structure can be 0.5%, 5%, 10%, 20%, 30%, or 40%, etc.

[0047] In terms of conductivity type, the semiconductor material structure can be an intrinsic semiconductor material structure. Because intrinsic semiconductor material structures have very poor conductivity, the source and drain regions can be isolated from the semiconductor substrate using an intrinsic semiconductor material structure, thus suppressing leakage current. Alternatively, the aforementioned semiconductor material structure can be doped with impurities, and the conductivity type of the semiconductor material structure can be opposite to that of the source or drain region. This can further improve parasitic channel leakage current and further enhance the operating performance of the semiconductor device. Furthermore, when the semiconductor material structure is doped with impurities and the conductivity type of the semiconductor material structure is opposite to that of the source or drain region, the portion of the semiconductor material structure located below the source and drain regions can form reverse-biased PN junctions with the source and drain regions, respectively, further suppressing leakage current.

[0048] When impurities are doped within the semiconductor material structure, the doping concentration of the impurities within the semiconductor material structure can be determined based on the actual application scenario, and no specific limitation is made here.

[0049] For example, the doping concentration of impurities within the aforementioned semiconductor material structure can be greater than or equal to 1E17 cm⁻¹. -3 And less than or equal to 1E19cm -3 For example, the doping concentration of impurities within a semiconductor material structure can be 1E17cm⁻¹. -3 3E17cm -3 5E17cm -3 8E17cm -3 1E18cm -3 3E18cm -3 5E18cm -3 8E18cm -3 Or 1E19cm -3 In this case, the doping concentration of impurities within the semiconductor material structure is within the above-mentioned range. This can prevent poor leakage current suppression due to low impurity doping concentration within the semiconductor material structure. In addition, it can also prevent inter-band tunneling problems between the source and drain regions due to high impurity doping concentration within the semiconductor material structure, thus ensuring high operating performance of the semiconductor device.

[0050] It is worth noting that, such as Figure 15 As shown, the aforementioned semiconductor material structure 17 includes a portion located below the source region 12 and the drain region 13, and this portion has the function of suppressing leakage current. Based on this, in the actual fabrication process, it is not necessary to additionally use epitaxial growth and etching processes to form a leakage-proof semiconductor structure below the source region 12 and the drain region 13 in order to suppress leakage current, which simplifies the semiconductor device fabrication process and can also reduce the manufacturing cost of semiconductor devices.

[0051] Regarding the thickness of the semiconductor material structure, the height of the portion located below the source region, drain region, and part of the first inner wall, as well as the height of the remaining portion of the semiconductor material structure, will affect the height of the second inner wall along the thickness direction of the semiconductor substrate, thereby affecting the effect of suppressing parasitic channel leakage based on the second inner wall. Secondly, the material of the semiconductor material structure will also affect the thickness difference between its different regions. Therefore, the height of the semiconductor material structure can be determined based on the material of the semiconductor material structure in the actual application scenario and the requirements for suppressing parasitic channel leakage.

[0052] For example, along the thickness direction of the semiconductor substrate, the maximum height of the semiconductor material structure can be greater than or equal to 10 nm and less than or equal to 40 nm. For instance, the maximum height of the semiconductor material structure can be 10 nm, 15 nm, 20 nm, 30 nm, 35 nm, or 40 nm. In this case, the maximum height of the semiconductor material structure is within the above range. This prevents a small thickness difference between the taller and shorter portions of the semiconductor material structure (i.e., a smaller height of the second inner wall), which would result in poor leakage current suppression through the second inner wall, thus contributing to higher electrical performance of the semiconductor device. Furthermore, it also prevents a large amount of consumables from being used in the fabrication of the semiconductor device due to a large maximum height, thus helping to control the manufacturing cost of the semiconductor device.

[0053] For the aforementioned second inner wall, as Figure 8 and Figure 9 As shown, the second inner wall 18 can be integrally formed with the first inner wall 16, meaning the second inner wall 18 and the first inner wall 16 can be formed simultaneously based on the same material. In this case, the material of the second inner wall 18 is the same as the material of the first inner wall 16. Alternatively, the first inner wall 16 and the second inner wall 18 can also be formed sequentially in different operation steps. In this case, the material of the second inner wall 18 can be different from or the same as the material of the first inner wall 16. When the material of the second inner wall 18 is different from the material of the first inner wall 16, the material of the second inner wall 18 can be any insulating material different from the first inner wall 16, such as silicon dioxide.

[0054] Secondly, the second inner sidewall is flush with the sidewall of the semiconductor material structure and the first inner sidewall is flush with the sidewall of the gate stack structure.

[0055] Furthermore, the semiconductor device provided in this embodiment of the invention does not specifically limit the thickness of the second inner wall along the length direction of the gate stack structure; it can be any value greater than 0 and less than the thickness of the first inner wall. As for the height of the second inner wall along the thickness direction of the semiconductor substrate, it can be determined according to the actual application scenario and is not specifically limited here.

[0056] In one example, such as Figure 15As shown, the semiconductor device provided in this embodiment of the invention may further include a gate sidewall 33 and / or an interlayer dielectric layer 20. The gate sidewall 33 is located at least on both sides of the gate stack structure 15 along its length to isolate the gate from other conductive structures, prevent leakage, and improve the electrical reliability of the semiconductor device. The interlayer dielectric layer 20 covers the semiconductor substrate 11, and its top is flush with the top of the gate stack structure 15, protecting the source region 12 and drain region 13 of the active structure from etching and cleaning operations during the removal of the sacrificial gate. The materials of the gate sidewall 33 and the interlayer dielectric layer 20 can be set according to the actual application scenario, as long as they can be applied to the semiconductor device provided in this embodiment of the invention.

[0057] As can be seen from the above, such as Figure 15As shown, the semiconductor device provided in this embodiment of the invention includes a first inner wall 16 formed between the gate stack structure 15 and the source region 12, and between the gate stack structure 15 and the drain region 13, to limit the length of the gate stack structure 15 and reduce the parasitic capacitance between the source region 12 and the drain region 13 and the gate stack structure 15, respectively, thereby improving the operating performance of the semiconductor device. Furthermore, the semiconductor device provided in this embodiment of the invention also includes a semiconductor material structure 17 formed on the semiconductor substrate 11 and located below the active structure. The height of the portion of the semiconductor material structure 17 located below the source region 12, the drain region 13, and a portion of the first inner wall 16 is less than the height of the remaining portion of itself (the remaining portion of the semiconductor material structure 17 is located below a portion of the channel region 14). At this time, there is a gap between the bottom of the first inner wall 16 and the portion of the semiconductor material structure 17 corresponding to the portion below the first inner wall 16. Based on this, the semiconductor device also includes second inner walls 18 formed on both sides of the semiconductor material structure 17 along the length direction of the gate stack structure 15, the second inner walls 18 filling the aforementioned gap. Furthermore, since the second inner wall 18 is located between the semiconductor material structure 17 and the source region 12, and between the semiconductor material structure 17 and the drain region 13, while the channel region 14 is located between the source region 12 and the drain region 13 included in the active structure, the length of the semiconductor material structure 17 located between the second inner walls 18 along the length direction of the gate stack structure 15 is less than the length of the channel region 14. Simultaneously, the aforementioned second inner wall 18 is a non-conductive structure. Based on this, under the same dimensional conditions, compared to the parasitic channel contact between the bottom of the gate stack structure included in the prior art ring-gate transistor and a length equal to the width of the channel region, the effective contact length between the bottom of the gate stack structure 15 and the portion of the semiconductor material structure 17 below the corresponding channel region 14 in the semiconductor device provided by the embodiments of the present invention is smaller. In the above situation, when the semiconductor device is in operation, the path width of the carriers that can be formed in the semiconductor material structure 17 is smaller under the gate control effect of the gate stack structure 15. This significantly reduces the leakage current conducted through the semiconductor material structure 17 between the source region 12 and the drain region 13, thus improving the leakage current of the parasitic channel in the semiconductor device. Simultaneously, the presence of the second inner wall 18 prevents source-drain punch-through, improving the electrical performance of the semiconductor device. Furthermore, the semiconductor material structure 17 and the channel region 14 are made of different materials. Based on this, as... Figure 6 and Figure 7As shown, in the process of fabricating the semiconductor device provided in this embodiment of the invention, by using different materials for the semiconductor material structure 17 and the channel region, an etchant that has an etching effect on the semiconductor material structure 17 can be selected. This allows for selective lateral etching only on both sides of the semiconductor material pre-formed structure 22 used to fabricate the semiconductor material structure 17 along the length of the gate stack structure, without affecting or minimally affecting the channel layer 25 used to fabricate the channel region. This improves the yield of the semiconductor device while reducing the fabrication difficulty. Furthermore, the semiconductor device provided in this embodiment of the invention can suppress parasitic channel leakage by selectively etching the semiconductor material pre-formed structure 22 and forming the second inner sidewall 18. This eliminates the need for expensive semiconductor substrates with buried oxide layers, such as silicon-on-insulator (SiI), thereby reducing the manufacturing cost of semiconductor devices including gate-around transistors.

[0058] Secondly, embodiments of the present invention provide a fabrication process for a semiconductor device. The following will describe, based on... Figures 1 to 15 The illustrated perspective view or cross-sectional view describes the fabrication process. Specifically, the fabrication process of this semiconductor device includes the following steps:

[0059] First, a semiconductor substrate is provided. The material and structure of the semiconductor substrate can be referred to in the previous text, and will not be repeated here.

[0060] Next, as Figure 3 As shown, a fin structure 21 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 21 includes a semiconductor material preform structure 22 and at least one stacked layer 23 located on the semiconductor material preform structure 22. Each stacked layer 23 includes a sacrificial layer 24 and a channel layer 25 located on the sacrificial layer 24. The material of the semiconductor material preform structure 22 is different from the materials of the sacrificial layer 24 and the channel layer 25, respectively. Along the length direction of the fin structure 21, at least one stacked layer 23 has a source formation region 26, a drain formation region 27, and a channel formation region 28 located between the source formation region 26 and the drain formation region 27.

[0061] Specifically, the aforementioned semiconductor material preform structure is used to fabricate the semiconductor material structure included in the semiconductor device. Therefore, the material and thickness of the semiconductor material preform structure can refer to the material and maximum height of the semiconductor material structure described above. Furthermore, the channel layer included in the aforementioned stack is used to fabricate the channel region included in the active structure described above. Therefore, the material and number of channel layers included in the stack can be determined based on the material of the channel region in the active structure, as well as the number of nanostructures included in the channel region and the arrangement of different nanostructures.

[0062] For example, if the material of the channel region is silicon, the material of the channel layer is also silicon.

[0063] For example: Figure 15 As shown, along the thickness direction of the semiconductor substrate 11, the channel region 14 includes at least two spaced-apart nanostructures. In this case, as... Figure 3 As shown, the number of channel layers 25 included in the above-mentioned stack 23 is equal to the number of nanostructure layers included in the channel region 14.

[0064] As for the sacrificial layers included in the stack, the number and material of the sacrificial layers can be determined based on the number of channel layers included in the stack, as long as each two adjacent channel layers can be separated. For example, when the stack includes two channel layers, the stack also includes two sacrificial layers.

[0065] Secondly, such as Figure 6 and Figure 7 As shown, by etching the two edge regions of each remaining sacrificial layer 24 along the length of the channel layer 25, a formation space for filling the first inner sidewall can be obtained. Furthermore, by etching the portion of the semiconductor material preform structure 22 (used to fabricate the semiconductor material structure 17) corresponding to the source formation region 26, drain formation region 27, and part of the channel formation region 28, the height of the remaining portion of the semiconductor material preform structure 22 corresponding to the source formation region 26, drain formation region 27, and part of the channel formation region 28 can be made smaller than the height of the remaining portion. After etching, the semiconductor material preform structure 22 forms the semiconductor material structure 17. The sidewall of the larger portion of this semiconductor material structure 17 is recessed inward relative to the sidewall of the remaining channel layer 25, obtaining a formation space for filling the second inner sidewall. Moreover, along the length of the gate stack structure, the thickness of the first inner sidewall is greater than the thickness of the second inner sidewall. In the above case, as... Figures 6 to 9 As shown, if etching is to be performed simultaneously on the two edge regions of each remaining sacrificial layer 24, as well as on portions of the source formation region 26, drain formation region 27, and partial channel formation region 28 corresponding to the semiconductor material preform structure 22, then the material of the sacrificial layer 24 needs to be determined based on the material of the semiconductor material structure 17 and the material of the channel layer 25. This ensures that during the etching process, the etching rate of the etchant on the two edge regions of each remaining sacrificial layer 24 is greater than the etching rate of the etchant on portions of the source formation region 26, drain formation region 27, and partial channel formation region 28 corresponding to the semiconductor material preform structure 22. For example, if both the sacrificial layer 24 and the semiconductor material preform structure 22 are made of germanium-silicon, and the germanium content in the semiconductor material preform structure 22 is less than the germanium content in the sacrificial layer 24, then the difference in germanium content between the sacrificial layer 24 and the semiconductor material preform structure 22 can be determined based on the requirements for the thickness difference between the first inner wall 16 and the second inner wall 18 in the actual application scenario; no specific limitation is made here.

[0066] When etching the corresponding parts of the semiconductor material preform structure and the sacrificial layer in different operation steps, the material of the sacrificial layer only needs to be different from the material of the semiconductor material preform structure and the channel layer. At this time, an etchant that only has an etching effect on the sacrificial layer can be selected to form a space for filling the first inner wall without affecting the semiconductor material preform structure and the channel layer (or with a small impact).

[0067] In actual fabrication processes, when the semiconductor substrate has an active region and an isolation region, the above-mentioned formation of a fin-like structure on the semiconductor substrate may include the following steps: Figure 1 As shown, along the thickness direction of the semiconductor substrate 11, a semiconductor material layer 29 and at least one stacked material layer 30 are sequentially formed on the semiconductor substrate 11. Figure 2 As shown, selective etching is performed on the semiconductor material layer and at least one stacked material layer to form fins 31 on the active region of the semiconductor substrate 11. The remaining portion of the semiconductor material layer forms a semiconductor material pre-formed structure 22, and the remaining portion of the at least one stacked material layer forms at least one stack 23. Figure 3 As shown, a shallow trench isolation structure 19 is formed on the isolation region of the semiconductor substrate 11. The top height of the shallow trench isolation structure 19 is less than or equal to the top height of the semiconductor material preform structure 22, and the portion of the fins exposed outside the shallow trench isolation structure 19 forms a fin structure 21.

[0068] Specifically, such as Figure 1 As shown, epitaxial growth and other processes can be used to sequentially form a semiconductor material layer 29 and at least one stacked material layer 30 on the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11. Then, as... Figure 2 As shown, photolithography and etching processes can be used to selectively etch the aforementioned semiconductor material layer and at least one stacked material layer to form fins 31 on the active region of the semiconductor substrate 11. Then, as... Figure 3 As shown, shallow trench isolation structures 19 can be formed on the isolation regions of the semiconductor substrate 11 using at least deposition and etching processes. The thickness and material of the shallow trench isolation structure 19 can be referred to the previous text and will not be repeated here. The portion of the fins exposed outside the shallow trench isolation structure 19 is the fin structure 21. In the fin structure 21, the range of the channel formation region 28 of at least one stack 23 can be determined based on the range of the channel region 14 in the semiconductor device. The source formation region 26 and drain formation region 27 of at least one stack 23 are the regions on both sides of its own channel formation region 28 along the length direction.

[0069] Next, as Figure 5As shown, at least one layer 23 is selectively removed from the source formation region and the drain formation region.

[0070] For example, the selective removal of portions of at least one layer corresponding to the source formation region and the drain formation region may include the steps of: Figure 4 As shown, a sacrificial gate 32 and a gate sidewall 33 are formed across a portion of the corresponding channel formation region of at least one layer of stack 23; the gate sidewall 33 is located at least on both sides of the sacrificial gate 32 along its length. Next, as... Figure 5 As shown, under the masking effect of the sacrificial gate 32 and the gate sidewall 33, at least one layer of stack 23 is selectively removed from the source formation region and the drain formation region.

[0071] Specifically, such as Figure 4 As shown, a sacrificial gate 32 and a gate sidewall 33 can be sequentially formed on the semiconductor substrate 11 using processes such as deposition and etching. The material of the sacrificial gate 32 can be polysilicon or other easily removable materials. The material of the gate sidewall 33 can be referred to the previous text. Next, a dry etching or wet etching process can be used to selectively etch at least one stacked layer 23 under the masking effect of the sacrificial gate 32 and the gate sidewall 33 to remove portions of each stacked layer 23 corresponding to the source and drain formation regions.

[0072] It should be noted that the above-described etching method is an optional removal process for portions of at least one stacked layer corresponding to the source and drain formation regions when using a gate stack structure to form a semiconductor device with a replacement gate. Those skilled in the art can also use other methods to selectively remove portions of at least one stacked layer corresponding to the source and drain formation regions. For example, after forming the fin structure, in addition to forming the sacrificial gate and gate sidewalls as described above, other mask layers with the same formation range as the sacrificial gate and gate sidewalls and providing protection can be formed. Then, under the masking effect of this mask layer, the portions of at least one stacked layer corresponding to the source and drain formation regions can be selectively removed.

[0073] Next, as Figure 6 and Figure 7 As shown, along the length of the fin structure 21, the two side edges of each remaining sacrificial layer 24 are etched so that the sidewalls of the remaining portion of each sacrificial layer 24 are recessed inward relative to the sidewalls of the remaining channel layer 25; and the height of the portion of the remaining semiconductor material preform structure 22 corresponding to the source formation region, drain formation region, and part of the channel formation region is less than the height of the rest of its own portion. The remaining portion of the semiconductor material preform structure forms the semiconductor material structure 17.

[0074] Specifically, such as Figure 6 and Figure 7As shown, dry etching or wet etching processes can be used to simultaneously etch the two side edges of each remaining sacrificial layer 24, as well as portions of the semiconductor material pre-formed structure 22 corresponding to the source formation region, drain formation region, and partial channel formation region. Alternatively, an etchant that etches only the semiconductor material pre-formed structure and each sacrificial layer can be used to etch the two side edges of each remaining sacrificial layer, as well as portions of the semiconductor material pre-formed structure corresponding to the source formation region, drain formation region, and partial channel formation region, respectively.

[0075] Next, as Figure 8 and Figure 9 As shown, along the length of the channel layer 25, a first inner wall 16 is formed on both sides of the remaining portion of each sacrificial layer 24, and a second inner wall 18 is formed below the first inner wall 16. The thickness of the second inner wall 18 is less than the thickness of the first inner wall 16.

[0076] Specifically, chemical vapor deposition and etching processes can be used to form the aforementioned first and second inner sidewalls.

[0077] It should be noted that when the first inner sidewall and the second inner sidewall are formed sequentially in different operation steps, the second inner sidewall can be formed first in the manner described above after the height of the remaining semiconductor material pre-formed structure corresponding to the source formation region, drain formation region, and part of the channel formation region is less than the height of its remaining portion; then, the two side edges of each sacrificial layer are etched to form the first inner sidewall. Alternatively, the first inner sidewall can be formed first, followed by the second inner sidewall.

[0078] Next, as Figure 10 and Figure 11 As shown, at least epitaxial growth or other processes can be used to form source region 12 and drain region 13 on at least the portions of semiconductor material structure 17 corresponding to source and drain regions, respectively. The materials of source region 12 and drain region 13 can be referred to the previous text.

[0079] Next, as Figure 12 As shown, an interlayer dielectric layer 20 covering the semiconductor substrate 11 can be formed using processes such as deposition and chemical mechanical polishing. The top of this interlayer dielectric layer 20 is flush with the top of the sacrificial gate 32. The material of the interlayer dielectric layer 20 can be referred to above.

[0080] Next, if a sacrificial gate and gate sidewall are formed across the fin structure after the fin structure is formed, then after the source and drain regions are formed on the semiconductor substrate, and before subsequent operations are performed, the fabrication process of the above-mentioned semiconductor device further includes the following steps: Figure 13 As shown, the sacrificial gate is removed to expose the remaining channel layer 25 and the remaining sacrificial layer 24.

[0081] Next, as Figure 14 As shown, dry etching or wet etching processes can be used to selectively remove the remaining portion of each sacrificial layer, so that the channel layer located above the semiconductor material structure 17 forms the channel region 14, thereby obtaining an active structure. The active structure includes the channel region 14, the source region 12, and the drain region 13.

[0082] Then, as Figure 15 As shown, a gate stack structure 15 surrounding the channel region 14 can be formed on the semiconductor substrate 11 using processes such as atomic layer deposition. The specific structure and materials of this gate stack structure 15 can be referred to the previous text and will not be repeated here.

[0083] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0084] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0085] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Semiconductor substrate, An active structure is formed on the semiconductor substrate; the active structure includes a source region, a drain region, and a channel region located between the source region and the drain region; the channel region is in contact with the source region and the drain region, respectively; A gate stack structure is formed on the semiconductor substrate and surrounds the outer periphery of the channel region; A first inner wall is formed between the gate stack structure and the source region, and between the gate stack structure and the drain region; A semiconductor material structure is formed on the semiconductor substrate and located below the active structure; a gap exists between the semiconductor material structure and the channel region, and the semiconductor material structure and the channel region are made of different materials; the height of the portion of the semiconductor material structure located below the source region, drain region, and part of the first inner wall is less than the height of the rest of its portion; A second inner wall is formed below the first inner wall; along the length of the gate stack structure, the second inner wall is located between the semiconductor material structure and the source region, and between the semiconductor material structure and the drain region; along the length of the gate stack structure, the thickness of the second inner wall is less than the thickness of the first inner wall.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor material structure is made of germanium-silicon, and the germanium content in the semiconductor material structure is greater than 0 and less than or equal to 40%; and / or, The material of the channel region is silicon.

3. The semiconductor device according to claim 1, characterized in that, Along the thickness direction of the semiconductor substrate, the maximum height of the semiconductor material structure is greater than or equal to 10 nm and less than or equal to 40 nm.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor material structure is doped with impurities, and the conductivity type of the semiconductor material structure is opposite to that of the source region or the drain region.

5. The semiconductor device according to claim 4, characterized in that, The doping concentration of impurities within the semiconductor material structure is greater than or equal to 1E17 cm⁻¹. -3 And less than or equal to 1E19cm -3 .

6. The semiconductor device according to claim 1, characterized in that, The semiconductor substrate has an active region and an isolation region; the semiconductor material structure and the active structure are formed on the active region; The semiconductor device further includes a shallow trench isolation structure formed on the isolation region, the top height of the shallow trench isolation structure being less than or equal to the top height of the portion of the semiconductor material structure located between the second inner sidewalls.

7. A process for fabricating a semiconductor device, characterized in that, include: Provide a semiconductor substrate; A fin-like structure is formed on the semiconductor substrate; Along the thickness direction of the semiconductor substrate, the fin structure includes a semiconductor material preform structure and at least one stacked layer on the semiconductor material preform structure; each stacked layer includes a sacrificial layer and a channel layer on the sacrificial layer; the material of the semiconductor material preform structure is different from the materials of the sacrificial layer and the channel layer, respectively; along the length direction of the fin structure, the at least one stacked layer has a source formation region, a drain formation region, and a channel formation region located between the source formation region and the drain formation region; Selectively remove portions of the at least one layer corresponding to the source formation region and the drain formation region; Along the length of the fin-like structure, the two side edges of each remaining sacrificial layer are etched so that the sidewalls of the remaining portion of each sacrificial layer are recessed inward relative to the sidewalls of the remaining channel layer; and the height of the portion of the remaining semiconductor material preform structure corresponding to the source formation region, the drain formation region, and part of the channel formation region is less than the height of its remaining portion; the remaining portion of the semiconductor material preform structure forms a semiconductor material structure; Along the length of the channel layer, a first inner wall is formed on both sides of the remaining portion of each sacrificial layer, and a second inner wall is formed below the first inner wall; the thickness of the second inner wall is less than the thickness of the first inner wall. The source region and the drain region are formed at least on the portions of the semiconductor material structure corresponding to the source formation region and the drain formation region, respectively. The remaining portion of each sacrificial layer is selectively removed to form a channel region in the channel layer located above the semiconductor material structure, thereby obtaining an active structure; the active structure includes the channel region, the source region, and the drain region; A gate stack structure is formed on the semiconductor substrate, surrounding the outer periphery of the channel region.

8. The semiconductor device fabrication process according to claim 7, characterized in that, The semiconductor substrate has an active region and an isolation region; The formation of the fin-like structure on the semiconductor substrate includes: Along the thickness direction of the semiconductor substrate, a semiconductor material layer and at least one stacked material layer are sequentially formed on the semiconductor substrate; Selective etching is performed on the semiconductor material layer and the at least one stacked material layer to form fins on the active region of the semiconductor substrate; the remaining portion of the semiconductor material layer is the semiconductor material preform structure, and the remaining portion of the at least one stacked material layer forms the at least one stacked layer. A shallow trench isolation structure is formed on the isolation region of the semiconductor substrate; the top height of the shallow trench isolation structure is less than or equal to the top height of the semiconductor material pre-formed structure, and the portion of the fin exposed outside the shallow trench isolation structure forms the fin structure.

9. The semiconductor device fabrication process according to claim 7, characterized in that, The selective removal of the portion of the at least one stack corresponding to the source formation region and the drain formation region includes: forming a sacrificial gate and a gate sidewall that span the portion of the at least one stack corresponding to the channel formation region; the gate sidewall is located at least on both sides of the sacrificial gate along the length direction; and then, under the masking effect of the sacrificial gate and the gate sidewall, selectively removing the portion of the at least one stack corresponding to the source formation region and the drain formation region. After forming source and drain regions respectively on at least the portions of the semiconductor material structure corresponding to the source and drain formation regions, and before selectively removing the remaining portions of each sacrificial layer, the fabrication process of the semiconductor device further includes: removing the sacrificial gate.

10. The fabrication process of the semiconductor device according to any one of claims 7 to 9, characterized in that, Both the sacrificial layer and the semiconductor material preform are made of germanium-silicon, and the germanium content in the semiconductor material preform is less than the germanium content in the sacrificial layer; and / or, The channel layer is made of silicon.

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