Refrigeration type focal plane chip and preparation method thereof

Abstract

The present application relates to the technical field of focal plane chip, and provides a preparation method of a refrigeration type focal plane chip, comprising the following steps: S1, inversely welding interconnection of a sensitive array and a readout circuit to form a plurality of pixel interconnection structures and a fence arranged outside the plurality of pixel interconnection structures, S2, removing a substrate of the sensitive array, and S3, opening the fence to make the inside of the fence communicate with the outside. The present application also provides a refrigeration type focal plane chip prepared by the above preparation method. The chip prepared by the present application is free of resin filling glue with a large thermal expansion coefficient, and the thermal stress is greatly reduced, so that the performance of the prepared chip is better. The temporary indium fence can block various solutions from entering the chip during chip processing, such as acetone, alcohol, various acid solutions and the like. In addition, the indium fence is opened after chip processing, so that the defect of chip burst during subsequent vacuum packaging is solved.

Description

Technical Field

[0001] This invention relates to the field of focal plane array (FLA) chip technology, specifically to a cooled FLA chip and its fabrication method. Background Technology

[0002] The fabrication process of the cooled infrared focal plane array chip is as follows: the sensitive array and the readout circuit are interconnected by flip soldering, the bottom is filled with resin glue, the substrate is removed, and the anti-reflection layer is deposited by vapor deposition.

[0003] In existing technologies, an intermediate layer composed of indium pillars and filler adhesive exists between the sensing array and the readout circuit. On one hand, the sandwich structure of readout circuit-intermediate layer-sensor array, due to the difference in thermal expansion coefficients, generates in-plane stress on the sensing array. On the other hand, the significant difference in thermal expansion coefficients between indium in the intermediate layer and filler adhesive generates normal stress perpendicular to the plane at their interface. The presence of either type of stress will lead to defects in the devices on the focal plane array, resulting in performance degradation. Summary of the Invention

[0004] The purpose of this invention is to provide a cooled focal plane array chip and its preparation method, which can at least solve some of the defects in the prior art.

[0005] To achieve the above objectives, embodiments of the present invention provide the following technical solution: a method for fabricating a cooled focal plane array chip, comprising the following steps:

[0006] S1, the sensitive array and readout circuit are flip-soldered together to form a multi-pixel interconnect structure and a wall surrounding the multi-pixel interconnect structure.

[0007] S2, the substrate of the sensitive array is removed.

[0008] S3, open the fence to connect the inside of the fence with the outside.

[0009] Furthermore, the enclosure includes a diffusion layer and a molten layer located on the diffusion layer, and the enclosure opens when the molten layer melts.

[0010] Furthermore, the diffusion layer is a gold sheet disposed on the readout circuit, and the fusion layer is an indium wall fixedly connected to the gold sheet.

[0011] Furthermore, the focal plane chip is subjected to heat treatment, and the molten layer spreads horizontally on the diffusion layer. At this time, the molten layer collapses and breaks in the height direction, thereby forming an opening.

[0012] Furthermore, the focal plane chip is heat-treated by baking it in an oven.

[0013] Furthermore, the width of the gold sheet is more than twice the width of the indium wall.

[0014] Furthermore, in step S2, an organic solvent is used to remove the substrate of the sensitive array.

[0015] Furthermore, the interconnect structure is an indium pillar.

[0016] Furthermore, before step S1, pixel bumps and wall material to be welded are provided on both the sensitive array and the readout circuit. During step S1, the pixel bumps on the sensitive array and the readout circuit are welded together to form a pixel interconnect structure, and the wall material on the sensitive array and the readout circuit is welded together to form a wall. After flip soldering, the pixel interconnect structure and the wall are formed synchronously.

[0017] This invention provides another technical solution: a cooled focal plane array chip, which is prepared by the above-described method for preparing a cooled focal plane array chip.

[0018] Compared with the prior art, the beneficial effects of the present invention are:

[0019] 1. Since the prepared chip does not have a resin filler with a large coefficient of thermal expansion, the thermal stress is greatly reduced, resulting in better performance of the final chip. In addition, the temporary indium wall can prevent various solutions such as acetone, alcohol, and various acids from entering the chip during chip processing. Furthermore, opening the indium wall after chip processing solves the defect of chip cracking during subsequent vacuum packaging.

[0020] 2. Indium pillars are placed on gold sheets. After heat treatment of the chip, indium and Au dissolve and diffuse with each other. Indium walls spread horizontally on the Au sheet. At this time, the indium walls will become shorter in the height direction and open up, so that the inside of the chip can be connected to the outside. The method of connecting indium pillars and Au is fast and does not require additional complicated processes. Attached Figure Description

[0021] Figure 1 This is a schematic diagram illustrating the setting of an indium wall on a gold sheet in a method for fabricating a cooled focal plane array chip according to an embodiment of the present invention.

[0022] Figure 2 for Figure 1 Enlarged view of the area circled in dashed shape;

[0023] Figure 3 This is a schematic diagram showing the indium wall breaking after heat treatment in a method for preparing a cooled focal plane array chip according to an embodiment of the present invention.

[0024] Figure 4 for Figure 3 Enlarged view of the area circled in dashed shape;

[0025] In the attached diagram, the labels are: 1-readout circuit; 2-indium pillar; 3-sensitive array; 4-wall; 5-gold sheet. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] Please see Figure 1 , Figure 2 , Figure 3 and Figure 4 This invention provides a method for fabricating a cooled focal plane array chip, comprising the following steps: S1, flip-soldering a sensitive array 3 and a readout circuit 1 to form multiple pixel interconnect structures and a perimeter wall 4 surrounding the multiple pixel interconnect structures; S2, removing the substrate of the sensitive array 3; S3, opening the perimeter wall 4 to allow communication between the inside and outside of the perimeter wall 4. In fabricating the focal plane array chip, after flip-soldering the sensitive array 3 and the readout circuit 1, before processing the focal plane array chip, the pixel interconnect structures within the chip are surrounded by the perimeter wall 4. The sealed chamber formed by the perimeter wall 4 prevents the solution from entering the chip during processing. Traditional fabrication methods typically use filler adhesive to eliminate gaps and prevent corrosion of the interconnect structures. However, due to differences in thermal expansion coefficients, stress can occur, leading to defects in the devices on the focal plane array and consequently performance degradation. Therefore, this embodiment eliminates the need for filler adhesive by using the perimeter wall 4, resulting in a high-quality focal plane array chip. Therefore, in this embodiment, an opening is made in the enclosure 4 after the chip is processed, allowing the inside of the chip to communicate with the outside and maintain the same air pressure. How to open the enclosure is also a challenge, and the following embodiment will explain this in detail.

[0028] As an optimized solution for an embodiment of the present invention, please refer to Figures 1 to 4The enclosure 4 includes a diffusion layer and a molten layer located on the diffusion layer. When the molten layer melts, the enclosure 4 opens. A gold sheet 5 is provided on the readout circuit 1, and the gold sheet 5 is the diffusion layer. The molten layer is an indium wall fixedly connected to the gold sheet 5. The molten layer is fixed on the gold sheet 5, and at room temperature, the enclosure 4 can be tightly connected to the gold sheet 5. The diffusion layer and the molten layer are a whole, which can form a sealed space within the enclosure 4. The shape of the enclosure 4 can be determined by the shape of the pixel interconnect structure, but the whole enclosure is a barrier around the outer ring of the pixel interconnect structure. For example, it can be circular, square, or other shapes. The thickness of the enclosure can also be selected according to the actual situation. This embodiment does not limit these. The reason for setting the indium wall on the gold sheet 5 and fixing the indium wall with the gold sheet 5 instead of using conventional glue is to facilitate the subsequent heating to open the indium wall. This method is a brand-new way of opening indium walls in focal plane chip fabrication.

[0029] For further optimization of the above solution, please refer to [link / reference]. Figure 3 and Figure 4 The focal plane chip is heat-treated, and the molten layer spreads horizontally on the diffusion layer. Simultaneously, the molten layer collapses and breaks in the height direction, forming an opening. In this embodiment, the enclosure 4 can be opened by heat treatment. Under accelerated temperature, indium and gold dissolve and diffuse, and the indium wall spreads horizontally on the gold sheet 5. Simultaneously, the indium wall shortens and opens in the height direction, allowing communication between the chip's interior and exterior. This opening method requires only two steps: first, placing the indium wall on the gold sheet 5; second, heating to open the indium wall. The entire process is very rapid. The gold sheet 5 is pre-set, and subsequent heating opens the indium wall without requiring additional complex procedures. Compared to existing physical methods, such as breaking the indium wall by striking it, this method makes it easier to open the indium wall without damaging the chip, greatly improving work efficiency and chip quality. Preferably, an oven baking method can be used to heat-treat the focal plane chip, making it easy to control the heating temperature.

[0030] To further optimize the above scheme, the width of the gold sheet 5 is more than twice the width of the indium wall. Controlling the width of the gold sheet 5 allows the indium wall to spread along it, facilitating its diffusion and opening. Ultimately, the indium wall can be partially retained or completely removed.

[0031] As an optimized embodiment of the present invention, in step S3, an organic solvent is used to remove the substrate of the sensitive array 3. In this embodiment, organic solvents such as acetone, alcohol, and various acids are used to remove the chip substrate and perform other related processes, which will not be described in detail here. These organic solvents will corrode the indium pillars 2, but the indium pillars 2 are prevented from being damaged by the enclosure 4.

[0032] As an optimized embodiment of the present invention, after opening the enclosure 4, subsequent processing steps such as anti-reflective layer evaporation are completed to obtain the final focal plane chip product.

[0033] As an optimized embodiment of the present invention, the pixel interconnection structure is an indium pillar 2. The indium pillar 2 serves as the pixel bump.

[0034] As an optimized embodiment of the present invention, before step S1, pixel bumps and wall material to be soldered are provided on both the sensitive array 3 and the readout circuit 1. During step S1, the pixel bumps on the sensitive array 3 and the readout circuit 1 are soldered together to form a pixel interconnect structure, and the wall material on the sensitive array 3 and the readout circuit 1 is soldered together to form a wall 4. After flip soldering, the pixel interconnect structure and the wall are formed synchronously. During fabrication, the indium pillar 2 and the indium wall are formed synchronously after flip soldering, improving work efficiency.

[0035] Please see Figure 1 , Figure 2 , Figure 3 and Figure 4 This invention provides a cooled focal plane array chip, prepared by the above-described method. The resulting focal plane array chip has no filler adhesive, significantly reducing thermal stress and improving chip performance. By using a temporary indium wall to prevent various solutions from entering the chip during processing, and then opening the indium wall, the final product has only a small amount of indium wall or has the indium wall completely removed, thus solving the defect of chip cracking during subsequent vacuum packaging.

[0036] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for fabricating a cooled focal plane array chip, characterized in that, Includes the following steps: S1, the sensitive array and readout circuit are flip-soldered together to form a multi-pixel interconnect structure and a wall surrounding the multi-pixel interconnect structure. S2, the substrate of the sensitive array is removed. S3, Open the fence to connect the inside of the fence with the outside. The enclosure includes a diffusion layer and a molten layer located on the diffusion layer. When the molten layer melts, the enclosure opens. The diffusion layer is a gold sheet disposed on the readout circuit, and the molten layer is an indium wall fixedly connected to the gold sheet. The focal plane chip is heat-treated, and the molten layer spreads horizontally on the diffusion layer. At this time, the molten layer collapses and breaks in the height direction, thereby forming an opening.

2. The method for preparing a cooled focal plane array chip as described in claim 1, characterized in that: The focal plane chip is heat-treated by baking it in an oven.

3. The method for fabricating a cooled focal plane array chip as described in claim 1, characterized in that: The width of the gold sheet is more than twice the width of the indium wall.

4. The method for fabricating a cooled focal plane array chip as described in claim 1, characterized in that: In step S2, an organic solvent is used to remove the substrate of the sensitive array.

5. The method for fabricating a cooled focal plane array chip as described in claim 1, characterized in that: The pixel interconnect structure is an indium pillar.

6. The method for fabricating a cooled focal plane array chip as described in claim 1, characterized in that: Before step S1, pixel bumps and wall material to be welded are provided on both the sensitive array and the readout circuit. During step S1, the pixel bumps on the sensitive array and the readout circuit are welded together to form a pixel interconnect structure, and the wall material on the sensitive array and the readout circuit is welded together to form a wall. After flip soldering, the pixel interconnect structure and the wall are formed synchronously.

7. A cooled focal plane array chip, characterized in that: It is prepared by the method for preparing a cooled focal plane array chip as described in any one of claims 1-6.

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