Event-driven adaptive transient response enhancement circuit and ldo chip

Abstract

The application discloses an event-driven adaptive transient response enhancement circuit and an LDO chip, the event-driven adaptive transient response enhancement circuit comprising a transient detection circuit, an adaptive strength control circuit and a charge pump, the input end of the adaptive strength control circuit being connected with the output end of the transient detection circuit to convert a transient response digital signal into a continuously changing analog quantity; the output end of the adaptive strength control circuit being connected with the control end of the charge pump to adaptively adjust the drain current of the charge pump according to the continuously changing analog quantity. The application can solve the trade-off problem among the transient response, stability and power consumption performance of the existing transient response enhancement circuit, and the LDO chip adopting the event-driven adaptive transient response enhancement circuit can realize ultra-low power consumption while obtaining fast transient response on the premise of maintaining system stability, which is very helpful for low-power Internet of Things application.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and particularly to an event-driven adaptive transient response enhancement circuit and an LDO chip. Background Technology

[0002] Power management chips play a crucial role in modern electronic devices, responsible for providing stable power voltages to ensure normal operation. Among these, low-dropout linear regulators (LDOs) hold a significant position, widely used in many electronic products, especially high-performance and noise-sensitive applications, due to their simplicity and low noise levels, ensuring reliable power supply under various load conditions. Capacitorless LDOs (OCL-LDOs) eliminate the need for bulky external capacitors, reducing cost and increasing integration, thus gaining widespread use in portable Internet of Things (IoT) devices. However, OCL-LDO regulators present a trade-off between power consumption and other important design parameters such as loop stability and transient response performance. Furthermore, in energy-efficient IoT devices, which are typically in standby mode, ultra-low quiescent current (If) in the nanoamp range is required to extend battery life. Q In addition, these devices require fast response during state transitions, which necessitates that the power management chip LDO exhibit rapid transient response during state transitions and provide excellent dynamic performance in active states.

[0003] In the design of an LDO without external capacitors, since there are no large external capacitors to store charge and compensate for output voltage changes, the LDO's response speed relies entirely on its internal regulation circuitry. Achieving ultra-low power consumption by reducing the quiescent current to the nanoamp level sacrifices unity-gain bandwidth, potentially leading to a slower transient response. This is because reducing the quiescent current increases the impedance of each node, reduces transconductance, and causes poles and zeros to shift to lower frequencies, resulting in a reduced bandwidth. Furthermore, the slew rate of internal nodes is proportional to the bias current of the corresponding branch; a lower quiescent current leads to a lower slew rate. Therefore, achieving a fast transient response in an nA-LDO becomes a major design challenge.

[0004] Existing technologies include several transient response enhancement techniques to achieve fast transient response or low I / O. Q For example, adaptive current biasing technology, such as Figure 1aAs shown, this structure allows the circuit to maintain a low quiescent current during steady-state operation, while immediately increasing the driver current to enhance transient response in the event of a transient event. However, since this current is not directly injected into the gate of the power transistor, this approach still exhibits relatively poor undershoot. Furthermore, excessively low output voltage caused by transient undershoot can lead to device instability or even system failure. Event-driven charge pump (CP) structures have been introduced, such as... Figure 1b As shown, this structure not only allows transient current to be directly injected into the gate of the power transistor to enhance transient response, but also keeps it off during steady-state operation, thereby reducing quiescent current. However, using an event-driven charge pump structure requires a sensitive transient detection circuit, typically implemented using a voltage comparator (these conventional comparators sacrifice large current to obtain an accurate voltage detection threshold), which consumes considerable additional power. In low-power solutions, while the accuracy of the voltage threshold can be sacrificed, the system introduces a significant delay, which can lead to stability issues. To ensure system stability under low-power conditions, a portion of the transient response is usually sacrificed. This means that the charge pump strength needs to be relatively low, resulting in inefficient utilization of its potential and thus an insufficiently fast transient response. Therefore, transient response enhancement circuits in the prior art still suffer from a trade-off between transient response, stability, and power consumption performance. Summary of the Invention

[0005] This invention aims to address at least one of the technical problems existing in the prior art. To this end, this invention proposes an event-driven adaptive transient response enhancement circuit and an LDO chip, which can solve the trade-off between transient response, stability, and power consumption performance in existing transient response enhancement circuits. It can achieve ultra-low power consumption and fast transient response while maintaining system stability.

[0006] An event-driven adaptive transient response enhancement circuit according to a first aspect of the present invention includes: a transient detection circuit for detecting changes in the output voltage of an LDO chip and outputting a transient response digital signal; an adaptive intensity control circuit, the input of which is connected to the output of the transient detection circuit for converting the transient response digital signal into a continuously varying analog quantity; and a charge pump, the output of which is connected to the control terminal of the charge pump for adaptively adjusting the drain current of the charge pump pull-up / pull-down transistors according to the continuously varying analog quantity, thereby obtaining an adaptive charge pump output adjustment signal.

[0007] The event-driven adaptive transient response enhancement circuit according to a first aspect embodiment of the present invention has at least the following beneficial effects:

[0008] This invention incorporates an adaptive intensity control circuit between the transient detection circuit and the charge pump. This circuit converts the digital signal generated by the transient detection circuit into a continuously varying analog signal, adaptively adjusting the gate signals of the charge pump's pull-up / pull-down transistors, and consequently, the gate signals of the MOS transistors in the LDO chip. Because of this adaptive intensity control circuit, the digital signal is converted into an analog signal with continuously varying effective levels. During multiple triggers, the circuit's output voltage exhibits a gradually decaying trend, and its effective level acting on subsequent circuits can be considered a gradually decaying, continuously varying envelope curve, leading to system convergence. This invention uses an adaptive intensity control circuit to control the charge pump intensity, making the charge pump's output current more controllable and fundamentally avoiding the large-signal oscillation problem caused by traditional event-driven charge pump structures. Due to the use of an adaptive intensity-controlled charge pump circuit, the transient detection circuit in this invention does not require a precise voltage detection threshold. This reduces the requirements for the comparator of the transient detection current without sacrificing other performance characteristics, providing faster comparison speeds and lower power consumption. This invention breaks through the traditional trade-off between transient response, stability, and power consumption performance in transient response enhancement circuits, and can achieve ultra-low power consumption and fast transient response while maintaining system stability.

[0009] According to some embodiments of the present invention, the adaptive intensity control circuit includes a MOSFET M N1 MOSFET M N2 MOSFET M N3 MOSFET M P1 MOSFET M P2 MOSFET M P3 Capacitor C DO Capacitor C UP Resistor R1, Resistor R2, Power supply terminal V BAT Grounding terminal VSS, output terminal V DO2 and output terminal V UP2 ;

[0010] The first output terminal of the transient detection circuit is connected to capacitor C. UP Connect one end of the resistor R1 and the MOSFET M respectively. P1 The gate of the MOS transistor M N2 The source and output terminals V UP2 The MOS transistor M P1 The drains of the MOSFETs are respectively connected to the M N2 The gate and the MOS transistor M N1 The drain of the MOS transistor M N1 The source is grounded, and the power supply terminal V BATConnect the other end of the resistor R1 and the MOSFET M respectively. P1 The source and the MOS transistor M N2 The drain, the output terminal V UP2 Connect one control terminal of the charge pump;

[0011] The second output terminal of the transient detection circuit is connected to capacitor C. DO Connect one end of the resistor R2 and the MOSFET M respectively. N3 The gate of the MOS transistor M P3 The source and output terminals V UO2 The MOS transistor M N3 The drains of the transistors are respectively connected to the MOS transistor M. P3 The gate and the MOS transistor M P2 The drain of the MOS transistor M P2 The source is connected to the power supply terminal V. BAT The ground terminal VSS is connected to the other end of the resistor R2 and the MOSFET M. N3 The source and the MOS transistor M P3 The drain, the output terminal V UO2 Connect to another control terminal of the charge pump.

[0012] According to some embodiments of the present invention, the charge pump includes a pull-up transistor M. UP and pull-down transistor M DO The pull-up transistor M UP The source is connected to the power supply terminal V. BAT The pull-up transistor M UP The drain of the pull-down transistor M is connected. DO The drain of the transistor serves as the output terminal of the charge pump, and the pull-down transistor M... DO The source of the transistor is connected to the ground terminal VSS, and the pull-up transistor M UP The gate is connected to the output terminal V. UP2， The pull-down transistor M DO The gate is connected to the output terminal V. DO2 .

[0013] According to some embodiments of the present invention, the transient detection circuit employs a current comparator.

[0014] According to a second aspect of the present invention, an LDO chip includes a MOSFET M p The dynamic bias error amplifier loop and the aforementioned event-driven adaptive transient response enhancement circuit, wherein the output of the dynamic bias error amplifier loop is connected to the MOS transistor M. p The gate of the MOS transistor M pThe output terminals are respectively connected to the input terminal of the transient detection circuit and the feedback terminal of the dynamic bias error amplifier loop. The output terminal of the charge pump is connected to the output terminal of the dynamic bias error amplifier loop and the MOS transistor M. p Between the gates.

[0015] The LDO chip according to the second aspect of the present invention has at least the following beneficial effects:

[0016] This invention incorporates an adaptive intensity control circuit between the transient detection circuit and the charge pump. This circuit converts the digital signal generated by the transient detection circuit into a continuously varying analog signal, adaptively adjusting the gate signals of the charge pump's pull-up / pull-down transistors, and consequently, the gate signals of the MOS transistors in the LDO chip. Because of this adaptive intensity control circuit, the digital signal is converted into an analog signal with continuously varying effective levels. During multiple triggers, the output voltage of this circuit exhibits a gradually decaying trend, and its effective level acting on subsequent circuits can be considered as a gradually decaying, continuously varying envelope curve, leading to system convergence. This invention uses an adaptive intensity control circuit to control the charge pump intensity, making the output current more controllable and fundamentally avoiding the large-signal oscillation problem caused by traditional event-driven charge pump structures. Due to the use of an adaptive intensity-controlled charge pump circuit, the transient detection circuit in this invention does not require a precise voltage detection threshold, reducing the requirements for the transient detection current comparator without sacrificing other performance characteristics, and providing faster comparison speeds and lower power consumption. This invention breaks through the traditional trade-off between transient response, stability, and power consumption performance in transient response enhancement circuits, and can achieve ultra-low power consumption and fast transient response while maintaining system stability.

[0017] According to some embodiments of the present invention, the MOS transistor M p It is an NMOS transistor.

[0018] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments, wherein:

[0020] Figure 1a This is a circuit diagram of an LDO chip with an adaptive bias current structure in the prior art.

[0021] Figure 1b This is a circuit diagram of an LDO chip with an event-driven charge pump structure in the prior art;

[0022] Figure 2 This is a circuit diagram of the adaptive intensity control circuit in an embodiment of the present invention;

[0023] Figure 3 This is a circuit diagram of the LDO chip in an embodiment of the present invention;

[0024] Figure 4a The load transient response waveform of an LDO chip that does not employ a charge pump loop structure in the prior art;

[0025] Figure 4b The image shows the load transient response waveform of an LDO chip that uses a conventional event-driven adaptive transient response enhancement circuit in the prior art.

[0026] Figure 4c The image shows the load transient response waveform of an LDO chip using the event-driven adaptive transient response enhancement circuit of this invention. Detailed Implementation

[0027] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0028] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, etc., are based on the orientation or positional relationship shown in the drawings and are only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0029] In the description of this invention, "multiple" refers to two or more. The use of "first" and "second" is for distinguishing technical features only and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features or their sequential relationship.

[0030] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0031] Reference Figure 3As shown, an event-driven adaptive transient response enhancement circuit of the present invention includes: a transient detection circuit, an adaptive intensity control circuit, and a charge pump. The input terminal of the transient detection circuit is connected to the MOS transistor in the LDO chip, used to detect the output voltage change of the LDO chip and output a transient response digital signal UP / DN; the input terminal of the adaptive intensity control circuit is connected to the output terminal of the transient detection circuit to convert the transient response digital signal UP / DN into a continuously changing analog quantity; the output terminal of the adaptive intensity control circuit is connected to the control terminal of the charge pump to adaptively adjust the drain current of the charge pump pull-up / pull-down transistor according to the continuously changing analog quantity, thereby obtaining an adaptive charge pump output adjustment signal; the output terminal of the charge pump is connected to the gate of the power transistor in the LDO chip to inject transient current into the gate of the power transistor.

[0032] refer to Figure 2 As shown, the adaptive intensity control circuit in this embodiment of the invention includes a MOS transistor M N1 MOSFET M N2 MOSFET M N3 MOSFET M P1 MOSFET M P2 MOSFET M P3 Capacitor C DO Capacitor C UP Resistor R1, Resistor R2, Power supply terminal V BAT Grounding terminal VSS, output terminal V DO2 and output terminal V UP2 ;

[0033] The first output terminal of the transient detection circuit is connected to capacitor C. UP Connect one end of resistor R1 and MOSFET M respectively. P1 Gate, MOSFET N2 The source and output terminals V UP2 The transient detection circuit outputs a digital UP signal through the first output terminal, and the MOSFET M P1 The drains of the transistors are connected to the MOSFET M. N2 The gate and MOSFET M N1 The drain of the MOSFET M N1 The source of the MOSFET is grounded. N1 The gate is connected to the bias voltage source V. BIN Power supply terminal V BAT Connect the other end of resistor R1 and MOSFET M respectively. P1 The source and MOSFET M N2 The drain, the output terminal V UP2 Pull-up transistor M connected to the charge pump UP The gate;

[0034] The second output terminal of the transient detection circuit is connected to capacitor C. DO Connect one end of resistor R2 and MOSFET M respectively. N3 Gate, MOSFET P3 The source and output terminals V UO2 The transient detection circuit outputs a digital DN signal through the second output terminal, and the MOSFET M N3 The drains of the transistors are connected to the MOSFET M. P3 The gate and MOSFET M P2 The drain of the MOSFET M P2 The source terminal is connected to the power supply terminal V. BAT MOS transistor M P2 The gate is connected to the bias voltage source V. BIP The ground terminal VSS is connected to the other end of resistor R2 and MOSFET M. N3 The source and MOSFET M P3 The drain, the output terminal V UO2 Pull-down transistor M connected to the charge pump DO The gate.

[0035] The following explains the specific working principle of the adaptive intensity control circuit:

[0036] refer to Figure 2 and Figure 3 As shown, MOS transistor M P2 MOSFET M P3 and MOSFET M N3 In steady state, the charge pump pull-down transistor M DO A high impedance is established on the gate, which helps capacitor C DO High coupling efficiency. V OUT For MOSFET M P The voltage terminal between the transient detection circuit input and the transient detection circuit input terminal, in V OUT Taking an overshoot as an example, when V OUT When an overshoot occurs, the transient detection circuit detects the output voltage of the LDO chip and generates a digital DN signal with a rising edge. The DN signal passes through capacitor C. DO Rapidly coupled to MOSFET M N3 and charge pump pull-down transistor M DO The gate of the charge pump pull-down transistor M. DO It can quickly lower V G , making V OUT Adjustments and recovery began quickly. Simultaneously, the MOSFET M... N3 Pull low MOSFET M P3 The gate of the transistor M is pulled down by the charge pump. DO A low-impedance path is established from the gate to ground VSS, generating a continuously varying, adaptively adjusted gate control signal V. DO2That is, M. DO The gate impedance decreases, I G Therefore, it decreases. Once V is determined OUT It has been restored; the falling edge of DN pulls down the charge pump transistor M. DO The gate is coupled to a negative voltage, thereby generating enough voltage to turn off the charge pump pull-down transistor M. DO Potential V DO2 To stop CP. Due to capacitor C DO This negative voltage can pull down transistor M in the charge pump. DO The time stored on the gate is much longer than the turn-off delay time t. D When the next digital DN signal arrives, the charge pump pulls down transistor M. DO The gate remains at a negative voltage. The pull current I... G The trigger will be smaller than the previous one to ensure the stability of CP. Because I G It will decrease after each CP trigger within a short period of time, and the system will eventually converge after several triggers due to self-decay.

[0037] It should be understandable that, similarly, when V OUT When an overshoot occurs, the transient detection circuit detects the output voltage of the LDO chip and generates a digital UP signal with a falling edge. The UP signal passes through capacitor C. UP Rapidly coupled to MOSFET M P1 and charge pump pull-up transistor M UP The gate of the charge pump pull-up transistor M. UP It can quickly raise the V-shape. G , making V OUT Adjustments and recovery began quickly. Simultaneously, the MOSFET M... P1 Pull low MOSFET M N2 The gate of the transistor M is pulled up from the charge pump. UP Gate to power supply V BAT A low-impedance path was established to generate a continuously varying, adaptively adjusted gate control signal V. UP2 That is, the charge pump pull-up transistor M. UP gate voltage V UP2 It will gradually decrease, I G Therefore, it decreases. Once V is determined OUT It has been restored; the rising edge of UP pulls up the charge pump transistor M. UP The gate is coupled to a high level, generating enough to turn off the charge pump pull-up transistor M. UP The potential is set, and CP is stopped in time to ensure the system converges and stabilizes.

[0038] Therefore, the adaptive intensity control circuit in this invention can convert the digital signals UP\DN generated by the transient detection circuit into continuously changing analog signals V.UP2 \V DO2 Adaptively adjust the charge pump pull-up transistor M UP and pull-down transistor M DO The gate signal is used to adaptively adjust the MOSFET M in the LDO chip. P The gate signal. During multiple triggers, due to capacitor C DO C UP The potential holding effect means that the initial level of the secondary and subsequent trigger pulses is the potential at the end of the previous trigger, thus exhibiting a gradual self-decaying trend. The effective level acting on the gate of the charge pump transistor can be regarded as a continuously changing envelope curve. Compared to a fixed-level digital signal, this effect fundamentally avoids large-signal oscillations.

[0039] It should be noted that the transient detection circuit in this invention can achieve low-power operation. The low-power transient detector is powered by an internal voltage regulator, and the highest level of the output signal DN and the lowest level of UP are respectively used to make M DO、 M UP The voltage operating in the saturation region. M DO and M UP The transistor's output current becomes more controllable. Thanks to the adaptive intensity control charge pump circuit proposed in this invention, the transient detection circuit does not require setting a precise voltage detection threshold. Therefore, the transient detection circuit does not need to use a conventional voltage comparator, as voltage comparators sacrifice large current to achieve a precise voltage detection threshold. Instead, the transient detection circuit in this application can employ a current comparator, which provides faster comparison speed and lower power consumption. A smaller threshold also allows for more precise control of the charge pump.

[0040] Therefore, the transient detection circuit in this application can use a current comparator instead of a traditional voltage comparator, providing faster comparison speed and lower power consumption without sacrificing other performance characteristics. It should be understood that the addition of an adaptive intensity control circuit in this application broadens the comparator selection range for the transient detection circuit; obviously, a traditional voltage comparator could also be used for the transient detection circuit in this application.

[0041] It should be noted that the charge pump of the present invention consists of two voltage-controlled current sources, namely pull-up transistors M. UP and pull-down transistor M DO During operation, both transistors are in the saturation region, and the input control signal of the charge pump is an analog signal, which is significantly different from the transient enhancement circuit of the traditional event-driven charge pump.

[0042] refer to Figure 3 As shown, the present invention also relates to an LDO chip, including a MOS transistor M pThe dynamic bias error amplifier loop and the event-driven adaptive transient response enhancement circuit of the above embodiments, wherein the dynamic bias error amplifier loop includes an error amplifier and a capacitor C G Resistance R OUT and capacitor C O The output of the error amplifier is connected to the MOS transistor M. p The gate of the MOSFET M p The source terminals are connected to the input terminal of the transient detection circuit and the inverting terminal of the error amplifier, respectively. The charge pump pull-up transistor M... UP and pull-down transistor M DO The drains of both are connected to the output of the error amplifier and the MOSFET M. p Between the gates, the output of the error amplifier is connected through capacitor C. G Grounded, the non-inverting input of the error amplifier is connected to the reference voltage V. REF The inverting input of the error amplifier is connected in parallel with resistors R. OUT and capacitor C O Connect to the ground terminal VSS.

[0043] It should be noted that, in order to improve transient response, the MOSFET M in this invention... p An NMOS transistor is used. NMOS transistors have higher carrier mobility than PMOS transistors. In power management integrated circuits such as those used in battery-powered systems, the higher gate voltage V required for proper NMOS operation can be achieved by powering the error amplifier and charge pump. G These power supplies can come from battery V. BAT .

[0044] The LDO chip of the present invention applies the event-driven adaptive transient response enhancement circuit in the above embodiments, which can effectively manage large load changes.

[0045] When a state transition event occurs, that is, during a transient moment, the transient detection circuit detects the change in output voltage and converts the change in output voltage into a digital control signal UP\DN. Then, the adaptive intensity control circuit converts the digital control signal UP\DN into a continuously changing, adaptive gate control signal V. UP2 \V DO2 This controls the gates of the charge pump's pull-up and pull-down transistors, adaptively adjusting the charge pump's pull-up or pull-down current. Subsequently, the charge pump drives the power transistors to regulate the output voltage.

[0046] This invention adaptively adjusts the pull-up or drain current of the charge pump during transient periods (Ip). GThis allows for dynamic control of the charge pump's strength, fundamentally alleviating the trade-offs inherent in traditional event-driven transient enhancement circuit-based LDOs. Furthermore, it includes a dynamic bias error amplifier loop for precise voltage adjustment.

[0047] This invention utilizes an adaptive intensity-controlled charge pump circuit mechanism to achieve optimal recovery rates even with low threshold voltages and slow detection circuitry. The design also employs dynamic biasing technology for the error amplifier. After transient triggering, the bias current of the error amplifier dynamically increases to improve the speed of precise voltage regulation.

[0048] refer to Figures 4a-4c The following are key transient waveforms for three types of LDO chips. Figure 4a The waveform diagram shows an LDO chip without a transient response enhancement circuit. Due to the lack of a transient response enhancement circuit, the recovery time of the LDO is relatively long. Figure 4b The LDO chip uses a traditional event-driven adaptive transient response enhancement circuit, which has a fast response speed, but it faces stability problems caused by the delay of the detection circuit. Figure 4c The waveform diagram shows the LDO chip of the event-driven transient enhancement circuit with adaptive intensity control of the present invention. It not only solves the stability problem, but also achieves a fast voltage recovery speed with extremely low quiescent current.

[0049] In summary, this invention incorporates an adaptive intensity control circuit between the transient detection circuit and the charge pump. This circuit converts the digital signal generated by the transient detection circuit into a continuously varying analog signal, adaptively adjusting the gate signals of the charge pump's pull-up / pull-down transistors, and consequently, the gate signals of the MOS transistors in the LDO chip. Because of this adaptive intensity control circuit, the digital signal is converted into an analog signal with continuously varying effective levels. During multiple triggers, the output voltage of this circuit exhibits a gradually decaying trend, and its effective level acting on subsequent circuits can be considered as a gradually decaying, continuously varying envelope curve, leading to system convergence. This invention uses an adaptive intensity control circuit to control the charge pump intensity, making the output current more controllable and fundamentally avoiding the large-signal oscillation problem caused by traditional event-driven charge pump structures. Due to the use of an adaptive intensity-controlled charge pump circuit, the transient detection circuit in this invention does not require a precise voltage detection threshold, reducing the requirements for the transient detection current comparator without sacrificing other performance characteristics, and providing faster comparison speeds and lower power consumption. This invention breaks through the trade-off between transient response, stability, and power consumption performance in traditional transient response enhancement circuits. The LDO using this event-driven adaptive transient response enhancement circuit can achieve ultra-low power consumption and fast transient response while maintaining system stability, which is very helpful for low-power IoT applications.

[0050] The LDO chip in this application incorporates the event-driven adaptive transient response enhancement circuit of this invention to effectively manage large load changes. This is achieved by adaptively adjusting I during transient periods. G This allows for dynamic control of the charge pump intensity, fundamentally alleviating the trade-offs in traditional LDO chips based on event-driven transient enhancement circuits. It also achieves rapid voltage recovery with extremely low quiescent current.

[0051] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. An event-driven adaptive transient response enhancement circuit, characterized in that, include: Transient detection circuit, which is used to detect the output voltage change of LDO chip and output transient response digital signal; An adaptive intensity control circuit, wherein the input terminal of the adaptive intensity control circuit is connected to the output terminal of the transient detection circuit for converting the transient response digital signal into a continuously changing analog quantity; The output of the adaptive intensity control circuit is connected to the control terminal of the charge pump to adaptively adjust the drain current of the charge pump pull-up / pull-down transistor according to the continuously changing analog quantity, thereby obtaining an adaptive charge pump output adjustment signal. The adaptive intensity control circuit includes a MOSFET M N1 MOSFET M N2 MOSFET M N3 MOSFET M P1 MOSFET M P2 MOSFET M P3 Capacitor C DO Capacitor C UP Resistor R1, Resistor R2, Power supply terminal V BAT Grounding terminal VSS, output terminal V DO2 and output terminal V UP2 ; The first output terminal of the transient detection circuit is connected to capacitor C. UP Connect one end of the resistor R1 and the MOSFET M respectively. P1 The gate of the MOS transistor M N2 The source and output terminals V UP2 The MOS transistor M P1 The drains of the MOSFETs are respectively connected to the M N2 The gate and the MOS transistor M N1 The drain of the MOS transistor M N1 The source is grounded, and the power supply terminal V BAT Connect the other end of the resistor R1 and the MOSFET M respectively. P1 The source and the MOS transistor M N2 The drain of the output terminal V UP2 Connect one control terminal of the charge pump; The second output terminal of the transient detection circuit is connected to capacitor C. DO Connect one end of the resistor R2 and the MOSFET M respectively. N3 The gate of the MOS transistor M P3 The source and output terminals V DO2 The MOS transistor M N3 The drains of the MOSFETs are respectively connected to the M P3 The gate and the MOS transistor M P2 The drain of the MOS transistor M P2 The source is connected to the power supply terminal V. BAT The ground terminal VSS is connected to the other end of the resistor R2 and the MOSFET M. N3 The source and the MOS transistor M P3 The drain of the output terminal V DO2 Connect to another control terminal of the charge pump; The charge pump includes a pull-up transistor M. UP and pull-down transistor M DO The pull-up transistor M UP The source is connected to the power supply terminal V. BAT The pull-up transistor M UP The drain of the pull-down transistor M is connected. DO The drain of the transistor serves as the output terminal of the charge pump, and the pull-down transistor M... DO The source of the transistor is connected to the ground terminal VSS, and the pull-up transistor M UP The gate is connected to the output terminal V. UP2， The pull-down transistor M DO The gate is connected to the output terminal V. DO2 .

2. The event-driven adaptive transient response enhancement circuit according to claim 1, characterized in that, The transient detection circuit employs a current comparator.

3. An LDO chip, characterized in that, Including MOSFET M p The dynamic bias error amplifier loop and the event-driven adaptive transient response enhancement circuit according to any one of claims 1 to 2, wherein the output terminal of the dynamic bias error amplifier loop is connected to the MOS transistor M. p The gate of the MOS transistor M p The output terminals are respectively connected to the input terminal of the transient detection circuit and the feedback terminal of the dynamic bias error amplifier loop. The output terminal of the charge pump is connected to the output terminal of the dynamic bias error amplifier loop and the MOS transistor M. p Between the gates.

4. The LDO chip according to claim 3, characterized in that, The MOS transistor M p It is an NMOS transistor.

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