A DC-DC converter

Abstract

This invention belongs to the field of DC-DC converter control technology, and particularly relates to a DC-DC converter. The invention includes a DC input power supply V. IN First switch S1, second switch S2, third switch S3, fourth switch S4, fifth switch S5, inductor L, flying capacitor C F and output capacitor C L By applying different control methods to five switches to achieve different operating modes, this invention can function as a buck-boost converter, eliminating the right-half-plane zero point of traditional buck-boost converters and greatly improving transient response. As a buck-boost converter, the output voltage of this invention can be greater than 2*V. IN And not limited to 0 to 2*V IN The output voltage range is wide; furthermore, this invention can also be used as a buck converter with no minimum duty cycle limitation, achieving a very small Vo. OUT / V IN Depending on the different input and output voltage relationships, this invention can also insert a pass-through state in the buck-boost converter or operate in buck mode to achieve high efficiency in different voltage ranges.

Description

Technical Field

[0001] This invention belongs to the field of DC-DC converter control technology, and particularly relates to a DC-DC converter. Background Technology

[0002] Traditional four-switch Buck-Boost, such as Figure 2 As shown. When it operates in continuous conduction mode (CCM), it has two operating phases: one is the D phase (as shown in the image). Figure 3 Inductor L stores energy, while load R... L Relying solely on the output capacitor C OUT Provides energy; the second is the 1-D stage (such as...) Figure 4 Inductor L releases energy, and part of the released energy is used to replenish the output capacitor C. OUT The energy consumed in stage D is partly used to power the load R. L It provides energy. In other words, under stable operating conditions, the inductor L stores the load R during the D phase. L The energy required throughout the entire cycle (i.e., stage D and stage 1-D) is released in stage 1-D, which is "store energy first, then release energy".

[0003] However, when the load R L When the load current suddenly decreases, that is, when the load current suddenly increases, the load R L The energy required throughout the cycle increases, and the controller ( Figures 2-4 (Not shown in the diagram) This increases the duration of stage D to allow inductor L to store more energy to meet the load R. L The demand is met, but increasing the duration of the D stage leads to a shorter duration of the 1-D stage. Since the inductor's energy increase requires several cycles, the energy released by the inductor in the 1-D stage actually decreases in the short term, resulting in a decrease in the output voltage V. OUT First, the voltage decreases. As the inductor's energy gradually increases, the energy released by the inductor in the 1-D stage increases, and the output voltage gradually rises until it returns to its original value. This is the behavior of the right half-plane zero in the time domain, which is essentially caused by the discontinuity between the inductor current and the load current.

[0004] In the frequency domain, a right-half-plane zero increases the loop gain while decreasing the phase, which severely compromises loop stability. Therefore, for loops with right-half-plane zeros, to minimize the impact of the right-half-plane zeros when designing the loop's unity-gain bandwidth, the bandwidth is generally designed at 1 / 7 to 1 / 10 of the right-half-plane zero frequency.

[0005] For a four-switch Buck-Boost operating in continuous conduction mode (CCM), the angular frequency of the zero point in the right half-plane is:

[0006]

[0007] Among them, R L R is the load resistance, L is the inductance, and D is the duty cycle. Therefore, when the load resistance R... L When the duty cycle D increases or the inductance L increases, the zero point in the right half-plane will shift to a lower frequency, which further limits the loop bandwidth. The limitation on the loop bandwidth will slow down the loop speed. In addition, the presence of the zero point in the right half-plane will make the overshoot / undershoot of the output voltage greater when disturbed, and the transient response will be worse.

[0008] Patent document CN101640478B discloses a DC-DC converter. This converter features low output voltage ripple, good noise immunity, and fast load response. It also has a wider output voltage range (its output voltage can rise or fall compared to the input voltage) and can effectively disconnect the input and output when necessary. However, the output voltage of this DC-DC converter is only 0–2V. IN Between these values, the maximum output voltage will not exceed 2V. IN Therefore, the output voltage range is limited.

[0009] Furthermore, for traditional buck converters, V OUT / V IN =D, the delay in the circuit determines the minimum duty cycle, that is, the duty cycle D cannot be infinitely small, which leads to V OUT < <V IN The buck converter has become a challenge. Summary of the Invention

[0010] To address the above problems, this invention proposes a DC-DC converter.

[0011] The technical solution of this invention is as follows:

[0012] A DC-DC converter, characterized in that it includes a DC input power supply V IN First switch S1, second switch S2, third switch S3, fourth switch S4, fifth switch S5, inductor L, flying capacitor C F and output capacitor C L ;

[0013] The DC input power supply V IN The positive terminal is connected to the first terminal of the first switch S1;

[0014] The second terminal of the first switch S1 is connected to the first terminal of the second switch S2 and the flying capacitor C, respectively. F The first end and the first end of the fourth switch S4;

[0015] The second terminal of the second switch S2 is connected to the first terminal of the third switch S3 and the first terminal of the inductor L, respectively.

[0016] The second terminal of the third switch S3 is connected to the flying capacitor C. F The second end and the first end of the fifth switch S5;

[0017] The second terminal of the fifth switch S5 is connected to the second terminal of the inductor L and the output capacitor C. L The positive end;

[0018] The DC input power supply V IN The negative terminal, the second terminal of the fourth switch S4, and the output capacitor C L The negative terminals are all grounded;

[0019] Within one switching cycle, different operating modes are achieved by applying different control methods to the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, and the fifth switch S5. Specifically, these include:

[0020] Buck converter operating mode: In one switching cycle, the first switch S1 and the third switch S3 are simultaneously turned on and the second switch S2, the fourth switch S4 and the fifth switch S5 are simultaneously turned off within a preset time. During the remaining time, the first switch S1 and the third switch S3 are simultaneously turned off and the second switch S2, the fourth switch S4 and the fifth switch S5 are simultaneously turned on.

[0021] The buck-boost converter operates in a pass-through mode: In one switching cycle, during the first preset time period, the first switch S1 and the third switch S3 are simultaneously turned on while the second switch S2, the fourth switch S4, and the fifth switch S5 are simultaneously turned off; during the second preset time period, the first switch S1 and the second switch S2 are simultaneously turned on while the third switch S3, the fourth switch S4, and the fifth switch S5 are simultaneously turned off; during the remaining time, the second switch S2, the fourth switch S4, and the fifth switch S5 are simultaneously turned on while the first switch S1 and the third switch S3 are simultaneously turned off.

[0022] Step-down working mode: The second switch S2 remains on, the third switch S3 and the fifth switch S5 remain off. In one switching cycle, the first switch S1 is on and the fourth switch S4 is off within a preset time. During the remaining time, the first switch S1 is off and the fourth switch S4 is on.

[0023] Buck converter operating mode: In one switching cycle, the first switch S1, the second switch S2 and the fifth switch S5 are simultaneously turned on and the third switch S3 and the fourth switch S4 are simultaneously turned off within a preset time. During the remaining time, the first switch S1, the second switch S2 and the fifth switch S5 are simultaneously turned off and the third switch S3 and the fourth switch S4 are simultaneously turned on.

[0024] Furthermore, the first switch S1, the third switch S3, and the fifth switch S5 employ one of the following devices: MOSFET, IGBT, and GaN HEMT.

[0025] Furthermore, the second switch S2 and the fourth switch S4 employ one of the following devices: diode, MOSFET, IGBT, and GaN HEMT.

[0026] The beneficial effects of this invention are as follows:

[0027] 1. This invention can be used as a buck-boost converter, eliminating the right half-plane zero point of traditional buck-boost converters and greatly improving transient response;

[0028] 2. As a buck-boost converter, the output voltage of this invention can be greater than 2*V. IN And not limited to 0 to 2*V IN The output voltage range is wide; furthermore, this invention can also be used as a buck converter with no minimum duty cycle limitation, achieving a very small Vo. OUT / V IN ;

[0029] 3. Depending on the different input and output voltage relationships, this invention can insert a pass-through state in the buck-boost converter or operate in buck mode to achieve high efficiency in different voltage ranges. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the overall structure of the present invention;

[0031] Figure 2 This is a schematic diagram of a traditional four-switch Buck-Boost topology;

[0032] Figure 3 This is a schematic diagram of a traditional four-switch Buck-Boost in stage D.

[0033] Figure 4 This is a schematic diagram of a traditional four-switch Buck-Boost in the 1-D stage;

[0034] Figure 5 This is a schematic diagram of the present invention as a buck-boost converter;

[0035] Figure 6 This is the transient response of the present invention after forming a closed loop as a buck-boost converter;

[0036] Figure 7 for Figure 5The present invention is used as a buck-boost converter in the case of D>0.5 within the time period (1-D)*T.

[0037] Figure 8 for Figure 5 The present invention is a schematic diagram of the current flow direction of each device in a buck-boost converter during the time period (1-D)*T, when D=0.5;

[0038] Figure 9 for Figure 5 The present invention is used as a buck-boost converter in the case of D<0.5 within the time period (1-D)*T.

[0039] Figure 10 This is a schematic diagram of the present invention as a buck-boost converter with a through-hole configuration;

[0040] Figure 11 This is a schematic diagram comparing the inductor current before and after the buck-boost converter of the present invention is inserted into the shoot-through state;

[0041] Figure 12 This is a schematic diagram of the invention operating in buck mode;

[0042] Figure 13 This is a schematic diagram of the present invention as a buck converter;

[0043] Figure 14 for Figure 13 The graph shows the relationship between the duty cycle and voltage conversion ratio of the converter. Detailed Implementation

[0044] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.

[0045] like Figure 1 As shown, the present invention provides a DC-DC converter, including a DC input power supply V. IN First switch S1, second switch S2, third switch S3, fourth switch S4, fifth switch S5, inductor L, flying capacitor C F and output capacitor C L DC input power supply V IN The positive terminal is connected to the first terminal of the first switch S1, and the second terminal of the first switch S1 is connected to the first terminal of the second switch S2 and the flying capacitor C. F The first terminal of the first switch and the first terminal of the fourth switch S4, and the second terminal of the second switch S2 are respectively connected to the first terminal of the third switch S3 and the first terminal of the inductor L. The second terminal of the third switch S3 is respectively connected to the flying capacitor C. F The second terminal of the fifth switch S5 is connected to the first terminal of the fifth switch S5, and the second terminal of the fifth switch S5 is connected to the second terminal of the inductor L and the output capacitor C.L The positive terminal of the DC input power supply V IN The negative terminal, the second terminal of the fourth switch S4, and the output capacitor C L The negative terminals are all grounded. This also includes the load R. L Load R L The positive terminal is connected to the output capacitor C. L The positive terminal; load R L The negative terminal is grounded.

[0046] The first switch S1 and the third switch S3 need to be actively turned on and off, therefore they can be any controllable device other than a diode, such as a MOSFET, IGBT, or GaN HEMT. If the fifth switch S5 is a diode, since the forward voltage drop of a diode is usually large, it hinders the flow of the flying capacitor C. F The fifth switch S5 can be any controllable device other than a diode, such as a MOSFET, IGBT, or GaN HEMT, for charging. The second switch S2 and the fourth switch S4 can be passively turned on and off; therefore, they can be diodes or any controllable device such as a MOSFET, IGBT, or GaN HEMT.

[0047] Different beneficial effects can be achieved by changing the control method of the first to the fifth switches S1-S5 within a switching cycle.

[0048] Example 1 (Boost-Buck Converter):

[0049] like Figure 5 As shown, in one switching cycle: within a preset time period, the first switch S1 and the third switch S3 are simultaneously turned on while the second switch S2, the fourth switch S4, and the fifth switch S5 are simultaneously turned off; for the remaining time period, the first switch S1 and the third switch S3 are simultaneously turned off while the second switch S2, the fourth switch S4, and the fifth switch S5 are simultaneously turned on. This can form a buck-boost converter without a right half-plane zero and with a wide output voltage range. Furthermore, if the duty cycle D is close to 0.5, the switching conduction losses and Figure 2 Approaching the traditional four-switch Buck-Boost.

[0050] Let the switching period be T and the duty cycle be D. During the time interval (1-D)*T, the first switch S1 and the third switch S3 are simultaneously turned off, while the second switch S2, the fourth switch S4, and the fifth switch S5 are simultaneously turned on. The inductor L and the output capacitor C... L Release energy to supply the flying capacitor C F and load R L Ignoring the on-resistance of all switches and all parasitic resistances, the flying capacitor C... F The voltage at the first terminal is 0, and the flying capacitor CF The voltage at the second terminal is V OUT Therefore, the flying capacitor C F The voltage difference between the two ends is V OUT The voltage across the first terminal of inductor L is 0, and the voltage across the second terminal of inductor L is V. OUT Therefore, the current in inductor L decreases linearly with time, with a slope of -V. OUT / L.

[0051] During the D*T time period, the first switch S1 and the third switch S3 are simultaneously turned on, while the second switch S2, the fourth switch S4, and the fifth switch S5 are simultaneously turned off, and the flying capacitor C... F The current is the same as the current in inductor L, and the input power supply V IN Hefei capacitor C F The released energy is partially stored in the inductor L and partially used to replenish the output capacitor C. L The energy released at (1-D)*T is used to power the load R. L Ignoring the on-resistance of all switches and all parasitic resistances, in steady state, the flying capacitor C... F The voltage at the first terminal is V IN Flying capacitor C F Because of its large capacitance, it can be considered a constant voltage source; therefore, the flying capacitor C... F The voltage at the second terminal is V IN +V OUT The voltage across the first terminal of inductor L is V. IN +V OUT The voltage across the second terminal of inductor L is V. OUT Therefore, the current in inductor L increases linearly with time, and the slope of the change is V. IN / L.

[0052] In a steady state, the decrease in current to inductor L over the time interval (1-D)*T is equal to the increase over the time interval D*T:

[0053]

[0054] Therefore, it can be intuitively concluded that:

[0055]

[0056] Using power electronics theory and the state-space averaging method, the large-signal relationship of the power stage in this embodiment is calculated as follows:

[0057]

[0058]

[0059] Where r5 is the on-resistance of the fifth switch S5, I OUT It is the load R L The current, I L It is the inductor current. When D is satisfied... 2 r5<<(1-D) 3 R L When formula (3) is used, it can be approximated as formula (2). Therefore, the voltage conversion ratio (V) in this embodiment is... OUT / V IN )and Figure 2 Traditional four-switch Buck-Boost converters have the same voltage conversion ratio. When the duty cycle D < 0.5, V OUT <V IN When the duty cycle D = 0.5, V OUT =V IN When the duty cycle D > 0.5, V OUT >V IN Furthermore, when the duty cycle D > 2 / 3, V OUT 2*V IN The output voltage range of this embodiment is large, indicating that it has a wide range.

[0060] When the load R L When the load current suddenly decreases, that is, when the load current suddenly increases, the load R L The energy required throughout the cycle increases, and the duty cycle D increases to allow the inductor L to store more energy to meet the load R. L The demand is met. Since all inductor current flows to the output during the D*T time period, increasing the duty cycle D will directly transfer more energy from the inductor to the output capacitor C. L and load R L This allows the output voltage to recover to a stable value more quickly. Therefore, this embodiment does not have the traditional four-switch Buck-Boost mechanism of "storing energy first and then releasing energy". The storage and release of energy are carried out simultaneously, and there is no discontinuity between the inductor current and the load current. Therefore, this embodiment does not have a right half-plane zero point.

[0061] Using power electronics theory and the state-space averaging method, the small-signal transfer function from inductor current to output voltage of the power stage in this embodiment is calculated as follows:

[0062]

[0063] Transfer function G vi There are two poles and two zeros, where the expression for the zeros is:

[0064]

[0065] in,

[0066] Where D' = 1 - D. ω z1,2 The sign of the zeros determines their positions. For both zeros to be in the left half-plane, b < 0 must first be satisfied, that is...

[0067]

[0068] L / R L and C F r5 are all time constants, L / R L C represents the speed at which energy from an inductor is transferred to a load. F r5 represents the energy of the inductor used to power the flying capacitor C. F The charging speed, and for the flying capacitor C F The charging process reduces the energy transferred to the load. Therefore, formula (7) indicates that the net energy flow from the inductor into the load is not present. The traditional four-switch Buck-Boost mechanism of "storing energy first, then releasing energy" does not exist, which further explains why there is no right-half-plane zero in this embodiment. Secondly, when c < 0, ω z1,2 It will be a pair of conjugate complex zeros in the left half-plane; when c>0, in order to ensure ω z1,2 All are less than zero, so 0 is required. <c<b 2 , that is:

[0069]

[0070] At this point, two real zeros in the left half-plane can be obtained. Therefore, after rigorous derivation, it is proven that under certain conditions, this embodiment does not have any zeros in the right half-plane, but only two zeros in the left half-plane.

[0071] Since this embodiment lacks a right-half-plane zero, the simulation results of the transient response to a load step after adding the controller and corresponding compensation are as follows: Figure 6 As can be seen, when the load current I... load When jumping from 0 to 300mA, regardless of the input voltage V IN Is it greater than, equal to, or less than the output voltage V? OUT (3.3V), Output voltage V OUT The overshoot / undershoot is only 48mV, and the settling time is only 20us, which greatly improves the transient response.

[0072] In addition, if the duty cycle D is close to 0.5, the conduction loss of the fourth switch S4 is very small, which is beneficial to the improvement of efficiency. Figure 5 During the D*T time period, the flying capacitor C FSince it is connected in series with an inductor, the currents in both are equal. During the (1-D)*T time interval, in a steady state, the flying capacitor needs to replenish the charge consumed during the D*T time interval to maintain charge balance. Ignoring current ripple, we can obtain:

[0073] I L *D=I CF *(1-D) (9)

[0074] Among them I CF It is a flying capacitor C F The current flowing through it. When the duty cycle D > 0.5, during the time interval (1-D)*T, I L CF Therefore, the output capacitor C L An additional current needs to be supplied, along with the inductor current I. L Superimposed, together providing power to the flying capacitor C F Charging, such as Figure 7 The medium current is 100, and the current magnitude is I. CF -I L From the output capacitor C L Departure, passing through Flying Capacitor C F The current flows to the fourth switch S4. Therefore, the closer D is to 0.5, the smaller the current in the fourth switch S4. When the duty cycle D = 0.5, within the time interval (1-D)*T, I L =I CF The current in the fourth switch S4 is 0, such as Figure 8 As shown. When the duty cycle D < 0.5, within the time interval (1-D)*T, I L >I CF Therefore, it is necessary to reduce the inductor current I. L Partially offset and then given to the flying capacitor C F Charging. The offsetting current is as follows: Figure 9 As shown in Figure 200, the size is I. L -I CF The direction starts from the fourth switch S4 and passes through the flying capacitor C. F The current flows to the load. Therefore, the closer D is to 0.5, the smaller the current of the fourth switch S4. In summary, the conduction loss of the fourth switch S4 is very small, even close to zero, when D is close to 0.5, which is beneficial to the improvement of efficiency.

[0075] Example 2 (Boost / Buck converter with through-hole connection):

[0076] like Figure 10 As shown, in one switching cycle: within the first preset time period, the first switch S1 and the third switch S3 are simultaneously turned on, while the second switch S2, the fourth switch S4, and the fifth switch S5 are simultaneously turned off (e.g., ...). Figure 10 ​(a)) During the second preset time period, the first switch S1 and the second switch S2 are simultaneously turned on, and the third switch S3, the fourth switch S4, and the fifth switch S5 are simultaneously turned off (e.g., Figure 10 (b)) During the remaining time, the second switch S2, the fourth switch S4, and the fifth switch S5 are simultaneously turned on, and the first switch S1 and the third switch S3 are simultaneously turned off (e.g., ...). Figure 10 (c)). Unlike the first embodiment, this embodiment inserts a "straight-through state" period between the two time periods of a switching cycle. The straight-through state is the input power supply V. IN The inductor L is directly connected to the output V. OUT Connected, such as Figure 10 (b)

[0077] When V IN and V OUT When approaching a point of contact, incorporating a direct current state can reduce the ripple and DC value of the inductor current, thus improving efficiency. (Using V...) IN =V OUT For example, assuming the load current is constant, the inductor current of the buck-boost converter in the first embodiment during one cycle is as follows: Figure 11 As shown in FGI, the absolute values ​​of the slopes of FG and GI are equal, which is V. IN / L=V OUT / L. Because segment FG corresponds to Figure 5 During the D*T time period, all inductor current flows to the load, so the amount of charge transferred to the load is the area of ​​the trapezoidal OEGF (the area of ​​the shaded part). In this embodiment, a direct-through state is inserted. Since the voltage difference across the inductor current is 0 in the direct-through state, the slope of the inductor current is 0, that is... Figure 11 In the inductor current ABCH, segment BC (segment AB corresponds to segment FG, segment CH corresponds to segment GI, and the absolute values ​​of their slopes are all equal). Since the inductor current in the shoot-through state also flows directly to the load, the amount of charge transferred to the load in one cycle is the area of ​​polygon ABCDO (the area of ​​the shaded vertical line). Assuming the load current is constant, the area of ​​trapezoid OEGF should be equal to the area of ​​polygon ABCDO. Obviously, the ripple and DC value of the inductor current after adding the shoot-through state are significantly reduced, thus reducing conduction losses. Therefore, when V IN and V OUT When approaching, the switching control method according to this embodiment can improve efficiency.

[0078] Example 3 (Buck Mode):

[0079] like Figure 12As shown, the second switch S2 remains on, while the third switch S3 and the fifth switch S5 remain off. Within one switching cycle: for a preset time period, the first switch S1 is on and the fourth switch S4 is off; for the remaining time period, the first switch S1 is off and the fourth switch S4 is on. This mode is equivalent to a traditional two-switch Buck converter and is suitable for V... IN >V OUT The situation is such that V satisfies OUT =D*V IN .

[0080] When V IN >V OUT In contrast to the first embodiment, this embodiment reduces losses in the following two aspects.

[0081] First, in the first embodiment, the inductor current is greater than the load current, being 1 / (1-D) times the load current, as shown in Formula 4; while in this embodiment, the DC value of the inductor current is the same as the load current. In the first embodiment, combining Formula (2) and the voltage across the inductor L, the ripple value of the inductor current is:

[0082]

[0083] In this embodiment, the ripple value of the inductor current is:

[0084]

[0085] Subtracting the two equations, we get:

[0086]

[0087] Therefore, when V IN >V OUT In this embodiment, compared to the first embodiment, the DC value of the inductor current and the ripple value are lower, resulting in lower conduction losses and improved efficiency. Furthermore, since all the inductor current flows to the load, lower inductor current ripple means lower output voltage ripple.

[0088] Secondly, compared to the first embodiment, this embodiment has fewer switching operations and fewer flying capacitors C. F The circuit remains in an open state, which effectively reduces losses. With the third switch S3 and the fifth switch S5 remaining off and the second switch S2 remaining on, AC switching losses and gate charge losses from the third switch S3, the fifth switch S5, and the second switch S2 are eliminated. (Flying capacitor C) F Keeping it in an open state eliminates the flying capacitor C. F The resulting ESR loss.

[0089] Example 4 (Buck Converter):

[0090] like Figure 13 As shown, in one switching cycle: within a preset time period, the first switch S1, the second switch S2, and the fifth switch S5 are simultaneously turned on, while the third switch S3 and the fourth switch S4 are simultaneously turned off; for the remaining time period, the first switch S1, the second switch S2, and the fifth switch S5 are simultaneously turned off, while the third switch S3 and the fourth switch S4 are simultaneously turned on. This control method can also achieve the function of voltage reduction, but unlike the third embodiment or the traditional two-switch Buck converter, this embodiment can achieve a very small V... OUT / V IN There is no minimum duty cycle limitation as with traditional two-switch Buck converters.

[0091] When V IN >V OUT During the D*T time period, the first switch S1, the second switch S2, and the fifth switch S5 are simultaneously turned on, while the third switch S3 and the fourth switch S4 are simultaneously turned off. The voltage across the first terminal of inductor L minus the voltage across the second terminal of inductor L equals V. IN -V OUT Therefore, the inductor current increases linearly with a slope of (V IN -V OUT ) / L. Part of the inductor current is due to the flying capacitor C. F Charging, the remainder supplies power to the load, flying capacitor C F The voltage at the second terminal minus the flying capacitor C F The voltage at the first terminal is V OUT -V IN During the time interval (1-D)*T, the first switch S1, the second switch S2, and the fifth switch S5 are simultaneously turned off, while the third switch S3 and the fourth switch S4 are simultaneously turned on. Due to the flying capacitor C... F The voltage difference across the two ends can be considered constant, therefore the flying capacitor C F The voltage at the second terminal is V OUT -V IN Therefore, the voltage across the first terminal of inductor L minus the voltage across the second terminal of inductor L is -V. IN The inductor current decreases linearly with a slope of -V. IN / L. Flying Capacitor C F Both the inductor L and the inductor L discharge to supply the load.

[0092] In a steady state, the increase in current through inductor L over the time interval D*T is equal to the decrease over the time interval (1-D)*T:

[0093] Therefore, we can conclude that:

[0094]

[0095] like Figure 14as shown, when 0<D<0.5, V OUT / V IN <0, this embodiment constitutes an inverting DC converter; when 0.5<D<1, V OUT / V IN >0, and V OUT / V IN the smaller it is, the closer D is to 0.5. While for the conventional two-switch Buck converter, V OUT / V IN =D, due to the limitation of the minimum duty cycle, V OUT / V IN has a minimum value. Therefore, this embodiment can achieve a very small V OUT / V IN .

Claims

1. A DC-DC converter, characterized in that, Including DC input power supply V IN First switch S1, second switch S2, third switch S3, fourth switch S4, fifth switch S5, inductor L, flying capacitor C F and output capacitor C L ; The DC input power supply V IN The positive terminal is connected to the first terminal of the first switch S1; The second terminal of the first switch S1 is connected to the first terminal of the second switch S2 and the flying capacitor C, respectively. F The first end and the first end of the fourth switch S4; The second terminal of the second switch S2 is connected to the first terminal of the third switch S3 and the first terminal of the inductor L, respectively. The second terminal of the third switch S3 is connected to the flying capacitor C. F The second end and the first end of the fifth switch S5; The second terminal of the fifth switch S5 is connected to the second terminal of the inductor L and the output capacitor C. L The positive end; The DC input power supply V IN The negative terminal, the second terminal of the fourth switch S4, and the output capacitor C L The negative terminals are all grounded; Within one switching cycle, different operating modes are achieved by applying different control methods to the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, and the fifth switch S5. Specifically, these include: Buck converter operating mode: In one switching cycle, the first switch S1 and the third switch S3 are simultaneously turned on and the second switch S2, the fourth switch S4 and the fifth switch S5 are simultaneously turned off within a preset time. During the remaining time, the first switch S1 and the third switch S3 are simultaneously turned off and the second switch S2, the fourth switch S4 and the fifth switch S5 are simultaneously turned on. The buck-boost converter operates in a pass-through mode: In one switching cycle, during the first preset time period, the first switch S1 and the third switch S3 are simultaneously turned on while the second switch S2, the fourth switch S4, and the fifth switch S5 are simultaneously turned off; during the second preset time period, the first switch S1 and the second switch S2 are simultaneously turned on while the third switch S3, the fourth switch S4, and the fifth switch S5 are simultaneously turned off; during the remaining time, the second switch S2, the fourth switch S4, and the fifth switch S5 are simultaneously turned on while the first switch S1 and the third switch S3 are simultaneously turned off. Step-down working mode: The second switch S2 remains on, the third switch S3 and the fifth switch S5 remain off. In one switching cycle, the first switch S1 is on and the fourth switch S4 is off within a preset time. During the remaining time, the first switch S1 is off and the fourth switch S4 is on. Buck converter operating mode: In one switching cycle, the first switch S1, the second switch S2 and the fifth switch S5 are simultaneously turned on and the third switch S3 and the fourth switch S4 are simultaneously turned off within a preset time. During the remaining time, the first switch S1, the second switch S2 and the fifth switch S5 are simultaneously turned off and the third switch S3 and the fourth switch S4 are simultaneously turned on.

2. A DC-DC converter according to claim 1, characterized in that, The first switch S1, the third switch S3, and the fifth switch S5 use one of the following devices: MOSFET, IGBT, and GaN HEMT.

3. A DC-DC converter according to claim 1, characterized in that, The second switch S2 and the fourth switch S4 use one of the following devices: diode, MOSFET, IGBT, and GaN HEMT.

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