Intermodulation distortion suppression circuit and method

Abstract

This disclosure relates to an intermodulation distortion suppression circuit and method. Described herein relates to an apparatus for communication. In one aspect, the apparatus includes a first circuit configured to generate a first signal and a second signal at a first frequency from a third signal at a second frequency higher than the first frequency. The first and second signals can have opposite phases from each other. In one aspect, the apparatus includes a second circuit configured to provide a difference between the first signal and the second signal as a fourth signal. In one aspect, the apparatus includes a third circuit configured to provide the first signal to the second circuit and resonate at a third frequency between the first frequency and the second frequency. In one aspect, the apparatus includes a fourth circuit configured to provide the second signal to the second circuit and resonate at the third frequency.

Description

Technical Field

[0001] This disclosure generally relates to circuits and methods for suppressing intermodulation distortion. Background Technology

[0002] The quality of radio frequency (RF) signals used for communication can be degraded due to intermodulation distortion. Intermodulation distortion can be a distortion of the RF signal caused by intermodulation signals generated by mixing two signals of different frequencies. Due to the nonlinearity of the transmitter, two signals of different frequencies may be mixed. If the frequency of the intermodulation signal is close to the frequency of the RF signal used for communication, such intermodulation signals may interfere with the RF signal. If sufficient separation is provided between the frequency of the RF signal used for communication and the frequency of the intermodulation signal, the intermodulation signal can be filtered out to protect or preserve the RF signal. However, if the frequency of the intermodulation signal and the frequency of the RF signal used for communication are close to each other, the intermodulation signal may not be effectively filtered or suppressed. Summary of the Invention

[0003] The various embodiments disclosed herein relate to an apparatus for communication. In some embodiments, the apparatus includes a first circuit configured to generate a first signal and a second signal at the first frequency based on a third signal at a second frequency higher than the first frequency. The first signal and the second signal may have opposite phases to each other. In some embodiments, the apparatus includes a second circuit configured to provide the difference between the first signal and the second signal as a fourth signal. In some embodiments, the apparatus includes a third circuit configured to provide the first signal to the second circuit and resonate at a third frequency between the first frequency and the second frequency. In some embodiments, the apparatus includes a fourth circuit configured to provide the second signal to the second circuit and resonate at the third frequency.

[0004] In some embodiments, the first circuit is time-controlled according to the third signal at the second frequency to generate the first signal and the second signal at the first frequency. In some embodiments, the third frequency is the difference between the second frequency and the first frequency.

[0005] In some embodiments, the third circuit includes a first capacitor and a first inductor coupled in parallel to each other to resonate at the third frequency. In some embodiments, the fourth circuit includes a second capacitor and a second inductor coupled in parallel to each other to resonate at the third frequency.

[0006] In some embodiments, the capacitances of the first capacitor and the second capacitor are tunable.

[0007] In some embodiments, the device includes a fifth circuit coupled in series to the third circuit between the first and second circuits. The fifth circuit may be configured to resonate at a fourth frequency between the first and second frequencies. In some embodiments, the device includes a sixth circuit coupled in series to the fourth circuit between the first and second circuits. The sixth circuit may be configured to resonate at the fourth frequency.

[0008] In some embodiments, the first circuit is time-controlled according to the third signal at the second frequency to generate the first signal and the second signal at the first frequency. In some embodiments, the difference between the second frequency and the first frequency is higher than the third frequency and lower than the fourth frequency.

[0009] In some embodiments, the first circuit is a digital-to-analog converter circuit, and the second circuit is a balun.

[0010] In some embodiments, the third circuit is a first transformer, and the fourth circuit is a second transformer.

[0011] This document discloses an apparatus for communication. In some embodiments, the apparatus includes a first circuit comprising a first port configured to provide a first signal at a first frequency and a second port configured to provide a second signal at the first frequency. In some embodiments, the apparatus includes a second circuit comprising a third port configured to receive the first signal, a fourth port configured to receive the second signal, and a fifth port configured to provide a third signal corresponding to the difference between the first signal and the second signal. In some embodiments, the apparatus includes a first inductor and a first capacitor coupled between the first port of the first circuit and the third port of the second circuit. The first inductor and the first capacitor may be configured to resonate at a second frequency different from the first frequency. In some embodiments, the apparatus includes a second inductor and a second capacitor coupled between the second port of the first circuit and the fourth port of the second circuit. The second inductor and the second capacitor may be configured to resonate at the second frequency.

[0012] In some embodiments, the first circuit performs timing control at a third frequency to generate the first signal and the second signal at the first frequency. The third frequency may be higher than the first frequency and the second frequency. The second frequency may be the difference between the third frequency and the first frequency.

[0013] In some embodiments, the device includes a third inductor and a third capacitor coupled between a first port of the first circuit and a third port of the second circuit. The third inductor and the third capacitor may be configured to resonate at a third frequency different from the first frequency. In some embodiments, the device includes a fourth inductor and a fourth capacitor coupled between a second port of the first circuit and a fourth port of the second circuit. The fourth inductor and the fourth capacitor may be configured to resonate at the third frequency.

[0014] In some embodiments, i) a third circuit including the first inductor and the first capacitor and ii) a fourth circuit including the third inductor and the third capacitor are coupled in series between the first port of the first circuit and the third port of the second circuit. In some embodiments, i) a fifth circuit including the second inductor and the second capacitor and ii) a sixth circuit including the fourth inductor and the fourth capacitor are coupled in series between the second port of the first circuit and the fourth port of the second circuit.

[0015] In some embodiments, the first circuit performs timing control at a fourth frequency to generate the first signal and the second signal at the first frequency. The fourth frequency may be higher than the first frequency, the second frequency, and the third frequency. The difference between the fourth frequency and the first frequency may be higher than the second frequency and lower than the third frequency.

[0016] In some embodiments, the second circuit is a balun.

[0017] In some embodiments, the first signal and the second signal have opposite phases.

[0018] In some embodiments, the first inductor and the first capacitor are part of a first transformer, and the second inductor and the second capacitor are part of a second transformer.

[0019] In some embodiments, the capacitances of the first capacitor and the second capacitor are adjustable.

[0020] The various embodiments disclosed herein relate to an apparatus for communication. In some embodiments, the apparatus includes a first circuit configured to provide a first signal and a second signal at a first frequency. In some embodiments, the apparatus includes a second circuit configured to provide a third signal corresponding to the difference between the first signal and the second signal. In some embodiments, the apparatus includes a first inductor and a first capacitor configured to provide the first signal to the second circuit. In some embodiments, the apparatus includes a second inductor and a second capacitor configured to provide the second signal to the second circuit. In some embodiments, the first inductor, the first capacitor, the second circuit, the second inductor, and the second capacitor have a first impedance at a second frequency higher than the first frequency and a second impedance at a third frequency higher than the second frequency. The second impedance may be higher than the first impedance.

[0021] In some embodiments, the first inductor, the first capacitor, the second circuit, the second inductor, and the second capacitor have a third impedance at the first frequency. The third impedance may be higher than the first impedance.

[0022] In some embodiments, the first circuit performs timing control at a fourth frequency higher than the third frequency to generate the first signal and the second signal at the first frequency. The third frequency may be the difference between the fourth frequency and the first frequency. Attached Figure Description

[0023] The various objects, aspects, features, and advantages of this disclosure will become more apparent and better understood through a detailed description taken in conjunction with the accompanying drawings, in which similar reference numerals identify corresponding elements throughout. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0024] Figure 1 This is a block diagram of a communication system including a base station and a client device according to some embodiments.

[0025] Figure 2 This is a block diagram of an apparatus for communicating via a wireless communication link, according to some embodiments.

[0026] Figure 3 This is a schematic block diagram of a transmitter according to some embodiments.

[0027] Figure 4 It is a graph that displays the frequency curves of various signals from the transmitter.

[0028] Figure 5This is a schematic block diagram of an interface circuit including a resonant circuit according to some embodiments.

[0029] Figure 6 This is to illustrate according to some embodiments Figure 5 The graph shows the impedance curve of the input port of the interface circuit.

[0030] Figure 7 This is a graph illustrating a comparison between the common-mode rejection ratio (CMRR) of an emitter including a resonant circuit and that of an emitter without a resonant circuit, according to some embodiments.

[0031] Figure 8 This is a schematic block diagram of an interface circuit including a resonant circuit according to some embodiments.

[0032] Figure 9 This is to illustrate according to some embodiments Figure 8 The graph shows the impedance curve of the input port of the interface circuit.

[0033] Figure 10 This is a graph illustrating a comparison between the common-mode rejection ratio (CMRR) of an emitter including a resonant circuit and that of an emitter without a resonant circuit, according to some embodiments.

[0034] Figure 11 This is a schematic block diagram of an interface circuit that includes a transformer as a resonant circuit, according to some embodiments.

[0035] Figure 12 This is a flowchart illustrating operations for suppressing intermodulation distortion according to some embodiments.

[0036] Details of various embodiments of the method and system are set forth in the accompanying drawings and the following description. Detailed Implementation

[0037] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0038] Furthermore, for ease of description, spatial relative terms such as "below," "under," "down," "above," "top," "bottom," etc., may be used herein to describe the relationship between one element or feature and another element or feature illustrated in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0039] This document discloses circuits and methods for suppressing distortion in a transmitter. The distortion can be intermodulation distortion caused by intermodulation signals. Intermodulation signals can be caused or generated by mixing or converting two signals of different frequencies. The two signals may include an RF signal for transmission and an image signal of the RF signal. The image signal may be a signal at a frequency corresponding to the difference between i) the clock frequency of a clock signal and ii) the frequency of the RF signal for transmission. Due to the nonlinearity of the transmitter, the RF signal for transmission and the image signal may be mixed. In one aspect, one or more resonant circuits can be provided to suppress or reduce intermodulation distortion. The resonant circuit may include an inductor and a capacitor tuned or configured to resonate at the frequency of the image signal. The resonant circuit can provide high impedance at the frequency of the image signal, thereby reducing or eliminating intermodulation between the image signal and the RF signal. By reducing the intermodulation between the image signal and the RF signal for transmission, intermodulation distortion can be reduced, and the quality of the RF signal can be maintained or improved.

[0040] In one aspect, the transmitter is implemented for radio frequency (RF) communication, such as cellular communication (3G, 4G, 5G, 6G, etc.), Wi-Fi communication, Bluetooth communication, etc. In some embodiments, the transmitter is a transmitter of a base station (e.g., an eNodeB (eNB), gNodeB (gNB), etc.) providing wireless communication. In one aspect, the transmitter includes or is implemented as a digital-to-analog converter (DAC) operating at high speed (e.g., more than 5 Gigabit samples per second). The DAC converts a modulated signal under RF, represented digitally, into an analog signal, represented analogly. The DAC provides the analog signal to a preamplifier or power amplifier for transmission via an antenna, making it possible to omit an analog upconverter or analog mixer. By omitting the analog upconverter or analog mixer, the transmitter can reduce power consumption, improve linearity, provide design flexibility, and can be implemented with a small form factor. Furthermore, the modulation or up-conversion of a baseband frequency (e.g., 100 MHz to 1 GHz) signal to an RF frequency (e.g., 1 to 10 GHz) can be performed by digital logic circuitry, which is less susceptible to noise than analog circuitry, allowing the transmitter to improve signal quality. In some embodiments, the DAC is provided in an integrated circuit package (e.g., a multi-chip module or a single-chip package). Although the DAC disclosed herein is provided for transmitters used in wireless communication, the DAC can be implemented for various applications. For example, the DAC disclosed herein can be implemented for wired communication, optical communication, or any computing device that performs high-speed digital-to-analog conversion.

[0041] In some embodiments, the DAC provides differential signals as output. The differential signals may have opposite phases to represent the signal, data, or information to be provided. For example, a first differential signal may have a first voltage corresponding to the sum of i) a common-mode voltage and ii) a data voltage corresponding to the data or information to be provided, and a second differential signal may have a second voltage corresponding to the difference between i) the common-mode voltage and ii) the data voltage. In one aspect, the differential signals may suppress or mitigate common-mode noise. Common-mode noise may be noise added to the common-mode voltage or noise added equally to the differential signals. In some embodiments, the differential signals may be converted to single-ended signals. For example, a balun may obtain the difference between i) the first voltage of the first differential signal and ii) the second voltage of the second differential signal as the voltage of the single-ended signal. Ideally, the voltage of the single-ended signal is or corresponds to twice the data voltage without a common-mode voltage. However, due to imbalances or mismatches in the generation of the differential signal, the common-mode voltage may affect or influence the single-ended signal. For example, due to the nonlinearity of the DAC, intermodulation of the common-mode voltage of the image signal can degrade or distort the single-ended signal output from the balun. In one aspect, one or more resonant circuits can be implemented between the DAC and the balun. These resonant circuits can be set or tuned to resonate at the frequency of the image signal to provide high impedance at that frequency. By implementing one or more resonant circuits that resonate at the frequency of the image signal, intermodulation of the image signal can be eliminated or reduced, thus maintaining the quality of the single-ended signal from the balun despite nonlinearity or imbalance in the DAC.

[0042] Figure 1 This is a block diagram of a communication system 100 including a base station 120 and client devices 110A, 110B, and 110C according to some embodiments. The base station 120 and client devices 110A, 110B, and 110C can communicate via a wireless communication link. The wireless communication link can be a cellular communication link conforming to 3G, 4G, 5G, 6G, or other cellular communication protocols. In one aspect, client devices 110A…110C are located within a geographical boundary 150 with respect to base station 120 and can communicate with or through base station 120. In some embodiments, the communication system 100 includes more than Figure 1 The number of base stations 120 and / or client devices 110 shown may be more, less, or different from the number shown.

[0043] In some embodiments, the client device 110 may be a user device, such as a mobile phone, smartphone, personal digital assistant (PDA), tablet computer, laptop computer, wearable computing device (e.g., head-mounted display, smartwatch), etc. The client device 110 may also be referred to as user equipment (UE). Each client device 110 can communicate with the base station 120 via a corresponding communication link. For example, the client device 110 can transmit or provide RF wireless signals to the base station 120 via a wireless communication link (e.g., 3G, 4G, 5G, 6G, or other cellular communication links), and / or receive RF wireless signals from the base station 120 via a wireless communication link (e.g., 3G, 4G, 5G, 6G, or other cellular communication links). The wireless signals may be signals exchanged or provided through a wireless medium (e.g., air). The wireless signals may contain or carry data such as audio data, image data, text, etc.

[0044] In some embodiments, base station 120 may be an apparatus configured to provide wireless communication to client devices 110 within a geographical boundary 150. Examples of base station 120 include eNB, gNB, etc. Base station 120 may be communicatively coupled to another base station 120 or other communication apparatus via a wireless communication link and / or a wired communication link. Base station 120 may receive RF wireless signals from client devices 110 or another base station 120 via a wireless communication link. Additionally or alternatively, base station 120 may transmit or provide RF wireless signals to another client device 110, another base station 120, or another communication apparatus via a wireless communication link. Therefore, base station 120 allows communication between client devices 110 associated with base station 120 or other client devices 110 associated with different base stations 120.

[0045] Figure 2 This is a block diagram of an apparatus 210 for communicating via a wireless communication link according to some embodiments. In some embodiments, apparatus 210 may be a base station 120, a client device 110, or any device that can communicate via a wireless communication link. In some embodiments, apparatus 210 includes an antenna 215, a wireless interface 220, a processor 230, and a memory device 240. These components may be embodied in hardware, software, firmware, or a combination thereof. In some embodiments, apparatus 210 includes a... Figure 2 The device may contain more, fewer, or different components than those shown in the diagram. For example, device 210 may include an electronic display and / or input device. For example, device 210 may include, in addition to... Figure 2 In addition to the antenna 215 and wireless interface 220 shown in the image.

[0046] In some embodiments, antenna 215 is a component that receives and / or transmits wireless signals under RF over a wireless medium (e.g., air). Antenna 215 may be a dipole antenna, patch antenna, loop antenna, or any suitable antenna for wireless communication. In one aspect, a single antenna 215 is used to transmit and receive wireless signals. To receive wireless signals, antenna 215 may detect wireless signals having electromagnetic wave variations in a wireless medium (e.g., air) and provide an electrical signal of RF having a voltage and / or current corresponding to the detected electromagnetic wave variations to wireless interface 220. The electrical signal of RF may be referred to herein as an RF signal. To transmit wireless signals, antenna 215 may receive the electrical signal of RF having a voltage and / or current from wireless interface 220 and transmit a wireless signal having electromagnetic wave variations corresponding to the electrical signal over a wireless medium (e.g., air). In some embodiments, different antennas 215 may be used to transmit and receive wireless signals. In some embodiments, multiple antennas 215 may be used to support multiple-input multiple-output (MIMO) communication.

[0047] In some embodiments, wireless interface 220 is circuitry or a component capable of providing or receiving RF signals to or from antenna 215. In some embodiments, wireless interface 220 includes transmitter 224 and receiver 228. In some embodiments, transmitter 224 and receiver 228 may be implemented in the same integrated circuit. In some embodiments, transmitter 224 and receiver 228 may be implemented in different integrated circuits. Transmitter 224 may be circuitry or a component capable of generating or providing RF signals for transmitting data. In one aspect, transmitter 224 may receive baseband signals from processor 230, the baseband signals containing or representing data (e.g., audio data, image data, text, or any data) for transmission at a baseband frequency (e.g., 0 to 1 GHz), and upconvert the baseband signals to generate RF signals. Transmitter 224 may provide the RF signals to antenna 215 for transmission. Receiver 228 may be circuitry or a component capable of receiving RF signals for receiving data. In one aspect, receiver 228 may receive an RF signal from antenna 215 and down-convert the RF signal to a baseband frequency (e.g., 0 to 1 GHz) to obtain a down-converted signal at the baseband frequency. The down-converted signal at the baseband frequency may contain or represent data (e.g., audio data, image data, text, or any data) generated by another device (e.g., another base station 120, another client device 110, etc.). Receiver 228 may provide the down-converted signal to processor 230. In one configuration, transmitter 224 and receiver 228 may be coupled to the same antenna 215. In another configuration, transmitter 224 and receiver 228 may be coupled to different antennas 215.

[0048] Processor 230 is a component that processes data. Processor 230 may be embodied in an FPGA, ASIC, logic circuit, etc. Processor 230 may obtain instructions from memory device 240 and execute those instructions. In one aspect, processor 230 may receive a down-converted signal at a baseband frequency from wireless interface 220 and decode or process data contained in or represented by the down-converted signal. For example, processor 230 may obtain audio data or image data from the down-converted signal. In one aspect, processor 230 may generate or obtain data for transmission at a baseband frequency and encode or process the data. For example, processor 230 may encode or process image data or audio data at a baseband frequency and provide a baseband signal containing or representing the encoded or processed data to wireless interface 220 for transmission.

[0049] Memory device 240 is a component for storing data. Memory device 240 may be embodied as RAM, flash memory, ROM, EPROM, EEPROM, register, hard disk, removable disk, CD-ROM, or any device capable of storing data. Memory device 240 may be embodied as a non-transitory computer-readable medium storing instructions executable by processor 230 to perform the various functions of the device 210 disclosed herein. In some embodiments, memory device 240 and processor 230 are integrated as a single component (or integrated circuit). In some embodiments, memory device 240, processor 230, and wireless interface 220 are integrated as a single component (or integrated circuit). In some embodiments, memory device 240, processor 230, and wireless interface 220 are implemented as discrete components (or separate integrated circuits).

[0050] Figure 3 This is a schematic block diagram of a transmitter 224 according to some embodiments. In some embodiments, the transmitter 224 includes a DAC 310 (also referred to as "DAC circuit 310"), a modulator 320, an interface circuit 370, and a power amplifier (PA) 380. These components can operate together to generate an RF signal 385 for transmission. In one aspect, the modulator 320 operates in the digital domain, while the interface circuit 370 and PA 380 operate in the analog domain. The DAC circuit 310 can operate in both the analog and digital domains and can serve as an interface between the modulator 320 operating in the digital domain and the interface circuit 370 and PA 380 operating in the analog domain. In some embodiments, the transmitter 224 includes a... Figure 3 The components shown may be more, fewer, or different from those shown. For example, modulator 320 may be implemented as part of processor 230.

[0051] In some embodiments, modulator 320 is a circuit or component capable of receiving a baseband signal comprising K-bit data In_A…In_K in digital representation and performing modulation or up-conversion on the K-bit data In_A…In_K. Modulation or up-conversion may be multiplying the value represented by the K-bit data In_A…In_K by a sine or cosine function of the carrier frequency under RF. The carrier frequency may be a frequency at which it transmits a wireless signal (e.g., 2 to 60 GHz). In one method, modulator 320 may perform the multiplication of the value represented by the K-bit data In_A…In_K with a sine or cosine function of the carrier frequency via digital logic circuitry to obtain N-bit data D_A…D_N representing the up-converted signal under RF. Modulator 320 may provide the N-bit data D_A…D_N in digital representation to DAC circuit 310.

[0052] In some embodiments, the DAC circuit 310 is a circuit or component capable of performing digital-to-analog conversion. In some embodiments, the DAC circuit 310 includes a plurality of DAC units 325A…325N, a resistor ladder 330, a detector 340, and a calibrator 350. These components can operate together to receive N-bit data D_A…D_N in digital representation and provide signals 335A, 335B corresponding to the N-bit data D_A…D_N in analog representation. For example, the voltage amplitudes of signals 335A, 335B may represent or correspond to the values ​​of the N-bit data D_A…D_N. In some embodiments, the DAC circuit 310 includes a ratio Figure 3 More, fewer, or different components are shown in the document.

[0053] In some embodiments, DAC unit 325 is a circuit or component capable of receiving a single bit of data D and generating a current 328 corresponding to that single bit of data D. In one configuration, DAC unit 325 includes an input port coupled to modulator 320 and an output port coupled to a corresponding resistor in resistor ladder 330. The port may be a pad, metal rail, or any conductive component capable of receiving or providing an electrical signal (e.g., voltage or current). The input port may be a port for receiving a signal, while the output port may be a port for providing or outputting a signal. In this configuration, DAC unit 325 may receive a single bit of data D and provide a current 328 having an amplitude corresponding to that single bit of data D. For example, in response to a single bit of data D having a value of "0", DAC unit 325 may bypass the current supply. For example, in response to a single bit of data D having a value of "1", DAC unit 325 may provide a current 328 with a certain amplitude to resistor ladder 330.

[0054] In some embodiments, the resistor ladder 330 is a circuit or component that provides voltage signals 335A, 335B corresponding to currents 328A…328N from a group of DAC units 325A…325N. In one configuration, the resistor ladder 330 includes various resistors connected in an R-2R configuration. In one configuration, the output ports of different DAC units 325A can be coupled to corresponding resistors of the resistor ladder 330. In one configuration, the resistor ladder 330 includes an output port coupled to an input port of interface circuitry 370. In this configuration, the resistor ladder 330 can combine currents 328A…328N from a group of DAC units 325 and generate or provide voltage signals 335A, 335B corresponding to the combined currents. The voltage signals 335A, 335B can be differential signals having opposite phases to each other. In one aspect, the amplitude of the combined currents corresponds to the amplitude of the voltage signals 335A, 335B. For example, for the 4-bit input data "0001" corresponding to the value "1", the difference in amplitude between voltage signals 335A and 335B can be 100mV corresponding to the current from a single DAC unit 325. For example, for the 4-bit input data "0111" corresponding to the value "3", the difference in amplitude between voltage signals 335A and 335B can be 300mV corresponding to the current from three DAC units 325. Resistor ladder 330 can provide voltage signals 335A and 335B at its output port.

[0055] In some embodiments, detector 340 is a circuit or component capable of detecting errors in one or more DAC units 325. Detector 340 may be implemented as analog circuitry, digital logic circuitry, or a combination of analog and digital logic circuitry. In one configuration, detector 340 includes one or more input ports coupled to resistor ladder 330 and an output port coupled to the input ports of calibrator 350. In this configuration, detector 340 can detect characteristics of one or more DAC units 325. Examples of characteristics of DAC units 325 include the timing of providing current 328, the amplitude of current 328, etc. Detector 340 can generate one or more feedback signals indicating the detected characteristics of DAC units 325 and provide one or more feedback signals to calibrator 350.

[0056] In some embodiments, calibrator 350 is circuitry or a component capable of performing calibration of DAC unit 325. In one aspect, each DAC unit 325 may have errors due to process corner variations, voltage variations, temperature variations, or combinations thereof. Examples of errors may include timing errors and amplitude errors. For example, timing errors or differences in the timing of currents 328A…328N provided by different DAC units 325 can lead to errors in combining currents 328A…328N from different DAC units 325, and can lead to inaccuracies in generating voltage signals 335A, 335B corresponding to N bits of data. For example, if a particular DAC unit 325 provides current 328 later than other DAC units 325 or does not provide current 328 during the time period allocated for providing current 328, then the current 328 from DAC unit 325 may not be correctly combined, and may result in incorrect values ​​representing N bits of data in the amplitude of voltage signals 335A, 335B. For example, amplitude errors or differences in the amplitudes of the currents 328A…328N provided by different DAC units 325A…325N may cause amplitude errors in the combined currents from the different DAC units 325…325N, and may lead to inaccuracies in the amplitudes of the voltage signals 335A, 335B generated based on the combined currents. For example, if a particular DAC unit 325 provides a current 328 with an amplitude that is less than or greater than the amplitude of the current 328 from other DAC units 325, then the amplitudes of the voltage signals 335A, 335B generated based on the combined currents may represent an incorrect value for N bits of data. In one aspect, the calibrator 350 may configure or adjust each DAC unit 325 to reduce timing errors and amplitude errors.

[0057] In one aspect, the calibrator 350 may receive one or more feedback signals from the detector 340 indicating the characteristics of one or more DAC units 325, and adjust the configuration or settings of each DAC unit 325 according to the one or more feedback signals. Examples of the configuration or settings of the DAC unit 325 include configurations for adjusting the drive strength of generating or providing current 328 and / or configurations for adjusting the amplitude of current 328. The calibrator 350 may determine a target configuration or target setting for each DAC unit 325 and provide a configuration signal indicating the determined configuration or setting to each DAC unit 325. For example, if the calibrator 350 determines based on one or more feedback signals that a particular DAC unit 325 is slower than other DAC units 325, then the calibrator 350 may generate a configuration signal that causes the DAC unit 325 to increase the drive strength to provide current 328 more quickly. For example, if the calibrator 350 determines, based on one or more feedback signals, that a particular DAC unit 325 provides a current 328 with an amplitude greater than that provided by other DAC units 325, then the calibrator 350 may generate a configuration signal that causes the DAC unit 325 to provide a current 328 with a lower amplitude.

[0058] In some embodiments, interface circuitry 370 is a circuit or component that can interface between DAC circuitry 310 and PA 380. Examples of interface circuitry 370 include baluns, impedance matching circuits, etc. In one configuration, interface circuitry 370 includes a first input port coupled to a first output port of resistor ladder 330, a second input port coupled to a second output port of resistor ladder 330, and an output port coupled to an input port of PA 380. In this configuration, interface circuitry 370 can convert differential signals 335A and 335B into signal 375. For example, interface circuitry 370 can obtain the amplitude difference between signals 335A and 335B and provide the difference as signal 375. In one aspect, interface circuitry 370 can provide impedance matching between DAC circuitry 310 and PA 380, such that the input port of PA 380 can have an impedance within a certain range (e.g., 40 to 60 ohms) to ensure proper operation of PA 380.

[0059] In some embodiments, PA 380 is a circuit or component that amplifies signal 375 to obtain an RF signal 385 for driving antenna 215. In some embodiments, PA 380 includes a single amplifier circuit or two or more amplifier circuits cascaded together. In one configuration, PA 380 includes an input port coupled to the output port of interface circuitry 370 and an output port coupled to antenna 215. In this configuration, PA 380 amplifies the amplitude of signal 375 to obtain an RF signal 385 with amplified amplitude and provides the RF signal 385 to antenna 215 for transmission.

[0060] Figure 4 These are graphs 400A, 400B, 450A, and 450B, displaying the frequency curves of various signals from the transmitter. The transmitter can be transmitter 224. Graph 400A displays the frequency curve of signal 335A from DAC circuit 310, and graph 400B displays the frequency curve of signal 335B from DAC circuit 310. Graph 450A displays the frequency curve of signal 375 from interface circuit 370 when signals 335A and 335B are balanced or matched. Graph 450B displays the frequency curve of signal 375 from interface circuit 370 when signals 335A and 335B are unbalanced or mismatched. Signals 335A and 335B can be differential signals. Signals 335A and 335B can be matched or balanced when signal 335A is the sum of i) the common-mode voltage and ii) the data voltage corresponding to the data or information to be provided, and signal 335B is the difference between i) the common-mode voltage and ii) the data voltage. Signals 335A and 335B may be mismatched or unbalanced when signal 335A deviates from the sum of i) the common-mode voltage and ii) the data voltage corresponding to the data or information to be provided, and / or signal 335B deviates from the difference between i) the common-mode voltage and ii) the data voltage.

[0061] As shown in graph 400A, signal 335A may include or may be a combination of signals 412A, 414A, and 416A, respectively, at RF frequency Fin, intermodulation frequency Fim2, and image frequency Fimg. RF frequency Fin may be the frequency (e.g., 400MHz to 7.2GHz) of RF signals 412A and 412B that contain or represent data used for transmission. Image frequency Fimg may be the frequency of image signal 416A of RF signal 412A relative to a clock signal. Clock signal may be a signal generated by DAC circuit 310 based on its operability or time-controllability to generate signals 335A and 335B. Clock frequency Fclk may be the frequency of the clock signal (e.g., 16 to 20GHz). Clock frequency may be higher than frequency Fin. Image frequency Fimg may be the difference between i) the clock frequency Fclk of the clock signal and ii) the RF frequency Fin of RF signals 412A and 412B. The intermodulation signal 414A at the intermodulation frequency Fim2 can be the second-order intermodulation product of the intermodulation between the image signal 416A and the RF signal 412A. Intermodulation may occur due to nonlinearities in the DAC circuit 310 (e.g., nonlinearities of the output cascaded transistors, terminating resistors, capacitors, etc.). The intermodulation frequency Fim2 can be the difference between the image frequency Fimg and the RF frequency Fin.

[0062] As shown in graph 400B, signal 335B may include or may be a combination of signals 412B, 414B, and 416B located at RF frequency Fin, intermodulation frequency Fim2, and image frequency Fimg, respectively. Signals 412B, 414B, and 416B may be similar to signals 412A, 414A, and 416A of signal 335A, except that signals 412A and 412B at RF frequency Fin have opposite polarities (or opposite phases) and signals 416A and 416B at image frequency Fimg have opposite polarities (or opposite phases). Signals 414A and 414B at intermodulation frequency Fim2 may have the same polarity (or the same phase) because signals 414A and 414B may correspond to the common-mode voltage of the intermodulation between image signals 416A and 416B and RF signals 412A and 412B.

[0063] As shown in graph 450A, if signals 335A and 335B are balanced or matched, then signal 375 may have or may be a combination of signals 462A and 466A at RF frequency Fin and image frequency Fimg, respectively. Signal 462A at RF frequency Fin may correspond to the difference between signals 412A and 412B, and signal 466A may correspond to the difference between signals 416A and 416B. If signals 416A and 416B at image frequency Fimg and signals 412A and 412B at RF frequency Fin are balanced or matched in phase and amplitude, then signals 414A and 414B can be canceled out.

[0064] As shown in graph 450B, if signals 335A and 335B are unbalanced or mismatched, then signal 375 may have or may be a combination of signals 462B, 464B, and 466B at RF frequency Fin, intermodulation frequency Fim2, and image frequency Fimg, respectively. Signal 462B may be similar to signal 462A, and signal 466B may be similar to signal 466A. Signal 464B may correspond to the difference between signals 414A and 414B at intermodulation frequency Fim2. In one aspect, due to the mismatch or imbalance of signals 335A and 335B, signal 375 may have signal 464B at intermodulation frequency Fim2, such that signals 414A and 414B at intermodulation frequency Fim2 are not canceled out. In one aspect, the image frequency Fimg of signals 466A and 466B can be separated from the RF frequency Fin of signals 462A and 462B, making signals 466A and 466B filterable. However, the intermodulation frequency Fim2 of signal 464B may be close to the RF frequency Fin of signals 462A and 462B, making signal 464B potentially difficult to filter.

[0065] Figure 5This is a schematic block diagram of an interface circuit 370A according to some embodiments. In some embodiments, the interface circuit 370A includes resistors R1, R2, resonant circuits 520A, 520B, a controller 530, and a balun 550. These components can operate together to combine differential signals 335A, 335B and generate or obtain a single-ended signal 375 corresponding to the differential signals 335, 335B. In some embodiments, resistors R1, R2, resonant circuits 520A, 520B, controller 530, and balun 550 can be implemented in a single integrated circuit having DAC circuit 310. In some embodiments, resistors R1, R2, resonant circuits 520A, 520B, controller 530, and DAC circuit 310 can be implemented as an integrated circuit, wherein the balun 550 can be implemented as a separate circuit or a separate component (e.g., an off-chip component). In some embodiments, resistors R1, R2, resonant circuits 520A, 520B, and balun 550 may be implemented as separate circuits or separate components (e.g., off-chip components) separate from DAC circuit 310 and controller 530. In some embodiments, interface circuit 370A includes more than Figure 5 More, fewer, or different components are shown in the document.

[0066] In some embodiments, resistor R1 is a circuit or component that provides resistance. In one configuration, a first electrode of resistor R1 is coupled to a first input port 505A of interface circuitry 370A, and a second electrode of resistor R1 is coupled to a metal rail that provides a reference voltage Vref. The first input port 505A may be a pad, a metal rail, or any conductive component capable of providing signal 335A. In some embodiments, the first input port 505A is a bonding pad or output pad of DAC circuitry 310. In this configuration, resistor R1 may provide resistance at the first input port 505A of interface circuitry 370A.

[0067] In some embodiments, resistor R2 is a circuit or component that provides resistance. In one configuration, the first electrode of resistor R2 is coupled to the second input port 505B of interface circuitry 370A, and the second electrode of resistor R2 is coupled to a metal rail that provides a reference voltage Vref. The second input port 505B may be a pad, a metal rail, or any conductive component capable of providing signal 335B. In some embodiments, the second input port 505B is a bonding pad or output pad of DAC circuitry 310. In this configuration, resistor R2 may provide resistance at the second input port 505B of interface circuitry 370A.

[0068] In some embodiments, resonant circuit 520A is a circuit or component that resonates at a specific frequency. Resonant circuit 520A may include a capacitor C1 and an inductor L1 coupled in parallel between the first input port 505A of interface circuit 370A and the first input port 545A of balun 550. In one aspect, inductor L1 and capacitor C1 may resonate at image frequency Fimg to provide high impedance at image frequency Fimg. Image frequency Fimg may be the difference between i) the clock frequency Fclk of DAC circuit 310 which is time-controlled thereunder and ii) the RF frequency Fin of signal 412A used for transmitting data. In some embodiments, capacitor C1 is implemented as a tunable capacitor or a varactor diode. In one aspect, the capacitance of capacitor C1 may be adjusted according to a control signal from controller 530.

[0069] In some embodiments, the resonant circuit 520B is a circuit or component that resonates at a specific frequency. The resonant circuit 520B may include a capacitor C2 and an inductor L2 coupled in parallel between the second input port 505B of the interface circuit 370A and the second input port 545B of the balun 550. In one aspect, the inductor L2 and capacitor C2 may resonate at the image frequency Fimg to provide high impedance at the image frequency Fimg. In some embodiments, the capacitor C2 is implemented as a tunable capacitor or a varactor diode. In one aspect, the capacitance of the capacitor C2 may be adjusted according to a control signal from the controller 530.

[0070] In some embodiments, the balun 550 is a circuit or component that converts a differential signal into a single-ended signal. In one configuration, the balun 550 includes a first input port 545A coupled to a resonant circuit 520A, a second input port 545B coupled to a resonant circuit 520B, and an output port 555 coupled to a PA 380. In this configuration, the balun 550 can obtain the amplitude difference between the differential signals 335A and 335B and provide the amplitude difference as a single-ended signal 375. The balun 550 can provide the single-ended signal 375 to the PA 380 at the output port 555.

[0071] In some embodiments, controller 530 is a circuit or component that generates control signals to configure resonant circuits 520A, 520B. Controller 530 may be embodied as logic circuitry. In some embodiments, controller 530, processor 230, and DAC circuit 310 may be implemented as integrated circuits. In some embodiments, controller 530 may be implemented as a component separate from processor 230 and DAC circuit 310 (e.g., an off-chip component). In some embodiments, controller 530 receives a frequency selection signal 532 and a calibration signal 534. Controller 530 may receive the frequency selection signal 532 and the calibration signal 534 from processor 230 or DAC circuit 310. In one aspect, frequency selection signal 532 represents or corresponds to an image frequency Fimg. In one aspect, calibration signal 534 may indicate how to adjust or tune capacitors C1, C2. In this configuration, controller 530 may generate control signals based on frequency selection signal 532 and calibration signal 534 and provide the control signals to resonant circuits 520A, 520B to set or adjust the capacitance of capacitors C1, C2. By setting or adjusting the capacitance of capacitors C1 and C2, the resonant frequencies of resonant circuits 520A and 520B can be set or adjusted.

[0072] In one aspect, resonant circuits 520A and 520B help suppress intermodulation distortion caused by the intermodulation of image signals 416A and 416B and the RF signals 412A and 412B to be transmitted. (See above regarding...) Figure 4 As described, due to the nonlinearity of the DAC circuit 310 and the mismatch or imbalance of the generated signals 335A and 335B, an intermodulation signal 464B may exist at the intermodulation frequency Fim2. In one aspect, resonant circuits 520A and 520B can resonate at the image frequency Fimg to provide high impedance at the image frequency Fimg, so that the common-mode voltage of the image signals 416A and 416B at the image frequency Fimg can be suppressed or reduced. This is because the amplitude and phase balance of the image signals 416A and 416B become less dependent on the amplitude and phase balance of the signals at the input ports 545A and 545B of the balun 550 at the image frequency Fimg. By reducing or suppressing the common-mode voltage of the image signals 416A and 416B at the image frequency Fimg, the intermodulation signal 464B can be reduced or suppressed.

[0073] Figure 6 This is to illustrate according to some embodiments Figure 5 The impedance ZL of the input ports 505A and 505B of the interface circuit 370A is plotted in graph 600. Impedance ZL can represent the impedance measured at the input ports 505A and 505B toward the resonant circuits 520A and 520B of the interface circuit 370A and the balun 550. In one aspect, impedance ZL corresponds to the load impedance of the DAC circuit 310.

[0074] In one aspect, resonant circuits 520A and 520B can selectively provide high impedance at the image frequency Fimg. As shown in graph 600, the impedance ZL at frequencies Fin, Fclk / 2 (or half of the clock frequency Fclk), and the clock frequency Fclk can be lower than or close to the resistance of resistors R1 and R2. The impedance ZL at the image frequency Fimg can be higher than at frequencies Fin, Fclk / 2, and the clock frequency Fclk because resonant circuits 520A and 520B resonate at the image frequency Fimg.

[0075] Figure 7 This is a graph 700 illustrating a comparison between the common-mode rejection ratio (CMRR) 710 of an transmitter including resonant circuits 520A, 520B and the CMRR 720 of an transmitter without resonant circuits 520A, 520B, according to some embodiments.

[0076] In one aspect, CMRR indicates the degree to which the common-mode voltage of the differential signals 335A and 335B can be suppressed. As shown in graph 700, if resonant circuits 520A and 520B are not implemented, the transmitter may suffer a poor CMRR 720 at the image frequency Fimg. By implementing resonant circuits 520A and 520B, CMRR 710 can be increased at the image frequency Fimg because a high impedance can be provided at the image frequency Fimg. By providing a high CMRR 710 at the image frequency Fimg, the intermodulation signal 464B can be reduced or suppressed.

[0077] Figure 8 This is a schematic block diagram of an interface circuit 370B that includes resonant circuits 520A, 520B, 520C, and 520D, according to some embodiments. Interface circuit 370B may be similar to interface circuit 370A, except that interface circuit 370B additionally includes resonant circuits 520C and 520D. Therefore, for the sake of brevity, detailed descriptions of repeated portions are omitted herein.

[0078] In one aspect, resonant circuit 520C is coupled in series with resonant circuit 520A between the first input port 505A of interface circuit 370B and the first input port 545A of balun 550. Resonant circuit 520C may include an inductor L3 and a capacitor C3 coupled in parallel with each other. In some embodiments, capacitor C3 is implemented as a tunable capacitor or a varactor diode. In one aspect, the capacitance of capacitor C3 can be adjusted according to a control signal from controller 530.

[0079] In one aspect, resonant circuit 520D and resonant circuit 520B are coupled in series between the second input port 505B of interface circuit 370B and the second input port 545B of balun 550. Resonant circuit 520D may include an inductor L4 and a capacitor C4 coupled in parallel to each other. In some embodiments, capacitor C4 is implemented as a tunable capacitor or a varactor diode. In one aspect, the capacitance of capacitor C4 can be adjusted according to a control signal from controller 530.

[0080] In one aspect, resonant circuits 520A and 520B are tuned to resonate at a first frequency offset by a first amount from the image frequency Fimg, and resonant circuits 520C and 520D are tuned to resonate at a second frequency offset by a second amount from the image frequency Fimg, wherein the image frequency Fimg may be between the first and second frequencies. By implementing resonant circuits 520A and 520B tuned to resonate at the first frequency and resonant circuits 520C and 520D tuned to resonate at the second frequency, resonant circuits 520A, 520B, 520C, and 520D can provide high impedance for a wider range compared to implementing resonant circuits 520A and 520B. Therefore, interface circuit 370B can suppress / reject image signals for a wider frequency range.

[0081] Figure 9 This is to illustrate according to some embodiments Figure 8 The impedance ZL of the input ports 505A and 505B of the interface circuit 370B is plotted in graph 900. Impedance ZL represents the impedance of the resonant circuits 520A, 520B, 520C, 520D and the balun 550 of the interface circuit 370B, measured at the input ports 505A and 505B. In one aspect, impedance ZL corresponds to the load impedance of the DAC circuit 310.

[0082] In one aspect, resonant circuits 520A and 520B are resonant to selectively provide high impedance at a first frequency F1 below the image frequency Fimg, and resonant circuits 520C and 520D are resonant to selectively provide high impedance at a second frequency F2 above the image frequency Fimg. Alternatively, resonant circuits 520A and 520B are resonant to selectively provide high impedance at a second frequency F2 above the image frequency Fimg, and resonant circuits 520C and 520D are resonant to selectively provide high impedance at a first frequency F1 below the image frequency Fimg.

[0083] As shown in graph 900, the impedance ZL at frequencies Fin, Fclk / 2, and clock frequency Fclk can be lower than or close to the resistances of resistors R1 and R2. The impedance ZL at frequencies F1, image frequency Fimg, and F2 can be higher than at frequencies Fin, Fclk / 2, and clock frequency Fclk because resonant circuits 520A and 520B can resonate at frequency F1, and resonant circuits 520C and 520D can resonate at frequency F2 relative to image frequency Fimg.

[0084] Figure 10 This is a graph 1000 illustrating a comparison between a transmitter CMRR 1010 including resonant circuits 520A, 520B, 520C, 520D and a transmitter CMRR 1020 without resonant circuits 520A, 520B, 520C, 520D, according to some embodiments.

[0085] As shown in graph 1000, if resonant circuits 520A, 520B, 520C, and 520D are not implemented, the transmitter may suffer a poor CMRR 1020 at the image frequency Fimg. By implementing resonant circuits 520A, 520B, 520C, and 520D, CMRR 1010 can be increased at the first frequency F1, the image frequency Fimg, and the second frequency F2 because high impedance can be provided at these frequencies. By providing high CMRR 1010 at the first frequency F1, the image frequency Fimg, and the second frequency F2, the intermodulation signal 464B can be reduced or suppressed.

[0086] Figure 11 This is a schematic block diagram of an interface circuit 370C including resonant circuits 520E and 520F according to an embodiment. In one aspect, the interface circuit 370C is similar to the interface circuit 370A, except that the interface circuit 370C includes resonant circuits 520E and 520F, instead of resonant circuits 520A and 520B. Therefore, for the sake of brevity, detailed descriptions of repeated portions are omitted herein. Each of the resonant circuits 520E and 520F may include a transformer. The transformer may be tuned or configured to resonate at a wide range of frequencies (e.g., frequencies F1, F2) through mutual coupling of the transformers, such that the interface circuit 370C can have, for example, Figure 9 and 10 The impedance ZL and common-mode rejection are shown in the diagram. Therefore, the interface circuit 370C can suppress / reject image signals over a wider frequency range.

[0087] Figure 12This is a flowchart illustrating operation 1200 for suppressing intermodulation distortion according to an embodiment. In some embodiments, operation 1200 is performed by interface circuitry (e.g., interface circuitry 370A, 370B, 370C). In some embodiments, operation 1200 is performed by other entities. In some embodiments, operation 1200 includes... Figure 12 The steps shown in the document may be more, fewer, or different from those shown elsewhere.

[0088] In one approach, interface circuitry receives a first signal (e.g., signals 335A, 335B) for transmission at a first frequency (e.g., RF frequency Fin). The first signal may be a differential signal having opposite phases to each other. The first signal may be generated based on a second signal (e.g., a clock signal) at a second frequency (e.g., clock frequency Fclk) higher than the first frequency. For example, DAC circuitry 310 may be timed at the second frequency (e.g., 16 to 20 GHz) to generate the first signal for transmission at the first frequency (e.g., 400 MHz to 7.2 GHz).

[0089] In one method, the interface circuitry suppresses a third signal (e.g., an image signal) at a third frequency (e.g., an image frequency Fimg). The third frequency may be the difference between a second frequency (e.g., a clock frequency Fclk) and a first frequency (e.g., an RF frequency Fin). In one aspect, the interface circuitry implements one or more resonant circuits (e.g., resonant circuits 520A to 520F) that are set or tuned to resonate at the third frequency. The resonant circuits may resonate at the third frequency to provide high impedance at the third frequency. By providing high impedance at the third frequency, intermodulation between the third signal and the first signal can be reduced, thereby reducing or eliminating intermodulation signals close to the first signal.

[0090] In one approach, the interface circuitry provides a fourth signal (e.g., signal 375) at a first frequency (e.g., RF frequency Fin) based on a first signal. In one aspect, the interface circuitry implements a balun (e.g., balun 550) configured to convert a differential signal into a single-ended signal corresponding to the differential signal. For example, the balun may obtain the amplitude difference between the first signal or the differential signal and provide the amplitude difference as the fourth signal. In one aspect, a third signal (e.g., an image signal) at a third frequency may be suppressed, such that a fourth signal can be provided without distortion or with reduced distortion due to intermodulation between the first and third signals.

[0091] The term "coupling" and its variations encompass two components joined directly or indirectly to each other. The term "electrical coupling" and its variations encompass two components joined directly or indirectly to each other via a conductive material (e.g., a metal or copper trace). Such coupling can be fixed (e.g., permanent or fixed) or movable (e.g., removable or releasable). Such coupling can be achieved by directly coupling two components or directly coupling each other, wherein the two components are coupled to each other using a separate intervening component and any additional intermediate component coupled to each other, or wherein the two components are coupled to each other using an intervening component integrally formed with one of the two components as a single unit. If "coupling" or its variations are modified by an additional term (e.g., direct coupling), then the general definition of "coupling" provided above is modified by the colloquial meaning of the additional term (e.g., "direct coupling" means that two components are joined without any separate intervening component), resulting in a narrower definition than the general definition of "coupling" provided above. Such coupling can be mechanical, electrical, or fluid.

[0092] The foregoing summary outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alternatives may be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A communication apparatus comprising: A first circuit is configured to generate a first signal and a second signal at the first frequency based on a third signal at a second frequency higher than the first frequency, the first signal and the second signal having opposite phases to each other; A second circuit is configured to provide the difference between the first signal and the second signal as a fourth signal; The third circuit is configured as follows: Provide the first signal to the second circuit, and Resonance occurs at a third frequency between the first frequency and the second frequency; and The fourth circuit is configured as follows: Provide the second signal to the second circuit, and It resonates at the third frequency.

2. The apparatus according to claim 1, The first circuit is time-controlled according to the third signal at the second frequency to generate the first signal and the second signal at the first frequency. The third frequency is the difference between the second frequency and the first frequency.

3. The apparatus according to claim 1, The third circuit includes a first capacitor and a first inductor coupled in parallel to each other to resonate at the third frequency, and The fourth circuit includes a second capacitor and a second inductor coupled in parallel to each other to resonate at the third frequency.

4. The apparatus of claim 3, wherein the capacitances of the first capacitor and the second capacitor are tunable.

5. The apparatus according to claim 1, further comprising: A fifth circuit, which is connected in series to the third circuit between the first and second circuits, is configured to resonate at a fourth frequency between the first and second frequencies; and A sixth circuit, which is coupled in series to the fourth circuit between the first and second circuits, is configured to resonate at the fourth frequency.

6. The apparatus according to claim 5, The first circuit is time-controlled according to the third signal at the second frequency to generate the first signal and the second signal at the first frequency. The difference between the second frequency and the first frequency is higher than the third frequency and lower than the fourth frequency.

7. The apparatus according to claim 1, The first circuit is a digital-to-analog converter circuit, and The second circuit is a balun.

8. The apparatus according to claim 1, The third circuit is the first transformer, and The fourth circuit mentioned above is the second transformer.

9. An apparatus for communication, comprising: The first circuit includes: The first port is configured to provide a first signal at a first frequency, and A second port, configured to provide a second signal at the first frequency; The second circuit includes: The third port is configured to receive the first signal. The fourth port is configured to receive the second signal, and The fifth port is configured to provide a third signal corresponding to the difference between the first signal and the second signal; A first inductor and a first capacitor are coupled between the first port of the first circuit and the third port of the second circuit, wherein the first inductor and the first capacitor are configured to resonate at a second frequency different from the first frequency. and A second inductor and a second capacitor are coupled between the second port of the first circuit and the fourth port of the second circuit, wherein the second inductor and the second capacitor are configured to resonate at the second frequency.

10. The apparatus according to claim 9, The first circuit performs timing control at a third frequency to generate the first signal and the second signal at the first frequency, wherein the third frequency is higher than the first frequency and the second frequency, and The second frequency is the difference between the third frequency and the first frequency.

11. The apparatus of claim 9, further comprising: A third inductor and a third capacitor are coupled between the first port of the first circuit and the third port of the second circuit, wherein the third inductor and the third capacitor are configured to resonate at a third frequency different from the first frequency. and A fourth inductor and a fourth capacitor are coupled between the second port of the first circuit and the fourth port of the second circuit, wherein the fourth inductor and the fourth capacitor are configured to resonate at the third frequency.

12. The apparatus according to claim 11, Wherein, i) a third circuit comprising the first inductor and the first capacitor and ii) a fourth circuit comprising the third inductor and the third capacitor are coupled in series between the first port of the first circuit and the third port of the second circuit, and Wherein i) a fifth circuit including the second inductor and the second capacitor and ii) a sixth circuit including the fourth inductor and the fourth capacitor are coupled in series between the second port of the first circuit and the fourth port of the second circuit.

13. The apparatus according to claim 11, The first circuit performs timing control at a fourth frequency to generate the first signal and the second signal at the first frequency. The fourth frequency is higher than the first frequency, the second frequency, and the third frequency, and The difference between the fourth frequency and the first frequency is higher than the second frequency and lower than the third frequency.

14. The apparatus of claim 9, wherein the second circuit is a balun.

15. The apparatus of claim 9, wherein the first signal and the second signal have opposite phases to each other, and the apparatus is a digital-to-analog converter in an integrated circuit package.

16. The apparatus according to claim 9, The first inductor and the first capacitor are part of the first transformer, and The second inductor and the second capacitor are part of the second transformer.

17. The apparatus of claim 9, wherein the capacitances of the first capacitor and the second capacitor are adjustable.

18. An apparatus for communication, comprising: A first circuit is configured to provide a first signal and a second signal at a first frequency; A second circuit is configured to provide a third signal corresponding to the difference between the first signal and the second signal; A first inductor and a first capacitor are configured to provide the first signal to the second circuit; and A second inductor and a second capacitor are configured to provide the second signal to the second circuit. The components include the first inductor, the first capacitor, the second circuit, the second inductor, and the second capacitor. It has a first impedance at a second frequency higher than the first frequency, and It has a second impedance at a third frequency higher than the second frequency, and the second impedance is higher than the first impedance.

19. The apparatus of claim 18, wherein the first inductor, the first capacitor, the second circuit, the second inductor, and the second capacitor have a third impedance at the first frequency, the third impedance being higher than the first impedance.

20. The apparatus according to claim 18, The first circuit performs timing control at a fourth frequency higher than the third frequency to generate the first signal and the second signal at the first frequency. The third frequency is the difference between the fourth frequency and the first frequency.

Images