Sram cell, memory including sram cell, and electronic device

Abstract

Disclosed are a static random access memory (SRAM) cell, a memory including the SRAM cell, and an electronic device. According to embodiments, the SRAM cell can include a substrate, first and second interconnect structures parallel to a top surface of the substrate and opposite each other, a first pull-down (PD) transistor and a first pass gate (PG) transistor on the first interconnect structure, a second PD transistor and a second PG transistor on the second interconnect structure, a first pull-up (PU) transistor vertically overlapping the first PD transistor under the first interconnect structure, and a second PU transistor vertically overlapping the second PD transistor under the second interconnect structure. Each of the transistors includes a first source / drain layer, a channel layer, and a second source / drain layer. The channel layer of each of the first PU, PD, and PG transistors is biased on a side away from the second interconnect structure with respect to the first interconnect structure. The channel layer of each of the second PU, PD, and PG transistors is biased on a side away from the first interconnect structure with respect to the second interconnect structure.

Description

Technical Field

[0001] This disclosure relates to the semiconductor field, and more specifically, to static random access memory (SRAM) cells and methods of manufacturing the same, as well as memories and electronic devices including such SRAM cells. Background Technology

[0002] In horizontal devices such as metal-oxide-semiconductor field-effect transistors (MOSFETs), the source, gate, and drain are arranged in a direction generally parallel to the substrate surface. Due to this arrangement, horizontal devices are not easily miniaturized further. In contrast, in vertical devices, the source, gate, and drain are arranged in a direction generally perpendicular to the substrate surface. Therefore, vertical devices are easier to miniaturize than horizontal devices.

[0003] In addition, there is a desire to increase integration to increase storage density, so vertical devices are promising for use in storage devices such as static random access memory (SRAM). Summary of the Invention

[0004] In view of the above, the purpose of this disclosure is at least in part to provide a static random access memory (SRAM) cell with improved performance, a method of manufacturing the same, and a memory and electronic device including such an SRAM cell.

[0005] According to one aspect of this disclosure, an SRAM cell is provided, comprising: a substrate; a first interconnect structure and a second interconnect structure extending substantially parallel to and opposite to the upper surface of the substrate; a first pull-down transistor and a first pass-through transistor disposed on the first interconnect structure; a second pull-down transistor and a second pass-through transistor disposed on the second interconnect structure; a first pull-up transistor disposed under the first interconnect structure and at least partially overlapping the first pull-down transistor in the vertical direction; and a second pull-up transistor disposed under the second interconnect structure and at least partially overlapping the second pull-down transistor in the vertical direction. Each of the first pull-up transistor, second pull-up transistor, first pull-down transistor, second pull-down transistor, first pass-through transistor, and second pass-through transistor includes a first source / drain layer, a channel layer, and a second source / drain layer sequentially disposed in the vertical direction. The channel layer of each of the first pull-up transistor, first pull-down transistor, and first pass-through transistor is biased relative to the first interconnect structure on a side away from the second interconnect structure. The channel layer of each of the second pull-up transistor, second pull-down transistor, and second pass-through transistor is biased relative to the second interconnect structure on a side away from the first interconnect structure.

[0006] According to another aspect of this disclosure, a method for manufacturing an SRAM cell is provided, comprising: sequentially depositing a first group of first source / drain layers, a first channel defining layer, and a second source / drain layer on a substrate, and a second group of first source / drain layers, a second channel defining layer, and a second source / drain layer on a substrate; forming a hard mask layer on the stack, the hard mask layer having: a rectangular ring pattern having a first side and a third side extending in a first direction and opposite to each other, and a second side and a fourth side extending in a second direction intersecting the first direction and opposite to each other; and a first protruding pattern and a second protruding pattern disposed on the first side of the rectangular ring pattern, and a third protruding pattern and a fourth protruding pattern disposed on the third side of the rectangular ring pattern; patterning the outer side of the stack using the hard mask layer; and refining the channel defining layer such that the first channel defining layer retains a first pull-up portion and a second pull-up portion that overlap with the first protruding pattern and the third protruding pattern in the vertical direction, respectively, while these portions are recessed in the lateral direction relative to the first protruding pattern and the third protruding pattern, respectively, and the second channel defining layer... The channel defining layer retains a first pull-down portion, a first pass-through portion, a second pull-down portion, and a second pass-through portion that overlap vertically with the first to fourth protruding patterns, while these portions are recessed laterally relative to the first to fourth protruding patterns; a channel layer is formed on the vertical sidewalls of the ends of the first pull-up portion, second pull-up portion, first pull-down portion, first pass-through portion, second pull-down portion, and second pass-through portion of the channel defining layer in the second direction; and the inner side of the stack is patterned using a hard mask layer, wherein the patterning process further includes: selectively etching the second source / drain layer of the second group to separate it into four separate portions corresponding to the first to fourth protruding patterns; removing the second channel defining layer; cutting the second source / drain layer of the first group and the first source / drain layer of the first group in the region between the first protruding pattern and the fourth side and in the region between the third protruding pattern and the second side to form a first interconnect structure and a second interconnect structure; and removing the first channel defining layer.

[0007] According to another aspect of this disclosure, an electronic device is provided, including a memory device having the above-described SRAM cells.

[0008] According to embodiments of this disclosure, the constituent transistors of an SRAM cell can be arranged in a vertically stacked manner, thereby saving area. The upper and lower transistor layers can be stacked in a self-aligned manner, further saving area. The channel layers of the transistors can be formed using separate epitaxial processes, thus ensuring the material quality of the grown film and precisely controlling the film thickness. Furthermore, the channel widths of the pull-down transistors and gate transistors in the SRAM cell can be flexibly set using photolithography, and the channel length of the pull-up transistor can be continuously adjusted by controlling the thickness of the epitaxially grown film. Therefore, the transistor driving force of the entire SRAM cell can be flexibly adjusted for each transistor type. The constituent transistors in the SRAM cell can be interconnected with each other using silicon interconnect technology, which saves area and avoids the stress of back-channel metal interconnects. Attached Figure Description

[0009] The above and other objects, features and advantages of this disclosure will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 The equivalent circuit diagram of a static random access memory (SRAM) cell is schematically shown.

[0011] Figure 2 A perspective view of an SRAM cell according to an embodiment of the present disclosure is shown schematically;

[0012] Figure 3(a) , 3(b) Figure 3(c) shows Figure 2 An exploded perspective view of the SRAM cell shown;

[0013] Figures 4 to 46(c) The illustrations schematically depict some stages in the process of manufacturing an SRAM cell according to embodiments of the present disclosure;

[0014] Figure 47 A perspective view of an SRAM according to an embodiment of the present disclosure is shown schematically.

[0015] Throughout the accompanying drawings, the same or similar reference numerals denote the same or similar parts. Detailed Implementation

[0016] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0017] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0018] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0019] According to embodiments of this disclosure, a static random access memory (SRAM) cell based on vertical nanosheet / nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) is provided. In the SRAM cell, the vertical devices that form the SRAM cell can be stacked in the vertical direction to further improve integration density.

[0020] Figure 1 The equivalent circuit diagram of an SRAM cell is shown schematically.

[0021] like Figure 1 As shown, an SRAM cell can have a 6T structure, comprising six transistors M1 to M6, such as field-effect transistors (FETs). Of these six transistors, four transistors M1, M2, M3, and M4 can form two cross-coupled inverters, serving as storage locations for one bit within the SRAM cell. The other two transistors, M5 and M6, under the control of the word line WL, can control the data transfer between the storage location and the bit line BL and complementary bit line / BL, respectively, to achieve read and write operations.

[0022] In the four transistors M1, M2, M3, and M4 that constitute the cross-coupled inverter, two p-type transistors, M2 and M4, can be connected to the power supply voltage V. DD The first transistor, M1, can be called a "pull-up transistor" (PU). The two n-type transistors, M1 and M3, can be connected to ground and are therefore called "pull-down transistors" (PD). Transistors M5 and M6 (which can also be n-type) can control read and write operations, or data transfer, and are therefore called "access control transistors" or "pass-through gate transistors" (PG).

[0023] The read and write operations of this 6T SRAM cell are briefly described below.

[0024] First, the read operation is described. Assume the bit stored in the memory location is "1", meaning it's high at node Q and low at node / Q. At the start of the read cycle, bit line BL and complementary bit line / BL can be pre-charged to logic 1, and then word line WL can be charged high to turn on access control transistors M5 and M6. Due to the high level at Q, pull-up transistor M2 is turned off while pull-down transistor M1 is turned on. Thus, pull-down transistor M1 and access control transistor M5 connect complementary bit line / BL to ground, causing the pre-charged value on complementary bit line / BL to be discharged, resulting in a value of 0 on complementary bit line / BL. On the other hand, due to the low level at / Q, pull-up transistor M4 is turned on while pull-down transistor M3 is turned off. Thus, pull-up transistor M4 and access control transistor M6 connect bit line BL to the power supply voltage V. DD The circuit is connected and thus maintains a pre-charged value, i.e., a value of 1 on bit line BL. If the stored bit is "0", the opposite circuit state will cause a value of 1 on the complementary bit line / BL and a value of 0 on bit line BL. The stored bit "0" or "1" can be read by distinguishing which bit line BL or the complementary bit line / BL has a higher potential.

[0025] During a write operation, at the start of the write cycle, the state to be written is loaded onto bit line BL. For example, to write "0", bit line BL is set to "0" (and the complementary bit line / BL is set to "1"). Word line WL can then be charged high to turn on access control transistors M5 and M6, thus loading the state of bit line BL into the storage location of the SRAM cell. This is achieved by designing the bit line input drive (transistor) to be more robust than the storage location (transistor), allowing the bit line state to override the previous state of the cross-coupled inverter in the storage location.

[0026] Figure 2 A perspective view of an SRAM cell according to an embodiment of the present disclosure is schematically shown. Figure 3(a) , 3(b) Figure 3(c) shows Figure 2 The exploded perspective view of the SRAM cell is shown.

[0027] like Figure 2 , 3(a) As shown in 3(b) and 3(c), a 6T SRAM cell may include six transistors, specifically two pull-up transistors PU-1 and PU-2, two pull-down transistors PD-1 and PD-2, and two pass-gate transistors PG-1 and PG-2. These transistors can all be vertical nanosheet / nanowire transistors.

[0028] Each transistor may include an active region extending in a vertical direction (e.g., substantially perpendicular to the upper surface of the substrate) relative to the upper surface of the substrate. The active region may include a channel region and source / drain regions located on opposite sides of the channel region in the vertical direction. As described below, the active region of the transistor may include a first source / drain layer, a channel layer, and a second source / drain layer stacked sequentially in the vertical direction. The source / drain regions may be formed substantially in the first source / drain layer and the second source / drain layer, respectively, and the channel region may be formed substantially in the channel layer. For example, the source / drain regions may be implemented using doped regions in the source / drain layers. The gate stack may be formed around at least a portion or even all of the outer periphery of the channel region. (Note: The last sentence appears to be a typo and can be omitted.) Figure 2 In the perspective view, the position of the gate stack is schematically shown with dashed lines.

[0029] As shown in the figure, the active region, particularly the channel layer, can take the form of a nanosheet. The nanosheet can have a width in a first direction (e.g., the x-direction) and a thickness in a second direction intersecting (e.g., perpendicular to) the first direction (e.g., the y-direction), and can have a certain height in a vertical direction (e.g., the z-direction). Generally, the width of the nanosheet is greater than its thickness. When the width is small, the nanosheet can become a nanowire. In this example, the nanosheet is shown as having a lateral extension portion extending laterally relative to the substrate (more specifically, extending on the top or bottom surface of the respective source / drain layer) and a vertical extension portion extending vertically. Depending on the process parameters (e.g., etching depth in the etching process described later, film thickness in the epitaxial growth process, etc.), the lateral extension portion of the nanosheet can be relatively small or inconspicuous, so that the channel layer as a whole takes the form of a vertical nanosheet (or nanowire). The first and second source / drain layers can be substantially self-aligned with the channel layer in the vertical direction.

[0030] Pull-up transistors PU-1 and PU-2 can be vertically self-aligned with pull-down transistors PD-1 and PD-2 respectively, and can at least partially overlap in the vertical direction.

[0031] According to embodiments of this disclosure, such a transistor can be a conventional FET. In the case of a conventional FET, the source / drain regions on both sides of the channel region can be doped with the same conductivity type (e.g., n-type or p-type). A conductive channel can be formed between the source / drain regions located at both ends of the channel region through the channel region. Alternatively, such a transistor can be a tunneling FET. In the case of a tunneling FET, the source / drain regions on both sides of the channel region can be doped with different conductivity types (e.g., n-type and p-type, respectively). In this case, charged particles such as electrons can tunnel from the source region through the channel region into the drain region, thereby forming a conductive path between the source and drain regions. Although the conduction mechanisms in conventional FETs and tunneling FETs are not the same, they both exhibit electrical performance in which the conduction between the source and drain regions can be controlled by the gate. Therefore, for conventional FETs and tunneling FETs, the terms "source / drain layer (source / drain region)" and "channel layer (channel region)" are used interchangeably, although a "channel" in the conventional sense does not exist in a tunneling FET.

[0032] Unlike conventional technologies where the constituent transistors in an SRAM cell are arranged in a planar layout, according to embodiments of this disclosure, the constituent transistors in an SRAM cell can be stacked vertically to further save the area occupied by the SRAM cell.

[0033] According to an embodiment, the constituent transistors in an SRAM cell can be stacked vertically to save the area occupied by the SRAM cell. For example, transistors of the same conductivity type can be disposed on one layer (e.g., at substantially the same height from the upper surface of the substrate), and transistors of different conductivity types can be disposed on two layers (e.g., at different heights from the upper surface of the substrate), and these two layers can at least partially overlap in the vertical direction.

[0034] exist Figure 2 , 3(a) In the examples shown in 3(b) and 3(c), the pull-up transistors PU-1 and PU-2, which are p-type transistors, are disposed on one layer, while the pull-down transistors PD-1 and PD-2, which are n-type transistors, and the gate transistors PG-1 and PG-2 are disposed on one layer. In this example, the p-type transistors are on the lower layer and the n-type transistors are on the upper layer, but this disclosure is not limited thereto. For example, by... Figure 2 , 3(a) By flipping the structures shown in 3(b) and 3(c) upside down (with the substrate remaining at the bottom) and adjusting the interconnect structure accordingly, the p-type transistors can be placed on the upper layer and the n-type transistors on the lower layer.

[0035] Since the electrical connections to the pull-down transistors PD-1 and PD-2, which are n-type transistors, and the gate transistors PG-1 and PG-2 are relatively complex, it is advantageous to place the n-type transistors on the upper layer, for example, to facilitate the fabrication of electrical connections. In the accompanying drawings and the following description, the example of placing the n-type transistors on the upper layer is used.

[0036] These transistors can be electrically connected to each other in the 6T layout described above.

[0037] like Figure 2 , 3(a) As shown in 3(b) and 3(c), the source / drain layer S / D4_U (e.g., a drain region formed therein) on the upper side of the first pull-up transistor PU-1 can be connected to the source / drain layer S / D3_L (e.g., a drain region formed therein) on the lower side of the first pull-down transistor PD-1, and the first node between them corresponds to, for example... Figure 1 The Q node in the first transistor. The source / drain layer S / D6_L on the lower side of the gate transistor PG-1 can be connected to the first node, while the source / drain layer S / D6_U on the upper side can be connected to the first bit line through the corresponding contact plug BL-1 (e.g., Figure 1 (Bit line BL in the diagram). Here, the connection between the source / drain layers of the first pull-up transistor PU-1, the first pull-down transistor PD-1, and the first pass-gate transistor PG-1 is shown as the first interconnect structure IIC1.

[0038] Similarly, the source / drain layer S / D2_U (e.g., a drain region formed therein) on the upper side of the second pull-up transistor PU-2 can be connected to the source / drain layer S / D1_L (e.g., a drain region formed therein) on the lower side of the second pull-down transistor PD-2, and the second node between them corresponds to, for example... Figure 1 The / q node. The second source / drain layer S / D5_L below the gate transistor PG-2 can be connected to the second node, while the upper source / drain layer S / D5_U can be connected to the second bit line via the corresponding contact plug BL-2 (e.g., Figure 1 (Bit line / BL in the diagram). Here, the connection between the source / drain layers of the second pull-up transistor PU-2, the second pull-down transistor PD-2, and the second pass-gate transistor PG-2 is shown as the second interconnect structure IIC2. As described below, the first interconnect structure IIC1 and the second interconnect structure IIC2 are not necessarily separate conductive layers, but can also be implemented through the material layers where the source / drain layers of the transistors are located.

[0039] The first interconnect structure IIC1 may include a first segment SEG1 extending along a first direction (e.g., the x-direction) and a second segment SEG2 extending along a second direction (e.g., the y-direction). The first segment SEG1 and the second segment SEG2 may be continuous with each other (e.g., integral with each other). Here, the first interconnect structure IIC1 is shown as an L-shape formed by the first segment SEG1 and the second segment SEG2. However, it should be noted that due to factors such as manufacturing process or process margin, the first interconnect structure IIC1 may also include additional portions, for example, a small segment extending substantially parallel to the first segment SEG1 may be connected to the end of the second segment SEG2.

[0040] Similarly, the second interconnect structure IIC2 may include a third SEG3 extending along a first direction (e.g., the x-direction) and a fourth SEG4 extending along a second direction (e.g., the y-direction). The third SEG3 and the fourth SEG4 may be continuous with each other (e.g., integral with each other). Here, the second interconnect structure IIC2 is shown as an L-shape formed by the third SEG3 and the fourth SEG4. However, it should be noted that due to factors such as manufacturing process or process margin, the second interconnect structure IIC2 may also include additional portions; for example, a small segment extending substantially parallel to the third SEG3 may be connected to the end of the fourth SEG4. In the top view, the first interconnect structure IIC1 and the second interconnect structure IIC2 may form a substantially closed loop (e.g., a rectangle).

[0041] The first interconnect structure IIC1 may include a first sub-interconnect structure IIC1-1 and a second sub-interconnect structure IIC1-2 superimposed on the first sub-interconnect structure IIC1-1. The first sub-interconnect structure IIC1-1 and the second sub-interconnect structure IIC1-2 may be in contact with each other. Although the interface between the first sub-interconnect structure IIC1-1 and the second sub-interconnect structure IIC1-2 is shown in the figure, they may be integral with each other (e.g., formed by the same material layer, but with different doping, as described below). The first sub-interconnect structure IIC1-1 and the second sub-interconnect structure IIC1-2 may have substantially the same pattern as each other, for example, they may substantially overlap each other in a top view.

[0042] Similarly, the second interconnect structure IIC2 may include a third sub-interconnect structure IIC2-1 and a fourth sub-interconnect structure IIC2-2 stacked on top of the third sub-interconnect structure IIC2-1. The third sub-interconnect structure IIC2-1 and the fourth sub-interconnect structure IIC2-2 may be in contact with each other. Although the interface between the third sub-interconnect structure IIC2-1 and the fourth sub-interconnect structure IIC2-2 is shown in the figure, they may be integral with each other (e.g., formed by the same material layer, but with different doping, as described below). The third sub-interconnect structure IIC2-1 and the fourth sub-interconnect structure IIC2-2 may have substantially the same pattern, for example, they may substantially overlap each other in a top view.

[0043] The first sub-interconnect structure IIC1-1 and the third sub-interconnect structure IIC2-1 can be substantially coplanar and can have substantially the same doping. The second sub-interconnect structure IIC1-2 and the fourth sub-interconnect structure IIC2-2 can be substantially coplanar and can have substantially the same doping.

[0044] The first SEG1 may include a main body extending along a first direction (e.g., the x-direction) and a first protruding portion PR1 and a second protruding portion PR2 protruding from the main body in a direction away from the third SEG3 (e.g., along the y-direction). The first protruding portion PR1 (more specifically, the portion PR1-1 on the first sub-interconnect structure IIC1-1 and the portion PR1-2 on the second sub-interconnect structure IIC1-2) may form the upper source / drain layer S / D4_U of the first pull-up transistor PU-1 and the lower source / drain layer S / D3_L of the first pull-down transistor PD-1, and the second protruding portion PR2 (more specifically, the portion PR2-2 on the second sub-interconnect structure IIC1-2) may form the lower source / drain layer S / D6_L of the first through-gate transistor PG-1. Note that the second protruding portion PR2 may include the portion PR2-1 on the first sub-interconnect structure IIC1-1 (see Figure 3(c)). Figure 2 (and Figures 3(a) and 3(b) are not shown for clarity).

[0045] Similarly, the third SEG3 may include a main body extending along a first direction (e.g., the x-direction) and a third protruding portion PR3 and a fourth protruding portion PR4 protruding from the main body in a direction away from the first SEG1 (e.g., along the y-direction). The third protruding portion PR3 (more specifically, its portion PR3-1 on the third sub-interconnect structure IIC2-1 and its portion PR3-2 on the fourth sub-interconnect structure IIC2-2) may form the upper source / drain layer S / D2_U of the second pull-up transistor PU-2 and the lower source / drain layer S / D1_L of the second pull-down transistor PD-2, and the fourth protruding portion PR4 (more specifically, its portion PR4-2 on the fourth sub-interconnect structure IIC2-2) may form the lower source / drain layer S / D5_L of the second through-gate transistor PG-2. Note that the fourth protruding portion PR4 may include the portion PR4-1 on the third sub-interconnect structure IIC2-1 (see Figure 3(c)). Figure 2 (and Figures 3(a) and 3(b) are not shown for clarity).

[0046] The first protrusion PR1 and the fourth protrusion PR4 can be self-aligned in a second direction (e.g., the y-direction). Similarly, the second protrusion PR2 and the third protrusion PR3 can be self-aligned in a second direction (e.g., the y-direction).

[0047] The first pull-down transistor PD-1 may include an upper source / drain layer S / D3_U corresponding to the first protrusion PR1 (or, the lower source / drain layer S / D3_L), with a channel layer CH3 extending vertically between them. The upper source / drain layer S / D3_U may be self-aligned with the lower source / drain layer S / D3_L in the vertical direction (e.g., the z-direction). The first through-gate transistor PG-1 may include an upper source / drain layer S / D6_U corresponding to the second protrusion PR2 (or, the lower source / drain layer S / D6_L), with a channel layer CH6 extending vertically between them. The upper source / drain layer S / D6_U may be self-aligned with the lower source / drain layer S / D6_L in the vertical direction (e.g., the z-direction).

[0048] The second pull-down transistor PD-2 may include an upper source / drain layer S / D1_U corresponding to the third protrusion PR3 (or, the lower source / drain layer S / D1_L), with a channel layer CH1 extending vertically between them. The upper source / drain layer S / D1_U may be self-aligned with the lower source / drain layer S / D1_L in the vertical direction (e.g., the z-direction). The second through-gate transistor PG-2 may include an upper source / drain layer S / D5_U corresponding to the fourth protrusion PR4 (or, the lower source / drain layer S / D5_L), with a channel layer CH5 extending vertically between them. The upper source / drain layer S / D5_U may be self-aligned with the lower source / drain layer S / D5_L in the vertical direction (e.g., the z-direction).

[0049] The first pull-up transistor PU-1 may include a lower source / drain layer S / D4_L corresponding to the first protrusion PR1 (or, the upper source / drain layer S / D4_U), with a channel layer CH4 extending vertically between them. The lower source / drain layer S / D4_L may be self-aligned with the upper source / drain layer S / D4_U in the vertical direction (e.g., the z-direction). Similarly, the second pull-up transistor PU-2 may include a lower source / drain layer S / D2_L corresponding to the third protrusion PR3 (or, the upper source / drain layer S / D2_U), with a channel layer CH2 extending vertically between them. The lower source / drain layer S / D2_L may be self-aligned with the upper source / drain layer S / D2_U in the vertical direction (e.g., the z-direction).

[0050] The lower source / drain layer S / D4_L of the first pull-up transistor PU-1 and the lower source / drain layer S / D2_L of the second pull-up transistor PU-2 can be embedded in a ring structure of dielectric (see...). Figure 47 In particular, within the DILR segment. This ring structure can have a first side corresponding to the first SEG1 segment, a second side corresponding to the second SEG2 segment, a third side corresponding to the third SEG3 segment, and a fourth side corresponding to the fourth SEG4 segment. For example, this ring structure can be substantially self-aligned with the first interconnect structure IIC1 and the second interconnect structure IIC2, and can substantially overlap in the vertical direction (e.g., the z-direction) in a top view. In this ring structure, in addition to the lower source / drain layer S / D4_L of the first pull-up transistor PU-1 and the lower source / drain layer S / D2_L of the second pull-up transistor PU-2, a first dummy source / drain layer DPR1 can be embedded in the first side, and a second dummy source / drain layer DPR2 can be embedded in the third side. The first dummy source / drain layer DPR1 and the second dummy source / drain layer DPR2 may have substantially the same material as the lower source / drain layer S / D4_L of the first pull-up transistor PU-1 and the lower source / drain layer S / D2_L of the second pull-up transistor PU-2. This ring structure will be described in further detail below.

[0051] Each channel layer CH1 to CH6 can be self-aligned between the corresponding lower and upper source / drain layers. As described above, since the lower and upper source / drain layers of each transistor can be represented as protrusions on the interconnect structure or structures corresponding to protrusions (self-aligned and potentially overlapping vertically in a top view), the channel layers self-aligned between them can be biased relative to the interconnect structure. Specifically, the channel layer CH4 of the first pull-up transistor PU-1, the channel layer CH3 of the first pull-down transistor PD-1, and the channel layer CH6 of the first pass-gate transistor PG-1 are biased relative to the first interconnect structure IIC1 (particularly its first segment SEG1) on a side away from the second interconnect structure IIC2, and in particular, can be offset from the main body of the first segment SEG1 (e.g., not overlapping with the main body of the first segment SEG1 in a top view). Similarly, the channel layer CH2 of the second pull-up transistor PU-2, the channel layer CH1 of the second pull-down transistor PD-2, and the channel layer CH5 of the second pass-gate transistor PG-2 are biased relative to the second interconnect structure IIC2 (especially its third segment SEG3) on a side away from the first interconnect structure IIC1, and in particular, they can be offset from the main body of the third segment SEG3 (e.g., not overlapping with the main body of the third segment SEG3 in a top view).

[0052] Each channel layer CH1 to CH6 may have a C-shaped cross-section. More specifically, each channel layer CH1 to CH6 may include a first lateral extension extending on the top surface of the respective lower source / drain layer, a second lateral extension extending on the bottom surface of the respective upper source / drain layer, and a vertically extending portion connecting the first and second lateral extensions. The lower and upper source / drain layers define a space surrounding the channel layer, particularly its vertical portion, so that the gate stack embedded in this space may surround the outer periphery of the channel layer, particularly its vertical portion.

[0053] It should be noted that due to factors such as manufacturing process and materials, the C-shaped cross-sections of each channel layer CH1 to CH6 in the final device may not be obvious or can not be observed, and in fact they appear as vertically extending forms.

[0054] The gate electrodes of the first pull-up transistor PU-1 and the first pull-down transistor PD-1 can be electrically connected (e.g., in direct contact) to the second interconnect structure IIC2, and thus can be electrically connected to each other (defining the second node as...). Figure 1 (as shown in the node / Q). Similarly, the gate electrodes of the second pull-up transistor PU-2 and the second pull-down transistor PD-2 can be electrically connected (e.g., in direct contact) to the first interconnect structure IIC1, and thus can be electrically connected to each other (defining the first node as shown in the diagram). Figure 1 The node Q shown is shown.

[0055] The source / drain layers (e.g., source regions formed therein) on the underside of the first pull-up transistor PU-1 and the second pull-up transistor PU-2 can be disposed on the substrate and can receive the power supply voltage V through contact plugs to the substrate. DD The source / drain layers (e.g., source regions formed therein) on the upper sides of the first pull-down transistor PD-1 and the second pull-down transistor PD-2 can receive the ground voltage GND through corresponding contact plugs. The gate electrodes of the first pass-gate transistor PG-1 and the second pass-gate transistor PG-2 can be electrically connected to word lines (e.g., through corresponding contact plugs WL-1 and WL-2, respectively) Figure 1 The word line WL is shown.

[0056] like Figure 3(a) and 3(b) As shown, based on the first node and the second node, the six constituent transistors can be divided into two groups: a first pull-up transistor PU-1, a first pull-down transistor PD-1, and a first pass-gate transistor PG-1 are all connected to the first node (see Figure 3(a)); a second pull-up transistor PU-2, a second pull-down transistor PD-2, and a second pass-gate transistor PG-2 are all connected to the second node (see Figure 3(b)). These two groups can have the same or symmetrical layout (the layout shown in Figure 3(a) can be obtained by rotating it 180° to obtain the layout shown in Figure 3(b)). However, this disclosure is not limited to this. These two groups can have different or asymmetrical layouts.

[0057] Figures 4 to 46(c) The illustrations schematically depict some stages in the process of manufacturing an SRAM cell according to embodiments of the present disclosure.

[0058] The materials for each layer are listed in the following description. However, these are merely examples. The materials for each layer are primarily determined based on its function (e.g., semiconductor materials provide active regions, dielectric materials provide void filling and electrical isolation, etc.) and the required etch selectivity. In the description, it may not always be explicitly stated which other layers' materials exhibit etch selectivity, or it may simply be mentioned that "required etch selectivity" is necessary. This "required etch selectivity" can be determined at least in part from the relevant etching process.

[0059] like Figure 4As shown, a substrate 1001 is provided. This substrate 1001 can be of various forms. The substrate 1001 may include semiconductor materials, such as, but not limited to, bulk semiconductor materials like bulk Si, semiconductor-on-insulator (SOI), compound semiconductor materials like SiGe, etc. In the following description, for ease of explanation, a bulk Si substrate will be used as an example. In the substrate 1001, well regions (not shown) may be formed as needed, for example, by implanting impurities. In the example where a p-type transistor is disposed in the underlying layer, the implanted impurity may be an n-type impurity.

[0060] On substrate 1001, a contact layer 1003 can be formed to facilitate connection between the source / drain layers of the lower-layer transistors (e.g., p-type pull-up transistors) in the SRAM cell and the substrate-side contact layer. The contact layer 1003 can be formed by implanting impurities into the upper portion of substrate 1001. In the example where the p-type transistor is located in the lower layer, the implanted impurity can be a p-type impurity such as B or In, with a concentration of, for example, about 1E18-1E21 cm⁻¹. -3 For example, 1.5E20 cm -3 Alternatively, a contact layer 1003 can be formed on the substrate 1001 by epitaxial growth.

[0061] An active material layer may be disposed on the contact layer 1003. For example, a first source / drain layer 1007, a channel defining layer 1009, and a second source / drain layer 1011 for a p-type transistor, and a first source / drain layer 1013, a channel defining layer 1015, and a second source / drain layer 1017 for an n-type transistor may be sequentially formed by epitaxial growth. These layers may have the desired conductivity by in-situ doping during growth or by implanting impurities after growth.

[0062] Adjacent layers of semiconductor materials formed on substrate 1001 may have etch selectivity relative to each other. Except for the second source / drain layer 1011 for p-type transistors and the first source / drain layer 1013 for n-type transistors, they may have no etch selectivity or low etch selectivity relative to each other because they are treated almost as the same layer in subsequent processing, except that they are doped to different conductivity types to serve as source / drain layers for p-type and n-type transistors, respectively. Furthermore, for p-type transistors, the first source / drain layer 1007 and the second source / drain layer 1011 may comprise the same material. Similarly, for n-type transistors, the first source / drain layer 1013 and the second source / drain layer 1017 may comprise the same material.

[0063] In one example, these semiconductor material layers may comprise alternating stacks of Si and SiGe. For instance, if the substrate 1001 is Si, the contact layer 1003 may comprise SiGe. For a p-type transistor, the first source / drain layer 1007 may comprise Si with a thickness of about 20-50 nm; the channel defining layer 1009 may comprise SiGe with a thickness of about 10-100 nm; and the second source / drain layer 1011 may comprise Si with a thickness of about 10-30 nm. The first source / drain layer 1007 and the second source / drain layer 1011 may be p-type doped (e.g., doped with B) at a doping concentration of, for example, about 1E19-1E21 cm⁻¹. -3 (For example, 1.5E20 cm) -3 Similarly, for an n-type transistor, the first source / drain layer 1013 may comprise Si with a thickness of approximately 10-30 nm; the channel defining layer 1015 may comprise SiGe with a thickness of approximately 10-100 nm; and the second source / drain layer 1017 may comprise Si with a thickness of approximately 20-50 nm. The first source / drain layer 1013 and the second source / drain layer 1017 may be n-type doped (e.g., doped with As) at a doping concentration of, for example, approximately 1E19-1E21 cm⁻¹. -3 (For example, 2.5E20 cm) -3 ).

[0064] Although the second source / drain layer 1011 for the p-type transistor and the first source / drain layer 1013 for the n-type transistor are shown as two layers here to better illustrate the construction of p-type and n-type transistors, they can be the same material layer. For example, different types of doping can be achieved on the upper and lower halves of this material layer by performing different types of in-situ doping at different stages of growth. Therefore, there may not be an actual physical interface between the second source / drain layer 1011 for the p-type transistor and the first source / drain layer 1013 for the n-type transistor.

[0065] A hard mask can be placed on the active material layer to subsequently define the active regions and interconnect patterns. The hard mask is set up to provide proper pattern definition, etch stops, etc., in subsequent processes. The number of hard mask layers and the material of each layer can vary depending on the process. In this example, the layer configuration of the hard mask allows at least one layer of the hard mask to remain until at least the transistor fabrication is complete. In the hard mask setup, sidewalls (spacers) are used to achieve finer control over the pattern size.

[0066] For example, such as Figure 5(a) and 5(b)As shown in the top view and cross-sectional view along line AA′, an aluminum oxide (Al₂O₃) layer 1019 with a thickness of approximately 2-10 nm can be formed by deposition. The primary reason for choosing aluminum oxide is to consider its etching selectivity compared to dielectric materials used in subsequent processes, such as oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), and oxynitrides (e.g., silicon oxynitride). This aluminum oxide layer 1019 will be retained for most stages of the subsequent processes as part of a hard mask, particularly to define the main portion of the interconnect structure.

[0067] As described above, the interconnect structure can form a substantially closed pattern, such as a rectangle, in a top view. According to an embodiment, this pattern can be defined by sidewalls. To form the sidewalls, a mandrel 1021, for example, of polysilicon can be formed on the alumina layer 1019. The mandrel 1021 can be patterned, for example, into a rectangle by photolithography. Sidewalls 1023, for example, of nitride, can be formed on the sidewalls of the rectangular mandrel 1021 by a sidewall forming process. The sidewall forming process can include depositing a thin nitride layer on the above structure in a generally conformal manner, for example, by anisotropically etching the deposited nitride layer using reactive ion etching (RIE) along the vertical direction to remove its lateral extensions while leaving its vertical extensions. Thus, the sidewalls 1023 are formed as a closed pattern around the periphery of the mandrel 1021. In this example, the sidewall 1023 is in the shape of a rectangular ring, thus including two sides extending along a first direction (e.g., a horizontal direction within the plane of the paper in FIG. 5(a)) and two sides extending along a second direction intersecting (e.g., perpendicular to) the first direction (e.g., a vertical direction within the plane of the paper in FIG. 5(a)). Each side can have a substantially uniform thickness. This closed pattern can then define the main portion of the interconnect structure. The pattern of the sidewall 1023 varies with the pattern of the mandrel 1021, and the patterns of the mandrel 1021 and therefore the sidewall 1023 can be varied differently depending on the device layout design.

[0068] Additionally, protruding patterns can be defined on the edges of the rectangular ring pattern (e.g., two edges extending along the first direction) to define protruding portions of the interconnect structure as part of a hard mask in subsequent processes.

[0069] For example, such as Figure 6(a) and 6(b)As shown in the top view and cross-sectional view along line AA′, an alumina layer 1025, a nitride layer 1027 with a thickness of about 10-100 nm, and an alumina layer 1029 with a thickness of about 2-10 nm are sequentially formed on an alumina layer 1019 on which the core mold 1021 and sidewalls 1023 are formed, through deposition. The thickness of the alumina layer 1025 can exceed the thickness of the core mold 1021, thereby covering the top surface of the core mold 1021 (and the sidewalls 1023 on its sidewalls). The alumina layer 1025 can be planarized, such as by chemical mechanical polishing (CMP), and thus can have a substantially flat top surface.

[0070] Photoresist 1031 can be formed on a hard mask. Through exposure and development, the photoresist 1031 can be patterned into two strip-shaped portions 1031a and 1031b extending along a second direction (each intersecting one of the two sides of the sidewall 1023 extending along a first direction). Additionally, the photoresist 1031 may also include, for example, a circular portion 1031c outside the sidewall 1023 to define a portion for defining the applied power supply voltage V. DD The contact plugs. The linewidth (e.g., its width) of the strip portions 1031a and 1031b and the linewidth (e.g., its diameter) of the circular portion 1031c in the photoresist 1031 can be greater than the linewidth of the sidewall 1023.

[0071] like Figure 7 As shown in the cross-sectional view along line AA′, the photoresist 1031, configured as an etching mask, is used to sequentially etch the aluminum oxide layer 1029, the nitride layer 1027, and the aluminum oxide layers 1025 and 1019 anisotropically, for example, in a vertical RIE. When etching the nitride layer 1027, the sidewalls 1023 (which, in this embodiment, also include nitride) are unaffected because they are covered by the aluminum oxide layer 1025. Therefore, the core mold 1021 and the sidewalls 1023 on its sidewalls can be retained (the aluminum oxide layer 1019 beneath them is retained), and at the locations of the photoresist strip portions 1031a and 1031b, the strip structure extends across the core mold 1021 and the sidewalls 1023 on its sidewalls. Additionally, a vertical pillar structure is formed at the location of the circular portion 1031c of the photoresist. Afterwards, the photoresist 1031 can be removed.

[0072] The active layer can be patterned using the hard mask pattern described above. For example, as... Figure 8As shown in the cross-sectional view along line AA′, the second source / drain layer 1017, the channel defining layer 1015, and the first source / drain layer 1013 for an n-type transistor, and the second source / drain layer 1011 and the channel defining layer 1009 for a p-type transistor, can be etched sequentially using, for example, a re-etching process (RIE). The RIE can be performed in a direction substantially perpendicular to the substrate surface and can stop at the first source / drain layer 1007 for the p-type transistor. In this example, the patterning of the active material layer for the p-type transistor does not extend to the first source / drain layer 1007. This is primarily because if the first source / drain layer 1007 were also etched here, the underlying contact layer 1003 would be exposed. In the subsequent refinement process of the channel defining layer (in this example, SiGe), the exposed contact layer 1003 (in this example, SiGe) would be undesirably etched.

[0073] As described above, the channel defining layer can be refined. For example, such as... Figure 9 As shown in the cross-sectional view along line AA′, the channel defining layers 1009 and 1015 can be further selectively etched. Selective etching can be performed using atomic layer etching (ALE) to precisely control the etching depth. Here, the etching depth can be controlled such that after the channel layer is subsequently grown on the surface of the channel defining layer, the space left between the source / drain layers is sufficient to form a gate stack around the outer periphery of the channel layer.

[0074] Furthermore, the etching depth can be controlled, for example, to be less than the linewidth of the sidewall 1023, so that the refined channel defining layers 1009 and 1015 do not recess into the inner side of the sidewall 1023. This prevents other material layers formed in subsequent processes from entering the inner side of the sidewall 1023 through the recesses of the channel defining layers 1009 and 1015, thus complicating the subsequent etching of the active material layer inside the sidewall 1023. Additionally, the etching depth can be controlled to be less than half the linewidth of the strip structure (see the strip portions 1031a and 1031b shown in the top view of FIG. 6(a)). In this way, the channel defining layers 1009 and 1015 will not be severed when etched from both sides of the strip structure; that is, the channel defining layers 1009 and 1015 will still have strip portions corresponding to the strip structure on the outer side of the sidewall 1023. This is to ensure that the trench layers subsequently grown on the surfaces of the trench limiting layers 1009 and 1015 are located outside the sidewall 1023.

[0075] This refinement allows control over the width of the channel-defining layer beneath the strip structure on the outer sidewall 1023 (see the top view in Figure 10(a)). This width of the channel-defining layer determines the size of the channel layer subsequently grown on its surface (and thus at least partially determines the channel width defined by the channel layer). The channel width can be flexibly controlled by adjusting the parameters of the refinement process. Furthermore, as mentioned above, the channel length can be flexibly controlled by adjusting the thickness of the channel-defining layer. Therefore, the driving capability of the transistor can be flexibly adjusted according to the device design.

[0076] Currently, the strip structure of the hard mask and the corresponding portion of the active layer beneath it extend continuously in the second direction (see the top view in Figure 10(a)). These portions can be separated in the second direction to achieve device isolation.

[0077] For example, such as Figure 10(a) and 10(b) As shown in the top view and cross-sectional view along line AA′, respectively, a filling layer 1033, such as an oxide layer, can be formed on the resulting structure to fill various voids in the structure. The filling layer 1033 can be planarized, such as by CMP, to give it a substantially flat top surface. A mask layer 1035, such as polysilicon, can be formed on the filling layer 1033. The mask layer 1035 can be patterned to cover the area where the core mold 1021 and sidewalls 1023 are located. In a second direction, the mask layer 1035 can extend beyond the area where the core mold 1021 and sidewalls 1023 are located, thereby covering a portion of the strip structure outside the sidewalls 1023 (the protruding portion will be defined later). Additionally, the mask layer 1035 can cover the area where the column structure is located.

[0078] like Figure 11(a) and 11(b) As shown in the top view and cross-sectional view along line CC′, the mask layer 1035 can be used as an etching mask, and the underlying fill layer 1033, hard mask, and active layer can be etched sequentially via, for example, a vertical RIE. Similarly, the etching can stop at the first source / drain layer 1007 for the p-type transistor. Thus, the active layers (except for the first source / drain layer 1007) can be separated from each other in the second direction.

[0079] As shown in Figure 11(a), the resulting structure contains patterns such as: a closed pattern defined by the sidewall 1023, such as a rectangular ring, which can subsequently define the main body of the interconnect structure and the location of the gate stack; and a pattern protruding relative to the sidewall 1023 defined by the portion of the strip structure outside the sidewall 1023, which can subsequently define the location of the active regions (including the channel layer and source / drain layers) of the SRAM cells constituting the transistors.

[0080] More specifically, the closed pattern may include a first side S1, a second side S2, a third side S3, and a fourth side S4. The main body of the first interconnect structure IIC1 will be primarily defined by the first side S1 and the second side S2, and the main body of the second interconnect structure IIC2 will be primarily defined by the third side S3 and the fourth side S4. On the first side S1, there is a protruding pattern defined by a strip structure. The protruding pattern on the first side S1 may define the positions of the active regions of the first pull-down transistor PD-1 and the first pass-gate transistor PG-1 in the upper active layer (for n-type transistors), and may define the positions of the active regions of the first pull-up transistor PU-1 (which may be vertically aligned or overlapped with the first pull-down transistor PD-1) in the lower active layer (for p-type transistors). Similarly, on the third side S3, there is a protruding pattern defined by a strip structure. The protruding pattern on the third side S3 can define the positions of the active regions of the second pull-down transistor PD-2 and the second pass-gate transistor PG-2 in the upper active layer (for n-type transistors), and can define the positions of the active regions of the second pull-up transistor PU-2 (which can be aligned or overlapped with the second pull-down transistor PD-2 in the vertical direction) in the lower active layer (for p-type transistors).

[0081] Additionally, there may be a function to limit the applied power supply voltage V. DD The contact plug has a circular pattern. However, this disclosure is not limited thereto. The contact plug can be formed separately. In this case, the circular pattern can be omitted.

[0082] As shown in Figure 11(b), the sidewalls of the upper and lower channel defining layers 1009 and 1015 are exposed on opposite sides in the second direction. As described above, the patterns of the hard mask (the protruding patterns on the first side S1 and the third side S3) can define the positions of the four active regions, but only two transistors (the first pull-up transistor PU-1 and the second pull-up transistor PU-2) can be formed in the lower active region. Therefore, a masking layer can be used to mask two of the four active region positions in the lower layer (the positions below the first gate transistor PG-1 and the second gate transistor PG-2) to avoid forming unnecessary devices.

[0083] For example, such as Figure 12As shown in the cross-sectional view along line CC′, a masking layer 1037 can be formed on the resulting structure to mask the sidewalls of the underlying active layer, particularly the channel defining layer 1009. For example, an oxide layer 1037 can be formed by depositing an oxide layer, planarizing the deposited oxide layer (which may stop at mask layer 1035), and then etching back the planarized oxide layer. The top surface of the masking layer 1037 can extend above the top surface of the channel defining layer 1009 to adequately mask the channel defining layer 1009, for example, near the interface between the second source / drain layer 1011 for p-type transistors and the first source / drain layer 1013 for n-type transistors.

[0084] Then, as Figure 13(a) , 13(b) As shown in Figure 13(c) (top view, cross-sectional view along line CC′, and cross-sectional view along line DD′, respectively), the masking layer 1037 can be further patterned using, for example, photoresist (not shown), to mask areas where devices do not need to be formed, while exposing areas where devices need to be formed. More specifically, as shown in the top view of Figure 13(a), on the first side S1, the masking layer 1037 can be removed in the area containing a protruding pattern (the protruding pattern on the left in the figure) to expose the sidewalls of the underlying active layer, particularly the channel defining layer 1009, so that a channel layer can be subsequently grown thereon (based on which the first pull-up transistor PU-1 is formed), while in the area containing another protruding pattern (the protruding pattern on the right in the figure), the masking layer 1037 can be retained to mask the sidewalls of the underlying active layer, particularly the channel defining layer 1009, so that no channel layer is grown thereon (and Therefore, no device will be formed. On the third side S3, in the area where a protruding pattern (the protruding pattern on the right side of the figure) is located, the masking layer 1037 can be removed to expose the sidewalls of the underlying active layer, particularly the channel defining layer 1009, so that a channel layer can be subsequently grown thereon (based on which the second pull-up transistor PU-2 is formed). In the area where another protruding pattern (the protruding pattern on the left side of the figure) is located, the masking layer 1037 can be retained to mask the sidewalls of the underlying active layer, particularly the channel defining layer 1009, so that no channel layer will be grown thereon (and therefore no device will be formed).

[0085] Similarly, the channel definition layer can be refined. For example, such as... Figure 14(a) , 14(b)As shown in 14(c) (top view, cross-sectional view along line CC′, and cross-sectional view along line DD′, respectively), the channel defining layers 1009 and 1015 can be further selectively etched using, for example, ALE. Here, primarily the ends of the strip-shaped portions of the channel defining layers 1009 and 1015 outside the sidewall 1023 in the second direction are etched and recessed, while the remaining surfaces can be shielded by the shielding layer 1037 (this is due to the formation process of the shielding layer 1037, such as deposition followed by etching back as described above, so that the shielding layer 1037 can fill the channel defining layers due to the previous bonding). Figure 9 The refinement described is formed in the recess and the corresponding surface of the channel defining layer is masked. Similarly, the etching depth can be controlled such that after the channel layer is subsequently grown on the surface of the channel defining layer, the space left between the source / drain layers is sufficient to form a gate stack around the outer periphery of the channel layer.

[0086] Additionally, the etching depth can be controlled so that the strip-shaped portions of the refined channel defining layers 1009 and 1015 still protrude relative to the sidewall 1023, for example, by overlapping with the protruding pattern in the vertical direction. Figure 14(b) and 14(c) The location of the protruding pattern is schematically shown in a dashed box, and the outer wall of the sidewall 1023 is schematically shown in a vertical dashed line. The ends of the strip portions of the channel defining layers 1009 and 1015 in the second direction are outside the outer wall of the sidewall 1023 shown in the vertical dashed line, overlapping the protruding pattern shown in the dashed box in the vertical direction. This ensures that the channel layer subsequently grown on the sidewall of the channel defining layers 1009 and 1015 can be located outside the sidewall 1023.

[0087] As shown in the top view of Figure 14(a), due to the refinement of the channel defining layers, the channel defining layers 1009 and 1015 have the following pattern: the upper channel defining layer 1015 has four strip-shaped portions that overlap vertically with the four protruding patterns, and the sidewalls of these four strip-shaped portions are recessed laterally relative to the corresponding protruding patterns; the lower channel defining layer 1009 has two strip-shaped portions that overlap vertically with two of the four protruding patterns, and the sidewalls of these two strip-shaped portions are recessed laterally relative to the corresponding protruding patterns (it also has portions that overlap vertically with the other two protruding patterns, but the sidewalls of these portions, especially the sidewalls blocked by the shielding layer 1037, are not recessed laterally). Note that the top view of Figure 14(a) shows the outline of the upper channel defining layer 1015 with four strip-shaped portions.

[0088] The trench layer can be grown on the surface of the trench-defining layers 1009 and 1015 having this pattern. For example, as... Figure 15(a) , 15(b)As shown in Figures 15(a) and 15(c) (top view, cross-sectional view along line CC′, and cross-sectional view along line DD′, respectively), the channel layer 1039 can be formed, for example, by selective epitaxial growth. The growth film thickness is controlled such that after the formation of the channel layer 1039, the space left between the source / drain layers due to the refinement of the channel defining layer is not completely filled. The channel layer 1039 may have a vertical extension extending at the end of the strip-shaped portion of the channel defining layer as described above in the second direction (see the shaded dashed box in the top view of Figure 15(a)) and a lateral extension extending on the top or bottom surface of the respective source / drain layer. Due to selective epitaxial growth, the channel layer 1039 can be grown on the surface of the active layer of the semiconductor, but not on the surface of the dielectric layer. In particular, the channel layer 1039 may not be formed where it is shielded by the shielding layer 1037. When the mask layer 1035 is polycrystalline silicon, the channel layer can also be grown on the surface of the mask layer 1035 (not shown in the figure), but this will not affect subsequent processes. Since the channel layer 1039 is formed by separate epitaxial growth, its film thickness and crystal quality can be well controlled.

[0089] The material of the channel layer 1039 can be selected based on the device design. For example, the channel layer 1039 may include the same semiconductor material as the source / drain layer (Si in this example). Alternatively, the channel layer 1039 may include a different semiconductor material than the source / drain layer, such as SiGe, to improve device performance (e.g., increase carrier mobility).

[0090] According to embodiments, channel defining layers 1009 and 1015 may contain dopants (e.g., in-situ doping during growth). Annealing can be performed to drive the dopants in channel defining layers 1009 and 1015 into channel layer 1039, thereby giving channel layer 1039 a specific doping distribution. For example, for a p-type transistor, channel defining layer 1009 may contain an n-type dopant (e.g., As), and after annealing, channel layer 1039, particularly its vertically extending portions on the sidewalls of channel defining layer 1009, may have a diameter of approximately 1E17-2E18 cm. -3 (For example, 2E18 em) -3 The n-type doping concentration; for an n-type transistor, the channel defining layer 1015 may have a p-type dopant (e.g., B), and after annealing, the channel layer 1039, particularly its vertically extending portion on the sidewalls of the channel defining layer 1015, may have a dopant concentration of approximately 1E17-2E18 em. -3 (For example, 2E18 em) -3 The p-type doping concentration of the transistor. This doping concentration distribution in the channel layer helps to regulate the threshold voltage (V) of the transistor. t Lateral extensions of the channel layer may be driven with dopants from the source / drain layers.

[0091] At this point, the position of the active material layer on the outer side has been substantially defined using the outer side of the hard mask pattern (the aforementioned rectangular ring pattern and protruding pattern), except for the bottommost first source / drain layer 1007 and contact layer 1003 (which will be patterned later). Additionally, a channel layer overlapping the protruding pattern in the vertical direction is formed on the outer side of the sidewall 1023. Next, the position of the active material layer on the inner side can be defined using the inner side of the hard mask pattern. For this purpose, a masking layer can be formed on the substrate to mask the outer side of various structures on the substrate. For example, as... Figure 16(a) , 16(b) As shown in 16(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the mask layer 1035, the masking layer 1037, and the fill layer 1033 can be removed by selective etching. Then, as... Figure 17 As shown in the cross-sectional view along line AA′, a masking layer 1041 can be formed by depositing, for example, an oxide, and then planarizing the deposited oxide using CMP. The planarization process can stop at the mandrel 1021. In this way, the portion of the hard mask above 1021 can be removed.

[0092] Next, the inner side of the active material layer can be patterned.

[0093] For example, such as Figure 18 As shown in the cross-sectional view along line AA′, the core mold 1021 exposed due to the planarization process can be removed by selective etching, and the aluminum oxide layer 1019 exposed due to the removal of the core mold 1021 can be anisotropically etched by, for example, a vertical RIE. The etching of the aluminum oxide layer 1019 can stop at the second source / drain layer 1017 for the n-type transistor. The etching of the oxide layer 1019 can cause the aluminum oxide layer 1025 at the pillar structure corresponding to the circular portion 1031c to be recessed to a certain depth (approximately the thickness of the aluminum oxide layer 1019).

[0094] Thus, the alumina layer 1019 has a rectangular ring pattern defined by the sidewall 1023 (with a protruding pattern on its outer side, see...). Figure 19(b) and 19(c) (The cross-sectional diagram in the image) can then be used as a basis for mapping the source / drain layers and interconnect structures. This mapping can be done layer by layer from top to bottom.

[0095] For example, such as Figure 19(a) , 19(b)As shown in 19(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the second source / drain layer 1017 for the n-type transistor, exposed by etching of the aluminum oxide layer 1019, can be anisotropically etched using, for example, a vertical RIE, with the etching stopping at the channel defining layer 1015. Thus, the second source / drain layer 1017 for the n-type transistor can be formed with a rectangular ring pattern corresponding to the sidewall 1023, and also has a protruding pattern.

[0096] As described above, four n-type transistors can be formed on the upper layer: a first pull-down transistor PD-1, a first pass-gate transistor PG-1, a second pull-down transistor PD-2, and a second pass-gate transistor PG-2. These transistors can be separated from each other on the upper source / drain layers (e.g., see S / D3_U and S / D6_U in Figure 3(a) and S / D1_U and S / D5_U in Figure 3(b)). These separated source / drain layers can be defined by highlighting patterns. For example, as... Figure 20(a) , 20(b) As shown in Figures 20(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the second source / drain layer 1017 for n-type transistors can be further selectively etched, for example, by wet etching, to separate it into four portions, for example, corresponding to four transistors. Etching can be performed from the inside of the annular second source / drain layer 1017, so the portion of the second source / drain layer 1017 overlapping the annular sidewall 1023 in the vertical direction can be removed first. The etching depth can be controlled, for example, greater than the linewidth of the sidewall 1023, so that the portion of the second source / drain layer 1017 overlapping the annular sidewall 1023 in the vertical direction can be completely removed, but the portion of the second source / drain layer 1017 overlapping the protruding pattern in the vertical direction can be (at least partially) retained. ALE can be used for better control of the etching depth. Thus, the second source / drain layer 1017 is separated into four separate portions corresponding to the protruding patterns. To ensure process margin, etching can be performed to the outer side of sidewall 1023, and therefore... Figure 20(b) and 20(c) As shown by the dashed line in the cross-sectional view, the inner wall of the separated portion of the second source / drain layer 1017 can be located outside the sidewall 1023.

[0097] To ensure the integrity of the pattern, the area where the second source / drain layer 1017 is removed can be filled with a placeholder layer below the annular sidewall 1023 (and possibly below the protruding pattern, where the inner wall of the separated portion of the second source / drain layer 1017 is outside the sidewall 1023). For example, as... Figure 21(a) , 21(b)As shown in 21(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the occupant layer 1043 can be formed by depositing, for example, nitride (in an amount sufficient to fill the voids below the sidewall 1023 and any voids that may exist below the protruding pattern) and then etching back the deposited nitride, for example, with vertical RIE. The reason for choosing nitride here is at least to consider the etching selectivity relative to the layers already present in the structure, such as the alumina layer 1019, the masking layer 1041, etc.

[0098] Therefore, the occupant layer 1043 can have a rectangular ring pattern corresponding to the sidewall 1023, and may have a protrusion corresponding to the separation portion of the second source / drain layer 1017 (extending from below the sidewall 1023 towards the separation portion of the second source / drain layer 1017). During nitride etching, the sidewall 1023, which is also a nitride in this example, can be removed. However, the resulting structure still retains a ring structure: the alumina layer 1019 (with a protruding pattern on the outside) and the occupant layer 1043 (possibly with a protrusion).

[0099] The channel defining layer 1015 is exposed due to the patterning of the second source / drain layer 1017, and therefore can be removed. For example, as Figure 22(a) , 22(b) As shown in 22(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the channel defining layer 1015 can be selectively etched, such as by wet etching, to remove it. Thus, the channel layer 1039 can extend vertically between the first source / drain layer 1013 and the second source / drain layer 1017 on the outer side of the annular pattern (currently defined by the alumina layer 1019).

[0100] Similarly, to ensure pattern integrity, a placeholder layer can be formed in the gap created by the recess of the channel layer relative to the outer periphery of the hard mask (this gap will subsequently form a gate stack, so the placeholder layer occupying the gap can also be called a "sacrificial gate"). For example, as Figure 23(a) and 23(b) (These are cross-sectional views along line CC′ and line DD′, respectively.) As shown, the sacrificial gate 1005 can be formed by depositing, for example, oxide nitride (e.g., silicon oxynitride) and then etching back the deposited oxide nitride, for example, in the vertical direction (RIE). The reason for choosing oxide nitride here is at least to consider the etching selectivity relative to the layers already present in the structure, such as the hard mask layer, the masking layer 1041, the placeholder layer 1043, etc.

[0101] Next, the first source / drain layer 1013 for the n-type transistor and the second source / drain layer 1011 for the p-type transistor can be patterned. As described above, these two layers can be patterned identically and can be used to form interconnect structures. For example, as... Figure 24(a) , 24(b) As shown in 24(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the first source / drain layer 1013 for the n-type transistor and the second source / drain layer 1011 for the p-type transistor can be anisotropically etched, for example, by a vertical RIE, with the etching stopping at the channel defining layer 1009. Thus, the first source / drain layer 1013 for the n-type transistor and the second source / drain layer 1011 for the p-type transistor can be formed with a rectangular ring pattern corresponding to the hard mask layer, and with protruding patterns on the outer side. Two interconnect structures can be separated from this rectangular ring pattern. According to an embodiment, the separation of the interconnect structures can be performed later, with both sides of the first source / drain layer 1013 for the n-type transistor and the second source / drain layer 1011 for the p-type transistor exposed (see the following combination). Figures 31(a) to 32(c) (Description).

[0102] Similarly, such as Figure 25(a) , 25(b) As shown in 25(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the channel defining layer 1009 can be selectively etched, such as by wet etching, to remove it. Thus, the channel layer 1039 can extend vertically between the first source / drain layer 1007 and the second source / drain layer 1013 on the outer side of the annular pattern (currently defined by the alumina layer 1019).

[0103] Therefore, the position of the active material layer on the inner side is basically defined by the inner side of the hard mask pattern (the rectangular ring pattern and the protruding pattern mentioned above), except for the bottommost first source / drain layer 1007 and contact layer 1003 (which will be patterned last). In this way, the active material layer (except for the first source / drain layer 1007 and contact layer 1003) has been patterned on both the inner and outer sides based on the hard mask.

[0104] In the obtained structure, the occupant layer 1043 and the source / drain layer 1017 on its sidewall are patterned as a hard mask (rectangular ring pattern + protruding pattern), and the source / drain layers 1013 and 1011 are patterned as hard mask patterns. These two patterns are self-aligned with each other and can substantially overlap in the vertical direction.

[0105] Based on a hard mask, a placeholder layer can be filled between the placeholder layer 1043 and the source / drain layer 1017 and the source / drain layers 1013 and 1011, as well as between the source / drain layers 1013 and 1011 and the source / drain layer 1007. The placeholder layer thus formed can have a pattern defined by the hard mask and can serve as a self-aligned sacrificial gate to the channel layer 1039.

[0106] Considering the layout differences between upper and lower layer devices (e.g., four transistors can be formed in the upper layer and two transistors can be formed in the lower layer), resulting in different gate layouts for upper and lower layer devices, sacrificial gates can be formed separately for upper and lower layer devices from top to bottom.

[0107] For example, such as Figure 26(a) , 26(b) As shown in Figures 26(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the adjusted masking layer 1041′ can be obtained by depositing, for example, oxide, planarizing the oxide (e.g., CMP), and etching back the planarized oxide. The adjusted masking layer 1041′ can have a substantially flat top surface and can mask the active layer of the lower layer (for p-type transistors) while exposing the active layer of the upper layer (for n-type transistors). For example, the top surface of the filling layer 1041′ can be at or near the interface between the second source / drain layer 1011 for p-type transistors and the first source / drain layer 1033 for n-type transistors.

[0108] Therefore, the space outside the upper channel layer is released (its inner side has already formed the sacrificial gate 1005 as previously described). A sacrificial gate can be similarly formed in this released space. For example, as... Figure 27(a) , 27(b) As shown in Figure 27(a) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the sacrificial gate 1045 can be formed by depositing, for example, oxide nitride and then etching back the deposited oxide nitride, for example, with a vertical RIE. Oxide nitride is chosen here because it has the same etching selectivity as the previously formed sacrificial gate 1005, so that it can be removed together in the alternative gate process that forms the gate stack. Note that in the cross-sectional view of Figure 27(a), the previously formed sacrificial gate 1005 is shown together as sacrificial gate 1045 because they are treated the same in subsequent processes.

[0109] Therefore, the sacrificial gates 1005 and 1045 can be arranged as a rectangular ring pattern with a protruding pattern on the outer side, defined by a hard mask. The presence of the protruding pattern allows the sacrificial gates 1005 and 1045 to surround the channel layer. Thus, a surrounding gate structure can be formed. Furthermore, the sacrificial gates 1005 and 1045 can occupy the original position of the channel defining layer 1015, extending between the first source / drain layer 1013 and the second source / drain layer 1017 (most of which has been replaced by the placeholder layer 1043, with only four separate portions remaining below the protruding pattern) used for the n-type transistor. Therefore, the subsequent replacement of the sacrificial gates 1005 and 1045 can be self-aligned with the channel layer 1039 between the upper and lower source / drain layers.

[0110] A sacrificial gate can be similarly formed for the lower channel layer.

[0111] Considering the electrical isolation between the gate stacks of the two p-type transistors in the lower layer, a placeholder layer can be formed first. For example, as... Figure 28(a) , 28(b) As shown in 28(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the masking layer 1041′ can be anisotropically etched using, for example, a vertical RIE, with the etching stopping at the first source / drain layer 1007. Thus, the remaining masking layer 1041′ (hereinafter referred to as the placeholder layer 1047) can generally be a rectangular ring pattern defined by the hard mask layer, with a protruding pattern on the outer side.

[0112] Next, the placeholder layer 1047 can be patterned to leave space for the gate stack of p-type transistors. For example... Figure 29(a) , 29(b)As shown in Figures 29(a), 29(c), and 29(d) (top view, cross-sectional view along line AA′, cross-sectional view along line CC′, and cross-sectional view along line DD′, respectively), photoresist 1049 can be formed on the obtained structure, and the photoresist 1049 is patterned to expose the area where the gate stack of the p-type transistors needs to be formed. Specifically, in this example, as shown in the top view of Figure 29(a), space is left around the protruding pattern on the left side of the first side S1 in the mask pattern (which defines the location of the channel layer of the first pull-up transistor PU-1) and the protruding pattern on the right side of the third side S3 (which defines the location of the channel layer of the second pull-up transistor PU-2). In addition, in this example, the photoresist 1049 also exposes a portion of the fourth side S4, so that the gate stack of the subsequently formed first pull-up transistor PU-1 can extend into this area to be electrically connected to the gate stack of the first pull-down transistor PD-1 above it. Similarly, the photoresist 1049 also exposes a portion of the second side S2, allowing the gate stack of the subsequently formed second pull-up transistor PU-2 to extend into this region so as to be electrically connected to the gate stack of the upper second pull-down transistor PD-2.

[0113] Additionally, the photoresist 1049 can expose an area corresponding to the circular portion in the mask pattern. In this way, nanowires from the channel defining layers 1009 and 1015 are retained in the area corresponding to the circular portion in the mask pattern, and these nanowires can be surrounded by a sacrificial gate (see Figure 30(a)). The sacrificial gate can then be replaced with a gate electrode layer in a gate replacement process (e.g., see the following combination). Figures 40(a) to 43(d) (as described above), thereby reducing contact resistance.

[0114] The photoresist 1049 patterned as described above can be used as an etching mask to selectively etch the site layer 1047. For example... Figure 29(c) and 29(d) As shown, selective etching of the occupant layer 1047 can leave space around the underlying channel layer.

[0115] Then, a sacrificial gate can be formed around the lower channel layer. For example, as... Figure 30(a) , 30(b) As shown in 30(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the sacrificial gate 1051 can be formed by depositing, for example, oxide nitride and then etching back the deposited oxide nitride, for example, with a vertical RIE. Oxide nitride is chosen here because it has the same etching selectivity as the previously formed sacrificial gates 1005 and 1045, so that it can be removed together in the alternative gate process that forms the gate stack.

[0116] Therefore, the sacrificial gate 1051 and the occupant layer 1047 are generally arranged in a rectangular ring pattern with a protruding pattern on the outer side, defined by a hard mask. The sacrificial gate 1051 may include two parts for the first pull-up transistor PU-1 and the second pull-up transistor PU-2, which are isolated from each other by the occupant layer 1047.

[0117] In the example above, a placeholder layer 1047 is first formed, and then the placeholder layer 1047 is patterned to replace a portion of it with the sacrificial gate 1051. However, this disclosure is not limited thereto. For example, the sacrificial gate may be formed first (e.g., formed as a rectangular ring pattern having a protruding pattern on the outer side defined by a hard mask), and then the sacrificial gate may be patterned (e.g., using a photoresist with a complementary pattern to the photoresist 1049) to replace a portion of it with the placeholder layer.

[0118] In this example, the lower sacrificial gate 1051 is patterned before its replacement gate process. This is because it is not easy to pattern the lower gate stack after the replacement gate process. The upper sacrificial gates 1005 and 1045, however, can be patterned after the replacement gate process to achieve proper electrical isolation. Of course, similar to the lower sacrificial gate 1051, the upper sacrificial gates 1005 and 1045 can also be patterned before the replacement gate process. In this case, similar to the process of forming the lower sacrificial gate 1051, a placeholder layer can be formed and patterned before forming the sacrificial gates 1005 and 1045 (see the description below in conjunction with Figure 46(a) for the pattern), and then the sacrificial gates 1005 and 1045 can be formed.

[0119] Next, we can draw the interconnection structure.

[0120] The first source / drain layer 1013 for n-type transistors and the second source / drain layer 1011 for p-type transistors can be patterned according to the layout of the first interconnect structure and the second interconnect structure. For example, as Figure 31(a) , 31(b) As shown in 31(c) and 31(d) (top view, cross-sectional view along line BB′, cross-sectional view along line EE′, and cross-sectional view along line FF′, respectively), photoresist 1055 can be formed on the obtained structure. The photoresist 1055 can be patterned to expose the area that needs to be isolated between the first interconnect structure and the second interconnect structure.

[0121] As shown by the dashed box in the top view of Figure 31(a), the first interconnect structure IIC1 and the second interconnect structure IIC2 can be formed as two L-shapes that are opposite to each other and spaced apart from each other. The first interconnect structure IIC1 may include a first segment SEG1 extending along a first direction and a second segment SEG2 extending along a second direction. Similarly, the second interconnect structure IIC2 may include a third segment SEG3 extending along the first direction and a fourth segment SEG4 extending along the second direction.

[0122] The gate stack of the subsequently formed first pull-up transistor PU-1 can extend to overlap with the fourth segment SEG4 in the vertical direction (see the top view in FIG. 29(a)). As described above, the gate stack of the first pull-up transistor PU-1 can be electrically connected to the second interconnect structure IIC2. To ensure process margin, the second interconnect structure IIC2 may include a small segment extending from the fourth segment SEG4 on the first side S1. Similarly, the gate stack of the subsequently formed second pull-up transistor PU-2 can extend to overlap with the second segment SEG2 in the vertical direction (see the top view in FIG. 29(a)). As described above, the gate stack of the second pull-up transistor PU-2 can be electrically connected to the first interconnect structure IIC1. To ensure process margin, the first interconnect structure IIC1 may include a small segment extending from the second segment SEG2 on the third side S3. Thus, the isolation between the first interconnect structure IIC1 and the second interconnect structure IIC2 (defined by the opening in the photoresist 1055) can be achieved on the first side S1 and the third side S3.

[0123] Then, for example, Figure 32(a) , 32(b) As shown in Figures 32(c) (which are cross-sectional views along line BB′, line EE′, and line FF′, respectively), photoresist 1055 can be used as an etching mask to selectively etch, for example, ALE, the first source / drain layer 1013 for the n-type transistor and the second source / drain layer 1011 for the p-type transistor to cut them off. Thus, the first source / drain layer 1013 for the n-type transistor and the second source / drain layer 1011 for the p-type transistor can be separated into a first interconnect structure IIC1 and a second interconnect structure IIC2.

[0124] The first interconnect structure IIC1 may include a protruding portion (on the first segment SEG1) defined by a protruding pattern. More specifically, the first segment SEG1 may include a first protruding portion PR1 serving as the upper source / drain layer of the first pull-up transistor PU-1 (see S / D4_U in FIG. 3(a)) and the lower source / drain layer of the first pull-down transistor PD-1 (see S / D3_L in FIG. 3(a)), and a second protruding portion PR2 serving as the lower source / drain layer of the first through-gate transistor PG-1 (see S / D6_L in FIG. 3(a)).

[0125] Similarly, the second interconnect structure IIC2 may include a protrusion defined by a protruding pattern (on the third segment SEG3). More specifically, the third segment SEG3 may include a third protrusion PR3 serving as the upper source / drain layer of the second pull-up transistor PU-2 (see S / D2_U in FIG. 3(c)) and the lower source / drain layer of the second pull-down transistor PD-2 (see S / D1_L in FIG. 3(b)), and a fourth protrusion PR4 serving as the lower source / drain layer of the second through-gate transistor PG-2 (see S / D5_L in FIG. 3(b)).

[0126] A placeholder layer can be formed in the voids created beneath the hard mask due to the aforementioned etching. For example, such as Figure 33(a) , 33(b) As shown in 33(c) (which are cross-sectional views along line BB′, line EE′, and line FF′, respectively), a placeholder layer 1057 can be formed by depositing, for example, a nitride and then etching back the deposited nitride, such as in a vertical RIE. Thus, the placeholder layer 1057 can be formed between the first interconnect structure IIC1 and the second interconnect structure IIC2 on the first side S1 and between the first interconnect structure IIC1 and the second interconnect structure IIC2 on the third side S3. Here, a nitride is chosen because it has etch selectivity relative to the previously formed sacrificial gate and can have the same etch selectivity as the placeholder layer 1043.

[0127] Additionally, to avoid affecting the interconnect structure (first source / drain layer 1013 for n-type transistors and second source / drain layer 1011 for p-type transistors) during the patterning process of the first source / drain layer 1007 for p-type transistors, a protective layer can be formed on the sidewalls of the resulting structure. For example, as... Figure 34(a) , 34(b) As shown in 34(c) (top view, cross-sectional view along line AA′, and cross-sectional view along line CC′, respectively), a protective layer 1053 can be formed on the sidewalls of the resulting structure using a sidewall forming process. The protective layer 1053 may include (e.g., a material with desired etching selectivity relative to the first source / drain layer 1007, etc.), such as a nitride.

[0128] Next, the first source / drain layer 1007 can be patterned. For example, as shown... Figure 35(a) , 35(b)As shown in 35(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), a hard mask can be used as an etching mask to anisotropically etch the first source / drain layer 1007, for example, through a vertical RIE. Here, the contact layer 1003 can also be anisotropically etched together. The etching can stop at the substrate 1001. Thus, the first source / drain layer 1007 and the contact layer 1003 can form a rectangular ring pattern with a protruding pattern on the outer side, defined by the hard mask.

[0129] As described above Figure 20(a) , 20(b) As described in 20(c), the first source / drain layer 1007 can be separated into portions corresponding to each transistor. For example, as Figure 36(a) , 36(b) As shown in 36(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the first source / drain layer 1007 can be further selectively etched, for example, by wet etching, to separate it into, for example, four parts corresponding to the four protruding patterns. Combined with the above... Figure 20(a) , 20(b) Unlike the separation of the second source / drain layer 1017 for the n-type transistor described in 20(c) (etched from the inside as described above), etching can be performed from both the inside and outside of the first source / drain layer 1007. The etching depth can be controlled, for example, slightly greater than half the linewidth of the sidewall 1023, such that the portion of the first source / drain layer 1007 overlapping the annular pattern in the vertical direction can be completely removed, but the portion of the first source / drain layer 1007 overlapping the protruding pattern in the vertical direction can be (at least partially) retained. ALE can be used for better control of the etching depth.

[0130] Although the four portions obtained from separating the second source / drain layer 1017 for the n-type transistor (etched from the inside as described above) and the four portions obtained from separating the first source / drain layer 1007 for the p-type transistor (etched from both the inside and outside as described above) may not completely overlap in the vertical direction due to different etching conditions, they can be self-aligned with each other because their positions are defined based on the protruding pattern of the hard mask.

[0131] Here, the contact layer 1003 is used to facilitate contact between the substrate and the source / drain layer separated from the first source / drain layer 1007, so the contact layer 1003 can be treated similarly. The four portions separated from the contact layer 1003 can be self-aligned with the four portions separated from the first source / drain layer 1007, and can substantially overlap in the vertical direction.

[0132] At this point, the layout of the SRAM cells (including transistors and interconnect structures) has been largely completed. Next, alternative gate processes can be used to fabricate the transistors, and the interconnects between these transistors can be formed to complete the SRAM cell fabrication.

[0133] To enhance contact and / or reduce resistance, the source / drain layers can be siliconized.

[0134] For example, such as Figure 37(a) , 37(b) As shown in 37(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the protective layer 1053 (nitride in this example) can be removed by selective etching, for example, using wet etching with hot phosphoric acid, and the occupant layers 1043, 1057 (nitride in this example) and 1047 (oxide in this example) outside the sacrificial gate in the resulting structure can be removed to fully expose the source / drain layers (but the channel layer, especially its vertical extension, remains surrounded by the sacrificial gate). Silicification can be performed to at least partially or even completely silicide the exposed source / drain layers, thereby forming a silicide layer 1059, as shown in 37(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively). Figure 38(a) , 38(b) Figures 38(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively) show the process. The silicide treatment may include, for example, depositing a metal such as a NiPt alloy and heat-treating it at a temperature of, for example, about 200-600°C, to cause the deposited metal to react with semiconductor elements such as Si and / or Ge in the source / drain layers, thereby forming metal-semiconductor element compounds, such as silicides, germanides, or silicogermanides (hereinafter referred to as silicides). Afterward, unreacted excess metal can be removed.

[0135] It should be noted that although the silicide layer 1059 is shown as a thin layer here, some areas may be completely converted into silicide depending on the size of the site where the silicide reaction occurs and the duration of the silicide reaction.

[0136] To facilitate the formation of a self-aligned gate stack, a placeholder layer can be reformulated in the gaps beneath the hard mask. For example, as... Figure 39(a) , 39(b) As shown in Figures 39(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the berth layer 1061 can be reformed by depositing nitride and then anisotropically etching the deposited nitride, such as in a vertical RIE. The berth layer 1061 can occupy the locations of the previously removed berth layers 1043, 1047, and 1057. The reason for choosing nitride here is its etch selectivity relative to the sacrificial gate and the hard mask.

[0137] Next, an alternative gate process can be implemented.

[0138] For example, such as Figure 40(a) , 40(b) As shown in 40(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), sacrificial gates 1005, 1045, and 1051 can be removed by selective etching. Thus, channel layer 1039 can be exposed. Additionally, at the columnar structures corresponding to the circular pattern, the channel defining layer can be exposed. Then, as... Figure 41(a) , 41(b) As shown in 41(c) (which are cross-sectional views along line AA′, line CC′, and line DD′, respectively), the gate dielectric layer 1063 can be formed on the surface of the channel layer by deposition, such as atomic layer deposition (ALD). The gate dielectric layer 1063 can be formed in a generally conformal manner. The gate dielectric layer 1063 may include a suitable dielectric, such as a high-k dielectric like HfO2, with a thickness of about 0.5-4 nm.

[0139] It should be noted that the gate dielectric layer 1063 may have portions extending on the vertical sidewalls of the structure, portions extending on the top surface of the hard mask, portions extending on the surface of the substrate, etc. These portions do not affect the subsequent processes, and therefore are not shown in the figure for clarity.

[0140] However, this also forms a gate dielectric layer on the surface of the first and second interconnect structures, which hinders the electrical connection between the first and second interconnect structures and the subsequently formed gate electrode layer. Therefore, the gate dielectric layer on the surface of the first and second interconnect structures (and optionally, the channel defining layer at the pillar structure) can be removed. For example, as... Figure 42(a) , 42(b) As shown in 42(c), 42(d), and 42(e) (which are respectively top view, cross-sectional view along line AA′, cross-sectional view along line CC′, cross-sectional view along line BB′, and cross-sectional view along line HH′), photoresist 1065 can be formed on the obtained structure. The photoresist 1065 can be patterned to expose the areas where the gate dielectric layer needs to be removed, while covering the areas where the gate dielectric layer needs to be retained.

[0141] The space for gate stacking and interconnect structures are shown in the top view of Figure 42(a) using dashed lines, dotted lines, etc. For clarity, the space for gate stacking and interconnect structures shown are slightly larger or smaller than the hard mask pattern (in fact, as mentioned above, the space for gate stacking is defined by the hard mask pattern, and therefore they overlap in the top view). For the interconnect structures IIC1 and IIC2, refer to the description above, particularly in conjunction with Figure 31(a); for the space for the gate stacking of pull-up transistors PU-1 and PU-2, refer to the description above, particularly in conjunction with Figure 29(a). Furthermore, for the space for the gate stacking of pull-down transistors PD-1 and PD-2 and for the gate stacking of through-gate transistors PG-1 and PG-2, refer to the following description, particularly in conjunction with Figure 46(a).

[0142] As described above, the gate stacks of the first pull-up transistor PU-1 and the first pull-down transistor PD-1 can be electrically connected to each other and can be jointly electrically connected to the second interconnect structure IIC2. Therefore, in the space for the gate stack of the first pull-up transistor PU-1, the space for the gate stack of the first pull-down transistor PD-1, and the area where the second interconnect structure IIC2 overlaps with each other in the vertical direction (the lower left corner area of ​​the annular pattern), the gate dielectric layer 1063 (partially portions on the upper and lower surfaces of the second interconnect structure IIC2) can be exposed by photoresist 1065 so that it can be subsequently removed.

[0143] Similarly, the gate stacks of the second pull-up transistor PU-2 and the second pull-down transistor PD-2 can be electrically connected to each other and can be jointly electrically connected to the first interconnect structure IIC1. Therefore, in the space for the gate stack of the second pull-up transistor PU-2, the space for the gate stack of the second pull-down transistor PD-2, and the area where the first interconnect structure IIC1 overlaps with each other in the vertical direction (the upper right corner area of ​​the annular pattern), the gate dielectric layer 1063 (parts on the upper and lower surfaces of the first interconnect structure IIC1) can be exposed by photoresist 1065 so that it can be subsequently removed.

[0144] Additionally, in the areas where the gate stack for the first pull-up transistor PU-1, the gate stack for the first pull-down transistor PD-1, and the first interconnect structure IIC1 overlap vertically in the space of the gate stack for the first through-gate transistor PG-1 (mainly on the first side S1 of the annular pattern), the gate dielectric layer 1063 (partially on the upper and lower surfaces of the first interconnect structure IIC1) can be covered with photoresist 1065 so that it can be retained thereafter to ensure that the first interconnect structure IIC1 is electrically isolated from the respective gate stacks of the first pull-up transistor PU-1, the first pull-down transistor PD-1, and the first through-gate transistor PG-1.

[0145] Similarly, in the areas where the gate stack for the second pull-up transistor PU-2, the gate stack for the second pull-down transistor PD-2, and the second interconnect structure IIC2 overlap vertically with each other, and in the areas where the gate stack for the second pass-gate transistor PG-2 overlaps vertically with the second interconnect structure IIC2 (mainly on the third side S3 of the annular pattern), the gate dielectric layer 1063 (partially on the upper and lower surfaces of the second interconnect structure IIC2) can be covered with photoresist 1065 so that it can be subsequently retained to ensure that the second interconnect structure IIC2 is electrically isolated from the respective gate stacks of the second pull-up transistor PU-2, the second pull-down transistor PD-2, and the second pass-gate transistor PG-2.

[0146] Photoresist 1065 can be used as an etching mask to selectively etch the gate dielectric layer 1063 to remove its exposed portions. Afterwards, the photoresist 1065 can be removed.

[0147] As shown in the cross-sectional view of Figure 42(d), in the area corresponding to the lower left corner of the top view of Figure 42(a) (exposed by photoresist 1065), that is, in the left area of ​​the cross-sectional view along line BB′ in Figure 42(d), the gate dielectric layer on the upper and lower surfaces of the second interconnect structure IIC2 can be removed, and thus can be electrically connected to the gate electrode layer in the gate stack (the gate stack of the lower first pull-up transistor PU-1 and the gate stack of the upper first pull-down transistor PD-1) subsequently formed in the corresponding gate stack space. Additionally, on the first segment SEG1, the gate dielectric layer on the upper and lower surfaces of the first interconnect structure IIC1 can be covered by photoresist 1065 and thus can be retained, and thus can be electrically isolated from the gate electrode layer in the gate stack (the gate stack of the lower first pull-up transistor PU-1 and the gate stack of the upper first pull-down transistor PD-1 and the gate stack of the first through-gate transistor PG-1) subsequently formed in the corresponding gate stack space.

[0148] Similarly, as shown in the cross-sectional view of FIG42(e), in the region corresponding to the upper right corner of the top view of FIG42(a) (exposed by photoresist 1065), that is, in the right region of the cross-sectional view along line HH′ in FIG42(e), the gate dielectric layer on the upper and lower surfaces of the first interconnect structure IIC1 can be removed, and thus can be electrically connected to the gate electrode layer in the gate stack (the gate stack of the lower second pull-up transistor PU-2 and the gate stack of the upper second pull-down transistor PD-2) subsequently formed in the corresponding gate stack space. Additionally, on the third segment SEG2, the gate dielectric layer on the upper and lower surfaces of the second interconnect structure IIC2 can be covered by photoresist 1065 and thus can be retained, and thus can be electrically isolated from the gate electrode layer in the gate stack (the gate stack of the lower second pull-up transistor PU-2 and the gate stack of the upper second pull-down transistor PD-2 and the gate stack of the second through-gate transistor PG-2) subsequently formed in the corresponding gate stack space.

[0149] On the first SEG1 and the third SEG3, the gate dielectric layer can extend onto the placeholder layer 1057 to ensure effective electrical isolation.

[0150] After patterning the gate dielectric layer 1063, the gate electrode layer can be formed. For example, as... Figure 43(a) , 43(b) As shown in 43(c) and 43(d) (cross-sectional views along line AA′, line BB′, line CC′, and line DD′, respectively), the gate electrode layer 1067 can be formed in the void below the hard mask (the space where the sacrificial gate would have been) by deposition followed by etching back. For example, the gate electrode layer 1067 may include a work function layer and a conductive fill layer. For example, for a p-type transistor, the work function layer may include TiN, TiN, or a combination thereof, with a thickness of about 1-7 nm; the conductive fill layer may include W and / or Ti, with a thickness sufficient to fill the void below the hard mask.

[0151] To further improve performance, different gate electrode layers can be formed for p-type transistors and n-type transistors, for example, gate electrode layers with different effective work functions. For example, the work function layer of the gate electrode layer 1067 formed above can be for p-type transistors. Next, a gate electrode layer can be formed for the upper n-type transistor. For example, the gate electrode layer 1067 formed in the upper layer can be removed, and a separate gate electrode layer for the n-type transistor can be formed.

[0152] To avoid affecting the lower gate electrode layer 1067, the lower gate electrode layer 1067 can be shielded. For example, as Figure 44(A cross-sectional view along line AA′) shows that a masking layer 1069 can be formed on the resulting structure by depositing oxide and then etching back the deposited oxide. The main reason for choosing oxide here is its etching selectivity relative to a hard mask. Before etching back, the deposited oxide can also be planarized, such as by CMP. To fully mask the lower layer and expose the upper layer, the top surface of the masking layer 1069 after etching back can be located between the upper and lower layers, for example, at or near the interface between the first source / drain layer 1013 for an n-type transistor and the second source / drain layer 1011 for a p-type transistor. Then, as... Figure 45(a) , 45(b) As shown in 45(c) and 45(d) (cross-sectional views along line AA′, line BB′, line CC′, and line DD′, respectively), the upper gate electrode layer 1067 can be removed by selective etching, and a gate electrode layer 1071 for an n-type transistor can be formed on the upper layer in the same manner as forming the gate electrode layer 1067. For example, the gate electrode layer 1071 may include a work function layer and a conductive fill layer. For example, for an n-type transistor, the work function layer may include TiN, TiNa, TiAlC, or combinations thereof, with a thickness of about 1-7 nm; the conductive fill layer may include W and / or Ti, with a thickness sufficient to fill the voids under the hard mask.

[0153] Currently, the upper gate electrode layer 1071 extends continuously, requiring isolation between the pull-down transistor and the pass-through gate transistor, as well as between the first group of transistors and the second group of transistors. For example, as Figure 46(a) , 46(b)As shown in Figure 46(a) (top view, cross-sectional view along line AA′, and cross-sectional view along line BB′, respectively), the remaining hard mask (specifically, aluminum oxide layers 1019 and 1025) can be removed by selective etching, and photoresist 1073 can be formed on the resulting structure, patterning the photoresist 1073 to expose the areas that need to be isolated. Specifically, in the top view of Figure 46(a), the area between the first pull-down transistor PD-1 and the first pass-gate transistor PG-1 can be exposed on the first side S1; the area between the second pull-down transistor PD-2 and the second pass-gate transistor PG-2 can be exposed on the third side S3. In addition, the areas between two sets (corresponding to the first side S1 and the third side S3, respectively) can also be exposed. More specifically, the area between the first pull-down transistor PD-1 and the second pass-gate transistor PG-2 can be exposed on the second side S2, and the area between the second pull-down transistor PD-2 and the first pass-gate transistor PG-1 can be exposed on the fourth side S4. Photoresist 1073 can be used as an etching mask to etch downwards into layers such as the RIE (e.g., the placeholder layer 1061, the gate dielectric layer 1063, and the gate electrode layer 1071) until the gate electrode layer 1071 is cut off. When the device size is small or the opening in the photoresist 1073 is small, isotropic etching can be performed when etching the gate electrode layer 1071, and the gate electrode layer 1071 below the placeholder layer 1049 can be cut off by undercutting.

[0154] Therefore, the gate electrode layer 1071 can be divided into four parts respectively for the first pull-down transistor PD-1, the first pass-gate transistor PG-1, the second pull-down transistor PD-2, and the second pass-gate transistor PG-2 (see Figure 46(a)), and these four parts are separated from each other.

[0155] Additionally, the placeholder layer 1061 above the gate electrode layer 1071 (corresponding to the second source / drain layer 1017) can be similarly divided into four branches: branch BR1 corresponding to the first pull-down transistor PD-1 (hereinafter referred to as the "first pull-down branch"), branch BR2 corresponding to the first pass-gate transistor PG-1 (hereinafter referred to as the "first pass-gate branch"), branch BR3 corresponding to the second pull-down transistor PD-2 (hereinafter referred to as the "second pull-down branch"), and branch BR4 corresponding to the second pass-gate transistor PG-2 (hereinafter referred to as the "second pass-gate branch"). These branches are separated from the upper gate stack by the same etching process and can therefore be self-aligned with the corresponding upper gate stack.

[0156] The first pull-down branch BR1, the first through-gate branch BR2, the second pull-down branch BR3, and the second through-gate branch BR4 extend substantially along the annular pattern of the hard mask and are therefore self-aligned with other structures defined by the hard mask in the device (e.g., interconnect structures, dielectric rings, etc., as described below). The first pull-down branch BR1 and the first through-gate branch BR2 extend primarily along a first direction and are substantially aligned with each other in the first direction (originating from the same edge S1 of the annular pattern). The second pull-down branch BR3 and the second through-gate branch BR4 extend primarily along the first direction and are substantially aligned with each other in the first direction (originating from the same edge S3 of the annular pattern).

[0157] The upper source / drain layer of the first pull-up transistor can be disposed on the outer sidewall of the first pull-down branch BR1, the upper source / drain layer of the first gate transistor can be disposed on the outer sidewall of the first gate branch BR2, the upper source / drain layer of the second pull-up transistor can be disposed on the outer sidewall of the second pull-down branch BR3, and the upper source / drain layer of the second gate transistor can be disposed on the outer sidewall of the second gate branch BR4.

[0158] At this point, the fabrication of the SRAM cell is essentially complete. Next, interconnect structures can be fabricated, such as various vias and wiring, which will not be elaborated upon here.

[0159] Figure 47 A perspective view of an SRAM cell according to an embodiment of the present disclosure is shown schematically. Although due to the perspective, Figure 47 The back side of the device is not clearly shown in the perspective view, but as described above, the SRAM cell according to the embodiment can have a substantially symmetrical structure, and those skilled in the art can clearly understand the overall structure of the SRAM cell based on the previous related description.

[0160] like Figure 47 As shown, an SRAM cell can have a stacked structure, consisting of the following from bottom to top:

[0161] - The first level includes the dielectric ring DILR (formed by the placeholder layer 1061);

[0162] - The second level includes the gate stack for the lower transistors, and the corresponding channel layer surrounded by it is also at this level;

[0163] - The third level includes the first interconnect structure IIC1 and the second interconnect structure IIC2;

[0164] - The fourth level includes the gate stack for the upper transistors, and the corresponding channel layer surrounded by it is also at this level;

[0165] - The fifth level includes branches BR1 to BR4 and the upper source / drain layer of the upper transistor.

[0166] The SRAM cell as a whole can present a ring-shaped pattern defined by a hard mask plus a protruding pattern, as described previously (ignoring the contact plug on one side). Specifically, each layer can substantially present this pattern. The layers can be self-aligned with each other and can overlap each other in the vertical direction.

[0167] The dielectric ring DILR may include a fifth protrusion PR5, in which the lower source / drain layer of the first pull-up transistor PU-1 can be embedded (e.g., see the cross-sectional view shown in FIG. 43(c), where the first source / drain layer 1007 is embedded in the placeholder layer 1061). That is, the fifth protrusion PR5 may have a hole or cavity to accommodate the lower source / drain layer of the first pull-up transistor PU-1. Additionally, the dielectric ring DILR may include a seventh protrusion PR7, in which a dummy source / drain layer can be embedded (e.g., see the cross-sectional view shown in FIG. 43(d), where the first source / drain layer 1007 is embedded in the placeholder layer 1061). That is, the seventh protrusion PR7 may have a hole or cavity to accommodate the dummy source / drain layer.

[0168] Similarly, although in Figure 47 Not shown in the perspective view, the dielectric ring DILR may include a sixth protrusion in which the lower source / drain layer of the second pull-up transistor PU-2 can be embedded (e.g., see the cross-sectional view shown in FIG. 43(d)). That is, the sixth protrusion may have a hole or cavity to accommodate the lower source / drain layer of the second pull-up transistor PU-2. Additionally, the dielectric ring DILR may include an eighth protrusion in which a dummy source / drain layer can be embedded (e.g., see the cross-sectional view shown in FIG. 43(c)). That is, the eighth protrusion may have a hole or cavity to accommodate the dummy source / drain layer.

[0169] No channel layer or gate stack is formed between the dummy source / drain layer and the interconnect structure. The dielectric ring DILR may include a portion between the dummy source / drain layer and the interconnect structure above it.

[0170] The SRAM cells according to embodiments of this disclosure can be applied to various electronic devices. For example, a memory can be formed based on such SRAM cells, and an electronic device can be constructed therefrom. Therefore, this disclosure also provides a memory including the above-described SRAM cells and an electronic device including such a memory. The electronic device may also include components such as a processor that cooperate with the memory. Examples of such electronic devices include smartphones, computers, tablet computers (PCs), wearable smart devices, power banks, etc.

[0171] This disclosure also covers the following aspects.

[0172] 1. A method for manufacturing a static random access memory (SRAM) cell, comprising:

[0173] A stack of a first source / drain layer, a first channel defining layer and a second source / drain layer in a first group and a second source / drain layer in a second group are sequentially disposed on the substrate.

[0174] A hard mask layer is formed on the stack, the hard mask layer having: a rectangular ring pattern having a first side and a third side extending in a first direction and opposite to each other, and a second side and a fourth side extending in a second direction intersecting the first direction and opposite to each other; and a first protruding pattern and a second protruding pattern disposed on the first side of the rectangular ring pattern, and a third protruding pattern and a fourth protruding pattern disposed on the third side of the rectangular ring pattern.

[0175] Patterning is performed on the outer side of the stack using a hard mask layer;

[0176] The channel defining layer is refined such that the first channel defining layer retains a first pull-up portion and a second pull-up portion that overlap with the first protruding pattern and the third protruding pattern in the vertical direction, respectively, while these portions are recessed in the horizontal direction relative to the first protruding pattern and the third protruding pattern, respectively; and the second channel defining layer retains a first pull-down portion, a first passage gate portion, a second pull-down portion and a second passage gate portion that overlap with the first to fourth protruding patterns in the vertical direction, respectively, while these portions are recessed in the horizontal direction relative to the first to fourth protruding patterns, respectively.

[0177] A channel layer is formed on the vertical sidewall of each of the first upward pull-up portion, second upward pull-up portion, first downward pull-up portion, first passage gate portion, second downward pull-up portion, and second passage gate portion at their respective ends in the second direction; and

[0178] Using a hard mask layer, the inner side of the stack is patterned. This patterning process also includes:

[0179] The second source / drain layer of the second group is selectively etched to separate it into four separate portions corresponding to the first to fourth protruding patterns, respectively.

[0180] Remove the second channel limiting layer;

[0181] The second source / drain layer of the first group and the first source / drain layer of the first group are cut in the region between the first protruding pattern and the fourth side and in the region between the third protruding pattern and the second side to form the first interconnect structure and the second interconnect structure;

[0182] Remove the first channel limiting layer.

[0183] 2. The method according to the first aspect, wherein the rectangular ring pattern of the hard mask layer is defined by the sidewalls.

[0184] 3. The method according to aspect 1 or 2, wherein the first protruding pattern and the third protruding pattern are aligned with each other in a second direction, and the second protruding pattern and the fourth protruding pattern are aligned with each other in a second direction.

[0185] 4. The method according to any of the foregoing aspects, wherein the first protruding pattern and the third protruding pattern are defined by a strip structure extending in a second direction across the rectangular ring pattern, and the second protruding pattern and the fourth protruding pattern are defined by another strip structure extending in a second direction across the rectangular ring pattern.

[0186] 5. The method according to aspect 4, wherein,

[0187] The composition of the outer side of the stack includes:

[0188] In the presence of strip structures, the outer side of the stacked layers is patterned.

[0189] The refinement of the channel definition layer includes:

[0190] The first refinement of the channel definition layer;

[0191] A shielding layer is formed to cover the outer side of the stacked layers;

[0192] Device isolation is performed in the second direction, and the strip pattern is cut off in the isolation process to define the protruding pattern;

[0193] A shielding layer is formed to shield the portion of the first channel defining layer that overlaps with the second and fourth protruding patterns in the vertical direction;

[0194] The channel definition layer is further refined.

[0195] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0196] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A static random access memory (SRAM) cell, comprising: Substrate; The first interconnect structure and the second interconnect structure extend substantially parallel to and opposite to each other on the upper surface of the substrate; A first pull-down transistor and a first pass-through transistor are disposed on the first interconnect structure; A second pull-down transistor and a second pass-gate transistor are disposed on the second interconnect structure; A first pull-up transistor disposed under the first interconnect structure and at least partially overlapping the first pull-down transistor in the vertical direction; A second pull-up transistor is disposed under the second interconnect structure and at least partially overlaps with the second pull-down transistor in the vertical direction. The first pull-up transistor, the second pull-up transistor, the first pull-down transistor, the second pull-down transistor, the first gate transistor, and the second gate transistor each include a first source / drain layer, a channel layer, and a second source / drain layer sequentially arranged in the vertical direction. Wherein, the channel layers of the first pull-up transistor, the first pull-down transistor, and the first pass-gate transistor are each biased on a side away from the second interconnect structure relative to the first interconnect structure, and In this configuration, the channel layers of the second pull-up transistor, the second pull-down transistor, and the second pass-gate transistor are each biased on a side away from the first interconnect structure relative to the second interconnect structure.

2. The SRAM cell according to claim 1, wherein, The channel layer of the first pull-up transistor, the second pull-up transistor, the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor, and the second pass-gate transistor each includes a first lateral extension extending on the top surface of the first source / drain layer, a second lateral extension extending on the bottom surface of the second source / drain layer, and a vertical extension connecting the first lateral extension and the second lateral extension.

3. The SRAM cell according to claim 1, wherein, The channel layer is a nanosheet or nanowire.

4. The SRAM cell according to claim 1, wherein, The first interconnect structure includes a first segment extending along a first direction substantially parallel to the upper surface of the substrate and a second segment extending along a second direction substantially parallel to the upper surface of the substrate and intersecting the first direction; The second interconnect structure includes a third segment extending along the first direction and a fourth segment extending along the second direction, wherein the first segment and the third segment are opposite to each other, and the second segment and the fourth segment are opposite to each other. The first segment includes a first protruding portion and a second protruding portion protruding in a direction away from the third segment. The first protruding portion forms the first source / drain layer of the first pull-down transistor and the second source / drain layer of the first pull-up transistor. The second protruding portion forms the first source / drain layer of the first gate transistor. The third segment includes a third protruding portion and a fourth protruding portion protruding in a direction away from the first segment. The third protruding portion forms the first source / drain layer of the second pull-down transistor and the second source / drain layer of the second pull-up transistor, and the fourth protruding portion forms the first source / drain layer of the second pass-gate transistor.

5. The SRAM cell according to claim 4, wherein, The second source / drain layers of the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor, and the second pass-gate transistor are separated from each other and are self-aligned to their respective first source / drain layers.

6. The SRAM cell according to claim 4, wherein, The first interconnect structure includes a first sub-interconnect structure and a second sub-interconnect structure stacked on the first sub-interconnect structure, wherein the portion of the first protruding portion on the first sub-interconnect structure forms the second source / drain layer of the first pull-up transistor, and the portion of the first protruding portion on the second sub-interconnect structure forms the first source / drain layer of the first pull-down transistor. The second interconnect structure includes a third sub-interconnect structure and a fourth sub-interconnect structure superimposed on the third sub-interconnect structure, wherein the portion of the third protrusion on the third sub-interconnect structure forms the second source / drain layer of the second pull-up transistor, and the portion of the third protrusion on the fourth sub-interconnect structure forms the first source / drain layer of the second pull-down transistor.

7. The SRAM cell according to claim 4, further comprising: A ring structure of dielectric, the ring structure including a first side corresponding to the first segment, a second side corresponding to the second segment, a third side corresponding to the third segment, and a fourth side corresponding to the fourth segment. The first side includes a fifth protruding portion projecting away from the third side, wherein a hole is formed within the fifth protruding portion to accommodate the first source / drain layer of the first pull-up transistor, and The third side includes a sixth protruding portion that protrudes away from the first side, wherein a hole is formed in the sixth protruding portion to accommodate the first source / drain layer of the second pull-up transistor.

8. The SRAM cell according to claim 7, wherein, The first source / drain layers of the first pull-up transistor and the second pull-up transistor are respectively self-aligned with their respective second source / drain layers.

9. The SRAM cell according to claim 7, wherein, The first side to the fourth side are respectively self-aligned with the first segment to the fourth segment, and the first side to the fourth side overlap with the first segment to the fourth segment in the vertical direction.

10. The SRAM cell according to claim 7, wherein, The first side further includes a seventh protruding portion projecting in a direction away from the third side, wherein a hole is formed within the seventh protruding portion to accommodate a first dummy source / drain layer, and The third side further includes an eighth protruding portion that projects away from the first side, wherein the eighth protruding portion has a hole formed therein to accommodate the second dummy source / drain layer. Wherein, the first dummy source / drain layer and the second dummy source / drain layer have substantially the same material as the first source / drain layer of the first pull-up transistor and the first source / drain layer of the second pull-up transistor. The ring structure includes a portion between the first dummy source / drain layer and the first interconnect structure, and a portion between the second dummy source / drain layer and the second interconnect structure.

11. The SRAM cell according to claim 10, wherein, The fifth protruding portion, the sixth protruding portion, the seventh protruding portion, and the eighth protruding portion are respectively self-aligned with the first protruding portion, the third protruding portion, the second protruding portion, and the fourth protruding portion.

12. The SRAM cell according to claim 7, further comprising: The first pull-down branch and the first through-gate branch extend at least partially along the first direction and are substantially aligned in the first direction; A second pull-down branch and a second through-gate branch extending at least partially along and substantially aligned in a first direction, wherein the first pull-down branch, the second pull-down branch, the first through-gate branch, and the second through-gate branch comprise substantially the same dielectric material, and the first pull-down branch and the first through-gate branch are spaced apart from the second pull-down branch and the second through-gate branch in a second direction. The second source / drain layer of the first pull-down transistor is disposed on the sidewall of the first pull-down branch opposite to the second pass-through gate branch. The second source / drain layer of the first gate transistor is disposed on the sidewall of the first gate branch opposite to the second pull-down branch. The second source / drain layer of the second pull-down transistor is disposed on the sidewall of the second pull-down branch opposite to the first gate branch. The second source / drain layer of the second pass-gate transistor is disposed on the sidewall of the second pass-gate branch opposite to the first pull-down branch.

13. The SRAM cell according to claim 12, wherein, The first drop-down branch, the first pass-through branch, the second drop-down branch, and the second pass-through branch are self-aligned with the annular structure and overlap with the annular structure in the vertical direction.

14. The SRAM cell according to claim 2, wherein, The channel layer of the first pull-down transistor is C-shaped with an opening facing away from the second pass-through gate transistor. The channel layer of the first gate transistor is C-shaped with an opening facing away from the second pull-down transistor. The channel layer of the second pull-down transistor is C-shaped with an opening facing away from the first pass-through gate transistor. The second channel layer of the gate transistor is C-shaped with an opening facing away from the first pull-down transistor. The channel layer of the first pull-up transistor has an opening that faces the same direction as the C-shaped opening of the channel layer of the first pull-down transistor. The channel layer of the second pull-up transistor has an opening that is C-shaped in the same direction as the opening of the C-shape of the channel layer of the second pull-down transistor.

15. The SRAM cell according to claim 14, wherein, The channel layers of the first pull-up transistor, the second pull-up transistor, the first pull-down transistor, the second pull-down transistor, the first pass-gate transistor, and the second pass-gate transistor are self-aligned between their respective first source / drain layers and second source / drain layers.

16. The SRAM cell according to claim 7, further comprising: The first pull-up gate stack is self-aligned with the channel layer of the first pull-up transistor and surrounds the vertical portion of the channel layer of the first pull-up transistor. as well as The second pull-up gate stack is self-aligned to the channel layer of the second pull-up transistor and surrounds the vertical portion of the channel layer of the second pull-up transistor.

17. The SRAM cell according to claim 16, wherein, The first pull-up gate stack and the second pull-up gate stack are self-aligned to the annular structure and overlap with the annular structure in the vertical direction.

18. The SRAM cell according to claim 16, wherein, The first pull-up gate stack includes: a first portion, a vertical portion disposed between the first protruding portion and the fifth protruding portion surrounding the channel layer of the first pull-up transistor; and a second portion extending along the annular structure toward the fourth segment, wherein the first pull-up gate stack includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer, wherein the gate electrode layer has a protruding portion extending beyond the gate dielectric layer, the protruding portion of the gate electrode layer of the first pull-up gate stack being electrically connected to the second interconnect structure, while the gate electrode layer of the first pull-up gate stack is electrically insulated from the first interconnect structure through the gate dielectric layer of the first pull-up gate stack. The second pull-up gate stack includes: a first portion, a vertical portion of the channel layer surrounding the second pull-up transistor disposed between the third protrusion and the sixth protrusion; and a second portion, extending along the annular structure toward the second segment, wherein the second pull-up gate stack includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer, wherein the gate electrode layer has a protruding portion extending beyond the gate dielectric layer, the protruding portion of the gate electrode layer of the second pull-up gate stack being electrically connected to the first interconnect structure, while the gate electrode layer of the second pull-up gate stack being electrically insulated from the second interconnect structure through the gate dielectric layer of the second pull-up gate stack.

19. The SRAM cell according to claim 12, further comprising: The first drop-down grid stack is self-aligned to the first drop-down branch; The first passage gate stack is self-aligned with the first passage gate branch; The second drop-down grid stack is self-aligned to the second drop-down branch; as well as The second passage gate stack is self-aligned with the second passage gate branch.

20. The SRAM cell according to claim 19, wherein, The first pull-down gate stack includes: a first portion, a vertical portion disposed between the first protruding portion and the second source / drain layer of the first pull-down transistor surrounding the channel layer of the first pull-down transistor; and a second portion extending along the first pull-down branch, wherein the first pull-down gate stack includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer, wherein the gate electrode layer has a protruding portion extending beyond the gate dielectric layer, the protruding portion of the gate electrode layer of the first pull-down gate stack being electrically connected to the second interconnect structure, while the gate electrode layer of the first pull-down gate stack is electrically insulated from the first interconnect structure through the gate dielectric layer of the first pull-down gate stack. The first through-gate stack includes: a first portion, a vertical portion disposed between the second protruding portion and the second source / drain layer of the first through-gate transistor surrounding the channel layer of the first through-gate transistor; and a second portion extending along the first through-gate branch, wherein the first through-gate stack includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer, and the gate electrode layer of the first through-gate stack is electrically insulated from the first interconnect structure by the gate dielectric layer of the first through-gate stack. The second pull-down gate stack includes: a first portion, a vertical portion disposed between the third protruding portion and the second source / drain layer of the second pull-down transistor surrounding the channel layer of the second pull-down transistor; and a second portion extending along the second pull-down branch, wherein the second pull-down gate stack includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer, wherein the gate electrode layer has a protruding portion extending beyond the gate dielectric layer, the protruding portion of the gate electrode layer of the second pull-down gate stack being electrically connected to the first interconnect structure, while the gate electrode layer of the second pull-down gate stack is electrically insulated from the second interconnect structure through the gate dielectric layer of the second pull-down gate stack. The second through-gate stack includes: a first portion, a vertical portion of a channel layer surrounding the second through-gate transistor disposed between the fourth protruding portion and the second source / drain layer of the second through-gate transistor; and a second portion extending along the second through-gate branch, wherein the second through-gate stack includes a gate dielectric layer and a gate electrode layer on the gate dielectric layer, and the gate electrode layer of the second through-gate stack is electrically insulated from the second interconnect structure by the gate dielectric layer of the second through-gate stack.

21. A memory comprising an SRAM cell as claimed in any one of claims 1 to 20.

22. An electronic device comprising a memory as claimed in claim 21 and a processor operatively coupled to the memory.

23. The electronic device according to claim 22 includes a smartphone, a computer, a tablet computer, a wearable smart device, an artificial intelligence device, and a power bank.

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