Resistive memory and method of manufacturing resistive memory

Abstract

The application discloses a resistive memory and a manufacturing method thereof. The resistive memory comprises a first electrode part, a conversion layer, a second electrode part, and a first conductive layer and a barrier layer arranged on the side of the second electrode part facing the conversion layer. The surface of the first conductive layer on the side facing the conversion layer has roughness. The barrier layer is arranged on the side of the first conductive layer facing the conversion layer and is in contact with the conversion layer. The side of the barrier layer facing the conversion layer is longitudinally spaced apart from the side of the first conductive layer facing the conversion layer. Alternatively, the side of the barrier layer facing the conversion layer is flush with the side of the first conductive layer facing the conversion layer. Thus, the interface between the second electrode part and the conversion layer can be improved, the conductive performance, heat dissipation performance and stability of the resistive memory are further optimized, the randomness of the conductive filament generation position is reduced, and the working performance of the resistive memory is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory technology, and in particular to a resistive memory and a method for manufacturing a resistive memory. Background Technology

[0002] Resistive random access memory (RRAM or ReRAM) consists of a bottom electrode and a top electrode sandwiching a transition layer. To achieve better performance, optimize conductivity and heat dissipation, and reduce the randomness of the conductive wire's location, good contact between the bottom electrode and the transition layer is essential. By using a tungsten layer as the connection layer between the bottom electrode and the transition layer, the properties of tungsten can be fully utilized, reducing contact resistance and minimizing thermal damage to the resistive memory.

[0003] In related technologies, two methods are commonly used to deposit the tungsten layer when manufacturing resistive memory: one is to deposit the tungsten layer directly on the bottom electrode followed by the deposition of the conversion layer; the other is to perform chemical mechanical planarization on the tungsten layer after deposition, and then deposit the conversion layer. Both methods are prone to tungsten layer oxidation, resulting in high contact resistance between the tungsten layer and the conversion layer, leading to poor performance of the resistive memory. Therefore, it is necessary to optimize the contact interface between the tungsten layer and the conversion layer. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one object of the present invention is to provide a resistive memory with superior performance.

[0005] The present invention further proposes a method for manufacturing a resistive memory.

[0006] According to embodiments of the present invention, a resistive memory and a method for manufacturing a resistive memory include: a first electrode portion; a conversion layer disposed on one side of the first electrode portion and in contact with the first electrode portion; a second electrode portion disposed on the side of the conversion layer away from the first electrode portion, wherein a first conductive layer and a barrier layer are disposed on the side of the second electrode portion facing the conversion layer, the surface of the first conductive layer facing the conversion layer has a roughness, and the barrier layer is located on the side of the first conductive layer facing the conversion layer and in contact with the conversion layer, wherein the side of the barrier layer facing the conversion layer is longitudinally spaced from the side of the first conductive layer facing the conversion layer; and / or the side of the barrier layer facing the conversion layer is flush with the side of the first conductive layer facing the conversion layer.

[0007] Therefore, by simultaneously providing a first conductive layer and a barrier layer on the side of the second electrode portion facing the conversion layer, and having a rough surface on the side of the first conductive layer facing the conversion layer, and the barrier layer being located on the side of the first conductive layer facing the conversion layer and in contact with the conversion layer, the interface between the second electrode portion and the conversion layer can be improved, further optimizing the conductivity, heat dissipation, and stability of the resistive memory, reducing the randomness of the conductive wire generation position, and thus improving the working performance of the resistive memory.

[0008] In some examples of the present invention, the first conductive layer includes an electrode body and a protrusion, the protrusion being disposed on the electrode body and protruding toward the conversion layer, the side of the barrier layer facing the conversion layer being longitudinally spaced from the side of the electrode body facing the conversion layer, and the side of the barrier layer facing the conversion layer being longitudinally spaced from the side of the protrusion facing the conversion layer.

[0009] In some examples of the present invention, the side surface of the barrier layer facing the conversion layer is a ground and polished surface.

[0010] In some examples of the present invention, the first conductive layer includes an electrode body and a protrusion, the protrusion being disposed on the electrode body and protruding toward the conversion layer, the side of the barrier layer facing the conversion layer being longitudinally spaced from the side of the electrode body facing the conversion layer, and the side of the protrusion facing the conversion layer being flush with the side of the barrier layer facing the conversion layer.

[0011] In some examples of the present invention, the side surface of the protrusion facing the conversion layer and the side surface of the barrier layer facing the conversion layer are both ground and polished surfaces.

[0012] In some examples of the present invention, there are multiple protrusions, and the multiple protrusions are arranged laterally along the electrode body.

[0013] In some examples of the present invention, the root mean square roughness of the surface of the first conductive layer facing the conversion layer is Rq, and Rq satisfies the relationship: Rq=[5A,30A].

[0014] In some examples of the present invention, the material of the first conductive layer includes at least one selected from tungsten, titanium, silicon, aluminum, tantalum, tantalum nitride, tungsten nitride, and titanium nitride.

[0015] In some examples of the present invention, the material of the barrier layer includes at least one of tungsten nitride, titanium nitride, tantalum nitride, and silicon nitride.

[0016] The method for manufacturing a resistive memory according to an embodiment of the present invention is applicable to the resistive memory described above. The method for manufacturing a resistive memory includes the following steps: depositing a first conductive layer on one side of a second conductive layer, wherein the second electrode portion includes the second conductive layer, and the side of the first conductive layer opposite to the second conductive layer has a roughness; depositing a barrier layer on the side of the first conductive layer opposite to the second conductive layer; grinding and polishing the barrier layer until the side of the barrier layer opposite to the second conductive layer is longitudinally spaced from the protrusions of the first conductive layer; and depositing a conversion layer on the side of the barrier layer opposite to the first conductive layer.

[0017] In some examples of the present invention, after the step of depositing the barrier layer on the side of the first conductive layer away from the second conductive layer, the method further includes: grinding and polishing the barrier layer until the side of the barrier layer away from the second conductive layer is flush with the protrusion of the first conductive layer.

[0018] In some examples of the present invention, the step of grinding and polishing the barrier layer until the side of the barrier layer away from the second conductive layer is flush with the protrusion of the first conductive layer further includes: the protrusion of the first conductive layer is at least partially ground and polished, wherein the grinding selectivity of the protrusion of the first conductive layer is the same as the grinding selectivity of the barrier layer; or the grinding selectivity of the protrusion of the first conductive layer is different from the grinding selectivity of the barrier layer.

[0019] In some examples of the present invention, the step of depositing the barrier layer on the side of the first conductive layer away from the second conductive layer further includes: depositing three sub-barrier layers with different densities on the side of the first conductive layer away from the second conductive layer to form the barrier layer.

[0020] In some examples of the present invention, the step of depositing the first conductive layer on one side of the second conductive layer further includes: depositing the first conductive layer on one side of the second conductive layer by physical vapor deposition.

[0021] In some examples of the present invention, the step of depositing the first conductive layer on one side of the second conductive layer is further included before: grinding and polishing one side of the second conductive layer.

[0022] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0023] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0024] Figure 1 This is a cross-sectional view of a resistive memory according to an embodiment of the present invention;

[0025] Figure 2 This is a flowchart of a method for manufacturing a resistive memory according to an embodiment of the present invention;

[0026] Figure 3 This is a flowchart of a method for manufacturing a resistive memory according to another embodiment of the present invention;

[0027] Figure 4 This is a cross-sectional view of structure 1 according to an embodiment of the present invention;

[0028] Figure 5 This is a cross-sectional view of structure 2 according to an embodiment of the present invention;

[0029] Figure 6 This is a cross-sectional view of structure 3 according to an embodiment of the present invention;

[0030] Figure 7 This is a cross-sectional view of structure 4 according to an embodiment of the present invention;

[0031] Figure 8 This is a cross-sectional view of structure 5 according to an embodiment of the present invention;

[0032] Figure 9 This is a cross-sectional view of structure 6 according to an embodiment of the present invention;

[0033] Figure 10 This is a cross-sectional view of structure 7 according to an embodiment of the present invention.

[0034] Figure label:

[0035] 100. Resistive memory;

[0036] 10. First electrode section; 11. Third conductive layer; 12. Atom-providing layer;

[0037] 20. Transition Layer;

[0038] 30. Second electrode portion; 31. First conductive layer; 311. Electrode body; 312. Protrusion; 32. Barrier layer; 321. Sub-barrier layer; 33. Second conductive layer;

[0039] 40. First dielectric layer; 41. Metal layer; 42. Second dielectric layer; 43. Sidewall; 44. Protective layer. Detailed Implementation

[0040] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0041] The following is for reference. Figures 1-10A resistive memory 100 according to an embodiment of the present invention is described. The resistive memory 100 may be manufactured using a method for manufacturing a resistive memory 100.

[0042] Combination Figure 1 As shown, the resistive memory 100 according to an embodiment of the present invention may mainly include: a first electrode portion 10, a conversion layer 20, and a second electrode portion 30. The conversion layer 20 is disposed on one side of the first electrode portion 10 and in contact with the first electrode portion 10, and the second electrode portion 30 is disposed on the side of the conversion layer 20 away from the first electrode portion 10. Thus, the conversion layer 20 is sandwiched between the first electrode portion 10 and the second electrode portion 30, forming the basic structure of the resistive memory 100. The first electrode portion 10 and the second electrode portion 30 are used to receive voltage, and the conversion layer 20 can switch the resistive state under the action of voltage, thereby achieving the effect of digital signal storage and ensuring the normal operation of the resistive memory 100.

[0043] Combination Figure 1 As shown, the second electrode portion 30 is provided with a first conductive layer 31 and a barrier layer 32 on the side facing the conversion layer 20. The surface of the first conductive layer 31 facing the conversion layer 20 has roughness, and the barrier layer 32 is located on the side of the first conductive layer 31 facing the conversion layer 20 and is in contact with the conversion layer 20.

[0044] Specifically, by providing a first conductive layer 31 on the side of the second electrode portion 30 facing the conversion layer 20, and by further providing a second conductive layer 33 to the second electrode portion 30, the first conductive layer 31 can serve as a connection layer between the second electrode portion 30 and the conversion layer 20 by contacting the second conductive layer 33 and the conversion layer 20 respectively. The lattice matching degree between the first conductive layer 31 and the second conductive layer 33, and the lattice matching degree between the first conductive layer 31 and the conversion layer 20 are both higher than the lattice matching degree between the second conductive layer 33 and the conversion layer 20. That is, by providing the first conductive layer 31, a stable and good contact can be formed between the conversion layer 20 and the second electrode portion 30, reducing the contact resistance, thereby enabling rapid conduction to promote heat dissipation, reducing thermal damage to the resistive memory 100, improving the electrical uniformity of the resistive memory 100, and thus improving the reliability and performance of the resistive memory 100.

[0045] Furthermore, by making the surface of the first conductive layer 31 facing the conversion layer 20 rough, not only can the contact area between the first conductive layer 31 and the conversion layer 20 be increased, making the contact between the first conductive layer 31 and the conversion layer 20 tighter, thereby improving the heat dissipation capacity between the second electrode portion 30 and the conversion layer 20 and improving the heat dissipation performance of the resistive memory 100, but also the position of the formed conductive wire can be made regular, reducing the randomness of the conductive wire generation position, thereby improving the electrical uniformity and increasing the lifespan of the resistive memory 100.

[0046] Furthermore, considering that during the continuous formation and breakage of the conductive wire of the resistive memory 100, metal atoms may accumulate in the first conductive layer 31 or diffuse from the first conductive layer 31 into the conversion layer 20, and oxygen-vacancy exchange may occur at the interface between the first conductive layer 31 and the conversion layer 20, leading to a decrease in the stability of the conductive wire and a reduction in the number of cycles, a barrier layer 32 is provided on the side of the first conductive layer 31 facing the conversion layer 20. The barrier layer 32 is located between the conversion layer 20 and the first conductive layer 31. In this way, the barrier layer 32 can reduce the cumulative effect of metal elements in the first conductive layer 31, reduce the diffusion effect from the first conductive layer 31 to the conversion layer 20 during multiple cycles, and reduce the oxygen-vacancy exchange effect at the interface between the first conductive layer 31 and the conversion layer 20, thereby increasing the stability of the resistive memory 100.

[0047] In addition, the barrier layer 32 can also eliminate the stress between the first conductive layer 31 and the conversion layer 20, forming a resistance value with higher consistency, thereby making the electrical regularity and uniformity of the resistive memory 100 better.

[0048] After the barrier layer 32 is deposited on the first conductive layer 31, the barrier layer 32 needs to be ground and polished. By controlling the amount of grinding, the barrier layer 32 facing the conversion layer 20 and the first conductive layer 31 facing the conversion layer 20 can be longitudinally spaced apart, so that the barrier layer 32 is in contact with the conversion layer 20, while the first conductive layer 31 is not in contact with the conversion layer 20. Alternatively, the barrier layer 32 facing the conversion layer 20 and the first conductive layer 31 facing the conversion layer 20 can be made flush, so that both the barrier layer 32 and the first conductive layer 31 are in contact with the conversion layer 20. This allows for control of the contact point between the second electrode portion 30 and the conversion layer 20, adjustment of the formation voltage of the resistive memory 100, improvement of the performance of the resistive memory 100, and expansion of the applicable scenarios of the resistive memory 100.

[0049] Therefore, by simultaneously providing a first conductive layer 31 and a barrier layer 32 on the side of the second electrode portion 30 facing the conversion layer 20, and having a rough surface on the side of the first conductive layer 31 facing the conversion layer 20, and the barrier layer 32 being located on the side of the first conductive layer 31 facing the conversion layer 20 and in contact with the conversion layer 20, the interface between the second electrode portion 30 and the conversion layer 20 can be improved, further optimizing the conductivity, heat dissipation, and stability of the resistive memory 100, reducing the randomness of the conductive wire generation position, and thereby improving the working performance of the resistive memory 100.

[0050] Combination Figure 1 As shown, the first conductive layer 31 may mainly include an electrode body 311 and a protrusion 312. The protrusion 312 is disposed on the electrode body 311 and protrudes toward the conversion layer 20. The blocking layer 32 is longitudinally spaced from the side of the electrode body 311 toward the conversion layer 20.

[0051] Specifically, the side of protrusion 312 facing the conversion layer 20 and the side of electrode body 311 facing the conversion layer 20 together form a rough surface. Protrusion 312 is located between the side of barrier layer 32 facing the conversion layer 20 and the side of electrode body 311 facing the conversion layer 20. That is, the longitudinal distance between the side of barrier layer 32 facing the conversion layer 20 and the side of electrode body 311 facing the conversion layer 20 affects the longitudinal distance of protrusion 312. By longitudinally spacing the side of barrier layer 32 facing the conversion layer 20 and the side of electrode body 311 facing the conversion layer 20, a certain longitudinal distance can be ensured for protrusion 312, thereby ensuring the surface roughness of the side of first conductive layer 31 facing the conversion layer 20. This ensures that conductive wires can be generated at fixed points at protrusion 312, reducing the randomness of the formation position of conductive wires.

[0052] Combination Figure 1 As shown, there are multiple protrusions 312, which are arranged laterally along the electrode body 311. Specifically, by setting multiple protrusions 312 and arranging them laterally along the electrode body 311, local concentration of protrusions 312 on the electrode body 311 can be avoided. This ensures that the protrusions 312 are evenly distributed on the side of the electrode body 311 facing the conversion layer 20, guaranteeing the roughness of the surface of the first conductive layer 31 facing the conversion layer 20. This not only further increases the contact area between the first conductive layer 31 and the conversion layer 20, improving conductivity and heat dissipation, but also further reduces the randomness of the formation position of the conductive wires, making the position distribution of the conductive wires more regular and uniform, thereby further improving the working performance of the resistive memory 100.

[0053] In some embodiments of the present invention, the side of the barrier layer 32 facing the conversion layer 20 is longitudinally spaced from the side of the protrusion 312 facing the conversion layer 20. In this way, the barrier layer 32 can completely cover the protrusion 312. Under the premise that the barrier layer 32 is in contact with the conversion layer 20, the protrusion 312 and the conversion layer 20 are longitudinally spaced. This allows the side of the barrier layer 32 facing the conversion layer 20 to be longitudinally spaced from the side of the first conductive layer 31 facing the conversion layer 20. The barrier layer 32 can better reduce the cumulative effect of metal elements in the first conductive layer 31, better reduce the diffusion effect of the first conductive layer 31 to the conversion layer 20 during multiple cycles, and better reduce the oxygen-vacuum exchange effect at the interface between the first conductive layer 31 and the conversion layer 20.

[0054] Furthermore, the surface of the barrier layer 32 facing the conversion layer 20 is a polished surface. Specifically, the surface of the barrier layer 32 facing the conversion layer 20 is in direct contact with the conversion layer 20. By making the surface of the barrier layer 32 facing the conversion layer 20 a polished surface, the contact surface between the barrier layer 32 and the conversion layer 20 can be made more uniform and smooth, which facilitates the subsequent deposition of the conversion layer 20, improves the bonding force between the conversion layer 20 and the barrier layer 32, and thus improves the reliability of the resistive memory 100.

[0055] In other embodiments of the invention, combined with Figure 1 As shown, the side of the protrusion 312 facing the conversion layer 20 is flush with the side of the barrier layer 32 facing the conversion layer 20. In this way, the barrier layer 32 does not completely cover the protrusion 312. The protrusion 312 is flush with the barrier layer 32, so that the side of the barrier layer 32 facing the conversion layer 20 is flush with the side of the first conductive layer 31 facing the conversion layer 20. The protrusion 312 can contact the conversion layer 20, making the conductive wire thicker and improving the working performance of the resistive memory 100.

[0056] Furthermore, both the surface of the protrusion 312 facing the conversion layer 20 and the surface of the barrier layer 32 facing the conversion layer 20 are polished surfaces. Specifically, both the surface of the protrusion 312 facing the conversion layer 20 and the surface of the barrier layer 32 facing the conversion layer 20 are in direct contact with the conversion layer 20. By making both the surface of the protrusion 312 facing the conversion layer 20 and the surface of the barrier layer 32 facing the conversion layer 20 polished surfaces, the contact surfaces between the protrusion 312 and the barrier layer 32 and the conversion layer 20 are made more uniform and smooth. This facilitates the subsequent deposition of the conversion layer 20, improves the bonding force between the conversion layer 20 and the barrier layer 32 and the protrusion 312 respectively, and thus improves the reliability of the resistive memory 100.

[0057] In some embodiments of the present invention, the root mean square roughness of the surface of the first conductive layer 31 facing the conversion layer 20 is Rq, and Rq satisfies the relationship: Rq = [5A, 30A]. Specifically, by setting the roughness of the surface of the first conductive layer 31 facing the conversion layer 20 within a reasonable range, it not only prevents the roughness of the surface of the first conductive layer 31 facing the conversion layer 20 from being too small, resulting in an overly smooth surface, thus avoiding an overly uniform electric field and a large degree of randomness in the formed conductive wires, but also prevents the roughness of the surface of the first conductive layer 31 facing the conversion layer 20 from being too large, resulting in interference of the conductive wires. In this way, the structural design of the surface of the first conductive layer 31 facing the conversion layer 20 can be further optimized, which is beneficial for forming conductive wires at specific locations, thereby increasing the cycle life of the resistive memory 100.

[0058] In some embodiments of the present invention, the material of the first conductive layer 31 may mainly include at least one of tungsten, titanium, silicon, aluminum, tantalum, tantalum nitride, tungsten nitride, and titanium nitride. Specifically, the first conductive layer 31 serves as the connecting layer between the second electrode portion 30 and the conversion layer 20, and its thermal conductivity, electrical resistance, and chemical reactivity are subject to certain requirements. At least one of tungsten, titanium, silicon, aluminum, tantalum, tantalum nitride, tungsten nitride, and titanium nitride can be selected as the manufacturing material of the first conductive layer 31. This not only ensures that the first conductive layer 31 has good thermal conductivity and low electrical resistance, thereby enabling rapid heat conduction, promoting heat dissipation, and reducing heat generation, thus reducing thermal damage to the resistive memory 100, but also ensures that the first conductive layer 31 has higher inertness, thereby preventing the first conductive layer 31 from reacting chemically with the conversion layer 20 and ensuring the thermal stability of the resistive memory 100.

[0059] In some embodiments of the present invention, the material of the barrier layer 32 may primarily include at least one of tungsten nitride, titanium nitride, tantalum nitride, and silicon nitride. Specifically, at least one of tungsten nitride, titanium nitride, tantalum nitride, and silicon nitride may be selected as the manufacturing material of the barrier layer 32. This not only ensures that the barrier layer 32 blocks the diffusion between the conversion layer 20 and the first conductive layer 31, but also prevents chemical reactions between the barrier layer 32 and the first conductive layer 31 and the conversion layer 20, thereby further improving the stability of the resistive memory 100.

[0060] Combination Figures 1-10 As shown, the manufacturing method of the resistive memory 100 according to the embodiment of the present invention can be applied to the resistive memory 100 described above, thereby enabling the production and manufacturing of the resistive memory 100, ensuring the structural reliability of the resistive memory 100, and facilitating the mass production and application of the resistive memory 100.

[0061] In some embodiments of the present invention, combined with Figure 1 , Figure 2 as well as Figures 4-9 As shown, the manufacturing method of the resistive memory 100 may mainly include the following steps: depositing a first conductive layer 31 on one side of the second conductive layer 33, wherein the second electrode portion 30 includes the second conductive layer 33, and the side of the first conductive layer 31 away from the second conductive layer 33 has roughness; depositing a barrier layer 32 on the side of the first conductive layer 31 away from the second conductive layer 33; grinding and polishing the barrier layer 32 until the side of the barrier layer 32 away from the second conductive layer 33 is longitudinally spaced from the protrusions 312 of the first conductive layer 31; and depositing a conversion layer 20 on the side of the barrier layer 32 away from the first conductive layer 31.

[0062] Specifically, in manufacturing the resistive memory 100, a first conductive layer 31 can be deposited on one side of the second conductive layer 33 of the second electrode portion 30, and the side of the first conductive layer 31 facing away from the second conductive layer 33 can be roughened. After the deposition of the first conductive layer 31 is completed, a barrier layer 32 can be further deposited on the side of the first conductive layer 31 facing away from the second conductive layer 33. Then, the barrier layer 32 is ground and polished so that the side of the barrier layer 32 facing away from the second conductive layer 33 is longitudinally spaced from the protrusions 312 of the first conductive layer 31, and the side of the barrier layer 32 facing away from the second conductive layer 33 is exposed. Afterwards, a conversion layer 20 can be deposited on the side of the barrier layer 32 facing away from the first conductive layer 31. The conversion layer 20 can cover the barrier layer 32 and be in contact with the barrier layer 32.

[0063] In this way, the first conductive layer 31 and the barrier layer 32 can be used as the connection layer between the second conductive layer 33 and the conversion layer 20, which makes the production and manufacturing of the resistive memory 100 simpler and more convenient.

[0064] In other embodiments of the invention, combined with Figures 3-6 as well as Figure 10 As shown, the manufacturing method of the resistive memory 100 may mainly include the following steps: depositing a first conductive layer 31 on one side of the second conductive layer 33, wherein the second electrode portion 30 includes the second conductive layer 33, and the side of the first conductive layer 31 away from the second conductive layer 33 has roughness; depositing a barrier layer 32 on the side of the first conductive layer 31 away from the second conductive layer 33; polishing the barrier layer 32 until the side of the barrier layer 32 away from the second conductive layer 33 is flush with the protrusion 312 of the first conductive layer 31; and depositing a conversion layer 20 on the side of the barrier layer 32 away from the first conductive layer 31.

[0065] Specifically, in manufacturing the resistive memory 100, a first conductive layer 31 can be deposited on one side of the second conductive layer 33 of the second electrode portion 30, and the side of the first conductive layer 31 facing away from the second conductive layer 33 can be roughened. After the deposition of the first conductive layer 31 is completed, a barrier layer 32 can be further deposited on the side of the first conductive layer 31 facing away from the second conductive layer 33. Then, the barrier layer 32 is ground and polished so that the side of the barrier layer 32 facing away from the second conductive layer 33 is flush with the protrusion 312 of the first conductive layer 31, and both the barrier layer 32 and the protrusion 312 facing away from the second conductive layer 33 are exposed. Afterwards, a conversion layer 20 can be deposited on the side of the barrier layer 32 facing away from the first conductive layer 31. The conversion layer 20 can cover the barrier layer 32 and the protrusion 312 and is in contact with the barrier layer 32 and the protrusion 312.

[0066] In this way, the first conductive layer 31 and the barrier layer 32 can also be used as the connection layer between the second conductive layer 33 and the conversion layer 20, which can make the production and manufacturing of the resistive memory 100 simpler and more convenient.

[0067] Furthermore, the step of grinding and polishing the barrier layer 32 until the side of the barrier layer 32 facing away from the second conductive layer 33 is flush with the protrusion 312 of the first conductive layer 31 may further include: the protrusion 312 of the first conductive layer 31 is at least partially ground and polished, wherein the grinding selectivity of the protrusion 312 of the first conductive layer 31 may be the same as the grinding selectivity of the barrier layer 32, or the grinding selectivity of the protrusion 312 of the first conductive layer 31 may be different from the grinding selectivity of the barrier layer 32.

[0068] Specifically, since the protrusion 312 is wrapped by the barrier layer 32 after the barrier layer 32 is deposited on the side of the first conductive layer 31 away from the second conductive layer 33, when grinding and polishing the barrier layer 32, not only the barrier layer 32 needs to be ground, but also, as the grinding goes deeper, the protrusion 312 of the first conductive layer 31 will be ground and polished at least partially. Depending on the material properties and friction coefficient difference between the barrier layer 32 and the protrusion 312, the grinding selection ratio of the grinding system for the protrusion 312 of the first conductive layer 31 can be set to be the same as that for the barrier layer 32, or the grinding selection ratio of the grinding system for the protrusion 312 of the first conductive layer 31 can be set to be different from that for the barrier layer 32, so that the side of the barrier layer 32 away from the second conductive layer 33 is flush with the protrusion 312 of the first conductive layer 31, ensuring the flatness of the surface of the first electrode portion 30 facing the conversion layer 20. Preferably, the grinding selection ratio of the grinding system for the protrusions 312 of the first conductive layer 31 is set differently from the grinding selection ratio for the barrier layer 32.

[0069] Combination Figure 5 and Figure 6As shown, in the manufacturing method of the resistive memory 100 according to an embodiment of the present invention, the step of depositing a barrier layer 32 on the side of the first conductive layer 31 away from the second conductive layer 33 may include: depositing three sub-barrier layers 321 with different densities on the side of the first conductive layer 31 away from the second conductive layer 33 to form the barrier layer 32.

[0070] Specifically, in the step of depositing the barrier layer 32 on the side of the first conductive layer 31 away from the second conductive layer 33, it can be: depositing three sub-barrier layers 321 with different densities on the side of the first conductive layer 31 away from the second conductive layer 33, and stacking the three sub-barrier layers 321 to form the barrier layer 32.

[0071] Due to the friction coefficients of the three sub-blocking layers 321 and the differences in light reflection between each sub-blocking layer 321, the grinding system can perform precise grinding based on the changes in the friction coefficients of the blocking layer 32 and the first conductive layer 31, the sound changes, and the differences in the signals generated by light reflection during the grinding and polishing process of the blocking layer 32 or the grinding and polishing of the blocking layer 32 and the first conductive layer 31. This allows for precise grinding and surface roughness control of the blocking layer 32 and the first motor layer, preventing the protrusion 312 from being ground away and thus making it impossible to generate conductive wires at the protrusion 312.

[0072] In some embodiments of the present invention, the step of depositing the first conductive layer 31 on one side of the second conductive layer 33 may further include: depositing the first conductive layer 31 by physical vapor deposition on one side of the second conductive layer 33.

[0073] Specifically, when depositing the first conductive layer 31 on one side of the second conductive layer 33, physical vapor deposition can be used. That is, the first conductive layer 31 is deposited on one side of the second conductive layer 33 by physical vapor deposition. This not only simplifies the deposition of the first conductive layer 31 and avoids environmental pollution, but also reduces the materials required for deposition, thereby lowering costs. In addition, this method can make the film formation of the first conductive layer 31 more uniform and dense, ensuring the bonding force between the first conductive layer 31 and the second conductive layer 33, thereby optimizing the structure of the first conductive layer 31 and even the second electrode portion 30, and improving the structural stability of the resistive memory 100.

[0074] It should be noted that the first conductive layer 31 can also be deposited on one side of the second conductive layer 33 by atomic layer deposition, which is not specifically limited here.

[0075] Combination Figures 2-4 As shown, in the manufacturing method of the resistive memory 100 according to an embodiment of the present invention, before the step of depositing the first conductive layer 31 on one side of the second conductive layer 33, the method further includes: grinding and polishing one side of the second conductive layer 33.

[0076] Specifically, before depositing the first conductive layer 31 on one side of the second conductive layer 33, one side of the second conductive layer 33 can be ground and polished. This makes the surface of one side of the second conductive layer 33 uniform and smooth, that is, the contact surface between the second conductive layer 33 and the first conductive layer 31 can be uniform and smooth. This facilitates the deposition of the second conductive layer 33, ensures the bonding force between the first conductive layer 31 and the second conductive layer 33, and improves the structural stability of the resistive memory 100.

[0077] The following is combined Figure 1 as well as Figures 4-10 The manufacturing process of the resistive memory 100 according to an embodiment of the present invention is described by way of example:

[0078] like Figure 4 As shown, a substrate comprising a metal layer 41, a first dielectric layer 40, a second dielectric layer 42, and a second conductive layer 33 is provided, and one side of the second conductive layer 33 is ground and polished to form structure 1. The first dielectric layer 40 can be, for example, an oxide layer such as silicon dioxide, and the second conductive layer 33 can be a TINN layer.

[0079] like Figure 5 As shown, based on structure 1, tungsten is deposited on one side of the second conductive layer 33 to form a first conductive layer 31. The thickness of the first conductive layer 31 can be 90 Å-150 Å, and the surface roughness of the side of the first conductive layer 31 facing away from the second conductive layer 33 can be 5 Å-30 Å. This forms structure 2.

[0080] like Figure 6 As shown, based on structure 2, a barrier layer 32 is deposited, wherein the barrier layer 32 is composed of three sub-barrier layers 321 with different densities, thus forming structure 3.

[0081] like Figure 7 As shown, the barrier layer 32 is ground and polished based on structure 3. Specifically, the barrier layer 32 can be ground and polished until the side of the barrier layer 32 facing away from the second conductive layer 33 is flush with the protrusion 312 of the first conductive layer 31, forming structure 4.

[0082] like Figure 8 As shown, ALO is deposited on the basis of structure 4 to form a conversion layer 20, thus forming structure 5.

[0083] like Figure 9 As shown, ALN, TIN, and SiN are deposited sequentially on top of structure 5, and then etched to form structure 6. Here, ALN is the atom-providing layer 12, used to provide AL atoms; TIN is the third conductive layer 11; ALN and TIN together constitute the first electrode portion 10; and SiN is the protective layer 44 of TIN.

[0084] like Figure 1As shown, ALO is deposited on the basis of structure 6, ALO forms sidewall 43, then SiN is deposited, SiN serves as a protective layer 44, and finally etching is performed to obtain the resistive memory 100 of the present invention.

[0085] It should be noted that, in combination Figure 10 As shown, when manufacturing the resistive memory 100, the other steps are the same as those shown in the figure. However, after forming structure 3, the barrier layer 32 can also be ground and polished on the basis of structure 3 until the side of the barrier layer 32 facing away from the second conductive layer 33 is longitudinally spaced from the protrusion 312 of the first conductive layer 31 to form structure 7. The subsequent steps are the same and will not be described in detail here.

[0086] Furthermore, other configurations and operations of the resistive memory 100 according to embodiments of the present invention are known to those skilled in the art and will not be described in detail here.

[0087] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0088] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0089] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A resistive memory, characterized in that, include: First electrode section (10); A conversion layer (20) is disposed on one side of the first electrode portion (10) and is in contact with the first electrode portion (10); A second electrode portion (30) is disposed on the side of the conversion layer (20) away from the first electrode portion (10). A first conductive layer (31) and a barrier layer (32) are disposed on the side of the second electrode portion (30) facing the conversion layer (20). The surface of the first conductive layer (31) facing the conversion layer (20) has a roughness. The barrier layer (32) is located on the side of the first conductive layer (31) facing the conversion layer (20) and is in contact with the conversion layer (20). The first conductive layer (31) includes an electrode body (311) and a protrusion (312). The protrusion (312) is disposed on the electrode body (311) and protrudes toward the conversion layer (20). The blocking layer (32) is longitudinally spaced from the side of the electrode body (311) facing the conversion layer (20) and from the side of the protrusion (312) facing the conversion layer (20). The material of the barrier layer (32) includes at least one of tungsten nitride, titanium nitride, tantalum nitride, and silicon nitride.

2. The resistive memory according to claim 1, characterized in that, The surface of the barrier layer (32) facing the conversion layer (20) is a polished surface.

3. The resistive memory according to claim 1, characterized in that, The first conductive layer (31) includes an electrode body (311) and a protrusion (312). The protrusion (312) is disposed on the electrode body (311) and protrudes toward the conversion layer (20). The barrier layer (32) is longitudinally spaced from the side of the electrode body (311) facing the conversion layer (20) and the side of the barrier layer (32) facing the conversion layer (20). The side of the protrusion (312) facing the conversion layer (20) and the side of the barrier layer (32) facing the conversion layer (20) are flush with each other.

4. The resistive memory according to claim 3, characterized in that, The protrusion (312) facing the conversion layer (20) and the barrier layer (32) facing the conversion layer (20) are both ground and polished surfaces.

5. The resistive memory according to claim 1, characterized in that, There are multiple protrusions (312), and the multiple protrusions (312) are arranged laterally along the electrode body (311).

6. The resistive memory according to claim 1, characterized in that, The root mean square roughness of the surface of the first conductive layer (31) facing the conversion layer (20) is Rq, and Rq satisfies the relationship: Rq=[5A,30A].

7. The resistive memory according to claim 1, characterized in that, The material of the first conductive layer (31) includes at least one of tungsten, titanium, silicon, aluminum, tantalum, tantalum nitride, tungsten nitride and titanium nitride.

8. A method for manufacturing a resistive memory, applicable to the resistive memory according to any one of claims 1-7, characterized in that, Includes the following steps: The first conductive layer (31) is deposited on one side of the second conductive layer (33), wherein the second electrode portion (30) includes the second conductive layer (33), and the side of the first conductive layer (31) facing away from the second conductive layer (33) has roughness; The barrier layer (32) is deposited on the side of the first conductive layer (31) away from the second conductive layer (33); The barrier layer (32) is ground and polished until the side of the barrier layer (32) facing away from the second conductive layer (33) is longitudinally spaced from the protrusion (312) of the first conductive layer (31); The conversion layer (20) is deposited on the side of the barrier layer (32) opposite to the first conductive layer (31).

9. The method for manufacturing a resistive memory according to claim 8, characterized in that, The step of depositing the barrier layer (32) on the side of the first conductive layer (31) opposite to the second conductive layer (33) further includes: The barrier layer (32) is ground and polished until the side of the barrier layer (32) facing away from the second conductive layer (33) is flush with the protrusion (312) of the first conductive layer (31).

10. The method for manufacturing a resistive memory according to claim 9, characterized in that, The step of grinding and polishing the barrier layer (32) until the side of the barrier layer (32) facing away from the second conductive layer (33) is flush with the protrusion (312) of the first conductive layer (31) further includes: The protrusions (312) of the first conductive layer (31) are at least partially ground and polished, wherein the grinding selectivity of the protrusions (312) of the first conductive layer (31) is the same as that of the barrier layer (32); or the grinding selectivity of the protrusions (312) of the first conductive layer (31) is different from that of the barrier layer (32).

11. The method for manufacturing a resistive memory according to claim 8, characterized in that, The step of depositing the barrier layer (32) on the side of the first conductive layer (31) opposite to the second conductive layer (33) further includes: Three sub-barrier layers (321) with different densities are deposited on the side of the first conductive layer (31) away from the second conductive layer (33) to form the barrier layer (32).

12. The method for manufacturing a resistive memory according to claim 8, characterized in that, The step of depositing the first conductive layer (31) on one side of the second conductive layer (33) further includes: The first conductive layer (31) is deposited on one side of the second conductive layer (33) by physical vapor deposition.

13. The method for manufacturing a resistive memory according to claim 8, characterized in that, The step of depositing the first conductive layer (31) on one side of the second conductive layer (33) includes the following prior to the step of depositing the first conductive layer (31): One side of the second conductive layer (33) is ground and polished.

Images