Double-insulating-layer organic thin film transistor, preparation method and application thereof

Abstract

The application belongs to the technical field of organic thin film transistor preparation, and particularly relates to a double-insulating-layer organic thin film transistor and a preparation method and application thereof. The double-insulating-layer organic thin film transistor comprises, from bottom to top, a substrate, a gate electrode layer, a double-insulating layer, an active layer and a source-drain electrode. A poly-p-xylene layer is formed by evaporating poly-p-xylene on the gate electrode layer, a poly-methyl methacrylate solution is spin-coated on the poly-p-xylene layer, and the double-insulating layer of poly-p-xylene / poly-methyl methacrylate is obtained through annealing. Then, a poly(3-hexylthiophene) solution is spin-coated on the poly-methyl methacrylate layer of the double-insulating layer, and the active layer of poly(3-hexylthiophene) is obtained through annealing. In electrical applications, the double-insulating-layer organic thin film transistor can improve the carrier mobility, reduce the threshold voltage and improve the transconductance.

Description

Technical Field

[0001] This invention belongs to the field of organic thin-film transistor fabrication technology, specifically relating to a double-insulating-layer organic thin-film transistor, its fabrication method, and its applications. Background Technology

[0002] Poly(3-hexylthiophene) (P3HT), as a soluble conjugated polymer, is widely used in the semiconductor layer of organic field-effect transistors. However, as a semiconductor layer, the regularity of the π-π stacking and the increase in molecular weight within P3HT are limited. The final performance of organic field-effect transistors depends not only on the inherent characteristics of each functional component but also on the growth mode, molecular sequence / orientation, grain boundaries, and grain size of the semiconductor layer. Among these factors, the semiconductor / insulator interface is a key factor affecting carrier mobility and device performance.

[0003] Low-density charge trapping and good contact compatibility are key requirements for insulator / semiconductor interface engineering. For P3HT thin-film transistors, polymethyl methacrylate (PMMA) is frequently used as a standard material for the insulating layer. However, when PMMA is used alone as the gate dielectric, its poor insulation properties weaken the current regulation capability of the organic thin-film transistor.

[0004] In addition, parylene itself has excellent insulating properties and good electrical properties. However, when a single parylene layer is used as a gate dielectric, its surface has a relatively high root mean square roughness, which reduces the crystal growth of semiconductor molecules and increases the density of interface traps. This hinders the diffusion of organic semiconductor molecules, further causes grain boundaries and reduces the crystallinity of the organic semiconductor film. At the same time, it also induces polarization effects and interface charge trapping, leading to a decrease in device performance. Summary of the Invention

[0005] This invention provides a double-insulating-layer organic thin-film transistor, its preparation method, and its application.

[0006] The technical solution of the present invention is as follows:

[0007] This invention provides a double insulating layer organic thin film transistor, which, from bottom to top, consists of a substrate, a gate electrode layer, a double insulating layer, an active layer, and source / drain electrodes;

[0008] The double insulating layer comprises a lower layer and an upper layer, wherein the lower layer is a parylene layer and the upper layer is a polymethyl methacrylate layer;

[0009] The active layer is a poly(3-hexylthiophene) layer.

[0010] The thickness of the par-xylene in this invention is 750nm-870nm, the thickness of the polymethyl methacrylate is 80nm-160nm, and the thickness of the poly(3-hexylthiophene) is 80nm-100nm.

[0011] The double-insulating-layer organic thin-film transistor of the present invention is prepared by the following steps:

[0012] (1) Fix the gate electrode layer on the substrate, evaporate parylene on the gate electrode layer to form a parylene layer, spin coat a polymethyl methacrylate solution on the parylene layer to form a polymethyl methacrylate layer, and anneal to obtain a parylene / polymethyl methacrylate double insulating layer.

[0013] (2) A poly(3-hexylthiophene) solution was spin-coated onto the polymethyl methacrylate layer in the poly(p-xylene / polymethyl methacrylate) double insulating layer and annealed to obtain a poly(3-hexylthiophene) active layer.

[0014] (3) The source and drain electrodes were prepared on the poly(3-hexylthiophene) active layer, and the double insulating layer organic thin film transistor was obtained by annealing.

[0015] The polymethyl methacrylate solution in step (1) of the present invention has a concentration of 8-12 mg / mL and is prepared by dissolving polymethyl methacrylate in anisole.

[0016] The poly(3-hexylthiophene) solution in step (2) of the present invention has a concentration of 6-10 mg / mL and is prepared by dissolving poly(3-hexylthiophene) in o-dichlorobenzene.

[0017] The source and drain electrodes in step (3) of this invention are made by 3D printing and spraying conductive silver paste.

[0018] The substrate of this invention is polyethylene terephthalate, and the gate electrode layer is indium tin oxide.

[0019] The present invention also provides an application of a double-insulating-layer organic thin-film transistor in improving electrical performance.

[0020] The applications described in this invention include the use of double-insulating-layer organic thin-film transistors in improving carrier mobility and reducing threshold voltage.

[0021] The applications described in this invention also include the application of double-insulating-layer organic thin-film transistors in improving transconductance.

[0022] Beneficial effects

[0023] The double-insulating-layer organic thin-film transistor provided by this invention has a double insulating layer consisting of P3HT as the active layer, Parylene as the lower insulating layer, and PMMA as the upper insulating layer. The unique layered structure improves the current regulation capability of the organic thin-film transistor.

[0024] The double insulating layer organic thin film transistor provided by this invention uses Parylene as the lower insulating layer and PMMA as the upper insulating layer to form a double insulating layer. This allows for the direct spin-coating of the P3HT active layer onto the hydrophilic PMMA layer. Compared to using only the hydrophobic Parylene layer as the insulating layer, this avoids surface treatment of the Parylene layer, ensuring good contact at the semiconductor / insulator interface, which in turn helps the orderly growth of semiconductor molecules.

[0025] The Parylene / PMMA double insulating layer organic thin film transistor provided by this invention can improve carrier mobility, reduce threshold voltage and improve transconductance, and has good conductivity. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure of the double insulating layer organic thin film transistor of the present invention.

[0027] Wherein, 1 is the PET substrate, 2 is the ITO gate, 3 is the Parylene layer, 4 is the PMMA layer, 5 is the P3HT layer, 6 is the source, and 7 is the drain.

[0028] Figure 2 X-ray diffraction patterns of the Parylene layer, PMMA layer, and Parylene / PMMA double insulating layer.

[0029] Figure 3 A comparison diagram of the water contact angles of the Parylene layer (a) and the PMMA layer (b).

[0030] Figure 4 The surface morphology of the Parylene layer (a), (b) and the PMMA layer (c), (d) are shown.

[0031] Figure 5 The output characteristics (I) of Parylene / PMMA(a), Parylene(b), PMMA(c) and PMMA / Parylene(d) DS With drain-source voltage (V DS The relationship curve.

[0032] Figure 6 The transfer properties (I) of Parylene / PMMA(a), Parylene(b), PMMA(c) and PMMA / Parylene(d) DSWith drain-source voltage (V GS The relationship curve.

[0033] Figure 7 The curves show the relationship between transconductance (Gm) and gate voltage for Parylene / PMMA, Parylene, PMMA, and PMMA / Parylene. Detailed Implementation

[0034] The following examples are intended to illustrate the present invention, and not to further limit the invention.

[0035] This invention provides a double-insulating-layer organic thin-film transistor, such as... Figure 1 As shown, from bottom to top, the layers are: substrate, gate electrode layer, double insulating layer, active layer, and source / drain electrodes.

[0036] The double insulating layer comprises a lower layer and an upper layer, wherein the lower layer is a parylene layer and the upper layer is a polymethyl methacrylate (PMMA) layer;

[0037] The active layer is a poly(3-hexylthiophene) (P3HT) layer, the substrate is polyethylene terephthalate, and the gate electrode layer is indium tin oxide.

[0038] The double insulating layer structure of parylene / polymethyl methacrylate has a small surface polarity and a smooth surface, which is more conducive to the orderly growth of active layer semiconductors. The double insulating layer structure further increases the insulation performance of the parylene / polymethyl methacrylate layer, reduces the leakage current of the device, and facilitates the improvement of electrical performance.

[0039] Preferably, the thickness of the poly(p-xylene) is 750nm-870nm, the thickness of the polymethyl methacrylate is 80nm-160nm, and the thickness of the poly(3-hexylthiophene) is 80nm-100nm.

[0040] In addition, the source and drain electrodes are arranged in parallel to form a poly(3-hexylthiophene) active layer channel between the source and drain electrodes.

[0041] The double-insulating-layer organic thin-film transistor of the present invention is prepared by the following steps:

[0042] (1) Fix the gate electrode layer on the substrate, evaporate parylene on the gate electrode layer to form a parylene layer, spin coat a polymethyl methacrylate solution on the parylene layer to form a polymethyl methacrylate layer, and anneal to obtain a parylene / polymethyl methacrylate double insulating layer.

[0043] (2) A poly(3-hexylthiophene) solution was spin-coated onto the polymethyl methacrylate layer in the poly(p-xylene / polymethyl methacrylate) double insulating layer and annealed to obtain a poly(3-hexylthiophene) active layer.

[0044] (3) The source and drain electrodes were prepared on the poly(3-hexylthiophene) active layer, and the double insulating layer organic thin film transistor was obtained by annealing.

[0045] The organic thin-film transistor of the present invention has a simple fabrication process. The entire fabrication process adopts vapor deposition and spin coating processes, and the fabrication conditions are mild, which can effectively reduce the cost of semiconductor devices.

[0046] Specifically, to ensure good mechanical properties, the substrate is polyethylene terephthalate (PET), which has the characteristic of being resistant to bending; in addition, to ensure electrical properties, the gate electrode layer is indium tin oxide (ITO), which has good electrical conductivity.

[0047] To further ensure electrical performance, in step (1), specifically, the vapor deposition is carried out at a temperature of 120°C for 6-10 hours; the annealing is carried out at a temperature of 90°C for 0.5 hours.

[0048] Using vapor deposition of parylene enables the creation of uniform and pinhole-free coatings on large-area substrates. Furthermore, the low carrier trap density in the parylene layer contributes to its excellent insulation and stability.

[0049] Preferably, the polymethyl methacrylate solution in step (1) has a concentration of 8-12 mg / mL and is prepared by dissolving polymethyl methacrylate in anisole.

[0050] Depositing a polymethyl methacrylate layer on top of parylene can significantly reduce the overall roughness of the gate dielectric, which is more conducive to the crystal growth of active layer semiconductor molecules.

[0051] Based on the spin coating thickness of polymethyl methacrylate and the concentration of the polymethyl methacrylate solution, the spin coating in step (1) has a spin coating speed of 500-1500 r / min and a time of 60 s.

[0052] Furthermore, the poly(3-hexylthiophene) solution in step (2) has a concentration of 6-10 mg / mL and is prepared by dissolving poly(3-hexylthiophene) in o-dichlorobenzene.

[0053] Poly(3-hexylthiophene), as a soluble organic semiconductor polymer, exhibits excellent contact with polymethyl methacrylate (PMMA) layers, allowing for direct spin-coating of the PMMA layer without prior surface treatment. This excellent contact at the insulator / semiconductor interface contributes to improved carrier mobility.

[0054] Based on the spin coating thickness of poly(3-hexylthiophene) and the concentration of poly(3-hexylthiophene) solution, the spin coating in step (2) has a spin coating speed of 1500-2500 r / min and a time of 60 s.

[0055] In addition, the annealing in step (2) is carried out at a temperature of 120°C for 10 minutes to further ensure the crystal growth and crystallinity of the semiconductor layer molecules.

[0056] To further simplify the process, the source and drain in step (3) are made by 3D printing and spraying conductive silver paste. Meanwhile, conductive silver paste is a good conductive connector.

[0057] The annealing in step (3) is carried out at a temperature of 90°C for 10 minutes to ensure that the source and drain have good conductivity, thereby guaranteeing the conductivity of the organic thin film transistor.

[0058] The present invention also provides an application of a double-insulating-layer organic thin-film transistor in improving electrical performance.

[0059] Specifically, the application of double-insulating-layer organic thin-film transistors in improving carrier mobility, reducing threshold voltage, and increasing transconductance.

[0060] Example 1

[0061] (1) An ITO conductive film with a thickness of 0.125 mm was used as the gate electrode layer and fixed on a PET substrate with a thickness of 100 μm. Vapor deposition was performed on the ITO conductive film at 120 °C and 3 × 10⁻⁶ °C. -2 A Parylene layer with a thickness of 750 nm was formed by coating under Pa conditions for 6 hours. A PMMA solution was then spin-coated onto the Parylene layer at a spin speed of 500 r / min for 60 seconds to form a PMMA layer with a thickness of 80 nm. The mixture was then annealed at 90 °C for 0.5 hours to obtain a Parylene / PMMA double insulating layer. The PMMA solution had a concentration of 8 mg / mL and was prepared by dissolving PMMA in anisole.

[0062] (2) On the PMMA layer in the Parylene / PMMA double insulating layer, a P3HT solution was spin-coated at a spin-coating speed of 1500 r / min for 60 seconds, and then annealed at a temperature of 120℃ for 10 min to obtain a P3HT active layer with a thickness of 80 nm; wherein, the P3HT solution has a concentration of 6 mg / mL and is prepared by dissolving P3HT in o-dichlorobenzene.

[0063] (3) On the P3HT active layer, the source and drain electrodes are prepared by spraying conductive silver paste by 3D printing. The source and drain electrodes are arranged in parallel with a spacing of 1 mm and a length of 20 mm. The electrodes are annealed at 90°C for 10 min to obtain a double insulating layer organic thin film transistor.

[0064] Example 2

[0065] (1) An ITO conductive film with a thickness of 0.125 mm was used as the gate electrode layer and fixed on a PET substrate with a thickness of 100 μm. Vapor deposition was performed on the ITO conductive film at 120 °C and 3 × 10⁻⁶ °C. -2 A Parylene layer with a thickness of 800 nm was formed by coating under Pa conditions for 8 hours. A PMMA solution was then spin-coated onto the Parylene layer at a spin-coating speed of 1000 r / min for 60 seconds to form a PMMA layer with a thickness of 120 nm. The mixture was then annealed at 90 °C for 0.5 hours to obtain a Parylene / PMMA double insulating layer. The PMMA solution had a concentration of 8 mg / mL and was prepared by dissolving PMMA in anisole.

[0066] (2) On the PMMA layer in the Parylene / PMMA double insulating layer, a P3HT solution was spin-coated at a spin-coating speed of 2000 r / min for 60 seconds, and then annealed at a temperature of 120℃ for 10 min to obtain a P3HT active layer with a thickness of 90 nm; wherein, the P3HT solution has a concentration of 8 mg / mL and is prepared by dissolving P3HT in o-dichlorobenzene.

[0067] (3) On the P3HT active layer, the source and drain electrodes are prepared by spraying conductive silver paste by 3D printing. The source and drain electrodes are arranged in parallel with a spacing of 1 mm and a length of 20 mm. The electrodes are annealed at 90°C for 10 min to obtain a double insulating layer organic thin film transistor.

[0068] Example 3

[0069] (1) An ITO conductive film with a thickness of 0.125 mm was used as the gate electrode layer and fixed on a PET substrate with a thickness of 100 μm. Vapor deposition was performed on the ITO conductive film at 120 °C and 3 × 10⁻⁶ °C. -2A Parylene layer with a thickness of 870 nm was formed by coating under Pa conditions for 10 h. A PMMA solution was then spin-coated onto the Parylene layer at a spin speed of 1500 r / min for 60 seconds to form a PMMA layer with a thickness of 160 nm. The layer was then annealed at 90 °C for 0.5 h to obtain a Parylene / PMMA double insulating layer. The PMMA solution had a concentration of 12 mg / mL and was prepared by dissolving PMMA in anisole.

[0070] (2) On the PMMA layer in the Parylene / PMMA double insulating layer, a P3HT solution was spin-coated at a spin-coating speed of 2500 r / min for 60 seconds, and then annealed at a temperature of 120℃ for 10 min to obtain a P3HT active layer with a thickness of 100 nm; wherein, the P3HT solution has a concentration of 10 mg / mL and is prepared by dissolving P3HT in o-dichlorobenzene.

[0071] (3) On the P3HT active layer, the source and drain electrodes are prepared by spraying conductive silver paste by 3D printing. The source and drain electrodes are arranged in parallel with a spacing of 1 mm and a length of 20 mm. The electrodes are annealed at 90°C for 10 min to obtain a double insulating layer organic thin film transistor.

[0072] Comparative Example 1

[0073] Compared with Example 2, in step (1), no PMMA layer was prepared on the Parylene layer, and the insulating layer was only the Parylene layer. Other operations were the same as in Example 2.

[0074] Comparative Example 2

[0075] Compared with Example 2, in step (1), no Parylene layer was prepared on the ITO conductive film, and the insulating layer was only a PMMA layer. Other operations were the same as in Example 2.

[0076] Comparative Example 3

[0077] Compared with Example 2, in step (1), a PMMA layer is first prepared on the ITO conductive film, and then a Parylene layer is prepared on the PMMA layer to obtain a PMMA / Parylene double insulating layer. Other operations are the same as in Example 2.

[0078] Test Results

[0079] 1. Component analysis

[0080] Figure 2The X-ray diffraction patterns of the Parylene, PMMA, and P3HT layers are shown. The Parylene layer exhibits sharp diffraction peaks, indicating that it has a high degree of crystallinity. The PMMA layer shows two broad, diffuse diffraction peaks, indicating that it has an amorphous structure. The P3HT layer shows a sharp diffraction peak at 2θ = 4°, indicating that it has an ordered structure and high crystallinity, which can improve the charge transport performance of the semiconductor.

[0081] 2. Hydrophilicity / hydrophobicity analysis

[0082] To compare the hydrophilicity and hydrophobicity of the PMMA and Parylene layers, their water contact angles were tested. The water contact angle experiment was conducted in a dry environment at 25°C, with a droplet size of 100 μL. The test results were the average of five data points. Figure 3 As shown, the water contact angle of the Parylene layer is 91.93°, and that of the PMMA layer is 83.88°. This indicates that Parylene is a hydrophobic layer, while PMMA is a hydrophilic layer.

[0083] 3. Surface roughness analysis

[0084] The surface morphology of different insulating layers was studied using atomic force microscopy. Figure 4 (a), (b) and Figure 4 (c) and (d) show the surface morphology of the Parylene layer and the PMMA layer, respectively. Further calculations show that the surface roughness of the Parylene layer and the PMMA layer are 0.743 nm and 0.200 nm, respectively. It can be seen that the surface roughness of the PMMA layer is significantly smaller than that of the Parylene layer.

[0085] 4. Output and transfer characteristics analysis

[0086] The organic thin-film transistors fabricated in this application, using P3HT as the active layer and Parylene / PMMA (Example 2), Parylene (Comparative Example 1), PMMA (Comparative Example 2), and PMMA / Parylene (Comparative Example 3) as dielectric layers, had their output characteristic curves measured at room temperature. Figure 5 As shown. In V DS Below -60V, all four organic thin-film transistors exhibit significant linear and saturation characteristics, and can operate normally within an 80V range. Furthermore, the transfer characteristic curves of these four organic thin-film transistors were tested, as shown below. Figure 6 As shown.

[0087] To better compare performance, Figure 5and Figure 6 After further processing, the carrier mobility, subthreshold slope, and threshold voltage of the four organic thin-film transistors were obtained, as shown in the table below.

[0088]

[0089] Key performance parameters of organic thin-film transistors (OTCs) include carrier mobility and threshold voltage. Carrier mobility represents the speed at which carriers move within the active layer of an OTC transistor, while threshold voltage represents the gate voltage of the OTC transistor in the critical conduction state. As shown in the table above, the carrier mobility of the OTC transistor using a Parylene / PMMA (Example 2) double insulating layer is 28.3 times, 11.3 times, and 44.7 times that of the OTC transistors using only a Parylene layer (Comparative Example 1), only a PMMA layer (Comparative Example 2), and a PMMA / Parylene (Comparative Example 3) double insulating layer, respectively. Furthermore, the threshold voltage of the Parylene / PMMA (Example 2) double insulating layer OTC transistor is significantly lower than that of the OTC transistors using only a Parylene layer (Comparative Example 1), only a PMMA layer (Comparative Example 2), and PMMA / Parylene (Comparative Example 3) double insulating layer.

[0090] 5. Relationship between transconductance and gate voltage

[0091] transconductance This indicates the ability of an organic thin-film transistor to convert voltage into current. Figure 7 The graphs show the transconductance versus gate voltage of Parylene / PMMA (Example 2), Parylene (Comparative Example 1), PMMA / Parylene (Comparative Example 3), and PMMA (Comparative Example 2) organic thin-film transistors with gate voltages between 0 and -50V. GS At -50V, the G of four organic thin-film transistors m The values ​​are respectively, G m1 (Parylene / PMMA)=-0.979mS, G m2 (Parylene) = -0.201 mS, G m3 (PMMA) = -0.028 mS, G m4 (PMMA / Parylene) = -0.234 mS. Therefore, the transconductance of the double-insulating-layer Parylene / PMMA (Example 2) organic thin-film transistor is significantly higher than that of the single-layer Parylene (Comparative Example 1), PMMA (Comparative Example 2), and double-insulating-layer PMMA / Parylene (Comparative Example 3) organic thin-film transistors.

Claims

1. A double-insulating-layer organic thin-film transistor, characterized in that, From bottom to top, the layers are: substrate, gate electrode layer, double insulating layer, active layer, and source / drain electrodes. The double insulating layer comprises a lower layer and an upper layer, wherein the lower layer is a parylene layer and the upper layer is a polymethyl methacrylate layer; The active layer is a poly(3-hexylthiophene) layer; The thickness of the poly(p-xylene) is 750nm-870nm, the thickness of the polymethyl methacrylate is 80nm-160nm, and the thickness of the poly(3-hexylthiophene) is 80nm-100nm.

2. The double-insulating-layer organic thin-film transistor according to claim 1, characterized in that, It is prepared through the following steps: (1) Fix the gate electrode layer on the substrate, evaporate parylene on the gate electrode layer to form a parylene layer, spin coat polymethyl methacrylate solution on the parylene layer to form a polymethyl methacrylate layer, and anneal to obtain a parylene / polymethyl methacrylate double insulating layer. (2) A poly(3-hexylthiophene) solution was spin-coated onto the polymethyl methacrylate layer in the poly(p-xylene / polymethyl methacrylate) double insulating layer and annealed to obtain a poly(3-hexylthiophene) active layer; (3) The source and drain electrodes are prepared on the poly(3-hexylthiophene) active layer, and the double insulating layer organic thin film transistor is obtained by annealing.

3. The double-insulating-layer organic thin-film transistor according to claim 2, characterized in that, The polymethyl methacrylate solution in step (1) has a concentration of 8-12 mg / mL and is prepared by dissolving polymethyl methacrylate in anisole.

4. The double-insulating-layer organic thin-film transistor according to claim 2, characterized in that, The poly(3-hexylthiophene) solution in step (2) has a concentration of 6-10 mg / mL and is prepared by dissolving poly(3-hexylthiophene) in o-dichlorobenzene.

5. The double-insulating-layer organic thin-film transistor according to claim 2, characterized in that, The source and drain in step (3) are made by 3D printing and spraying conductive silver paste.

6. The double-insulating-layer organic thin-film transistor according to claim 2, characterized in that, The substrate is polyethylene terephthalate, and the gate electrode layer is indium tin oxide.

7. The application of a double-insulating-layer organic thin-film transistor as described in any one of claims 1-6 in improving electrical performance.

8. The application according to claim 7, characterized in that, Applications of double-insulating-layer organic thin-film transistors in improving carrier mobility and reducing threshold voltage.

9. The application according to claim 7, characterized in that, Application of double-insulating-layer organic thin-film transistors in improving transconductance.

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