Display substrate and display device

Abstract

This disclosure provides a display substrate and a display device. The display substrate includes a substrate, which includes at least one test unit group, comprising a reference unit and a simulation unit. Both the reference unit and the simulation unit include a first electrode layer, a dielectric layer, and a second electrode layer sequentially stacked on the substrate. In a first direction parallel to the substrate, the second electrode layer has opposing first and second side surfaces. The dielectric layer of the reference unit protrudes or is flush with the first and second side surfaces of the second electrode layer in the first direction. A portion of the dielectric layer of the simulation unit is recessed inward in the first direction relative to the first and second side surfaces of the second electrode layer of the simulation unit, forming a simulation groove. The size of the simulation groove is determined based on the capacitance value between the first and second electrode layers of the reference unit and the capacitance difference between the capacitance values ​​of the first and second electrode layers of the simulation unit.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] With the continuous development of display technology, users have increasingly higher requirements for screen-to-body ratio. Therefore, in order to improve the screen-to-body ratio of display products, the solution of setting openings in the display area of ​​the display substrate to house hardware such as cameras, light sensors, and fingerprint recognition sensors is receiving significant attention in the industry. However, openings in the screen can easily create channels for water and oxygen intrusion into the luminescent material layer, potentially leading to display failure.

[0003] Currently, to solve the problem of water and oxygen intrusion, the common approach is to set isolation pillars in the display substrate to block the channels for water and oxygen intrusion from the external environment and prevent packaging defects. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide a display substrate, including a substrate, characterized in that the substrate includes: a display area and a non-display area located around the display area, the non-display area including: at least one test unit group, the test unit group including: a reference unit and a simulation unit; the reference unit and the simulation unit each include: a first electrode layer, a dielectric layer and a second electrode layer sequentially stacked on the substrate, the second electrode layer having opposing first and second side sides in a first direction parallel to the substrate;

[0006] In this configuration, the dielectric layer of the reference unit protrudes or is flush with the first and second sides of the second electrode layer in the first direction; a portion of the dielectric layer of the simulation unit is recessed in the first direction relative to the first and second sides of the second electrode layer of the simulation unit to form a simulation groove, the size of which is determined based on the capacitance value between the first and second electrode layers of the reference unit and the capacitance difference between the capacitance values ​​of the first and second electrode layers of the simulation unit.

[0007] In some exemplary embodiments, the dielectric layer includes: a first portion having a first thickness and a second portion having a second thickness located around the first portion. The first portion and the second portion are disposed in the same layer, and the first thickness is greater than the second thickness. The thickness is the dimension in the second direction, and the second direction is perpendicular to the first direction; wherein, the second portion of the reference unit protrudes or is flush with the first side and the second side of the second electrode layer of the reference unit in the first direction; the second portion of the analog unit is recessed in the first direction compared with the first side and the second side of the second electrode layer of the analog unit.

[0008] In some exemplary embodiments, the dimension of the second portion of the reference unit in the first direction is greater than the dimension of the second portion of the analog unit in the first direction;

[0009] The dimension of the first portion of the reference unit in the first direction is the same as the dimension of the first portion of the analog unit in the first direction;

[0010] The dimension of the first electrode layer of the reference unit in the first direction is the same as the dimension of the first electrode layer of the analog unit in the first direction, and the dimension of the second electrode layer of the reference unit in the first direction is the same as the dimension of the second electrode layer of the analog unit in the first direction.

[0011] In some exemplary embodiments, the first portion and the second portion are formed by two lithography processes. The first portion is a multi-layer inorganic insulating film layer, and the second portion is a single-layer inorganic insulating film layer.

[0012] In some exemplary embodiments, the dimension of the first portion in the first direction is less than the dimension of the second electrode layer in the first direction, and the dimension of the second electrode layer in the first direction is less than the dimension of the first electrode layer in the first direction.

[0013] In some exemplary embodiments, the orthographic projection of the second electrode layer on the substrate falls within the edge of the orthographic projection of the first electrode layer on the substrate.

[0014] In some exemplary embodiments, the cross-sectional shape of the second electrode layer is "L"-shaped.

[0015] In some exemplary embodiments, in a plane parallel to the display substrate, the test unit group includes: a main area and virtual areas located on both sides of the main area. The main area includes: a plurality of reference units or a plurality of simulation units arranged continuously. The virtual areas include: a plurality of virtual units arranged at intervals.

[0016] In some exemplary embodiments, the non-display area further includes: a first test pad pair connected to the reference unit and a second test pad pair connected to the simulation unit, each test pad pair including: a first pad connected to the first electrode layer and a second pad connected to the second electrode layer.

[0017] In some exemplary embodiments, the display area includes: a driving structure layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. The driving structure layer includes: a pixel driving circuit, and the light-emitting structure layer includes: a light-emitting unit connected to the pixel driving circuit. The first electrode layer is disposed on the same layer as the gate electrode of the transistor in the pixel driving circuit and / or on the same layer as the first electrode plate of the storage capacitor in the pixel driving circuit. The second electrode layer is disposed on the same layer as the source electrode and drain electrode of the transistor in the pixel driving circuit and / or on the same layer as the connection electrode in the pixel driving circuit.

[0018] In some exemplary embodiments, the non-display area includes: a bonding area close to the display area and a test area located on the side of the bonding area away from the display area, the bonding area being configured to be bonded to a flexible circuit board, and the test unit group being located in the test area.

[0019] In some exemplary embodiments, the display area includes: a display area, an opening area, and a barrier area located between the display area and the opening area. The barrier area includes: at least one isolation groove; the isolation groove includes: a recess and a flange disposed on the side of the recess away from the substrate; the barrier area includes: a first structural layer and a second structural layer sequentially stacked in a direction away from the substrate, the first structural layer including a metal layer, the recess penetrating the second structural layer and exposing at least a portion of the surface of the metal layer, the flange being disposed on the surface of the second structural layer away from the substrate, and a portion of the flange extending in a direction parallel to the substrate and protruding relative to the sidewall of the recess; the size of the isolation groove is determined according to the size of the simulated recess in the simulation unit, and the size of the isolation groove is the distance between the side of the flange and the sidewall of the recess.

[0020] Secondly, embodiments of this disclosure provide a display device, including a display substrate as described in any of the exemplary embodiments above.

[0021] The display substrate and display device provided in this disclosure, by setting a reference unit and a simulation unit in the non-display area, each of the reference and simulation units includes a first electrode layer, a dielectric layer, and a second electrode layer sequentially stacked on the substrate. Thus, during the fabrication of the display substrate, both the reference and simulation units can form capacitors (using the first and second electrode layers as the two plates of the capacitor, and the dielectric layer located between the first and second electrode layers as the dielectric). The dielectric layer of the reference unit protrudes or is flush with the first and second sides of the second electrode layer in a first direction, while a portion of the dielectric layer of the simulation unit is recessed in the first direction relative to the first and second sides of the second electrode layer of the simulation unit, forming a simulated groove. Therefore, the size of the simulated groove in the simulation unit can be determined based on the capacitance difference between the capacitance values ​​of the reference unit and the simulation unit. This allows for monitoring of the display substrate during the etching process, preventing problems such as excessively small or large dimensions during etching, thereby reducing defects such as cracks and peeling, and improving product yield.

[0022] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings.

[0023] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0024] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0025] Figure 1 This is a schematic diagram of the planar structure of the display substrate in an exemplary embodiment of the present disclosure;

[0026] Figure 2 This is a schematic diagram of the structure of the display area in the display substrate according to an exemplary embodiment of the present disclosure;

[0027] Figure 3 This is a schematic diagram of a partial planar structure of the display substrate in an exemplary embodiment of this disclosure;

[0028] Figure 4 This is a schematic cross-sectional view of the analog unit in the display substrate in an exemplary embodiment of the present disclosure;

[0029] Figure 5 This is a schematic cross-sectional view of a reference unit in a display substrate according to an exemplary embodiment of the present disclosure;

[0030] Figure 6 This is a schematic cross-sectional view of the display area and non-display area in the display substrate according to an exemplary embodiment of the present disclosure;

[0031] Figure 7 This is a schematic diagram of the planar structure of the test unit group in the display substrate according to an exemplary embodiment of the present disclosure;

[0032] Figure 8 This is a schematic diagram of the planar structure of the second electrode layer of the test unit group in the display substrate in an exemplary embodiment of the present disclosure;

[0033] Figure 9 This is a schematic diagram of the barrier region in the display substrate according to an exemplary embodiment of the present disclosure;

[0034] Figure 10A This is a schematic diagram of the structure after the first electrode layer is formed during the fabrication of the display substrate in an exemplary embodiment of this disclosure;

[0035] Figure 10B This is a schematic diagram of the structure after the first portion of the dielectric layer is formed during the fabrication of the display substrate in an exemplary embodiment of this disclosure;

[0036] Figure 10C This is a schematic diagram of the structure after the second electrode layer is formed during the fabrication of the display substrate in an exemplary embodiment of this disclosure;

[0037] Figure 10D This is a schematic diagram of the structure after the simulation unit is formed during the fabrication of the display substrate in an exemplary embodiment of this disclosure;

[0038] Figure 10E This is a schematic diagram of the structure after the reference unit is formed during the fabrication of the display substrate in an exemplary embodiment of this disclosure;

[0039] Figure 11A This is a three-dimensional structural diagram of the reference unit in an exemplary embodiment of this disclosure;

[0040] Figure 11B This is a three-dimensional structural diagram of the simulation unit in an exemplary embodiment of this disclosure. Detailed Implementation

[0041] Several embodiments are described herein, but this description is exemplary and not restrictive, and many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the accompanying drawings and discussed in exemplary embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with or in lieu of any other feature or element in any other embodiment.

[0042] In describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to a specific order of steps to the extent that it does not depend on this specific order. Other sequences of steps are possible, as will be understood by those skilled in the art. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Furthermore, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders may be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0043] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0044] In the exemplary embodiments disclosed herein, ordinal numbers such as "first," "second," or "third" are provided to avoid confusion of constituent elements, rather than to limit in terms of quantity.

[0045] In the exemplary embodiments of this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," or "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to has a specific orientation, or is constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0046] In the exemplary embodiments disclosed herein, unless otherwise expressly specified and limited, the terms "installed," "connected," or "linked" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of the above terms in this disclosure based on the actual circumstances.

[0047] In this specification, a transistor is a device comprising at least three terminals: a gate electrode (also called a gate or control electrode), a drain electrode (also called a drain terminal, drain region, or drain), and a source electrode (also called a source terminal, source region, or source). A transistor has a channel region between the drain and source electrodes, and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0048] In this specification, to distinguish the two terminals of a transistor other than the control terminal, one terminal is directly described as the first terminal and the other as the second terminal. The first terminal can be the drain electrode and the second terminal can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0049] The transistors used in this disclosure can all be thin-film transistors (TFTs), field-effect transistors (FETs), or other devices with similar characteristics. For example, the thin-film transistors used in this disclosure can include, but are not limited to, oxide TFTs or low-temperature polysilicon TFTs (LTPS TFTs). For example, the thin-film transistor can be a bottom-gate structure thin-film transistor or a top-gate structure thin-film transistor, as long as it can achieve the switching function. Here, this disclosure does not limit this aspect.

[0050] In the embodiments of this disclosure, the use of terms such as "about," "approximately," or "approximately" refers to situations that do not strictly define limits and allow for process and measurement errors. For example, in this disclosure, "approximately" may mean a numerical difference of 10% or 5%, or it may represent one or more acceptable standard deviations for a particular value as determined by a person skilled in the art.

[0051] In the embodiments of this disclosure, the terms "stacked sequentially" and "layered sequentially" may refer to multiple film layers being stacked in one direction, but do not necessarily mean that these film layers are necessarily bonded together in pairs.

[0052] In the embodiments of this disclosure, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures through the same patterning process. This patterning process may include multiple exposure, development, or etching processes. The patterns can be continuous or discontinuous, and may be at different heights or have different thicknesses. Their materials can be the same or different. For example, the precursors forming multiple structures in a same-layer arrangement may be made of the same material, while the final materials may be the same or different.

[0053] In this disclosure, the use of “applies to,” “is configured to,” or “is set to” implies an open and inclusive language that does not exclude devices that are applicable to, configured to, or set to perform additional tasks or steps.

[0054] In the embodiments of this disclosure, the expressions "on," "formed on," "disposed on," or similar expressions can indicate that one layer is directly formed or disposed on another layer, or that one layer is indirectly formed or disposed on another layer, i.e., there are other layers between the two layers. In this document, unless otherwise stated, the term "located on the same layer" means that two layers, components, members, elements, or portions can be formed by the same patterning process, and that these two layers, components, members, elements, or portions are generally formed of the same material. In this document, unless otherwise stated, the expression "patterning process" generally includes steps such as photoresist coating, exposure, development, etching, and photoresist stripping. The expression "one-time patterning process" refers to a process of forming patterned layers, components, members, etc., using a single photomask.

[0055] With the development of display technology, full-screen or narrow-bezel products, with their large screen-to-body ratio and ultra-narrow bezels, have gradually become the development trend of display products. For products such as smart terminals, sensors such as camera sensors or fingerprint sensors are usually included. To reduce screen bezels and increase screen-to-body ratio, many display products use an AA Hole design, that is, an opening design is set in the active area (AA), allowing sensors such as cameras to be placed in the opening (Hole) area of ​​the display area AA. Since organic light-emitting diode (OLED) displays use an organic light-emitting material that emits light independently, openings in the screen can easily create channels for water and oxygen intrusion into the light-emitting material layer, potentially leading to display failure. Therefore, in the manufacturing process, it is necessary to consider how to prevent external water and oxygen from intruding into the display area to avoid damaging the organic light-emitting material and affecting the display.

[0056] Currently, to address the issue of water and oxygen intrusion, undercut structures, such as isolation trenches and isolation pillars, are typically designed into the display substrate to block the channels for water and oxygen intrusion from the external environment, thus preventing encapsulation defects. However, when the undercut depth is too small or even absent, the encapsulation film formed during the Chemical Vapor Deposition (CVD) film deposition stage cannot achieve the desired encapsulation effect, and the encapsulation film layer in the edge areas is prone to peeling, resulting in the risk of Growing Dark Spot (GDS) defects. Conversely, when the undercut depth is too large, after CVD film deposition, the top metal film layer of the undercut structure will experience significant stress under external stress, making it prone to cracking, thus still resulting in the risk of GDS defects. Therefore, the undercut size significantly affects the reliability and yield of display products. Therefore, monitoring the side etching dimensions and avoiding problems such as excessively small or large side etching dimensions during the side etching process is crucial for improving product yield and preventing product reliability risks.

[0057] An exemplary embodiment of this disclosure provides a display substrate, which may include a substrate and may include a display area and a non-display area located around the display area. The non-display area may include at least one Test Element Group (TEG), which may include a reference unit and a simulation unit. Both the reference unit and the simulation unit may include a first electrode layer, a dielectric layer, and a second electrode layer sequentially stacked on the substrate. In a first direction parallel to the substrate, the second electrode layer has opposing first and second side surfaces. The dielectric layer of the reference unit protrudes or is flush with the first and second side surfaces of the second electrode layer of the reference unit in the first direction. A portion of the dielectric layer of the simulation unit is recessed in the first direction relative to the first and second side surfaces of the second electrode layer of the simulation unit to form a simulation groove. The size of the simulation groove is determined based on the capacitance value between the first and second electrode layers of the reference unit and the capacitance difference between the capacitance values ​​between the first and second electrode layers of the simulation unit.

[0058] Thus, by setting reference units and analog units in the non-display area, each reference unit and analog unit includes a first electrode layer, a dielectric layer, and a second electrode layer sequentially stacked on the substrate. During the fabrication of the display substrate, both the reference unit and the analog unit can form a capacitor (using the first and second electrode layers as the two plates of the capacitor, and the dielectric layer between the first and second electrode layers as the dielectric). The dielectric layer of the reference unit protrudes or is flush with the first and second sides of the second electrode layer in a first direction, while a portion of the dielectric layer of the analog unit is recessed in the first direction compared to the first and second sides of the second electrode layer of the analog unit, forming a simulated groove. The size of the simulated groove in the analog unit can then be determined based on the capacitance difference between the capacitance values ​​of the reference unit and the analog unit. Therefore, the display substrate can be monitored during the etching process, and the structure of the analog unit design on the display substrate can be monitored. This avoids problems such as excessively small or large dimensions during etching, thereby reducing defects such as cracks and peeling, and improving product yield.

[0059] In some exemplary embodiments, the simulated grooves can be formed using an undercut process. Here, the structure of the simulated cell design can refer to a structure with grooves formed by the undercut process, such as an isolation groove or an isolation pillar.

[0060] In some exemplary embodiments, the dielectric layer may include: a first portion having a first thickness and a second portion having a second thickness located around the first portion, the first portion and the second portion being disposed in the same layer, the first thickness being greater than the second thickness, the thickness being a dimension in a second direction, the second direction being perpendicular to the first direction; wherein, the second portion of the reference unit is convex or flush with the first side and the second side of the second electrode layer of the reference unit in the first direction; the second portion of the simulation unit is recessed in the first direction with respect to the first side and the second side of the second electrode layer of the simulation unit.

[0061] In some exemplary embodiments, the second part of the reference unit has a larger dimension in the first direction than the second part of the simulation unit in the first direction; the first part of the reference unit has the same dimension in the first direction as the first part of the simulation unit in the first direction; and the area of ​​the second electrode layer and the first electrode layer of the reference unit facing each other in the second direction is the same as the area of ​​the second electrode layer and the first electrode layer of the simulation unit facing each other in the second direction.

[0062] In some exemplary embodiments, the size of the second part of the reference unit in the first direction is greater than the size of the second part of the analog unit in the first direction; the size of the first part of the reference unit in the first direction is the same as the size of the first part of the analog unit in the first direction; the size of the first electrode layer of the reference unit in the first direction is the same as the size of the first electrode layer of the analog unit in the first direction, and the size of the second electrode layer of the reference unit in the first direction is the same as the size of the second electrode layer of the analog unit in the first direction.

[0063] In some exemplary embodiments, the first part and the second part are formed by two patterning processes. The first part is a multi-layer inorganic insulating film layer, and the second part is a single-layer inorganic insulating film layer.

[0064] In some exemplary embodiments, the size of the first part in the first direction is smaller than the size of the second electrode layer in the first direction, and the size of the second electrode layer in the first direction is smaller than the size of the first electrode layer in the first direction.

[0065] In some exemplary embodiments, the orthographic projection of the second electrode layer on the substrate falls within the edge of the orthographic projection of the first electrode layer on the substrate.

[0066] In some exemplary embodiments, the cross-sectional shape of the second electrode layer is "L-shaped".

[0067] Figure 1 This is a schematic plan view of the display substrate in the exemplary embodiments of the present disclosure. As Figure 1As shown, in some exemplary embodiments, the display substrate may include: a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA may include: a bonding area BD located on one side of the display area AA and close to the display area AA, a test area TS located on the side of the bonding area BD away from the display area AA, and a border area BK located on other sides of the display area AA. The display area AA may include: a display area 10, a hole area 20, and a barrier area 30 located between the display area 10 and the hole area 20. The display area 10 is configured to display (dynamic or static) images, and the display area 10 may include at least a plurality of regularly arranged sub-pixels Pxij, where i and j can be natural numbers. Each sub-pixel may include a pixel driving circuit and a light-emitting unit connected to the pixel driving circuit. The display area 10 may at least partially surround the barrier area 30. The hole area 20 may have a certain transmittance and may have a display function. The barrier area 30 may at least partially surround the opening area 20. The barrier area 30 may include multiple isolation grooves (not shown in the figure), which are configured to block the organic light-emitting layer, ensuring that water and oxygen cannot enter the light-emitting structure layer. The position of the opening area 20 may correspond to the position of the optical device (not shown in the figure). The opening area 20 is configured to display images and transmit light, and the transmitted light can be received by the optical device. For example, the optical device may be an optical sensor such as a camera device or a fingerprint recognition device. In practical applications, the opening area 20 may also be referred to as the sensor corresponding area, the under-display camera display area, or the light-transmitting display area, etc.

[0068] In some exemplary embodiments, the light transmittance of the aperture region 20 is higher than that of the display region 10. Light transmittance refers to the ability of light to pass through a medium, and is the percentage of luminous flux passing through a transparent or translucent body relative to the incident luminous flux. Thus, since the position of the aperture region 20 can correspond to the position of the sensor, there is an overlap between the sensor's orthographic projection on the display substrate and the aperture region, allowing more light to pass through the display substrate and be received by the sensor. For example, the phrase "an overlap between the sensor's orthographic projection on the display substrate and the aperture region 20" can mean that a portion of the sensor's orthographic projection on the display substrate is located within the aperture region 20, or that the entire orthographic projection of the sensor on the display substrate is located within the aperture region 20, or that the sensor's photosensitive window's orthographic projection on the display substrate is located within the aperture region 20, etc. This disclosure does not limit this aspect.

[0069] In some exemplary embodiments, the shape of the opening area 20 in a plane parallel to the display substrate can be any one or more of the following: square, rectangle, polygon, circle, ellipse, semicircle, or pentagon, etc. For example, the shape of the display area AA of the display substrate can be a rectangle (such as a rounded rectangle), and the shape of the opening area 20 can be a circle. Of course, in addition to the exemplary shapes listed above, the shape of the opening area can also be other regular or irregular shapes, and this disclosure does not limit this. The descriptions of square, rectangle, polygon, circle, or ellipse used in the exemplary embodiments of this disclosure are not strictly defined, and can be approximately square, rectangular, polygonal, circular, or elliptical, etc., and may have some small deformations due to tolerances, and may have chamfered corners, curved edges, and other deformations, etc.

[0070] In some exemplary embodiments, the position of the aperture region 20 within the display area AA of the display substrate is not limited. The aperture region 20 may be located at the upper part, lower part, or edge of the display area AA. For example, the aperture region 20 may be located at the top center of the display area AA, and the blocking area 30 may surround the aperture region 20, while the display area 10 may surround the aperture region 20. Alternatively, the aperture region 20 may be located at other positions, such as the upper left or upper right corner of the display area, and the display area 10 may surround at least one side of the aperture region 20 (e.g., one side, the upper and lower sides, or the left and right sides). This disclosure does not limit the scope of the embodiments.

[0071] Figure 2 This is a schematic diagram of the structure of the display area in the display substrate in an exemplary embodiment of the present disclosure. Figure 1 A schematic diagram of the cross-sectional structure along line A-A'. Figure 2As shown, in some exemplary embodiments, the display substrate may include a substrate 101. On a plane perpendicular to the display substrate, the main structure of the display area 10 may include: a driving structure layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. The driving structure layer 102 may include a plurality of transistors 210 and a storage capacitor 211 disposed on the substrate 101 constituting a pixel driving circuit. The light-emitting structure layer 103 may include an anode 301 connected to the drain electrode of the transistor, a pixel definition layer 302 for defining a pixel opening region, an organic light-emitting layer 303 formed in the pixel opening region, and a cathode 304 formed on the organic light-emitting layer. Exemplarily, the organic light-emitting layer 303 may include a light-emitting layer (EML) and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). The encapsulation structure layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. For example, the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403 to prevent external moisture from entering the light-emitting structure layer 103. In some other exemplary embodiments, the display area 10 may also include other film layers, such as a touch structure layer. This disclosure does not limit this aspect. Figure 2 The diagram uses a transistor and a storage capacitor from a pixel driving circuit as an example.

[0072] Figure 3 This is a schematic diagram of a partial planar structure of the display substrate in an exemplary embodiment of this disclosure. Figure 1 A schematic diagram of the planar structure of region Q in the middle. (See diagram below.) Figure 3As shown, in some exemplary embodiments, the display substrate may include a display area AA and a non-display area NA located around the display area AA. The non-display area NA may include a bonding area BD near the display area AA and a test area TS located on the side of the bonding area BD away from the display area AA. The test area TS may include at least one test unit group, and each test unit group may include a reference unit 40 and a simulation unit 50. The simulation unit 50 has a simulation groove Udc, and the size of the simulation groove Udc can be determined based on the capacitance difference between the capacitance value of the reference unit 40 and the capacitance value of the simulation unit 50. Thus, during the fabrication of the display substrate, the size of the simulation groove Udc of the simulation unit can be accurately determined by detecting the capacitance difference between the capacitance value of the reference unit and the capacitance value of the simulation unit. Therefore, the etching size of the simulation unit design structure of the display substrate can be monitored during the etching process, which can avoid problems such as excessively small or large etching sizes during the etching process, reduce the occurrence of defects such as cracks and peeling, and improve product yield. Figure 3 The illustration uses the test unit group located in the bonding area BD on the side far from the display area AA as an example. In practical applications, other implementation methods can be used, such as setting it in other positions on the display substrate, like the bezel area BK. Here, this disclosure does not limit this.

[0073] In some exemplary embodiments, the simulated groove Udc of the simulated cell can be formed by a side etching process. Here, the size of the simulated groove Udc of the simulated cell can refer to the etching depth of the simulated groove Udc, that is, the size of the simulated groove Udc in the first direction DR1.

[0074] In some exemplary embodiments, such as Figure 3 As shown, the test area TS may further include: a first test pad pair 44 connected to the reference unit 40 and a second test pad pair 54 connected to the simulation unit 50. Each test pad pair may include: a first pad connected to the first electrode layer and a second pad connected to the second electrode layer. Thus, during the testing of the display substrate, the test probes of the test equipment can be connected to the test pad pairs. By providing a voltage signal through the test equipment, the capacitance values ​​of the reference unit 40 and the simulation unit 50 can be detected. The size of the simulated recess Udc can then be determined based on the capacitance difference between the reference unit 40 and the simulation unit 50.

[0075] In some exemplary embodiments, such as Figure 3As shown, the test area TS may further include: multiple test unit groups, which may include at least one of the following: at least a first test unit group, at least one second test unit group, and at least one third test unit group. The first test unit group may include: a first reference unit 40-1 and a first simulation unit 50-1; the second test unit group may include: a second reference unit 40-2 and a second simulation unit 50-2; and the third test unit group may include: a third reference unit 40-3 and a third simulation unit 50-3. The dimensions of the first reference unit 40-1, the second reference unit 40-2, and the third reference unit 40-3 may be different. Similarly, the dimensions of the first simulation unit 50-1, the second simulation unit 50-2, and the third simulation unit 50-3 may be different. Figure 3 The example setup uses two first test unit groups, two second test unit groups, and two third test unit groups.

[0076] In some exemplary embodiments, such as Figure 3 As shown, the test area TS may further include a circuit unit 90, such as a test unit, a driver integrated circuit (IC), or a flexible printed circuit (FPC), etc., and the circuit unit 90 is bonded to the bonding area BD. For example, the circuit unit 90 can be an FPC, and the bonding area BD is configured to be bonded to the FPC, allowing signals to be provided to the signal lines of the display area AA through the bonded FPC to drive the display area AA to display.

[0077] Figure 4 This is a schematic cross-sectional view of the analog unit in the display substrate according to an exemplary embodiment of this disclosure. Figure 4As shown, in some exemplary embodiments, in a plane perpendicular to the display substrate, the simulation unit 50 may include: a first conductive layer 51 (as the first electrode layer of the simulation unit 50), a second conductive layer 53 (as the second electrode layer of the simulation unit 50), and a first dielectric layer 52 (as the dielectric layer of the simulation unit 50 located between the first conductive layer 51 and the second conductive layer 53) located between the first conductive layer 51 and the second conductive layer 53. In the first direction DR1, the second conductive layer 53 (as the second electrode layer of the simulation unit 50) has opposing first side surfaces 531 and second side surfaces 532. The first dielectric layer 52 of the simulation unit 50 may be recessed in the first direction DR1 relative to the first side surface 531 and the second side surface 532 of the second conductive layer 53 to form a simulation groove Udc. The size Dp of the simulation groove Udc can be determined based on the capacitance value between the first electrode layer and the second electrode layer of the reference unit 40 and the capacitance difference between the capacitance values ​​between the first electrode layer and the second electrode layer of the simulation unit 50. For example, the size Dp of the simulated groove Udc in the simulation unit 50 can refer to the distance between one side of the first dielectric layer 52 and the first side 531 of the second conductive layer 53, or the distance between the other side of the first dielectric layer 52 and the second side 532 of the second conductive layer 53.

[0078] In some exemplary embodiments, such as Figure 4 As shown, the first dielectric layer 52 of the simulation unit 50 may include a first dielectric portion 521 with a first thickness (serving as a first part of the dielectric layer of the simulation unit) and a second dielectric portion 522 with a second thickness (serving as a second part of the dielectric layer of the simulation unit). The second dielectric portion 522 is located around the first dielectric portion 521. The first dielectric portion 521 (serving as a first part of the dielectric layer of the simulation unit) and the second dielectric portion 522 (serving as a second part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 are disposed in the same layer. The second dielectric portion 522 (serving as a second part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 is recessed inward in the first direction DR1 compared to the first side surface 531 and the second side surface 532 of the second conductive layer 53. The first thickness is greater than the second thickness, and the thickness is a dimensional feature in the second direction DR2. The second direction DR2 is perpendicular to the first direction DR1. The first direction DR1 may be a direction parallel to the substrate, and the second direction DR2 may be the thickness direction of the display substrate.

[0079] For example, such as Figure 4As shown, the dimension Dp of the simulation groove Udc in the simulation unit 50 can refer to the maximum distance between the surface of the second dielectric portion 522 (which is the second part of the dielectric layer of the simulation unit) away from the first dielectric portion 521 (which is the first part of the dielectric layer of the simulation unit) and the first side surface 531 of the second conductive layer 53, or the maximum distance between the surface of the second dielectric portion 522 away from the first dielectric portion 521 and the second side surface 532 of the second conductive layer 53.

[0080] In some exemplary embodiments, such as Figure 4 As shown, the first dielectric portion 521 (as the first part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 and the second dielectric portion 522 (as the second part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 are fabricated using a two-step patterning process.

[0081] In some exemplary embodiments, such as Figure 4 As shown, the first dielectric portion 521 (as the first part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 can be a multilayer inorganic insulating film layer, and the second dielectric portion 522 (as the second part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 can be a single-layer inorganic insulating film layer.

[0082] For example, the inorganic insulating film layer can be prepared using an inorganic insulating material, which can be at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON).

[0083] For example, the multilayer inorganic insulating film may include a first inorganic insulating film layer, a second inorganic insulating film layer, a third inorganic insulating film layer, and a fourth inorganic insulating film layer sequentially stacked along a direction away from the first conductive layer 51. For instance, the material of the first inorganic insulating film layer may be silicon nitride (SiNx), the material of the second inorganic insulating film layer may be silicon oxide (SiOx), the material of the third inorganic insulating film layer may be silicon nitride (SiNx), and the material of the fourth inorganic insulating film layer may be silicon nitride (SiNx). For example, the thickness of the first inorganic insulating film layer may be... (Å), the thickness of the second inorganic insulating film layer can be... (Å), the thickness of the third inorganic insulating film layer can be (Å), the thickness of the fourth inorganic insulating film layer can be... (angstrom).

[0084] In some exemplary embodiments, such as Figure 4As shown, the cross-sectional shape of the first dielectric portion 521 (which serves as the first part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 can be trapezoidal. The cross-sectional shape of the second dielectric portion 522 (which serves as the second part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 can be quadrilateral.

[0085] In some exemplary embodiments, such as Figure 4 As shown, the second conductive layer 53 (as the second electrode layer) of the simulation unit 50 protrudes toward the side away from the first conductive layer 51 (as the first electrode layer) of the simulation unit 50.

[0086] In some exemplary embodiments, such as Figure 4 As shown, the second dimension Lm2 of the first dielectric portion 521 (as the first part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 in the first direction DR1 is smaller than the first dimension Lm1 of the second conductive layer 53 (as the second electrode layer) of the simulation unit 50 in the first direction DR1, and the first dimension Lm1 of the second conductive layer 53 (as the second electrode layer) of the simulation unit 50 in the first direction DR1 is smaller than the fourth dimension Lm4 of the first conductive layer 51 (as the first electrode layer) of the simulation unit 50 in the first direction DR1.

[0087] In some exemplary embodiments, such as Figure 4 As shown, the third dimension Lm3 of the second dielectric portion 522 (which serves as the second part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 in the first direction DR1 is smaller than the difference between the first dimension Lm1 of the second conductive layer 53 (which serves as the second electrode layer) in the first direction DR1 of the simulation unit 50 and the second dimension Lm2 of the first dielectric portion 521 (which serves as the first part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 in the first direction DR1.

[0088] For example, the first dimension Lm1 of the second conductive layer 53 (as the second electrode layer) of the simulation unit 50 in the first direction DR1 can be approximately 10 μm (micrometers); the second dimension Lm2 of the first dielectric portion 521 (as the first part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 in the first direction DR1 can be approximately 6 μm; the third dimension Lm3 of the second dielectric portion 522 (as the second part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 in the first direction DR1 can be approximately 1.8 μm; and the fourth dimension Lm4 of the first conductive layer 51 (as the first electrode layer) of the simulation unit 50 in the first direction DR1 can be approximately 12.6 μm. The dimension Dp of the simulation groove Udc in the simulation unit 50 can be approximately 0.2 μm.

[0089] In some exemplary embodiments, such as Figure 4 As shown, the orthographic projection of the second conductive layer 53 (as the second electrode layer) of the simulation unit 50 onto the substrate falls within the edge of the orthographic projection of the first conductive layer 51 (as the first electrode layer) of the simulation unit 50 onto the substrate.

[0090] Figure 5 This is a schematic cross-sectional view of a reference unit in a display substrate according to an exemplary embodiment of this disclosure. Figure 5 As shown, in some exemplary embodiments, the reference unit 40 may include: a third conductive layer 41 (serving as the first electrode layer of the reference unit 40), a fourth conductive layer 43 (serving as the second electrode layer of the reference unit 40), and a second dielectric layer 42 (serving as the dielectric layer between the first electrode layer and the second electrode layer of the reference unit 40) located between the third conductive layer 41 and the fourth conductive layer 43. In the first direction DR1, the fourth conductive layer 43 (serving as the second electrode layer of the reference unit 40) has opposing first side surfaces 431 and second side surfaces 432. The second dielectric layer 42 of the reference unit 40 may protrude from or be flush with the first side surface 431 and the second side surface 432 of the fourth conductive layer 43 in the first direction DR1. Figure 5 The example shown is that the second dielectric layer 42 of the reference unit 40 protrudes relative to the first side 431 and the second side 432 of the fourth conductive layer 43.

[0091] In some exemplary embodiments, such as Figure 5 As shown, the second dielectric layer 42 of the reference unit 40 may include: a third dielectric portion 421 having a first thickness (serving as a first part of the dielectric layer of the reference unit 40) and a fourth dielectric portion 422 having a second thickness located around the third dielectric portion 421 (serving as a first part of the dielectric layer of the reference unit 40) and a fourth dielectric portion 422 having a second thickness (serving as a second part of the dielectric layer of the reference unit). The third dielectric portion 421 (serving as a first part of the dielectric layer of the reference unit) and the fourth dielectric portion 422 (serving as a second part of the dielectric layer of the reference unit) in the second dielectric layer 42 of the reference unit 40 are disposed in the same layer. The fourth dielectric portion 422 (serving as a second part of the dielectric layer of the reference unit) in the second dielectric layer 42 of the reference unit 40 protrudes or is flush with the first side surface 431 and the second side surface 432 of the fourth conductive layer 43 in the first direction DR1. The first thickness is greater than the second thickness, and the thickness is a dimensional feature in the second direction DR2. The second direction DR2 intersects the first direction DR1. The second direction DR2 may be the thickness direction of the display substrate. Here, Figure 5The example shown is that the fourth dielectric portion 422 in the second dielectric layer 42 of the reference unit 40 protrudes relative to the first side surface 431 and the second side surface 432 of the fourth conductive layer 43.

[0092] In some exemplary embodiments, such as Figure 5 As shown, the third dielectric portion 421 (as the first part of the dielectric layer of the reference unit 40) and the fourth dielectric portion 422 (as the second part of the dielectric layer of the reference unit 40) in the second dielectric layer 42 of the reference unit 40 are fabricated using a two-step patterning process.

[0093] In some exemplary embodiments, such as Figure 5 As shown, the third dielectric portion 421 (as the first part of the dielectric layer of the reference unit) in the second dielectric layer 42 of the reference unit 40 can be a multilayer inorganic insulating film layer, and the fourth dielectric portion 422 (as the second part of the dielectric layer of the reference unit) in the second dielectric layer 42 of the reference unit 40 can be a single-layer inorganic insulating film layer.

[0094] For example, the inorganic insulating film layer can be prepared using an inorganic insulating material, which can be at least one of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON).

[0095] For example, the multilayer inorganic insulating film may include a first inorganic insulating film layer, a second inorganic insulating film layer, a third inorganic insulating film layer, and a fourth inorganic insulating film layer sequentially stacked along a direction away from the third conductive layer 41. For instance, the material of the first inorganic insulating film layer may be silicon nitride (SiNx), the material of the second inorganic insulating film layer may be silicon oxide (SiOx), the material of the third inorganic insulating film layer may be silicon nitride (SiNx), and the material of the fourth inorganic insulating film layer may be silicon nitride (SiNx). For example, the thickness of the first inorganic insulating film layer may be... (Å), the thickness of the second inorganic insulating film layer can be... (Å), the thickness of the third inorganic insulating film layer can be (Å), the thickness of the fourth inorganic insulating film layer can be... (angstrom).

[0096] In some exemplary embodiments, such as Figure 5 As shown, the cross-sectional shape of the third dielectric portion 421 (which serves as the first part of the dielectric layer of the reference unit) in the second dielectric layer 42 of the reference unit 40 can be trapezoidal.

[0097] In some exemplary embodiments, such as Figure 5As shown, the fourth conductive layer 43 of the reference unit 40 (which serves as the second electrode layer of the reference unit 40) protrudes toward the side away from the third conductive layer 41 (which serves as the first electrode layer of the reference unit 40).

[0098] In some exemplary embodiments, such as Figure 5 As shown, the sixth dimension Lr2 of the third dielectric portion 421 in the second dielectric layer 42 of the reference unit 40 in the first direction DR1 is smaller than the fifth dimension Lr1 of the fourth conductive layer 43 (which serves as the second electrode layer of the reference unit 40) in the first direction DR1, and the fifth dimension Lr1 of the fourth conductive layer 43 (which serves as the second electrode layer of the reference unit 40) in the first direction DR1 is smaller than the eighth dimension Lr4 of the third conductive layer 41 (which serves as the first electrode layer of the reference unit 40) in the first direction DR1.

[0099] In some exemplary embodiments, such as Figure 5 As shown, the seventh dimension Lr3 of the fourth dielectric portion 422 (which serves as the second part of the dielectric layer of the reference unit 40) in the second dielectric layer 42 of the reference unit 40 in the first direction DR1 is greater than the difference between the fifth dimension Lr1 of the fourth conductive layer 43 (which serves as the second electrode layer of the reference unit 40) in the first direction DR1 and the sixth dimension Lr2 of the third dielectric portion 421 in the second dielectric layer 42 of the reference unit 40 in the first direction DR1.

[0100] For example, the fifth dimension Lr1 of the fourth conductive layer 43 of the reference unit 40 (as the second electrode layer of the reference unit 40) in the first direction DR1 can be about 10 μm (micrometers), the sixth dimension Lr2 of the third dielectric portion 421 in the second dielectric layer 42 of the reference unit 40 in the first direction DR1 can be about 6 μm, the seventh dimension Lr3 of the fourth dielectric portion 422 in the second dielectric layer 42 of the reference unit 40 (as the second part of the dielectric layer of the reference unit 40) in the first direction DR1 can be greater than 2 μm, and the eighth dimension Lr4 of the third conductive layer 41 of the reference unit 40 (as the first electrode layer of the reference unit 40) in the first direction DR1 can be about 12.6 μm.

[0101] In some exemplary embodiments, such as Figure 5 As shown, the orthographic projection of the fourth conductive layer 43 of the reference unit 40 (as the second electrode layer of the reference unit 40) onto the substrate falls within the edge of the orthographic projection of the third conductive layer 41 of the reference unit 40 (as the first electrode layer of the reference unit 40) onto the substrate.

[0102] In some exemplary embodiments, on a plane perpendicular to the display substrate, such as Figure 5As shown, the cross-sectional shape of the fourth conductive layer 43 (as the second electrode layer of the reference unit 40) of the reference unit 40 is in the shape of a "ji" character.

[0103] In some exemplary embodiments, in a plane parallel to the display substrate, the fourth conductive layers 43 (as the second electrode layers of the reference units 40) of multiple reference units 40 may be continuously arranged in the shape of a "bow" character.

[0104] In some exemplary embodiments, as Figure 4 and Figure 5 shown, the seventh dimension Lr3 of the fourth dielectric portion 422 (as the second part of the dielectric layer of the reference unit 40) in the second dielectric layer 42 of the reference unit 40 in the first direction DR1 is greater than the third dimension Lm3 of the second dielectric portion 522 (as the second part of the dielectric layer of the simulation unit 50) in the first dielectric layer 52 of the simulation unit 50 in the first direction DR1.

[0105] In some exemplary embodiments, as Figure 4 and Figure 5 shown, the dimension of the third dielectric portion 421 (as the first part of the dielectric layer of the reference unit 40) in the second dielectric layer 42 of the reference unit 40 in the first direction DR1 is the same as the dimension of the first dielectric portion 521 (as the first part of the dielectric layer of the simulation unit 50) in the first dielectric layer 52 of the simulation unit 50 in the first direction DR1.

[0106] In some exemplary embodiments, as Figure 4 and Figure 5 shown, the eighth dimension Lr4 of the third conductive layer 41 (as the first electrode layer of the reference unit 40) of the reference unit 40 in the first direction DR1 and the fourth dimension Lm4 of the first conductive layer 51 (as the first electrode layer of the simulation unit 50) of the simulation unit 50 in the first direction DR1.

[0107] In some exemplary embodiments, as Figure 4 and Figure 5 shown, the fifth dimension Lr1 of the fourth conductive layer 43 (as the second electrode layer of the reference unit 40) of the reference unit 40 in the first direction DR1 is the same as the first dimension Lm1 of the second conductive layer 53 (as the second electrode layer of the simulation unit 50) of the simulation unit 50 in the first direction DR1.

[0108] Figure 6 This is a schematic cross-sectional structure diagram of the display area and the non-display area in the display substrate in the exemplary embodiments of the present disclosure, which is the cross-sectional structure diagram of C-C' in Figure 1 In some exemplary embodiments, as Figure 6As shown, the display substrate may include: a substrate 101. In a plane perpendicular to the display substrate, the display area AA may include: a driving structure layer 102 disposed on the substrate 101 and a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101. The driving structure layer includes a pixel driving circuit, which includes multiple transistors and a storage capacitor. The light-emitting structure layer includes a light-emitting unit connected to the pixel driving circuit. The light-emitting unit includes an anode, an organic light-emitting layer, and a cathode sequentially stacked along the direction away from the substrate. In a plane perpendicular to the display substrate, the driving structure layer 102 may include: a first insulating layer, an active layer, a second insulating layer, a first gate metal layer (gate1), a third insulating layer, a second gate metal layer (gate2), a fourth insulating layer, a first source / drain metal layer (SD1), a fifth insulating layer, and a second source / drain metal layer (SD2) sequentially stacked on the substrate 101. For example, the first gate metal layer (gate1) may include: the gate electrode G of the transistor 210 in the pixel driving circuit and the first plate of the storage capacitor 211; the second gate metal layer (gate2) may include: the second plate of the storage capacitor 211; the first source-drain metal layer (SD1) may include: the source electrode S and the drain electrode D of the transistor 210 in the pixel driving circuit; and the second source-drain metal layer (SD2) may include: a connecting electrode, which is connected to the source electrode S and also connected to the anode in the light-emitting unit.

[0109] In some exemplary embodiments, such as Figure 6As shown, the non-display area NA may include at least one test unit group, each test unit group may include a reference unit 40 and a simulation unit 50. The simulation unit 50 may include a first conductive layer 51 (as the first electrode layer of the simulation unit 50), a second conductive layer 53 (as the second electrode layer of the simulation unit 50), and a first dielectric layer 52 (as the dielectric layer of the simulation unit 50 located between the first conductive layer 51 and the second conductive layer 53) between the first conductive layer 51 and the second conductive layer 53. The first conductive layer 51 (as the first electrode layer of the simulation unit 50) may be disposed on the same layer as the gate electrode G of the transistor in the pixel driving circuit, and / or, the first conductive layer 51 (as the first electrode layer of the simulation unit 50) may be disposed on the same layer as the first plate of the storage capacitor 211 in the pixel driving circuit; the second conductive layer 53 (as the second electrode layer of the simulation unit 50) may be disposed on the same layer as the source electrode S and drain electrode D of the transistor in the pixel driving circuit, and / or, the second conductive layer 53 (as the second electrode layer of the simulation unit 50) may be disposed on the same layer as the connection electrode in the pixel driving circuit. The reference unit 40 may include: a third conductive layer 41 (serving as the first electrode layer of the reference unit 40), a fourth conductive layer 43 (serving as the second electrode layer of the reference unit 40), and a second dielectric layer 42 (serving as the dielectric layer between the first electrode layer and the second electrode layer of the reference unit 40) located between the third conductive layer 41 and the fourth conductive layer 43. The third conductive layer 41 (serving as the first electrode layer of the reference unit 40) may be disposed on the same layer as the gate electrode G of the transistor in the pixel driving circuit, and / or, the third conductive layer 41 (serving as the first electrode layer of the reference unit 40) may be disposed on the same layer as the first electrode plate of the storage capacitor 211 in the pixel driving circuit; the fourth conductive layer 43 (serving as the second electrode layer of the reference unit 40) may be disposed on the same layer as the source electrode S and drain electrode D of the transistor in the pixel driving circuit, and / or, the fourth conductive layer 43 (serving as the second electrode layer of the reference unit 40) may be disposed on the same layer as the connection electrode in the pixel driving circuit, and / or, on the same layer as the data signal line in the pixel driving circuit. Thus, during the fabrication of the display substrate, the structure of the reference unit 40 and the analog unit 50 is formed simultaneously with the formation of the TFT array, thereby simplifying the fabrication process. Here, for ease of explanation... Figure 6 Only the structure and positional relationship of the substrate 101, a reference unit 40, and a simulation unit 50 in the display area AA and the non-display area NA are shown, while some other structures of the display substrate are omitted.

[0110] In some exemplary embodiments, the first conductive layer 51 (as the first electrode layer of the simulation unit 50) and the third conductive layer 41 (as the first electrode layer of the reference unit 40) are disposed in the same layer and with the same material.

[0111] In some exemplary embodiments, the second conductive layer 53 (as the second electrode layer of the simulation unit 50) and the fourth conductive layer 43 (as the second electrode layer of the reference unit 40) are disposed in the same layer and with the same material.

[0112] Figure 7 This is a schematic diagram of the planar structure of the test unit group in the display substrate according to an exemplary embodiment of this disclosure. Figure 3 A schematic diagram of the planar structure of a test unit group. In some exemplary embodiments, such as Figure 7 As shown, in a plane parallel to the display substrate, the test unit group may include: a main area 501 and dummy areas 502 located on both sides of the main area 501. The main area 501 may include: a plurality of spaced-apart simulation units 50, with a simulation isolation trench (including a simulation groove Udc of one simulation unit 50 and a simulation groove Udc of another simulation unit 50) formed between adjacent simulation units 50. The simulation unit 50 may include: a first conductive layer 51 (as a first electrode layer), a second conductive layer 53 (as a second electrode layer), and a first dielectric layer 52 located between the first conductive layer 51 and the second conductive layer 53 (as the dielectric layer of the simulation unit 50 located between the first electrode layer and the second electrode layer). The dummy areas 502 may include: a plurality of spaced-apart dummy units 55, and the structure of the dummy units 55 may be the same as that of the reference unit 40. In this way, etching uniformity can be improved. Figure 7 The example shown uses 5 reference units 50 consecutively.

[0113] In some exemplary embodiments, the number of the plurality of analog units 50 spaced apart in the main body region 501 can be 5, 25, 125, etc. Of course, it can also be other values ​​greater than or equal to 2. This disclosure does not limit this to any particular value.

[0114] In some exemplary embodiments, such as Figure 7 As shown, the size W of the test unit group on the third-direction DR3 can be approximately 200 micrometers. The opening size L of the simulation isolation trench formed between adjacent simulation units 50 in the test unit group can be approximately 6 micrometers. The size of the groove formed between the dielectric layers of adjacent simulation units 50 in the test unit group can be approximately 8.4 micrometers.

[0115] In other exemplary embodiments, within a plane parallel to the display substrate, the test unit group may include a main region 501 and dummy regions 502 located on both sides of the main region 501. The main region 501 may include a plurality of reference units 40 continuously disposed. Each reference unit 40 may include a third conductive layer 41 (serving as a first electrode layer), a fourth conductive layer 43 (serving as a second electrode layer), and a second dielectric layer 42 located between the third conductive layer 41 and the fourth conductive layer 43 (serving as a dielectric layer between the first and second electrode layers for the reference unit). The dummy regions 502 may include a plurality of spaced-apart dummy units 55, the dummy units 55 having the same structure as the reference units 40D. This improves etching uniformity.

[0116] Figure 8 This is a schematic diagram of the planar structure of the second electrode layer of the test unit group in the display substrate in an exemplary embodiment of this disclosure. Figure 7 A schematic diagram of the planar structure of the second electrode layer of a test unit group. In some exemplary embodiments, in a plane parallel to the display substrate, such as... Figure 8 As shown, the test unit group may include a plurality of consecutively arranged simulation units 50, and the shape of the second conductive layer 53 (as a second electrode layer) of the plurality of consecutively arranged simulation units 50 may be "bow" shaped. The ratio H1 / H2 between the width H1 (dimension in the first direction DR1) of the second conductive layer 53 (as a second electrode layer) of one simulation unit 50 and the spacing H2 (dimension in the first direction DR1) between two adjacent simulation units 50 can be approximately 10 / 6. For example, the width H1 of the second conductive layer 53 (as a second electrode layer) of one simulation unit 50 may be set to 10 micrometers, and the spacing H2 between two adjacent simulation units 50 can be set to 6 micrometers.

[0117] Figure 9 This is a schematic diagram of the barrier region in the display substrate according to an exemplary embodiment of the present disclosure. Figure 1 A schematic diagram of the cross-sectional structure between points B and B'. Figure 9 As shown, in some exemplary embodiments, the display area AA may include: a display area 10, a hole area 20, and a barrier area 30 located between the display area 10 and the hole area 20. The display substrate may include a substrate 101. On a plane perpendicular to the display substrate, the barrier area 30 may include: a plurality of isolation trenches 60 disposed on the substrate 101. The isolation trenches 60 are configured to block the organic light-emitting layer, ensuring that water and oxygen cannot enter the light-emitting structure layer. Thus, the test unit group is configured to determine the size of the isolation trenches 60 by detecting the size of the simulated grooves in the simulation unit. Here, for ease of explanation, Figure 9 Only the structure and positional relationship of the substrate 10 and multiple isolation pillars 60 in the barrier region 30 are shown, while some other structures of the display substrate are omitted.

[0118] In some exemplary embodiments, such as Figure 9 As shown, the isolation groove 60 includes a groove 601 and a retaining edge 602 disposed on the side of the groove 601 away from the substrate 101. In a plane perpendicular to the display substrate, the barrier region 30 includes a first structural layer 603 and a second structural layer 606 stacked sequentially in a direction away from the substrate 101. The groove 60 penetrates the second structural layer 606 and exposes at least a portion of the surface of the first structural layer 603. The retaining edge 602 is disposed on the surface of the second structural layer 606 away from the substrate 101, and a portion of the retaining edge 602 extends in a direction parallel to the substrate 101 and protrudes relative to the sidewall of the groove 60.

[0119] In some exemplary embodiments, such as Figure 9 As shown, the retaining edge 602 has an opening, and the opening size of the retaining edge 602 is smaller than the opening size of the groove 601.

[0120] In some exemplary embodiments, the groove 601 and the simulated groove Udc in the simulation unit 50 are formed using the same patterning process. For example, the groove 601 can be formed using a side etching process.

[0121] For example, the first structural layer 603 may include a metal layer, and the groove 60 penetrates the second structural layer 606 and exposes at least a portion of the surface of the metal layer.

[0122] For example, in the first direction DR1, the second structural layer 606 may include: a third dielectric layer 605 disposed around the groove 601 and a fourth dielectric layer 604 disposed on the side of the third dielectric layer 605 away from the groove 601, wherein the third dielectric layer 605 and the fourth dielectric layer 604 are disposed in the same layer. The dimension of the third dielectric layer 605 in the second direction DR2 is smaller than the dimension of the fourth dielectric layer 604 in the second direction DR2. The third dielectric layer 605 and the fourth dielectric layer 604 may be manufactured using a two-step patterning process. The third dielectric layer 605 may be a single-layer inorganic insulating film layer, and the fourth dielectric layer 604 may be a multi-layer inorganic insulating film layer. The material of the inorganic insulating film layer is an inorganic material. The third dielectric layer 605 may also be referred to as a planarization layer, and the fourth dielectric layer 604 may also be referred to as a composite insulating layer.

[0123] In some exemplary embodiments, such as Figure 9As shown, the groove bottom dimension of the groove 601 can refer to: the minimum distance between the first and second sidewalls of the third dielectric layer 605 opposite to each other in the first direction DR1 (denoted as the first distance d1), or the minimum distance between the first sidewall of the third dielectric layer 605 and the second sidewall of the fourth dielectric layer 604 opposite to each other in the first direction DR1 (denoted as the fourth distance d4), or the minimum distance between the first sidewall of the fourth dielectric layer 604 and the second sidewall of the third dielectric layer 605 opposite to each other in the first direction DR1 (denoted as the sixth distance d6 (not shown)). The first distance d1 is less than the fourth distance d4. The first distance d1 is less than the sixth distance d6. Exemplarily, the first distance d1 can be approximately 5.5 micrometers to 6.5 micrometers, for example, approximately 6 micrometers. Exemplarily, the fourth distance d4 can be approximately 5.7 micrometers to 6.7 micrometers, for example, approximately 6.2 micrometers.

[0124] In some exemplary embodiments, such as Figure 9 As shown, the opening size of the groove 601 can refer to: the maximum distance between the first and second sidewalls of the third dielectric layer 605 opposite to each other in the first direction DR1 (denoted as the second distance d2), or the maximum distance between the first sidewall of the third dielectric layer 605 and the second sidewall of the fourth dielectric layer 604 opposite to each other in the first direction DR1 (denoted as the seventh distance d7 (not shown)), or the maximum distance between the first sidewall of the fourth dielectric layer 604 and the second sidewall of the third dielectric layer 605 opposite to each other in the first direction DR1 (denoted as the eighth distance d8 (not shown)). The second distance d2 is less than the seventh distance d7. The second distance d2 is less than the eighth distance d8. Exemplarily, the second distance d2 can be from 7.9 micrometers to 8.9 micrometers, for example, it can be about 8.4 micrometers.

[0125] In some exemplary embodiments, such as Figure 9 As shown, the spacing between two adjacent grooves 601 can refer to the minimum distance (denoted as the third distance d3) between the second sidewall of the third dielectric layer 605 of the first groove 601 and the first sidewall of the third dielectric layer 605 of the second groove 601, which are opposite to each other in the first direction DR1. For example, the third distance d3 can be from 9.5 micrometers to 10.5 micrometers, for example, it can be about 10 micrometers.

[0126] In some exemplary embodiments, such as Figure 9 As shown, the opening size of the isolation groove 60 can refer to the distance between the sides of the flange 602 opposite to DR1 in the first direction.

[0127] In some exemplary embodiments, the isolation groove 60 and the simulation unit 50 are disposed in the same layer and made of the same material, and are formed by the same preparation process.

[0128] In some exemplary embodiments, in a plane perpendicular to the display substrate, the display area 10 may include: a driving structure layer 102 disposed on the substrate 101 and a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the substrate 101. The driving structure layer 102 may include a pixel driving circuit, which may include a plurality of transistors and a storage capacitor. The light-emitting structure layer may include a plurality of light-emitting units, which may include an anode, an organic light-emitting layer and a cathode sequentially stacked along the direction away from the substrate 101. In a plane perpendicular to the display substrate, the driving structure layer 102 may include: a first insulating layer, an active layer, a second insulating layer, a first gate metal (gate1) layer, a third insulating layer, a second gate metal (gate2) layer, a fourth insulating layer, a first source / drain metal (SD1) layer, a fifth insulating layer and a second source / drain metal (SD2) layer sequentially stacked on the substrate 101. For example, the first gate metal layer (gate1) may include: the gate electrode G of the transistor 210 in the pixel driving circuit and the first plate of the storage capacitor 211, and the scan signal line is connected to the gate electrode G. The second gate metal layer (gate2) may include: the second plate of the storage capacitor 211. The first source-drain metal layer (SD1) may include: the source electrode S and the drain electrode D of the transistor 210 in the pixel driving circuit. The second source-drain metal layer (SD2) may include: a connecting electrode, which is connected to the source electrode S and also connected to the anode in the light-emitting unit.

[0129] In some exemplary embodiments, such as Figure 9 As shown, the stop edge 602 of the isolation trench 60 is disposed on the same layer as the source electrode S and drain electrode D of the transistor 210 in the pixel driving circuit, or the stop edge 602 of the isolation trench 60 is disposed on the same layer as the connecting electrode. In some other exemplary embodiments, such as Figure 9 As shown, the first structural layer 603 of the isolation trench 60 is disposed on the same layer as the gate electrode G of the transistor 210 in the pixel driving circuit, or the first structural layer 603 of the isolation trench 60 is disposed on the same layer as the second electrode plate of the storage capacitor 211. In this way, the structure of the isolation trench 60 is formed simultaneously with the formation of the TFT array during the fabrication of the display substrate, thereby simplifying the fabrication process.

[0130] In some exemplary embodiments, during the fabrication of the display substrate, the third dielectric layer 605 can be removed using an EBB (Etch Bottom Bend) MASK process, and the fourth dielectric layer 604 can be removed using an EBA (Etch Bend After) MASK and an EBB MASK process to form the groove 601 in the isolation trench 60.

[0131] In some exemplary embodiments, such as Figure 9As shown, the display substrate may further include a trim line 70, which is disposed on the outer periphery of the isolation groove 60 on the side away from the display area 10, i.e., the trim line 70 is disposed on the outer periphery of the barrier area 30 on the side away from the display area 10. Exemplarily, the shape of the trim line 60 may be the same as the contour of the aperture area 20. Thus, after the display substrate testing is completed, the cutting equipment cuts the substrate area along the trim line 60 to form the aperture area 20 in the display substrate.

[0132] In some exemplary embodiments, such as Figure 9 As shown, the display substrate may further include: an isolation dam (Dam) 80, a portion of a plurality of isolation grooves 60 being disposed on the side of the isolation dam (Dam) 80 near the display area 10, and another portion of the plurality of isolation grooves 60 being disposed on the side of the isolation dam (Dam) 80 near the opening area 20.

[0133] In some exemplary embodiments, the opening area 20 may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer and a fifth insulating layer sequentially stacked on the substrate 101 in a plane perpendicular to the display substrate.

[0134] The structure of a display substrate is illustrated below with reference to the accompanying drawings through examples of the fabrication process of the display substrate. The "patterning process" described in the embodiments of this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching, and this disclosure does not limit the methods. A "thin film" refers to a thin film of a certain material fabricated on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0135] This disclosure also provides an exemplary embodiment of a method for fabricating a display substrate, wherein the display substrate is one or more of the exemplary embodiments described above, and the fabrication method may include:

[0136] S1. A substrate 101 is provided, comprising: a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA may include: a bonding area BD located on one side of the display area AA and close to the display area AA, a test area TS located on the side of the bonding area BD away from the display area AA, and a border area BK located on other sides of the display area AA. The display area AA may include: a display area, an aperture area, and a barrier area located between the display area and the aperture area.

[0137] S2. Multiple first electrode layers are formed on the test area TS of the substrate;

[0138] In some exemplary embodiments, S2 may include: depositing a first metal thin film on a substrate; forming a plurality of first electrode layers from the first metal film layer using the same etching process, the plurality of first electrode layers including: a first conductive layer 51 of the simulation unit 50 (serving as the first electrode layer of the simulation unit 50) and a third conductive layer 41 of the reference unit 40 (serving as the first electrode layer of the reference unit 40), such as Figure 10A As shown.

[0139] S3. First portions of multiple dielectric layers are formed on multiple first electrode layers and substrate 101, the first portions of the dielectric layers having openings; the first portions of the multiple dielectric layers include: a first portion 521 of the first dielectric layer 52 of the simulation unit 50 (serving as the first portion of the dielectric layer of the simulation unit 50) and a first portion 421 of the second dielectric layer 42 of the reference unit 40 (serving as the first portion of the dielectric layer of the reference unit 40), such as Figure 10B As shown.

[0140] In some exemplary embodiments, S3 may include: forming an insulating film on a plurality of first electrode layers and a substrate 101; forming first portions of a plurality of dielectric layers by the same etching process, wherein the first portions of the plurality of dielectric layers have openings between them.

[0141] S4. Form multiple flat thin films in the openings of the first portion of the multiple dielectric layers;

[0142] S5. A plurality of second electrode layers are formed on the first portion of a plurality of dielectric layers and on the side of a plurality of flat thin films away from the substrate;

[0143] In some exemplary embodiments, S5 may include: depositing a second metal film on the substrate-away side of a first portion of a plurality of dielectric layers and a plurality of planar thin films; forming a plurality of second electrode layers from the second metal film layer using the same etching process, the plurality of second electrode layers including: a second conductive layer 53 of the simulation unit 50 (serving as the second electrode layer of the simulation unit 50) and a fourth conductive layer 43 of the reference unit 40 (serving as the second electrode layer of the fourth conductive layer 43), such as Figure 10C As shown.

[0144] S6. Perform a side etching process on the flat thin film to form a second portion of multiple dielectric layers. The second portion of the multiple dielectric layers may include: a second portion 522 of the first dielectric layer 52 of the simulation unit 50 (serving as the second portion of the dielectric layer of the simulation unit 50) and a second portion 422 of the second dielectric layer 42 of the reference unit 40 (serving as the second portion of the dielectric layer of the reference unit 40), resulting in a reference unit as shown in the figure. Figure 10E The reference unit shown and as Figure 10D The simulation unit shown.

[0145] In some exemplary embodiments, S6 may include: performing a side etching process on the planar thin film using an EBB MASK process.

[0146] This disclosure also provides an etching depth detection method, applied to a display substrate as described in one or more of the above embodiments. The method may include: during the side etching process of the display substrate, obtaining the capacitance value of a reference unit and the capacitance value of a simulated unit; calculating the capacitance difference between the capacitance value of the reference unit and the capacitance value of the simulated unit; and calculating the size of the simulated groove in the simulated unit based on the obtained capacitance difference.

[0147] In some exemplary embodiments, such as Figure 11AAs shown, the reference unit 40 may include: a third conductive layer 41 (serving as a first electrode layer), a fourth conductive layer 43 (serving as a second electrode layer), and a second dielectric layer 42 located between the third conductive layer 41 and the fourth conductive layer 43 (serving as a dielectric layer of the reference unit located between the first electrode layer and the second electrode layer). The second dielectric layer 42 of the reference unit 40 may include: a third dielectric portion 421 having a first thickness (serving as a first portion of the dielectric layer of the reference unit), and a portion having a second thickness located around the third dielectric portion 421 (serving as a first portion of the dielectric layer of the reference unit). The fourth dielectric portion 422 (serving as the second part of the dielectric layer of the reference unit) is disposed in the same layer as the third dielectric portion 421 (serving as the first part of the dielectric layer of the reference unit) and the fourth dielectric portion 422 (serving as the second part of the dielectric layer of the reference unit) in the second dielectric layer 42 of the reference unit 40. The fourth dielectric portion 422 (serving as the second part of the dielectric layer of the reference unit) in the second dielectric layer 42 of the reference unit 40 protrudes from the first side and the second side of the fourth conductive layer 43. At this time, the reference unit 40 does not have a simulation groove compared to the simulation unit 50. Therefore, the capacitor formed by the reference unit 40 may include: a capacitor formed in the region where the third dielectric portion 421 is located (composed of the electrode portion in the third conductive layer 41 corresponding to the third dielectric portion 421, the third dielectric portion 421, and the electrode portion in the fourth conductive layer 43 corresponding to the third dielectric portion 421, forming a capacitor in the region where the first part of the dielectric layer in the reference unit is located), and a capacitor formed in the region where the fourth dielectric portion 422 is located (composed of the electrode portion in the third conductive layer 41 corresponding to the fourth dielectric portion 422, the fourth dielectric portion 422, and the electrode portion in the fourth conductive layer 43 corresponding to the fourth dielectric portion 422, forming a capacitor in the region where the second part of the dielectric layer in the reference unit is located).

[0148] In some exemplary embodiments, such as Figure 11BAs shown, the simulation unit 50 may include: a first conductive layer 51 (as a first electrode layer), a second conductive layer 53 (as a second electrode layer), and a first dielectric layer 52 (as a dielectric layer between the first electrode layer and the second electrode layer of the reference unit) located between the first conductive layer 51 and the second conductive layer 53. The first dielectric layer 52 of the simulation unit 50 may include: a first dielectric portion 521 having a first thickness (as a first part of the dielectric layer of the simulation unit) and a second dielectric portion 522 having a second thickness (as a second part of the dielectric layer of the simulation unit). The second dielectric portion 522 (as a second part of the dielectric layer of the simulation unit) in the first dielectric layer 52 of the simulation unit 50 is recessed relative to the first side and the second side of the second conductive layer 53, so that the simulation unit 50 has a simulation groove Udc. Therefore, the capacitor formed by the simulation unit 50 may include: a capacitor formed in the region where the simulation groove Udc is located (composed of the electrode portion in the first conductive layer 51 corresponding to the simulation groove Udc, the air in the simulation groove Udc, and the electrode portion in the second conductive layer 53 corresponding to the simulation groove Udc), a capacitor formed in the region where the second conductive layer 53 is located (composed of the electrode portion in the first conductive layer 51 corresponding to the first dielectric portion 521, the first dielectric portion 521, and the electrode portion in the second conductive layer 53 corresponding to the first dielectric portion 521, forming a capacitor in the region where the first part of the dielectric layer in the simulation unit is located), and a capacitor formed in the region where the second dielectric portion 522 is located (composed of the electrode portion in the first conductive layer 51 corresponding to the second dielectric portion 522, the second dielectric portion 522, and the electrode portion in the second conductive layer 53 corresponding to the second dielectric portion 522, forming a capacitor in the region where the second part of the dielectric layer in the simulation unit is located).

[0149] In some exemplary embodiments, besides setting the simulation unit 50 to have a simulation recess Udc while the reference unit 40 does not have a simulation recess Udc, the simulation unit and the reference unit can be set to have the same dimensions in other aspects, which facilitates the rapid determination of the size of the simulation recess Udc. Therefore, calculating the size of the simulation recess in the simulation unit 50 based on the obtained capacitance difference can include: calculating the size of the simulation recess in the simulation unit 50 according to the following formula based on the obtained capacitance difference:

[0150]

[0151]

[0152]

[0153] ΔC=C reference -C HIAA =C ref_HPLN1 -C HIAA_HPLN1-C Air ;

[0154]

[0155]

[0156] Where ε0 represents the vacuum permittivity (also known as the absolute permittivity); ε Air represents the dielectric constant of air; k represents the electrostatic constant; d represents the distance between the first and second electrode layers (dimension in the second direction DR2); L represents the length of the first and second electrode layers (dimension in the third direction DR3); W1 represents the dimensions of all simulated grooves Udc in the simulation unit (dimension in the first direction DR1); C Air ε represents the capacitance value of the region where the simulated groove Udc is located in the simulation cell; HPLN1 W0 represents the dielectric constant of the second portion in the dielectric layer; W0 represents the dimension (dimension in the first direction DR1) of the electrode portion in the second electrode layer of the reference cell corresponding to the second portion of the dielectric layer; C ref_HPLN1 This represents the capacitance value of the region where the second part of the dielectric layer in the reference cell is located; C HIAA_HPLN1 W1 represents the capacitance value of the region where the second part of the dielectric layer is located in the simulation unit; W2 represents the size of the electrode portion (the size in the first direction DR1) in the second electrode layer of the simulation unit corresponding to the second part of the dielectric layer; ΔC represents the capacitance difference, C reference This indicates the capacitance value of the capacitor formed by the reference cell; C HIAA This represents the capacitance value of the capacitor formed by the analog unit; d undercut The value represents the size of the simulated groove Udc in the simulation unit; K represents a coefficient calculated according to the formula, which is used to calculate the size of the simulated groove Udc (i.e., the side etching depth of the simulated groove Udc).

[0157] The inventors of this disclosure conducted experiments using three sets of test unit groups as an example, obtaining the experimental results shown in Tables 1 to 3 below. According to the three sets of experimental results, it can be seen that by comparing the three sets of test unit groups, the capacitance difference between the reference unit and the simulated unit is the same. Therefore, the side etching dimensions can be accurately detected during the fabrication of the display substrate. Here, by setting three sets of test unit groups of different sizes in the display substrate and comparing the three sets of detection results, the detection accuracy can be improved.

[0158] To improve detection sensitivity, the parameters of the three test unit groups can be set as follows: the number of finger numbers in the first test unit group (TEG1) is 5, the number of finger numbers in the second test unit group (TEG2) is 25, and the number of finger numbers in the third test unit group (TEG3) is 125. Here, as... Figure 7 As shown, Figure 7 One of the analog units 50 can be referred to as a finger unit, or a reference unit can be referred to as a finger unit. The length K1 (dimension in the third direction) of the three sets of test units can be set to 200 micrometers. In the display substrate, the distance K2 (dimension in the first direction DR1) between the second electrode layers 53 (as second electrode layers) in two adjacent analog units 50 is set to 10 micrometers (μm), 8 micrometers, and 6 micrometers, respectively, that is, the size of the opening formed between the second conductive layers 53 (as second electrode layers) in two adjacent analog units 50. For example, as Figure 9 As shown, when the display substrate has an isolation trench 60 with a structure similar to that of the analog unit 50, the distance K2 between the second conductive layer 53 (as the second electrode layer) in two adjacent analog units 50 can be equivalent to the opening size of the isolation trench 60, that is, the distance between the two opposite sides of the baffle 602 in the first direction DR1. In the display substrate, the distance K3 (the dimension in the first direction DR1) between the second dielectric portion 522 (as the second part in the dielectric layer) in two adjacent analog units 50 is set to 12.4 micrometers, 10.4 micrometers, and 8.4 micrometers, respectively, that is, the size of the opening formed between the dielectric layers in two adjacent analog units. For example, as Figure 9 As shown, when the display substrate is provided with an isolation groove 60 similar to that of the analog unit, the distance K3 between the second dielectric portion 522 (as the second part in the dielectric layer) in two adjacent analog units 50 can be equivalent to the opening size of the groove 601 in the isolation groove 60, that is, the distance between the third dielectric layers 605 on both sides of the groove 601 in the first direction DR1. Reference unit (denoted as Refer TEG) and analog unit (denoted as HIAA TEG).

[0159] Here, the present disclosure does not limit the parameter values ​​of the test unit group, and those skilled in the art can set other parameter values ​​according to the actual application scenario.

[0160] Table 1 Experimental Results

[0161]

[0162] Table 2 Experimental Results

[0163]

[0164] Table 3 Experimental Results

[0165]

[0166] The structure and fabrication process of the display substrate in the above-described embodiments are merely illustrative. In some exemplary embodiments, the structure can be modified and patterning processes can be added or reduced according to the actual application scenario. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with fabrication processes in some technologies, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0167] In some exemplary embodiments, the display substrate provided in this disclosure can be applied to display devices with pixel driving circuits, such as organic light-emitting diode (OLED), quantum dot light-emitting diode (QLED), or light-emitting diode display (Micro LED or Mini LED), etc. Here, this disclosure does not limit the application of the substrate.

[0168] In some exemplary embodiments, the display substrate may be an active-matrix organic light emitting diode (AMOLED) display substrate.

[0169] This disclosure also provides a display device, which may include: the display substrate described in one or more of the above embodiments.

[0170] In some exemplary embodiments, the opening area of ​​the display substrate may be opened, and the display device may further include a sensor located on the non-display side of the display substrate, wherein the orthographic projection of the sensor on the display substrate overlaps with the opening area of ​​the display substrate. For example, the opening area may be formed by laser cutting or mechanical stamping, and this opening area may penetrate the substrate.

[0171] Here, the display device can be a product with image (including still images or moving images, where moving images can be video) display capabilities. In some exemplary embodiments, the display device can be, but is not limited to, any product or component with display capabilities such as a mobile phone, tablet computer, television, monitor, laptop computer, or navigator. This disclosure does not limit the type of display device. Other essential components of the display device are understood by those skilled in the art and are not described in detail here, nor should they be construed as limiting this disclosure.

[0172] In some exemplary embodiments, the sensor may include, but is not limited to, a camera sensor, a fingerprint sensor, a light sensor, an infrared sensor, or an ultrasonic sensor. This disclosure does not limit the scope of the sensor.

[0173] In addition to the structures described above, the display device in this disclosure may also include other necessary components and structures, such as a circuit for providing electrical signals to the display substrate to drive the display substrate to emit light. This circuit can be called a control circuit, and it may include at least one of a circuit board and an integrated circuit (IC) electrically connected to the display substrate; or a power supply system for supplying power to the display substrate. Those skilled in the art can design and supplement accordingly based on the type of display substrate and the usage requirements, which will not be elaborated further here.

[0174] This disclosure also provides a display substrate motherboard, which may include: a substrate, the substrate including: a display substrate region and a non-display substrate region located around the display substrate region, the display substrate region including: a plurality of display substrates, the non-display substrate region including: a plurality of test component regions corresponding one-to-one with the plurality of display substrates, the test component region including: at least one test unit group, the test unit group including: a reference unit and a simulation unit; both the reference unit and the simulation unit include: a first electrode layer, a dielectric layer and a second electrode layer sequentially stacked on the substrate, the second electrode layer having opposing first side and second side in a first direction parallel to the substrate; wherein, the dielectric layer of the reference unit is convex or flush with the first side and second side of the second electrode layer in the first direction; a portion of the dielectric layer of the simulation unit is recessed in the first direction relative to the first side and second side of the second electrode layer of the simulation unit to form a simulation groove, the size of the simulation groove being determined according to the capacitance value between the first electrode layer and the second electrode layer of the reference unit and the capacitance difference between the capacitance values ​​between the first electrode layer and the second electrode layer of the simulation unit.

[0175] Alternatively, this disclosure also provides a display substrate motherboard, which may include: a substrate, the substrate including: a display substrate region and a non-display substrate region located around the display substrate region, the display substrate region including: a plurality of display substrates, at least one of the plurality of display substrates being the display substrate described in one or more of the above embodiments.

[0176] The descriptions of the above-described testing methods, display devices, and display substrate motherboard embodiments are similar to those of the above-described display substrate embodiments, and have similar beneficial effects. For technical details not disclosed in the testing methods, display devices, and display substrate motherboard embodiments of this disclosure, those skilled in the art should refer to the descriptions in the display substrate embodiments of this disclosure for understanding, and will not be repeated here.

[0177] While the embodiments disclosed herein are as described above, the above content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein, but the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising a substrate, characterized in that, The substrate includes a display area and a non-display area located around the display area. The non-display area includes at least one test unit group, and the test unit group includes a reference unit and a simulation unit. Both the reference unit and the simulation unit include a first electrode layer, a dielectric layer, and a second electrode layer that are sequentially stacked on the substrate. In a first direction parallel to the substrate, the second electrode layer has opposite first and second side surfaces. Among them, the dielectric layer of the reference unit protrudes or is flush with the first and second side surfaces of the second electrode layer in the first direction; a part of the dielectric layer of the simulation unit is recessed in the first direction compared with the first and second side surfaces of the second electrode layer of the simulation unit, forming a simulation groove. The size of the simulation groove is determined according to the capacitance difference between the capacitance value between the first electrode layer and the second electrode layer of the reference unit and the capacitance value between the first electrode layer and the second electrode layer of the simulation unit.

2. The display substrate according to claim 1, characterized in that, The dielectric layer includes a first part having a first thickness and a second part having a second thickness located around the first part. The first part and the second part are provided in the same layer. The first thickness is greater than the second thickness, and the thickness is the dimension in a second direction perpendicular to the first direction. Among them, the second part of the reference unit protrudes or is flush with the first and second side surfaces of the second electrode layer of the reference unit in the first direction; the second part of the simulation unit is recessed in the first direction compared with the first and second side surfaces of the second electrode layer of the simulation unit.

3. The display substrate according to claim 2, characterized in that, The dimension of the second part of the reference unit in the first direction is greater than the dimension of the second part of the simulation unit in the first direction. The dimension of the first part of the reference unit in the first direction is the same as the dimension of the first part of the simulation unit in the first direction. The dimension of the first electrode layer of the reference unit in the first direction is the same as the dimension of the first electrode layer of the simulation unit in the first direction, and the dimension of the second electrode layer of the reference unit in the first direction is the same as the dimension of the second electrode layer of the simulation unit in the first direction.

4. The display substrate according to claim 2, characterized in that, 5. The display substrate according to any one of claims 2 to 4, characterized in that, The first part and the second part are formed by two patterning processes. The first part is a multi-layer inorganic insulating film layer, and the second part is a single-layer inorganic insulating film layer.

6. The display substrate according to any one of claims 2 to 4, characterized in that, The dimension of the first part in the first direction is smaller than the dimension of the second electrode layer in the first direction, and the dimension of the second electrode layer in the first direction is smaller than the dimension of the first electrode layer in the first direction.

7. The display substrate according to any one of claims 2 to 4, characterized in that, The orthographic projection of the second electrode layer on the substrate falls within the edge of the orthographic projection of the first electrode layer on the substrate. The cross-sectional shape of the second electrode layer is "L-shaped".

8. The display substrate according to any one of claims 2 to 4, characterized in that, In a plane parallel to the display substrate, the test unit group includes: a main area and virtual areas located on both sides of the main area. The main area includes: a plurality of reference units or a plurality of simulation units arranged in succession. The virtual areas include: a plurality of virtual units arranged at intervals.

9. The display substrate according to any one of claims 2 to 4, characterized in that, The non-display area further includes: a first test pad pair connected to the reference unit and a second test pad pair connected to the simulation unit, each test pad pair including: a first pad connected to the first electrode layer and a second pad connected to the second electrode layer.

10. The display substrate according to any one of claims 2 to 4, characterized in that, The display area includes: a driving structure layer disposed on the substrate and a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate. The driving structure layer includes: a pixel driving circuit. The light-emitting structure layer includes: a light-emitting unit connected to the pixel driving circuit. The first electrode layer is disposed on the same layer as the gate electrode of the transistor in the pixel driving circuit and / or on the same layer as the first electrode plate of the storage capacitor in the pixel driving circuit. The second electrode layer is disposed on the same layer as the source electrode and drain electrode of the transistor in the pixel driving circuit and / or on the same layer as the connection electrode in the pixel driving circuit.

11. The display substrate according to any one of claims 2 to 4, characterized in that, The non-display area includes: a bonding area close to the display area and a test area located on the side of the bonding area away from the display area. The bonding area is configured to be bonded to the flexible circuit board, and the test unit group is located in the test area.

12. The display substrate according to claim 1, characterized in that, The display area includes: a display area, an opening area, and a barrier area located between the display area and the opening area. The barrier area includes: at least one isolation groove. The isolation groove includes: a recess and a baffle disposed on the side of the recess away from the substrate. The barrier area includes: a first structural layer and a second structural layer stacked sequentially in a direction away from the substrate. The first structural layer includes a metal layer. The recess penetrates the second structural layer and exposes at least a portion of the surface of the metal layer. The baffle is disposed on the surface of the second structural layer away from the substrate, and a portion of the baffle extends in a direction parallel to the substrate and protrudes relative to the sidewall of the recess. The size of the isolation groove is determined according to the size of the simulated recess in the simulation unit, and the size of the isolation groove is the distance between the side of the baffle and the sidewall of the recess.

13. A display device, characterized in that, include: The display substrate as described in any one of claims 1 to 12.

Images