Drive circuit, display device and driving method

Abstract

A driving circuit, a display device, and a driving method are disclosed. The driving circuit includes a level shifting unit and a gate driving unit. The level shifting unit includes multiple first clock signal input terminals and multiple first clock signal output terminals, configured to provide multiple first output signals to the gate driving unit at the multiple first clock signal output terminals respectively. The gate driving unit includes multiple second clock signal input terminals and 2n gate signal output terminals. The gate driving unit is configured to: respond to a first portion of a first output signal received by a first portion of the multiple second clock signal input terminals at a first moment, sequentially shift and output multiple first gate scan signals at the first portions of the gate signal output terminals; and respond to a second portion of the first output signals received by a second portion of the multiple second clock signal input terminals at a second moment, sequentially output multiple second gate scan signals at the second portions of the 2n gate signal output terminals. This method can alleviate problems such as display serialization or display errors.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a driving circuit, a display device, and a driving method. Background Technology

[0002] In the field of display technology, pixel arrays in liquid crystal display panels typically include multiple rows of gate lines and multiple columns of interlaced data lines. Driving the gate lines can be achieved through integrated, bonded driver circuits. In recent years, with the continuous improvement of amorphous silicon thin-film transistor (TFT) or oxide TFT fabrication processes, gate line driving circuits can also be directly integrated onto the TFT array substrate to form a GOA (Gate driver on Array) for driving the gate lines. For example, a GOA composed of multiple cascaded shift register units can be used to provide switching voltage signals (scan signals) to the multiple rows of gate lines in the pixel array, thereby controlling the multiple rows of gate lines to turn on sequentially. Simultaneously, data signals are provided from the data lines to the corresponding pixel units in the pixel array, forming the grayscale voltages required for each grayscale level of the displayed image in each pixel unit, thus displaying a frame of image. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a driving circuit, including: a level conversion unit and a gate driving unit. The level conversion unit includes a plurality of first clock signal input terminals and a plurality of first clock signal output terminals, and is configured to convert a plurality of first clock signals received by the plurality of first clock signal input terminals into a plurality of second clock signals, and to provide a plurality of first output signals to the gate driving unit respectively at the plurality of first clock signal output terminals; the gate driving unit includes a plurality of second clock signal input terminals and 2n gate signal output terminals, where n is an integer greater than or equal to 1, the plurality of second clock signal input terminals are used to receive the plurality of first output signals, and the gate driving unit is configured to: in response to a first portion of a first output signal received by a first portion of the plurality of second clock signal input terminals at a first moment, sequentially shift and output a plurality of first gate scan signals at the first portion of the 2n gate signal output terminals; in response to a second portion of a first output signal received by a second portion of the plurality of second clock signal input terminals at a second moment, sequentially output a plurality of second gate scan signals at the second portion of the 2n gate signal output terminals.

[0004] For example, in a driving circuit provided in one embodiment of this disclosure, the number of multiple first clock signal input terminals is less than or equal to the number of multiple first clock signal output terminals.

[0005] For example, in a driving circuit provided in one embodiment of this disclosure, the first part of the 2n gate signal output terminals is the output terminal with odd numbered sequence, and the second part of the 2n gate signal output terminals is the output terminal with even numbered sequence.

[0006] For example, in a driving circuit provided in an embodiment of this disclosure, at a first moment, the level conversion unit outputs at least one clock signal in the first part of the plurality of first clock signal output terminals, such that the first part of the plurality of first output signals is at least one clock signal, and outputs a non-trigger signal in the second part of the plurality of clock signal output terminals.

[0007] At the second moment, the level conversion unit outputs at least one clock signal in the second part of the plurality of first clock signal output terminals, so that the second part of the plurality of first output signals is at least one clock signal, and outputs a non-trigger signal in the first part of the plurality of clock signal output terminals.

[0008] For example, in a driving circuit provided in an embodiment of this disclosure, the level conversion unit further includes a control signal receiving end and a control signal output end. The control signal receiving end includes a first receiving end and a second receiving end, and the control signal output end includes a first output end and a second output end. The first receiving end is configured to receive a frame start signal, and the first output end is configured to provide a frame start signal to the gate driving unit so that the gate driving unit starts shifting and outputting a gate scan signal in response to the frame start signal. The second receiving end is configured to receive a reset signal, and the second output end is configured to provide a reset signal to the gate driving unit so that the gate driving unit resets in response to the reset signal.

[0009] For example, in a driving circuit provided in an embodiment of this disclosure, the level conversion unit includes a first conversion unit and a second conversion unit. The first conversion unit includes a first portion of a plurality of first clock signal output terminals, and the first portion of the plurality of first clock signal output terminals is configured to provide a plurality of first output signal first portions to the gate driving unit. The second conversion unit includes a second portion of a plurality of first clock signal output terminals, and the second portion of the plurality of first clock signal output terminals is configured to provide a plurality of first output signal second portions to the gate driving unit.

[0010] For example, in a driving circuit provided in one embodiment of this disclosure, the first conversion unit and the second conversion unit are integrated on the same chip.

[0011] For example, in a driving circuit provided in one embodiment of this disclosure, the first conversion unit and the second conversion unit are located on different chips.

[0012] For example, in a driving circuit provided in one embodiment of this disclosure, the driving circuit further includes a timing controller, which includes a plurality of initial clock signal output terminals and is configured to provide a plurality of first clock signals to the level conversion unit through the plurality of initial clock signal output terminals.

[0013] For example, in a driving circuit provided in one embodiment of this disclosure, the timing controller is further configured to provide a data signal for the display row, and the data signal for the display row provided at the first time and the second time are different.

[0014] For example, in a driving circuit provided in one embodiment of this disclosure, the data signals of the display rows provided at the first time and the second time are complementary to each other.

[0015] For example, in a driving circuit provided in an embodiment of this disclosure, the level conversion unit includes a first conversion unit and a second conversion unit, and the plurality of initial clock signal output terminals include a first output terminal group and a second output terminal group. The first output terminal group is configured to provide a first portion of a plurality of first clock signals to the first conversion unit, and the second output terminal group is configured to provide a second portion of a plurality of first clock signals to the second conversion unit.

[0016] At least one embodiment of this disclosure provides a display device, including: a driving circuit according to any embodiment of this disclosure; and a display panel, the display panel being coupled to the driving circuit, the driving circuit being configured to provide a first gate scan signal and a second gate scan signal to the display panel.

[0017] At least one embodiment of this disclosure provides a driving method applied to a driving circuit provided in any embodiment of this disclosure. The driving method includes: receiving a plurality of first clock signals at a plurality of first clock signal input terminals, converting the plurality of first clock signals into a plurality of second clock signals, and providing a first output signal from a plurality of first clock signal output terminals to a second clock signal input terminal; sequentially shifting and outputting a plurality of first gate scan signals at a first portion of a first output signal received at a first moment at a first moment at a first portion of a plurality of second clock signal input terminals; and sequentially outputting a plurality of second gate scan signals at a second portion of a plurality of gate signal output terminals at a second moment at a second moment at a second portion of a first output signal received at a second moment at a second moment at a second portion of a plurality of second clock signal input terminals. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0019] Figure 1A A schematic diagram of a special screen provided by at least one embodiment of the present disclosure is shown;

[0020] Figure 1B A block diagram of a driving circuit provided in at least one embodiment of the present disclosure is shown;

[0021] Figure 1CThe present disclosure illustrates at least one embodiment of an application provided for... Figure 1B A schematic diagram of the level conversion unit in the diagram;

[0022] Figure 2A A schematic diagram of a driving circuit provided in at least one embodiment of the present disclosure is shown.

[0023] Figure 2B The schematic diagram illustrates another driving circuit provided in at least one embodiment of the present disclosure;

[0024] Figure 2C The schematic diagram illustrates another driving circuit provided in at least one embodiment of the present disclosure;

[0025] Figure 3A and Figure 3B The timing diagram of the gate driving unit when displaying a black and white alternating image H1 provided in at least one embodiment of the present disclosure is schematically shown;

[0026] Figure 4A A schematic diagram of the structure of a gate driving unit provided in at least one embodiment of the present disclosure is shown;

[0027] Figure 4B A schematic diagram of the structure of a gate driving unit provided in at least one embodiment of this disclosure is shown; and

[0028] Figure 5 A schematic block diagram of a display device provided in at least one embodiment of the present disclosure is shown. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0030] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0031] With the development of science and technology and the improvement of living standards, some special images need to be displayed through display devices for purposes such as testing, analysis, and viewing. Driving the gate lines of a liquid crystal display panel using a gate driving circuit can easily lead to serial errors or display errors, resulting in low display quality for these special images. In some embodiments of this disclosure, the special image may be, for example, an image displayed in a pixel array in M ​​rows of pixels, where M is an integer greater than or equal to 1. Figure 1A A schematic diagram of a specific screen provided by at least one embodiment of this disclosure is shown. For example... Figure 1A As shown, in this example, M equals 1, and the special image is a black and white image.

[0032] At least one embodiment of this disclosure provides a driving circuit and a display device. The driving circuit includes a level conversion unit and a gate driving unit. The level conversion unit includes a plurality of first clock signal input terminals and a plurality of first clock signal output terminals, and is configured to convert the plurality of first clock signals received by the plurality of first clock signal input terminals into a plurality of second clock signals, and to provide a plurality of first output signals to the gate driving unit at the plurality of first clock signal output terminals respectively. The gate driving unit includes a plurality of second clock signal input terminals and 2n gate signal output terminals. The plurality of second clock signal input terminals are used to receive the plurality of first output signals, where n is an integer greater than or equal to 1. The gate driving unit is configured to: in response to a first portion of the first output signal received by a first portion of the plurality of second clock signal input terminals at a first moment, sequentially shift and output a plurality of first gate scan signals at the first portion of the 2n gate signal output terminals; and in response to a second portion of the first output signal received by a second portion of the plurality of second clock signal input terminals at a second moment, sequentially output a plurality of second gate scan signals at the second portion of the 2n gate signal output terminals. This driving circuit can alleviate or avoid display serialization or display errors in special scenes, and improve the display quality of special scenes.

[0033] Figure 1B A block diagram of a driving circuit according to at least one embodiment of the present disclosure is shown. This driving circuit is used, for example, in a display device, which may include a display panel, whereby the driving circuit can drive the display panel to perform display operations. The display panel may be, for example, a liquid crystal television panel, an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, etc.

[0034] like Figure 1B As shown, the driving circuit 100 includes a level conversion unit 10 and a gate driving unit 20. The level conversion unit 10 and the gate driving unit 20 are coupled together, and the gate driving unit 20 drives the pixel array of the display panel (…). Figure 1B (Not shown in the diagram, see the description below) Coupling. The pixel array consists of multiple rows and columns of pixels.

[0035] The level conversion unit 10 includes a plurality of first clock signal input terminals 101 and a plurality of first clock signal output terminals 102. The level conversion unit 10 is configured to convert the plurality of first clock signals (e.g., received by the plurality of first clock signal input terminals 101) into multiple first clock signals (e.g., ...). Figure 1B The multiple first clock signals (CLK1_IN to CLK4_IN) are converted into multiple second clock signals, and multiple first output signals (e.g., ...) are provided to the gate driving unit 20 at the multiple first clock signal output terminals 102 respectively. Figure 1B (Multiple first output signals CLK1 to CLK10 in the process).

[0036] The gate driving unit 20 includes a plurality of second clock signal input terminals 201 and 2n gate signal output terminals 202. The plurality of second clock signal input terminals 201 are used to receive a plurality of first output signals, where n is an integer greater than or equal to 1. For example, each gate signal output terminal can be used to provide a gate scan signal for a row of pixels in the pixel array of the display panel, so the 2n gate signal output terminals 202 can, for example, provide gate scan signals for 2n pixel rows respectively. Each pixel includes, for example, a switching element to receive a corresponding gate scan signal and a data signal. The switching element is turned on or off according to the gate scan signal to receive or not receive the data signal.

[0037] In some embodiments of this disclosure, for example, the number 2n of gate signal output terminals 202 is an integer multiple of the number of second clock signal input terminals 201, so that the multiple second clock signal input terminals 201 provide signals to the 2n gate signal output terminals 202 as a cyclic group, so that the 2n gate signal output terminals 202 output gate scan signals.

[0038] Gate driving unit 20 is configured to: respond to a first portion of a first output signal received at a first moment in response to a first portion 211 of a plurality of second clock signal input terminals 201 (e.g., Figure 1B The first output signals CLK1, CLK3, CLK5, CLK7, and CLK9 are sequentially shifted and output as multiple first gate scan signals at the first part 212 of the 2n gate signal output terminals 202, in response to the second part 221 of the multiple second clock signal input terminals 201 receiving the second part of the first output signal at a second time (e.g., ...). Figure 1B The first output signals CLK2, CLK4, CLK6, CLK7 and CLK10 are sequentially shifted and output as multiple second gate scan signals in the second part 222 of the 2n gate signal output terminals 202.

[0039] The driving circuit 100 divides the multiple output signals (e.g., the first output signal) of the level conversion unit 10 into multiple parts (e.g., the first part and the second part), which can be output to the gate driving unit 20 at different times. This causes the gate driving unit 20 to output the first gate scan signal and the second gate scan signal at different times. As a result, the switching elements of the pixels in the pixel row corresponding to the first gate scan signal and the pixel row corresponding to the second gate scan signal in the pixel array are turned on sequentially at different times. This alleviates or avoids problems such as serialization or display errors in the pixel row corresponding to the first gate scan signal and the pixel row corresponding to the second gate scan signal.

[0040] In some embodiments of this disclosure, the level conversion unit 10 can be implemented as a level conversion circuit or a chip for level conversion. For example, the level conversion unit 10 can change the period or amplitude of each of a plurality of first clock signals to obtain a plurality of second clock signals. For instance, the level conversion unit 10 can increase the voltage amplitude and period of a plurality of first clock signals.

[0041] Figure 1C The present disclosure illustrates at least one embodiment of an application provided for... Figure 1B A schematic diagram of the level conversion unit 10 in the diagram.

[0042] like Figure 1C As shown, the level conversion unit 10 may include a first conversion unit 11 and a second conversion unit 12.

[0043] The first conversion unit 11 includes a first portion 1021 of a plurality of first clock signal output terminals 102, the first portion 1021 of the first clock signal output terminals 102 provides a first portion of a plurality of first output signals to the gate driving unit 20. The second conversion unit includes a second portion 1022 of a plurality of first clock signal output terminals 102, the second portion 1022 of the plurality of first clock signal output terminals 102 provides a second portion of a plurality of first output signals to the gate driving unit 20.

[0044] exist Figure 1C In some examples, the first conversion unit 11 and the second conversion unit 12 are formed in the same level conversion circuit or integrated in the same chip.

[0045] In other embodiments, the first conversion unit and the second conversion unit may be formed in different level conversion circuits or different chips.

[0046] In some embodiments of this disclosure, such as Figure 1B As shown, the gate driving unit 20 is, for example, a gate driving circuit (GOA) fabricated on the array substrate of the display panel. The GOA is connected to a level conversion chip to receive multiple first output signals from the level conversion chip through multiple second clock signal input terminals of the GOA. For example, the gate driving circuit may include multiple cascaded shift register units.

[0047] In embodiments of this disclosure, for example, the GOA is configured to support grouping control of gate lines in the pixel array of a display panel. For example, the GOA may include a first shift register unit group and a second shift register unit group. The first shift register unit group can be used to provide gate scan signals for odd-numbered rows of gate lines in the display panel, and the second shift register unit group can be used to provide gate scan signals for even-numbered rows of gate lines in the display panel. For example, the first shift register unit group includes a first portion of a plurality of second clock signal inputs and a first portion of 2n gate signal outputs, and in response to a first portion of a received first output signal, the first portions of the 2n gate signal outputs sequentially shift to output a plurality of first gate scan signals; the second shift register unit group includes a second portion of a plurality of second clock signal inputs and a second portion of 2n gate signal outputs, and in response to a second portion of a received first output signal, the second portions of the 2n gate signal outputs sequentially shift to output a plurality of second gate scan signals. (The rest of the text is omitted as it is incomplete.) Figure 4A and Figure 4B The illustration shows two diagrams of GOAs, both of which can be used for, for example... Figure 1B The driving circuit is shown below. Please refer to the following for details. Figure 4A and Figure 4B The description.

[0048] like Figure 1B As shown, the driving circuit may further include a timing controller 30 in addition to the level conversion unit 10 and the gate driving unit 20.

[0049] The timing controller 30 includes multiple initial clock signal output terminals 301 and is configured to provide multiple first clock signals to the level conversion unit 10 through the multiple initial clock signal output terminals 301, and the level conversion unit 10 converts the multiple first clock signals into multiple second clock signals.

[0050] In some embodiments of this disclosure, the timing controller 30 is also configured to provide data signals for display rows to the display panel. The data signals for display rows provided at the first time and the second time are different. Therefore, the pixel rows activated at the first time and the second time receive different data signals (i.e., different gray levels), thereby enabling the display of different gray levels, for example.

[0051] In embodiments of this disclosure, a display row can refer to a pixel row where the gate lines are open. For example, at a first moment, if the gate lines of the pixel units in odd-numbered rows are opened sequentially, then the odd-numbered rows are display rows; at a second moment, if the gate lines of the pixel units in even-numbered rows are opened sequentially, then the even-numbered rows are display rows.

[0052] In some embodiments of this disclosure, the data signals of the display rows provided at the first time and the second time are complementary to each other.

[0053] In embodiments of this disclosure, complementary data signals mean, for example, that the sum of the gray values ​​of the pixel units provided by the two data signals is 255.

[0054] For example, at the first moment, the display rows are odd-numbered, and the grayscale value of each pixel unit in the odd-numbered rows is 255, that is, the odd-numbered rows display a white image; at the second moment, the display rows are even-numbered, and the grayscale value of each pixel unit in the even-numbered rows is 0, that is, the even-numbered rows display a black image. In this way, the two displayed images (white image and black image) can be combined to form a white and black image.

[0055] In some embodiments of this disclosure, such as Figure 1B As shown, the timing controller 30 has multiple initial clock signal output terminals 301, including a first output terminal group 311 and a second output terminal group 321. The first output terminal group 311 provides a first portion of the multiple first clock signals to the first conversion unit 11, and the second output terminal group 321 provides a second portion of the multiple first clock signals to the second conversion unit 12. For example, as... Figure 1B As shown, the multiple first clock signals include CLK1_IN, CLK2_IN, CLK3_IN and CLK4_IN. The first output terminal group 311 provides the first part of the multiple first clock signals, such as CLK1_IN and CLK2_IN, to the first conversion unit 11. The second output terminal group 321 provides the second part of the multiple first clock signals, such as CLK3_IN and CLK4_IN, to the second conversion unit 12.

[0056] For example, at a first moment, the first output group 311 of the timing controller 30 provides clock signals CLK1_IN and CLK2_IN to the first part of the first clock signal input, while the second output group 321 provides a low-level signal to the second part of the first clock signal input; at a second moment, the first output group 311 of the timing controller 30 provides a low-level signal to the first part of the first clock signal input, while the second output group 321 provides clock signals CLK3_IN and CLK4_IN to the second part of the first clock signal input.

[0057] In some embodiments of this disclosure, such as Figure 1B As shown, the level conversion unit 10 outputs at least one clock signal at a first moment in the first part 1021 of the plurality of first clock signal output terminals 102, so that the first part 112 of the first output signal is at least one clock signal, and outputs a non-trigger signal in the second part 1022 of the plurality of first clock signal output terminals 102.

[0058] For example, the non-trigger signal is a horizontal voltage signal, such as the low level of the clock signal (square wave signal).

[0059] For example, at the first moment, the first part of the first output signal (e.g., Figure 1B The first output signals CLK1, CLK3, CLK5, CLK7, and CLK9 are multiple clock signals. The first part 211 of the multiple second clock signal input terminals 201 receives the multiple clock signals, thereby the first part 212 of the 2n gate signal output terminals 202 sequentially shifts and outputs multiple first gate scan signals in response to the multiple clock signals. The multiple first gate scan signals can control the gate lines of the pixel rows (e.g., odd-numbered rows) corresponding to the first part 212 of the 2n gate signal output terminals 202 in the display panel to open sequentially. While the gate lines are opened sequentially, data signals are provided by data lines to the pixel units of the corresponding rows in the pixel array to form the grayscale voltage required for each grayscale level of the displayed image in each pixel unit, thereby displaying a frame of image.

[0060] For example, at a first moment, the second part 1022 of the plurality of first clock signal output terminals 102 outputs a non-trigger signal, so the second part 221 of the plurality of second clock signal input terminals 201 receives the non-trigger signal, and the second part 222 of the 2n gate signal output terminals 202 outputs a non-trigger signal, thereby the gate lines of the pixel rows (e.g., even rows) corresponding to the second part 222 of the 2n gate signal output terminals 202 in the display panel are in a closed state.

[0061] Therefore, at the first moment, the pixel units of the pixel row corresponding to the first part 212 of the 2n gate signal output terminals 202 in the pixel array form the gray level voltage required for each gray level of the image to be displayed. However, the pixel units of the pixel row corresponding to the second part 222 of the 2n gate signal output terminals 202 cannot be charged to write new data signals because the gate lines are in the closed state, and the data signals written before the first moment are retained.

[0062] Similarly, at the second moment, the second part of the first output signal (e.g., Figure 1BThe first output signals CLK2, CLK4, CLK6, CLK8, and CLK10 are multiple clock signals. The second part 221 of the multiple second clock signal input terminals 201 receives the multiple clock signals, thereby causing the second part 222 of the 2n gate signal output terminals 202 to sequentially shift and output multiple second gate scan signals in response to the multiple clock signals. The multiple second gate scan signals can control the gate lines of the pixel rows (e.g., even-numbered rows) corresponding to the second part 222 of the 2n gate signal output terminals 202 in the display panel to open sequentially. While the gate lines are opened sequentially, data signals are provided by data lines to the pixel units of the corresponding rows in the pixel array to form the grayscale voltage required for each grayscale level of the displayed image in each pixel unit, thereby displaying a frame of image.

[0063] In some embodiments of this disclosure, at a second moment, the first portion 1021 of a plurality of first clock signal output terminals 102 outputs a non-trigger signal, so the first portion 211 of a plurality of second clock signal input terminals 201 receives the non-trigger signal, and the first portion 212 of 2n gate signal output terminals 202 outputs a non-trigger signal, thereby displaying that the gate lines of the pixel rows (e.g., odd-numbered rows) corresponding to the first portion 212 of the 2n gate signal output terminals 202 in the display panel are in a closed state.

[0064] Therefore, at the second moment, the pixel units of the pixel row corresponding to the second part 222 of the 2n gate signal output terminals 202 in the pixel array form the gray level voltage required for each gray level of the image to be displayed, while the pixel units of the pixel row corresponding to the first part 212 of the 2n gate signal output terminals 202 retain the data signal written at the first moment because the gate lines are in the closed state.

[0065] In some embodiments of this disclosure, the first portion 212 of the 2n gate signal output terminals is an odd-numbered output terminal, and the second portion 222 of the 2n gate signal output terminals is an even-numbered output terminal. For example, the first portion 212 of the 2n gate signal output terminals is an output terminal with serial numbers 1, 3, 5…2n-1 (n is an integer greater than or equal to 1). For example, the gate signal output terminals with serial numbers 1, 3, 5…2n-1 are respectively connected to the gate lines in rows 1, 3, 5…2n-1 of the display panel. Similarly, for example, the second portion 222 of the 2n gate signal output terminals is an output terminal with serial numbers 2, 4, 6…2n (n is an integer greater than or equal to 1), and the gate signal output terminals with serial numbers 2, 4, 6…2n are respectively connected to the gate lines in rows 2, 4, 6…2n of the display panel.

[0066] like Figure 1BAs shown, for example, the odd-numbered first clock signal output terminals, as a group (i.e., the first part), provide the first part of multiple first output signals (e.g., clock signals CLK1, CLK3, CLK5, CLK7, and CLK9) to the first part 211 of the second clock signal input terminal at the first moment, and the even-numbered first clock signal output terminals, as a group (i.e., the second part), provide non-trigger signals to the second part 221 of the second clock signal input terminal. Then, the first part 212 of the 2n gate signal output terminals 202 outputs the first gate scan signal, and the second part 222 of the 2n gate signal output terminals 202 outputs the non-trigger signal. In this embodiment, if the gate signal output terminals numbered 1, 3, 5…2n-1 are connected to the gate lines in rows numbered 1, 3, 5…2n-1 in the display panel, then the gate lines with odd numbers in the display panel are turned on, and the gate lines with even numbers are turned off. Thus, data signals can be written into the pixel units in the odd-numbered rows, but cannot be written into the pixel units in the even-numbered rows. The even-numbered first clock signal output terminals provide a second portion of multiple first output signals (e.g., clock signals CLK2, CLK4, CLK6, CLK8, and CLK10) to the second portion 221 of the second clock signal input terminal at the second time. The odd-numbered first clock signal output terminals provide a non-trigger signal to the first portion 211 of the second clock signal input terminal. This causes the first portion 222 of the 2n gate signal output terminals 202 to output the second gate scan signal, and the second portion 222 of the 2n gate signal output terminals 202 to output the second gate scan signal, while the first portion 212 of the 2n gate signal output terminals 202 outputs the non-trigger signal. In this embodiment, the gate signal output terminals numbered 2, 4, 6…2n are respectively connected to the gate lines in rows 2, 4, 6…2n of the display panel, so that data signals can be written to pixel units in even-numbered rows but not to pixel units in odd-numbered rows.

[0067] In the above embodiments, the first clock signal output terminals are grouped according to odd and even numbers, providing gate scan signals to the gate lines in odd-numbered rows and to the gate lines in even-numbered rows, respectively. However, this is only one embodiment of the present disclosure and does not limit the scope of the present disclosure. For example, in some other embodiments of the present disclosure, the first clock signal output terminals are grouped in pairs, that is, adjacent pairs are treated as a whole, and multiple wholes are numbered. Multiple wholes with odd numbers are treated as a group, and wholes with even numbers are treated as a group. For example, the output terminals numbered 1 and 2, 5 and 6, and 9 and 10 are treated as a group, and the output terminals numbered 3 and 4, 7 and 8, and 11 and 12 are treated as a group. This ensures that at the first moment, the gate lines in rows 1, 2, 5, 6, 9, and 10 are turned on sequentially, and at the second moment, the gate lines in rows 3, 4, 7, 8, 11, and 12 in the element array are turned on sequentially. For example, the three adjacent outputs of the first clock signal can be treated as a whole, and multiple wholes can be numbered. Wholesale groups with odd numbers can be grouped together, and wholes with even numbers can be grouped together.

[0068] In some embodiments of this disclosure, the number of multiple first clock signal input terminals 101 is less than or equal to the number of multiple first clock signal output terminals 102. For example, as Figure 1B As shown, the level conversion unit 10 in the driving circuit 100 includes 4 first clock signal input terminals and 10 first clock signal output terminals.

[0069] In some embodiments of this disclosure, the level conversion unit 10 may further include a control signal receiving terminal and a control signal output terminal. For example... Figure 1B As shown, the control signal receiving end includes a first receiving end 103 and a second receiving end 104, and the control signal output end includes a first output end 105 and a second output end 106. The first receiving end 103 is used to receive a frame start signal STV1, and the first output end 105 is used to provide the frame start signal STV1 to the gate driving unit 20, so that the gate driving unit starts shifting and outputting a gate scan signal in response to the frame start signal STV1. The second receiving end 104 is used to receive a reset signal STV0, and the second output end 106 is used to provide the reset signal STV0 to the gate driving unit 20, so that the gate driving unit 20 resets in response to the reset signal STV0.

[0070] The following is combined Figure 2A , Figure 2B and Figure 2C The three embodiments shown further illustrate the driving circuit of this disclosure.

[0071] Figure 2A A schematic diagram of a driving circuit provided in at least one embodiment of the present disclosure is shown.

[0072] like Figure 2A As shown, in this embodiment, the driving circuit 200 includes a first conversion unit LS_1, a second conversion unit LS_2, a timing controller Tcon IC, and a gate driving unit GOA. The first conversion unit LS_1 and the second conversion unit LS_2 are components of the level conversion unit in the driving circuit 200; that is, the level conversion unit in the driving circuit 200 includes the first conversion unit LS_1 and the second conversion unit LS_2, which are located on two different chips. Hereinafter, the first conversion unit LS_1 and the second conversion unit LS_2 will be simply referred to as "two conversion chips".

[0073] like Figure 2A As shown, the number of first clock signal input terminals of the first conversion unit LS_1 is less than the number of first clock signal output terminals, and the number of first clock signal input terminals of the second conversion unit LS_2 is less than the number of first clock signal output terminals. Therefore, in this embodiment, the number of first clock signal input terminals in the level conversion unit is less than the number of first clock signal output terminals.

[0074] In this embodiment, for example, the timing controller Tcon IC outputs a reset signal STV0_IN1, a frame start signal STV1_IN1, and multiple first clock signals CLK1_IN1 to CLK4_IN1 to the two conversion chips. The Tcon IC groups CLK1_IN1 to CLK4_IN1, with the first clock signals CLK1_IN1 and CLK2_IN1 forming a first output group, and the first clock signals CLK3_IN1 and CLK4_IN1 forming a second output group.

[0075] For example, the reset signal STV0_IN1, the frame start signal STV1_IN1, and the first clock signals CLK1_IN1 to CLK2_IN1 are given to the first conversion unit LS_1, which is used by the first conversion unit LS_1 to generate STV0_IN1, STV1_IN1, and the first part of the first output signal CLK(2m-1) (m>=1) (for example, m=4, the first part of the first output signal includes the first output signal CLK1, the first output signal CLK3, the first output signal CLK5, the first output signal CLK7, and the first output signal CLK9). The reset signal STV0_IN1, the frame start signal STV1_IN1, and the first clock signals CLK3_IN1 to CLK4_IN1 are given to the second conversion unit LS_2, which is used to generate STV0_IN1, STV1_IN1, and the second part of the first output signal CLK(2m) (for example, m=4, the second part of the first output signal includes the first output signal CLK2, the first output signal CLK4, the first output signal CLK6, the first output signal CLK8, and the first output signal CLK10). In some embodiments of this disclosure (e.g., Figures 2A-2C In the example, the value of m can be determined based on the number of clock signals used by the GOA unit. For example, if the number of clock signals used by the GOA unit is 12, then m = 6; or if the number of clock signals used by the GOA unit is 8, then m = 4. Those skilled in the art can determine the value of n based on the number of clock signals used by the GOA.

[0076] For example, when the timing controller Tcon IC receives and detects a line of white and a line of black (hereinafter referred to as "H1 black and white alternation") data, it starts the mode detection function. Under the mode detection function, the timing controller Tcon IC normally outputs the reset signal STV0_IN1 and the frame start signal STV1_IN1. In the first frame, the Tcon IC normally outputs the clock signals CLK1_IN1 and CLK2_IN1, while CLK3_IN1 and CLK4_IN1 remain at a low level. At this time, the first conversion unit LS_1 controls the first part of the first clock signal output terminal to normally output the clock signals CLK1, CLK3, CLK5...CLK(2m-1), while the second conversion unit LS_2 controls the second part of the first clock signal output terminal to output a low level (i.e., a non-trigger signal). At this time, for example, the first part of the 2n gate signal output terminals corresponding to the first part of the first output signal drives the gate lines of the odd-numbered rows in the display panel to open and charge the pixel units of the odd-numbered rows. The timing controller Tcon IC sends and drives the pixel units to receive data with a grayscale value of 255. The display panel displays a white screen with a grayscale value of 255, while the gate lines of the even-numbered rows are not opened, displaying the previous frame before the H1 black and white alternating screen.

[0077] In the second frame, the timing controller Tcon IC normally outputs CLK3_IN1 and CLK4_IN1, while CLK1_IN1 and CLK21_IN drop to low level and remain there. At this time, the second conversion unit LS_2 controls the second part of the first clock signal output terminal to normally output clock signals CLK2, CLK4, CLK6...CLK(2m), while the first conversion unit LS_1 controls the first part of the first clock signal output terminal to output low level (i.e., non-trigger signal). At this time, for example, the second part of the 2n gate signal output terminals corresponding to the second part of the first output signal drives the gate lines of the even-numbered rows in the display panel to open and charge the pixel units of the even-numbered rows. The timing controller Tcon IC sends and drives the pixel units to receive data with a grayscale value of 0, and the display panel displays a black screen with a grayscale value of 0. The gate lines of the odd-numbered rows are closed because the clock signal is low, maintaining the white screen with a grayscale value of 255 from the previous frame.

[0078] The H1 black and white image is displayed by combining two consecutive frames and repeating in a loop, thus achieving the correct display of the H1 black and white image through the aforementioned pattern detection function.

[0079] Figure 2B The schematic diagram illustrates another driving circuit provided in at least one embodiment of the present disclosure.

[0080] like Figure 2B As shown, in this embodiment, the driving circuit 300 includes a level conversion unit LS, a timing controller TconIC0, and a gate driving unit GOA0. The level conversion unit LS includes a first conversion unit 310 and a second conversion unit 320, that is, in this embodiment, the first conversion unit 310 and the second conversion unit 320 are integrated on the same chip.

[0081] like Figure 2B As shown, the number of first clock signal input terminals (4) in the level conversion unit is less than the number of first clock signal output terminals (e.g., 10, 12, etc.).

[0082] In this embodiment, for example, the timing controller Tcon IC0 outputs a reset signal STV0_IN2, a frame start signal STV1_IN2, and multiple first clock signals CLK1_IN2 to CLK4_IN2 to the level conversion unit LS. Tcon IC0 groups CLK1_IN2 to CLK4_IN2, with CLK1_IN2 and CLK2_IN2 forming a first output group, and CLK3_IN2 and CLK4_IN2 forming a second output group. Signals CLK1_IN2 to CLK2_IN2 in the first output group serve as inputs to the first conversion unit 310, and signals CLK3_IN2 and CLK4_IN2 in the second output group serve as inputs to the second conversion unit 320.

[0083] The signals CLK1_IN2 to CLK2_IN2 in the first output group control the LS to output the first part of the first output signal. For example, at the first moment, the first part of the first output signal is the clock signals CLK1, CLK3, CLK5...CLK(2m-1) (m>=1). The signals CLK3_IN to CLK4_IN in the second output group control the LS to output the second part of the first output signal. For example, at the second moment, the second part of the first output signal is the clock signals CLK2, CLK4, CLK6...CLK(2m).

[0084] For example, when the timing controller Tcon IC0 receives and detects H1 black and white alternating data, it activates the mode detection function. Under mode detection, the timing controller Tcon IC0 normally outputs the reset signal STV0_IN2 and the frame start signal STV1_IN2. During the first frame, Tcon... IC0 normally outputs clock signals CLK1_IN2 and CLK2_IN2, while clock signals CLK3_IN2 and CLK4_IN2 remain low. At this time, LS receives clock signals CLK1_IN2 and CLK2_IN2 and controls the first part of multiple first clock signal output terminals to normally output clock signals CLK1, CLK3, CLK5...CLK(2m-1). LS also receives clock signals CLK3_IN2 and CLK4_IN2 and controls the second part of the first clock signal output terminals to output low. At this time, GOA0 drives the gate lines of odd-numbered rows in the display panel to open and charges the pixel units of odd-numbered rows. The timing controller TconIC0 sends and drives the pixel units to receive data with a grayscale value of 255. The display panel displays a white screen with a grayscale value of 255. The clock signal of even-numbered rows is low, causing the gate lines of even-numbered rows not to open, displaying the previous frame before the black and white alternating screen of H1.

[0085] In the second frame, the timing controller Tcon IC0 normally outputs clock signals CLK3_IN2 and CLK4_IN2, while CLK1_IN2 and CLK2_IN2 drop to low level and remain there. At this time, LS receives clock signals CLK3_IN2 and CLK4_IN2 and controls the second part of the first clock signal output terminal to normally output clock signals CLK2, CLK4, CLK6...CLK(2m). Meanwhile, the level conversion unit LS receives CLK1_IN2 and CLK2_IN2 and controls the first part of the first clock signal output terminal to output a low level. At this time, GOA0 drives the even-numbered rows of the pixel array in the display panel to open the gate lines and charge the even-numbered row pixel units. The timing controller Tcon IC0 sends and drives the pixel units to receive data with a grayscale value of 0, and the display panel displays a black screen with a grayscale value of 0. Meanwhile, the odd-numbered rows have their gate lines closed due to the low level of the clock signal, maintaining the white screen with a grayscale value of 255 from the previous frame.

[0086] The H1 black and white image is displayed by combining two consecutive frames and repeating in a loop, thus achieving the correct display of the H1 black and white image through the aforementioned pattern detection function.

[0087] Figure 2C The schematic diagram illustrates another driving circuit provided in at least one embodiment of the present disclosure.

[0088] like Figure 2C As shown, in this embodiment, the driving circuit 400 includes a level conversion unit LS1, a timing controller TconIC1, and a gate driving unit GOA1. The level conversion unit LS1 includes a first conversion unit 330 and a second conversion unit 340, that is, in this embodiment, the first conversion unit 330 and the second conversion unit 340 are integrated on the same chip.

[0089] like Figure 2C As shown, in this example, the number of first clock signal input terminals in the level conversion unit LS1 is equal to the number of first clock signal output terminals, both equal to 2m (m>=1). In this example, the number of clock signal channels supplied to LS1 by Tcon IC1 corresponds to the number of output signal channels output by LS1 to GOA1. Tcon IC1 groups the clock signals: CLK1_IN3, CLK3_IN3, CLK5_IN3...CLK(2m-1)_IN3 form the first output group, and CLK2_IN3, CLK4_IN3, CLK6_IN3...CLK(2m)_IN3 form the second output group.

[0090] The first output group CLK1_IN3, CLK3_IN3, CLK5_IN3...CLK(2m-1)_IN3 controls the first part of the first output signal CLK1, CLK3, CLK5...CLK(2m-1) (m>=1) output by LS1. The second output group CLK2_IN3, CLK4_IN3, CLK6_IN3...CLK(2m)_IN3 controls the second part of the first output signal CLK2, CLK4, CLK6...CLK(2m) output by LS1.

[0091] For example, when the timing controller Tcon IC1 receives and detects the black and white alternating data H1, it activates the mode detection function. Under mode detection, the timing controller Tcon IC1 normally outputs the reset signal STV0 and the frame start signal STV1_IN. In the first frame, Tcon IC1 normally outputs clock signals CLK1_IN3, CLK3_IN3, CLK5_IN3…CLK(2m-1)_IN3, while signals CLK2_IN3, CLK4_IN3, CLK6_IN3…CLK(2m)_IN3 remain low. LS1 receives the aforementioned clock signals CLK1_IN3, CLK3_IN3, CLK5_IN3…CLK(2m-1)_IN3 and boosts them before outputting. The first part of the first output signal normally outputs clock signals CLK1, CLK3, CLK5…CLK(2m-1), while the second part remains low. At this time, GOA1 drives the grid lines of the odd-numbered rows in the display panel to open and charge the pixel units of the odd-numbered rows. The timing controller Tcon IC1 sends and drives the pixel units to receive data with a grayscale value of 255. The display panel displays a white screen with a grayscale value of 255, while the grid lines of the even-numbered rows are not opened, and the previous frame before the black and white screen of H1 is displayed.

[0092] In the second frame, Tcon IC1 normally outputs clock signals CLK2_IN3, CLK4_IN3, CLK6_IN3...CLK(2m)_IN3, while signals CLK1_IN3, CLK3_IN3, CLK5_IN3...CLK(2m-1)_IN3 remain low. LS1 receives the aforementioned clock signals CLK2_IN, CLK4_IN3, CLK6_IN3...CLK(2m)_IN3 and boosts these clock signals before outputting them. The first part of the multiple first clock signal output terminals normally outputs clock signals CLK2, CLK4, CLK6...CLK(2m), while the second part of the multiple first clock signal output terminals outputs a low level. At this time, GOA1 drives the even-numbered rows of the display panel to open the grid lines and charge the even-numbered row pixel units. The timing controller Tcon IC1 sends and drives the pixel units to receive data with a grayscale value of 0. The display panel displays a black screen with a grayscale value of 0. Meanwhile, the odd-numbered rows have their grid lines closed due to the clock signal being at a low level, maintaining the white screen with a grayscale value of 255 from the previous frame.

[0093] The H1 black and white image is displayed by combining two consecutive frames and repeating in a loop, thus achieving the correct display of the H1 black and white image through the aforementioned pattern detection function.

[0094] Figure 3A and Figure 3B The illustration schematically shows a timing diagram of the gate driving unit when displaying a black and white alternating image H1 according to at least one embodiment of the present disclosure.

[0095] Figure 3A A timing diagram for when the first frame (e.g., a white screen) is displayed from the odd-numbered rows of the display panel at the first moment; Figure 3B This is a timing diagram for when the second frame (e.g., a black screen) is displayed in an even-numbered row of the display panel at a second moment.

[0096] Figure 3A and Figure 3B The timing diagram shown can be applied to Figures 2A to 2C Any of the embodiments described herein. In Figure 3A and Figure 3B In the example above, m equals 5. Figure 3A and Figure 3B In the text, CLK1_IN, CLK2_IN, CLK3_IN, and CLK4_IN represent respectively Figure 2A CLK1_IN1, CLK2_IN1, CLK3_IN1, and CLK4_IN1 in the data, or Figure 2B CLK1_IN2, CLK2_IN2, CLK3_IN2, and CLK4_IN2, or Figure 2CThe symbols CLK1_IN3, CLK2_IN3, CLK3_IN3, and CLK4_IN3 are used. STV0 represents the reset signal, and STV1_A and STV1_B both represent frame start signals. For example, STV1_A is the frame start signal input to the shift register cells in the odd-numbered rows of the gate drive unit, and STV1_B is the frame start signal input to the shift register cells in the even-numbered rows of the gate drive unit. It should be understood that the frame start signal STV1_A and the frame start signal STV1_B can be the same signal; they are distinguished here for the sake of clarity when differentiating between odd and even arrays.

[0097] like Figure 3A As shown, at the first moment, the timing controller (e.g., Tcon IC) outputs CLK1_IN and CLK2_IN normally, while CLK3_IN and CLK4_IN remain low.

[0098] The level conversion unit converts the CLK1_IN and CLK2_IN outputs from the timing controller into the second level signals described above, and outputs a clock signal from the first part of the first clock signal output terminal (e.g., the odd-numbered first clock signal output terminal), thereby causing the first part of the 2n gate signal output terminals of the gate drive unit (e.g., the odd-numbered output terminals) to output at least one clock signal. Figure 3A As shown, the odd-numbered output terminals in the gate drive unit output CLK1, CLK3, CLK5, CLK7 and CLK9 in sequence.

[0099] Since CLK3_IN and CLK4_IN remain low, a low-level signal is output from the second part of the first clock signal output terminal (e.g., the even-numbered first clock signal output terminal), thereby causing the second part of the 2n gate signal output terminals of the gate drive unit (e.g., the even-numbered output terminals) to output a non-trigger signal (e.g., a low-level signal).

[0100] like Figure 3A As shown, the even-numbered output terminals of the gate drive unit, CLK2, CLK4, CLK6, CLK8 and CLK10, are all low level.

[0101] In the embodiments of this disclosure, the timing of CLK1_IN and CLK2_IN is not necessarily related. Those skilled in the art can design the timing of CLK1_IN and CLK2_IN to control the generation of clock signals CLK1, CLK3, CLK5, CLK7, and CLK9. For example, in Figure 3AIn the illustrated embodiment, the later clock signal among CLK1, CLK3, CLK5, CLK7, and CLK9 is later than the earlier clock signal by one clock cycle of CLK1_IN and CLK2_IN. The clock cycles of CLK1, CLK3, CLK5, CLK7, and CLK9 are all three times the clock cycles of CLK1_IN and CLK2_IN.

[0102] like Figure 3B As shown, at the second moment, the timing controller (e.g., Tcon IC) normally outputs CLK3_IN and CLK4_IN, while CLK1_IN and CLK2_IN remain low. Similarly, in the embodiments of this disclosure, the timing of CLK3_IN and CLK4_IN is not necessarily related, and those skilled in the art can design the timing of CLK3_IN and CLK4_IN to control the generation of clock signals CLK2, CLK4, CLK6, CLK8, and CLK10.

[0103] The level conversion unit converts the CLK3_IN and CLK4_IN outputs from the timing controller into the second level signals described above, and outputs a clock signal from the second part of the first clock signal output terminal (e.g., the even-numbered first clock signal output terminal), thereby causing the second part of the 2n gate signal output terminals of the gate drive unit (e.g., the even-numbered output terminals) to output at least one clock signal. Figure 3B As shown, the odd-numbered output terminals of the gate drive unit output clock signals CLK2, CLK4, CLK6, CLK8 and CLK10 in sequence.

[0104] Since CLK1_IN and CLK2_IN remain low, a low-level signal is output from the first portion of the first clock signal output terminal (e.g., the odd-numbered first clock signal output terminal), thereby causing the first portion of the 2n gate signal output terminals of the gate drive unit (e.g., the odd-numbered output terminals) to output a non-trigger signal (e.g., a low-level signal). Figure 3B As shown, the outputs of CLK1, CLK3, CLK5, CLK7 and CLK9 from the odd-numbered output terminals in the gate drive unit are all at low levels.

[0105] Figure 4A A schematic diagram of the structure of a gate driving unit provided in at least one embodiment of the present disclosure is shown.

[0106] like Figure 4A As shown, the gate drive unit includes multiple cascaded shift register units (e.g., GOA1 to GOA5).

[0107] For example, such as Figure 4AAs shown, the gate drive unit is coupled to clock signal lines CK1', CK2', CK3', and CK4'. Clock signal line CK1' is connected, for example, to the clock signal terminal of the (4n-3)th stage shift register unit (n is an integer greater than 0); clock signal line CK2' is connected, for example, to the clock signal terminal of the (4n-2)th stage shift register unit; clock signal line CK3' is connected, for example, to the clock signal terminal of the (4n-1)th stage shift register unit; and clock signal line CK4' is connected, for example, to the clock signal terminal of the (4n)th stage shift register unit.

[0108] exist Figure 4A The following describes one structure of a gate driving unit, using the example of a gate driving unit (GOA) coupled to four clock signal lines CK1' to CK4' to drive the gate lines in a display panel to turn on. If the gate driving unit is coupled to the four clock signal lines CK1' to CK4', the level conversion unit may include four first clock signal output terminals. The first portion of the plurality of first clock signal output terminals (e.g., odd-numbered first clock signal output terminals) is coupled to clock signal lines CK1' and CK3', providing clock signals to clock signal lines CK1' and CK3'. The second portion of the plurality of clock signal output terminals (e.g., even-numbered first clock signal output terminals) is coupled to clock signal lines CK2' and CK4', providing clock signals to clock signal lines CK2' and CK4'.

[0109] For example, the input terminal INPUT of the first-stage shift register unit can be configured to receive the frame start signal STV1, and the reset terminal RST of the last-stage shift register unit can be configured to receive the reset signal STV0. The frame start signal STV1 and the reset signal STV0 are... Figure 4A Not shown in the image.

[0110] For example, such as Figure 4A As shown, the reset terminal of each shift register unit is connected to the output terminal of the next lower shift register unit, and the input terminal of each shift register unit is connected to the output terminal of the next higher shift register unit. Thus, the multiple cascaded shift register units of the gate drive unit are divided into two groups, with multiple shift register units separated by one level forming one group. For example, shift register units with odd-numbered positions form one group, and shift register units with even-numbered positions form another group.

[0111] Figure 4B A schematic diagram of the structure of a gate driving unit provided in at least one embodiment of the present disclosure is shown.

[0112] exist Figure 4BThe following describes one structure of a gate driving unit, using the example of a gate driving unit (GOA) coupled to four clock signal lines CK1 to CK4 to drive the gate lines in a display panel. If the gate driving unit is coupled to the four clock signal lines CK1 to CK4, the level conversion unit may include four first clock signal output terminals. The first portion of the plurality of first clock signal output terminals (e.g., odd-numbered first clock signal output terminals) is coupled to clock signal lines CK1 and CK3, providing clock signals to clock signal lines CK1 and CK3. The second portion of the plurality of clock signal output terminals (e.g., even-numbered first clock signal output terminals) is coupled to clock signal lines CK2 and CK4, providing clock signals to clock signal lines CK2 and CK4.

[0113] like Figure 4B As shown, the gate drive unit is divided into a first shift register unit group 401 and a second shift register unit group 402. For example, the first shift register unit group 401 can be used to provide a gate scan signal for odd-numbered rows of gate lines in the display panel, and the second shift register unit group can be used to provide a gate scan signal for even-numbered rows of gate lines in the display panel.

[0114] like Figure 4B As shown, the first shift register unit in each shift register unit group receives the frame start signal STV1, and each shift register unit in each shift register unit group is coupled to a clock signal line. For example, the first shift register unit group 401 is coupled to the odd-numbered clock signal lines CK1 and CK3, and the second shift register unit group 402 is coupled to the even-numbered clock signal lines CK2 and CK4.

[0115] like Figure 4B When each shift register unit outputs a high-level square wave on its coupled clock signal line, the output of the shift register unit acts on the gate line, turning the gate line on. The output of the shift register unit also acts as an input signal on the next shift register unit in the shift register unit group to which the shift register unit belongs.

[0116] Starting from the second shift register unit in each group, subsequent shift register units receive the INPUT signal from the preceding shift register unit. When their corresponding clock signal line goes high, they output a high-level square wave. This output is used not only to enable their corresponding gate line, but also as an INPUT signal for the next shift register unit, and as a RESET signal for the previous shift register unit. This continues until the last shift register outputs.

[0117] Figure 4B This diagram illustrates another gate driving unit provided in at least one embodiment of the present disclosure.

[0118] exist Figure 4A and Figure 4B The examples in this paper use the division of gate drive units into odd and even groups to illustrate the grouping control of gate drive units. However, this disclosure does not limit the grouping of gate drive units, and the grouping of gate drive units can be designed according to actual needs.

[0119] It is understood that this disclosure does not limit the structure of the gate driving unit. Figure 4A and Figure 4B The gate drive unit shown is merely an example; those skilled in the art can design the structure of the gate drive unit according to actual needs.

[0120] Figure 5 A schematic block diagram of a display device provided in at least one embodiment of the present disclosure is shown.

[0121] like Figure 5 As shown, the display device 1 includes a driving circuit 510 and a display panel 520, which are coupled together. The driving circuit 510 is configured to provide a first gate scan signal and a second gate scan signal to the display panel 520.

[0122] The driving circuit 510 can be any driving circuit provided in any embodiment of this disclosure; please refer to the description of the driving circuit above for details. For example... Figure 5 As shown, the driving circuit 510 may include a level conversion unit 502 and a gate driving unit 503 as described in any of the above embodiments, and the level conversion unit 502 and the gate driving unit 503 are coupled together. The driving circuit 510 may also include a timing controller 501, which is coupled to the level conversion unit 502 to provide a first clock signal to the level conversion unit 502.

[0123] The display panel 520 includes an array of multiple pixel units 530.

[0124] For example, the display device 1 may further include a data driving circuit 540. The data driving circuit 540 provides data signals to the pixel array; the driving circuit 510 provides gate scan signals (including a first gate scan signal and a second gate scan signal) to the pixel array. The data driving circuit 540 is electrically connected to the pixel unit 530 via a data line 521, and the driving circuit 510 is electrically connected to the pixel unit 530 via a gate line 511. Specifically, the second clock signal output terminal in the gate driving unit 103 of the driving circuit 510 is electrically connected to the pixel unit 530 via a gate line. The data driving unit 540 is coupled to a timing controller 501 to obtain data signals from the timing controller.

[0125] It should be noted that the display device 1 in this embodiment can be any product or component with display function, such as a liquid crystal panel, liquid crystal television, monitor, OLED panel, OLED television, electronic paper display device, mobile phone, tablet computer, laptop computer, digital photo frame, or navigator. The display device 1 may also include other conventional components, which are not limited in this embodiment.

[0126] The technical effects of the display device 1 provided in the embodiments of this disclosure can be referred to the corresponding description of the driving circuit in the above embodiments, which will not be repeated here.

[0127] This disclosure also provides a driving method applied to the driving circuit provided in any of the above embodiments. The driving method includes: receiving a plurality of first clock signals at a plurality of first clock signal input terminals, converting the plurality of first clock signals into a plurality of second clock signals, and providing a first output signal from a plurality of first clock signal output terminals to the second clock signal input terminals; sequentially shifting and outputting a plurality of first gate scan signals at a first portion of a first output signal received at a first moment at a first time at a second portion of a plurality of second clock signal input terminals; and sequentially outputting a plurality of second gate scan signals at a second portion of a plurality of gate signal output terminals at a second time at a second time at a second portion of a first output signal received at a second moment.

[0128] For example, in Figure 1B In the driving circuit shown, multiple first clock signal input terminals 101 receive multiple first clock signals (e.g., first clock signals CLK1_IN and CLK2_IN) from the timing controller 30. The level conversion unit 10 converts the multiple first clock signals into multiple second clock signals, and multiple first clock signal output terminals 102 provide a first output signal to the second clock signal input terminal 201.

[0129] In response to the first part of the first output signal received at a first moment by the first part 211 of the plurality of second clock signal input terminals 201, a plurality of first gate scan signals are sequentially shifted and output at the first part 212 of the 2n gate signal output terminals 202; and in response to the second part of the first output signal received at a second moment by the second part 221 of the plurality of second clock signal input terminals 201, a plurality of second gate scan signals are sequentially output at the second part 222 of the 2n gate signal output terminals 202.

[0130] This driving method can alleviate or avoid display serialization or display errors in special scenes, thereby improving the display quality of special scenes.

[0131] The following points need to be explained:

[0132] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0133] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0134] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A driving circuit, comprising: Level shifting unit and gate drive unit, The level conversion unit includes multiple first clock signal input terminals and multiple first clock signal output terminals, and is configured to convert multiple first clock signals received by the multiple first clock signal input terminals into multiple second clock signals, and provide multiple first output signals to the gate driving unit respectively at the multiple first clock signal output terminals; The gate driving unit includes a plurality of second clock signal input terminals and 2n gate signal output terminals, wherein the plurality of second clock signal input terminals are used to receive the plurality of first output signals, and n is an integer greater than or equal to 2. The gate driving unit includes a plurality of cascaded shift register units, and each of the 2n gate signal output terminals is configured to provide a gate scan signal for one pixel row of the pixel array of the display panel. The gate driving unit is configured to: respond to a first portion of the first output signal received by a first portion of the plurality of second clock signal input terminals at a first time moment, sequentially shift and output a plurality of first gate scan signals at the first portion of the 2n gate signal output terminals of the plurality of cascaded shift register units; and respond to a second portion of the first output signal received by a second portion of the plurality of second clock signal input terminals at a second time moment, sequentially output a plurality of second gate scan signals at the second portion of the 2n gate signal output terminals of the plurality of cascaded shift register units. At the first moment, the first gate scan signal is a trigger signal, causing the pixel row to receive the first gate scan signal to be in an open state, and the second gate scan signal is a non-trigger signal, causing the pixel row to receive the second gate scan signal to be in a closed state. At the second moment, the first gate scan signal is a non-trigger signal, causing the pixel row to receive the first gate scan signal to be in a closed state, and the second gate scan signal is a trigger signal, causing the pixel row to receive the second gate scan signal to be in an open state.

2. The driving circuit according to claim 1, wherein, The number of the plurality of first clock signal input terminals is less than or equal to the number of the plurality of first clock signal output terminals.

3. The driving circuit according to claim 1 or 2, wherein, The first part of the 2n gate signal output terminals is the output terminal with odd numbered sequence, and the second part of the 2n gate signal output terminals is the output terminal with even numbered sequence.

4. The driving circuit according to claim 1 or 2, wherein, At the first moment, the level conversion unit outputs at least one clock signal at the first part of the plurality of first clock signal output terminals, such that the first part of the plurality of first output signals is at least one clock signal, and outputs a non-trigger signal at the second part of the plurality of first clock signal output terminals, such that the first gate scan signal is a trigger signal and the second gate scan signal is a non-trigger signal. At the second moment, the level conversion unit outputs at least one clock signal at the second part of the plurality of first clock signal output terminals, such that the second part of the plurality of first output signals is at least one clock signal, and outputs a non-trigger signal at the first part of the plurality of first clock signal output terminals, such that the first gate scan signal is a non-trigger signal and the second gate scan signal is a trigger signal.

5. The driving circuit according to claim 1 or 2, wherein, The level conversion unit also includes a control signal receiving terminal and a control signal output terminal. The control signal receiving end includes a first receiving end and a second receiving end, and the control signal output end includes a first output end and a second output end. Wherein, the first receiving end is configured to receive a frame start signal, and the first output end is configured to provide the frame start signal to the gate driving unit, so that the gate driving unit starts shifting and outputting a gate scan signal in response to the frame start signal; The second receiving terminal is configured to receive a reset signal, and the second output terminal is configured to provide the reset signal to the gate driving unit so that the gate driving unit performs a reset in response to the reset signal.

6. The driving circuit according to claim 1 or 2, wherein, The level conversion unit includes a first conversion unit and a second conversion unit. The first conversion unit includes a first portion of the plurality of first clock signal output terminals, and the first portion of the plurality of first clock signal output terminals is configured to provide the first portion of the plurality of first output signals to the gate driving unit; The second conversion unit includes a second portion of the plurality of first clock signal output terminals, the second portion of the plurality of first clock signal output terminals being configured to provide the second portion of the plurality of first output signals to the gate driving unit.

7. The driving circuit according to claim 6, wherein, The first conversion unit and the second conversion unit are integrated on the same chip.

8. The driving circuit according to claim 6, wherein, The first conversion unit and the second conversion unit are located on different chips.

9. The driving circuit according to claim 1 or 2, wherein, The driving circuit also includes a timing controller. The timing controller includes multiple initial clock signal output terminals and is configured to provide the multiple first clock signals to the level conversion unit through the multiple initial clock signal output terminals.

10. The driving circuit according to claim 9, wherein, The timing controller is also configured to provide data signals for the display rows, and the data signals for the display rows provided at the first time and at the second time are different.

11. The driving circuit according to claim 10, wherein, The data signals of the display rows provided at the first time and the second time are complementary to each other.

12. The driving circuit according to claim 9, wherein, The level conversion unit includes a first conversion unit and a second conversion unit, and the plurality of initial clock signal output terminals include a first output terminal group and a second output terminal group. The first output terminal group is configured to provide a first portion of the plurality of first clock signals to the first conversion unit, and the second output terminal group is configured to provide a second portion of the plurality of first clock signals to the second conversion unit.

13. A display device, comprising: The driving circuit according to any one of claims 1 to 12; as well as Display panel, The display panel is coupled to the driving circuit, and the driving circuit is configured to provide the display panel with the first gate scan signal and the second gate scan signal.

14. A driving method applied to a driving circuit according to any one of claims 1 to 12, wherein, The driving method includes: In response to receiving multiple first clock signals at the multiple first clock signal input terminals, the multiple first clock signals are converted into multiple second clock signals, and the multiple first clock signal output terminals provide the first output signal to the second clock signal input terminals; In response to the first portion of the first output signal received at a first moment by the first portion of the plurality of second clock signal input terminals, a plurality of first gate scan signals are sequentially shifted and output by the first portion of the 2n gate signal output terminals of the first portion of the plurality of cascaded shift register units; and In response to the second part of the first output signal received at a second time by the second part of the plurality of second clock signal input terminals, a plurality of second gate scan signals are sequentially output by the second part of the 2n gate signal output terminals of the second part of the plurality of cascaded shift register units.

Images