Display substrate and display device

Abstract

The display substrate and display device disclosed herein include a substrate, the substrate including a display area and a border area located on at least one side of the display area; a transistor located on the substrate, the transistor being located in the display area, the transistor including a gate, a first electrode and an active layer; and a protective structure located on the substrate, the protective structure being disposed in the border area adjacent to the display area, and the protective structure being in the same layer and made of the same material as at least one of the active layer, the gate and the first electrode.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) have advantages such as light weight, low power consumption, high image quality, low radiation, and portability. They have gradually replaced traditional cathode ray tube displays (CRTs) and are widely used in modern information equipment, such as virtual reality (VR) headsets, laptops, televisions, mobile phones, and digital products. Summary of the Invention

[0003] The display substrate and display device provided in this disclosure are specifically designed as follows:

[0004] On one hand, embodiments of this disclosure provide a display substrate, including:

[0005] A substrate, the substrate including a display area and a border area located on at least one side of the display area;

[0006] A transistor is located on the substrate and in the display area. The transistor includes a gate, a first electrode, and an active layer.

[0007] A protective structure is located on the substrate, the protective structure is disposed adjacent to the display area in the border area, and the protective structure is in the same layer and made of the same material as at least one of the active layer, the gate, and the first electrode.

[0008] In some embodiments, in the display substrate provided in the present disclosure, the border area surrounds the display area, and the protective structure surrounds the display area within the border area.

[0009] In some embodiments, in the display substrate provided in the present disclosure, the border area includes: a first border area and a second border area placed opposite each other, and a third border area and a fourth border area placed opposite each other, wherein the third border area connects the first border area and the second border area, and the fourth border area connects the first border area and the second border area.

[0010] The display substrate further includes a gate line in the same layer and material as the gate, and a data line in the same layer and material as the first electrode. The extension direction of the gate line and the extension direction of the data line are intersected. The gate line passes through the display area and extends to the third border area and / or the fourth border area. The data line passes through the display area and extends to the first border area and the second border area.

[0011] The protective structure includes a plurality of protective portions that are disconnected in their extending direction; in the first frame area and the second frame area, the orthographic projection of at least a portion of the disconnection position between each of the protective portions on the substrate overlaps with the orthographic projection of the data line on the substrate; in the third frame area and the fourth frame area, the orthographic projection of at least a portion of the disconnection position between each of the protective portions on the substrate overlaps with the orthographic projection of the gate line on the substrate.

[0012] In some embodiments, in the display substrate provided in the present disclosure, the orthographic projection shape of the protective portion on the substrate is one or any combination of a straight line, a curve, and a broken line.

[0013] In some embodiments, in the display substrate provided in the present disclosure, the protection structure includes: a plurality of first sub-protective structures arranged sequentially at intervals in a direction away from the display area, wherein at least some of the disconnection positions of the first sub-protective structures are staggered in at least one of the first border area, the second border area, the third border area and the fourth border area.

[0014] In some embodiments, in the display substrate provided in the present disclosure, the disconnection positions of adjacent first sub-protective structures are staggered in at least one of the first border area, the second border area, the third border area, and the fourth border area.

[0015] In some embodiments, in the display substrate provided in the present disclosure, the disconnection position of the nth first sub-protective structure in the direction away from the display area is directly opposite to each other in at least one of the first border area, the second border area, the third border area and the fourth border area, where n is an odd or even number.

[0016] In some embodiments, in the display substrate provided in the present disclosure, the disconnection positions of all the first sub-protective structures are staggered in at least one of the first border area, the second border area, the third border area and the fourth border area.

[0017] In some embodiments, in the display substrate provided in the present disclosure, the protective structure is on the same layer and made of the same material as the active layer, and at least some of the disconnection positions of the first sub-protective structure are staggered in the first border area, the second border area, the third border area and the fourth border area.

[0018] In some embodiments, in the display substrate provided in the present disclosure, the protective structure is on the same layer and made of the same material as the gate. In the first frame area and the second frame area, at least some of the disconnection positions of the first sub-protective structure are staggered. In the third frame area and the fourth frame area, at least some of the disconnection positions of each of the first sub-protective structures are directly opposite each other. The gate line extends to at least some of the directly opposite disconnection positions and the gate line does not contact the protective portion.

[0019] In some embodiments, in the display substrate provided in the present disclosure, the protective structure is on the same layer and made of the same material as the first electrode. In the first frame area and the second frame area, all the disconnection positions of the first sub-protective structures are arranged facing each other. The data line extends to at least part of the disconnection positions that are arranged facing each other and the data line does not contact the protective part. In the third frame area and the fourth frame area, at least part of the disconnection positions of the first sub-protective structures are staggered.

[0020] In some embodiments, in the display substrate provided in this disclosure, the protective structure and the active layer, the gate, or the first electrode in the same layer satisfy the following relationship:

[0021]

[0022] Among them, S TFT S represents the projected area of ​​the active layer, the gate, or the first electrode, which are in the same layer as the protective structure, contained in a single pixel within the display area, on the substrate. pixel W represents the area of ​​a single pixel, S represents the line width of the protective portion, and S represents the spacing between two adjacent first sub-protective structures in the direction away from the display area.

[0023] In some embodiments, the display substrate provided in this disclosure further includes an electrostatic ring, the orthographic projection of which is located within the orthographic projection of the gap of the first sub-protective structure on the substrate.

[0024] In some embodiments, in the display substrate provided in the present disclosure, the border area surrounds the display area, and the shape of the border area is a rectangle with a cutout in the display area;

[0025] The protective structure is arranged around the four corners of the display area at the four corners of the rectangle.

[0026] In some embodiments, in the display substrate provided in the present disclosure, the protection structure includes a plurality of second sub-protection structures, and the distribution density of the second sub-protection structures in the area where the protection structure is located is approximately the same as the distribution density of the active layer, the gate, or the first electrode disposed in the same layer in the display area.

[0027] In some embodiments, in the display substrate provided in the present disclosure, the shape of the second sub-protection structure is substantially the same as the shape of the active layer, the gate, or the first electrode disposed in the same layer.

[0028] In some embodiments, in the display substrate provided in the present disclosure, the angle between the orthographic projection of the protective structure on the substrate and the side length between the four corners of the display area is an obtuse angle.

[0029] In some embodiments, in the display substrate provided in the present disclosure, the single-sided bezel area includes multiple rows of second sub-protective structures arranged sequentially in a direction away from the display area, and at both ends of the extension direction of the protective structures, the number of each row of second sub-protective structures in the direction away from the display area decreases sequentially.

[0030] In some embodiments, in the display substrate provided in the present disclosure, the length of the protective structure in its extending direction is greater than or equal to twice the width of the display area affected by diffraction light.

[0031] In some embodiments, in the display substrate provided in the present disclosure, the frame area includes: a first frame area and a second frame area placed opposite each other, and a third frame area and a fourth frame area placed opposite each other. The third frame area connects the first frame area and the second frame area, and the fourth frame area connects the first frame area and the second frame area. The first frame area includes a multiplexing circuit, the second frame area includes a test circuit, the third frame area includes a first gate driving circuit, and the fourth frame area includes a second gate driving circuit.

[0032] The width of the protective structure in the direction away from the display area is greater than or equal to the width of the display area affected by diffraction light, and the orthographic projection of the protective structure on the substrate does not overlap with the orthographic projections of the multiplexing circuit, the test circuit, the first gate driving circuit, and the second gate driving circuit on the substrate.

[0033] In some embodiments, the display substrate provided in this disclosure further includes an electrostatic ring located in the third border area and the fourth border area, wherein the orthographic projection of the electrostatic ring on the substrate is located between the orthographic projection of the protective structure on the substrate and the display area.

[0034] In some embodiments, the display substrate provided in this disclosure further includes an electrostatic ring located in the third border region and the fourth border region. The orthographic projection of the electrostatic ring on the substrate is located between the orthographic projection of the protective structure on the substrate and the orthographic projection of the first gate driving circuit on the substrate, and between the orthographic projection of the protective structure on the substrate and the orthographic projection of the second gate driving circuit on the substrate.

[0035] In some embodiments, in the display substrate provided in the present disclosure, the orthographic projection shape of the active layer on the substrate is approximately U-shaped or zigzag-shaped.

[0036] On the other hand, this disclosure provides a display device including the display substrate described above.

[0037] In some embodiments, the display device provided in the present disclosure is a virtual reality glasses;

[0038] The virtual reality glasses include one display substrate that provides an image to the left eye and another display substrate that provides an image to the right eye;

[0039] Alternatively, the virtual reality glasses may include a display substrate, the display area of ​​which includes a left-eye pixel area for providing images to the left eye and a right-eye pixel area for providing images to the right eye. Attached Figure Description

[0040] Figure 1 Images of the active layer in related technologies;

[0041] Figure 2 A schematic diagram showing diffraction occurring at the edge of the display area;

[0042] Figure 3 This is a schematic diagram of a display substrate provided in an embodiment of the present disclosure;

[0043] Figure 4 A schematic diagram of a structure for a sub-pixel within an effective pixel area;

[0044] Figure 5 Images of the active layer provided in embodiments of this disclosure;

[0045] Figure 6This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0046] Figure 7 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0047] Figure 8 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0048] Figure 9 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0049] Figure 10 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0050] Figure 11 for Figure 6 An enlarged schematic diagram of region Z1 in the middle;

[0051] Figure 12 for Figure 6 An enlarged schematic diagram of region Z2 in the middle;

[0052] Figure 13 for Figure 6 An enlarged schematic diagram of region Z3 in the middle;

[0053] Figure 14 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0054] Figure 15 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0055] Figure 16 for Figure 14 An enlarged schematic diagram of region Z4 in the middle;

[0056] Figure 17 for Figure 6 An enlarged schematic diagram of the Z5 region;

[0057] Figure 18 for Figure 6 An enlarged schematic diagram of region Z6 in the middle;

[0058] Figure 19 This is another schematic diagram of the structure of a sub-pixel within the effective pixel area provided in an embodiment of this disclosure;

[0059] Figure 20 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0060] Figure 21 for Figure 20 An enlarged schematic diagram of region Z7 in the middle;

[0061] Figure 22 This is a schematic diagram of yet another structure of the display substrate provided in an embodiment of this disclosure;

[0062] Figure 23 A schematic diagram of the structure of a display device provided in an embodiment of this disclosure;

[0063] Figure 24 This is another schematic diagram of the structure of the display device provided in the embodiments of this disclosure. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be noted that the dimensions and shapes of the figures in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0065] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure and the claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “inner,” “outer,” “upper,” and “lower” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0066] Ultra-high resolution (PPI) products, due to their smaller pixel size, result in smaller individual film layers in their display area (AA). During exposure and development, defects often occur in the film layers (such as the active layer) at the edges of the display area. Figure 1 As shown, after exposure and development, the pattern of the active layer can be preserved at the corners and connection points, but it breaks at other finer design locations, causing serious defects in ultra-high resolution products.

[0067] The reason for this is that the active layer pattern is mainly created through two steps: mask exposure and development. The light diffraction phenomenon during exposure and the catalyst density during development are the main factors affecting the active layer pattern. During exposure, light emitted from the light source passes through the mask and illuminates the photosensitive adhesive on the display substrate surface. When the light encounters an obstacle, it deviates from its straight-line propagation path and travels behind the obstacle, resulting in light diffraction. In ultra-high resolution displays, the pixel design is relatively dense, and the mask acts as a large obstacle, causing diffraction at the edges of the display area. The light diffraction phenomenon existing on one side of the display area in ultra-high resolution products is as follows: Figure 2 As shown. Figure 2 In the display substrate, the area with width 'a' represents the edge region of the display area affected by diffracted light. Irradiation by diffracted light causes the active layer linewidth at the edge of the display area to be smaller than that in the center after exposure, and may even lead to breakage. Furthermore, development is required after exposure. When the mask design is sparse or absent, a large area of ​​photosensitive emulsion develops, resulting in a high-density catalyst; conversely, when the mask design is dense, the photosensitive emulsion development area is smaller, resulting in a low-density catalyst. Due to penetration, the catalyst density in the low-density area gradually increases due to the influence of the catalyst density in the high-density area, affecting the development process in the low-density area. In ultra-high resolution product designs, the active layer is densely designed in the display area, and also densely designed in some border areas adjacent to the display area (GOA area, MUX area, CT area), resulting in a lower catalyst density during development. In other border areas adjacent to the display area, such as the corner areas corresponding to GOA and MUX (where no active layer is designed or the active layer density is low), the catalyst density is higher during development. Due to infiltration, catalyst from areas with higher catalyst density will enter areas with lower catalyst density. In some border areas (GOA, MUX, CT areas), the active layer design is dense, which itself has a certain effect of blocking catalyst infiltration. Therefore, the catalyst density in the display area is more easily affected by infiltration and increases. This causes the outermost active layer of the display area, especially the corner areas, such as the corner areas corresponding to GOA and MUX, to be over-developed, resulting in pattern breakage in the active layer.

[0068] To address the aforementioned technical problems in related technologies, this disclosure provides a display substrate, such as... Figure 3 and Figure 4 As shown, it includes:

[0069] The substrate 101 includes a display area AA and a border area (e.g., BB1, BB2, BB3, BB4) located on at least one side of the display area AA.

[0070] Transistor 102 is located on substrate 101 and in display area AA. Transistor 102 includes gate 21, first electrode 22 and active layer 23. Optionally, active layer 23 can be a polysilicon active layer, oxide active layer, etc. The materials of gate 21 and first electrode 22 can be metal materials or alloy materials. For example, gate 21 and first electrode 22 can be a single-layer metal structure or a multi-layer metal structure formed by molybdenum, aluminum and titanium. For example, the multi-layer metal structure is composed of stacked titanium metal layer / aluminum metal layer / titanium metal layer.

[0071] The protective structure 103 is located on the substrate 101. The protective structure 103 is disposed adjacent to the display area AA in the border area (e.g., BB1, BB2, BB3, BB4), and the protective structure 103 is in the same layer and made of the same material as at least one of the gate 21, the first electrode 22, and the active layer 23.

[0072] It should be noted that, in this disclosure, "same layer, same material" refers to a layer structure formed using the same film deposition process to create a film layer for a specific pattern, and then using the same mask to form a single patterning process. That is, one patterning process corresponds to one mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes. The specific pattern in the formed layer structure can be continuous or discontinuous; these specific patterns may be at the same height or have the same thickness, or they may be at different heights or have different thicknesses.

[0073] In the display substrate provided in this embodiment, by setting the protective structure 103 adjacent to the display area AA within the border area BB (e.g., BB1, BB2, BB3, BB4), the exposure protective structure 103 and the mask of the pixels of the display area AA form a barrier. During exposure, light bypasses this barrier and diffracts in the area where the protective structure 103 is located, thereby ensuring that the display area AA is not affected by diffracted light. During development, because the protective structure 103 is located adjacent to the display area AA, the high-density catalyst generated by large-area development on the side of the protective structure 103 away from the display area AA will penetrate into the area where the protective structure 103 is located. Due to the isolation effect of the protective structure 103, the catalyst density of the display area AA will not be affected by the high-density catalyst, thereby ensuring that the display area AA can be developed according to the normal catalyst density. Based on this, by setting a protective structure 103 adjacent to the display area AA in the border area (e.g., BB1, BB2, BB3, BB4), the gate 21, first electrode 22, active layer 23 and other components disposed in the same layer as the protective structure 103 in the display area AA can be protected and isolated during the exposure and development processes, thereby preventing the gate 21, first electrode 22, active layer 23 and other components in the display area AA from being broken, thus improving the product yield.

[0074] Optionally, this disclosure provides an image of the active layer 23 created using the scheme disclosed herein, such as... Figure 5 As shown. In comparison with related technologies... Figure 1 The image showing the fracture defects of the active layer 23 reveals that the active layer 23 fabricated using the technical solution of this disclosure does not exhibit fractures, significantly reducing the incidence of fracture defects in the active layer 23 of ultra-high resolution products.

[0075] It should be noted that, in order to completely avoid the influence of diffracted light on the gate 21, the first electrode 22, the active layer 23, etc. in the display area AA, Figure 3 The width K of the area where the protective structure 103 is located should be greater than or equal to the width of the area where the structure is located. Figure 2 The width 'a' of the display area AA affected by diffracted light is shown.

[0076] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 3 , Figure 6 and Figure 7 As shown, the border area (e.g., BB1, BB2, BB3, BB4) can surround the display area AA, and the protection structure 103 can be set within the border area (e.g., BB1, BB2, BB3, BB4) to surround the display area AA. The protection structure 103, which is set in a full circle, provides all-round protection and isolation for the edge of the display area AA, thereby effectively reducing the probability of wire breakage of the gate 21, first electrode 22, active layer 23, etc., which are set in the same layer as the protection structure 103 in the display area AA.

[0077] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 6 and Figure 7 As shown, the bezel area includes: a first bezel area BB1 and a second bezel area BB2 opposite to each other, and a third bezel area BB3 and a fourth bezel area BB4 opposite to each other. The third bezel area BB3 is connected to the first bezel area BB1 and the second bezel area BB2, and the fourth bezel area BB4 is connected to the first bezel area BB1 and the second bezel area BB2. The gate line 104 of the display area AA extends to the third bezel area BB3 and / or the fourth bezel area BB4 to be electrically connected to the first gate drive circuit GOA1 of the third bezel area BB3, and / or the second gate drive circuit GOA2 of the fourth bezel area BB2. The data line 105 of the display area AA extends to the first bezel area BB1 and the second bezel area BB2 to be electrically connected to the multiplexer circuit MUX of the first bezel area BB1 and the test circuit CT of the second bezel area BB2, respectively. In this disclosure, the orthographic projection of the protective structure 103 arranged around the entire border area (e.g., BB1, BB2, BB3, BB4) on the substrate 101 overlaps with the orthographic projections of the extension lines of the gate line 104 and the data line 105 on the substrate 101. This results in the formation of parasitic capacitance between the protective structure 103 and the extension lines of the gate line 104 and the data line 105. The presence of parasitic capacitance may interfere with the signals on the gate line 104 and the data line 105, thereby affecting the display effect. Based on this, the present disclosure provides a protective structure 103 including a plurality of protective portions 103' that are disconnected in its extending direction. In the first border region BB1 and the second border region BB2, the orthographic projection of at least a portion of the disconnected position between each protective portion 103' on the substrate 101 overlaps with the orthographic projection of the data line 105 on the substrate 101. In the third border region BB3 and the fourth border region BB4, the orthographic projection of at least a portion of the disconnected position between each protective portion 103' on the substrate 101 overlaps with the orthographic projection of the gate line 104 on the substrate 101. This reduces the area directly opposite the extension lines of the protective structure 103, the gate line 104, and the data line 105, thereby reducing the parasitic capacitance between the protective structure 103, the extension lines of the gate line 104, and the data line 105. This helps to reduce the interference of the protective structure 103 on the signals on the gate line 104 and the data line 105, ensuring the display effect.

[0078] Considering that a large disconnection distance between the protective portions 103' results in a higher catalyst density within that distance during development, potentially affecting the lower catalyst density in the display area, the disconnection distance between the protective portions 103' in this disclosure cannot be too large. Optionally, to maximize the parasitic capacitance between the lower protective portion 103' and the extension lines of the gate line 104 and the data line 105, the disconnection distance between the protective portions 103' can be equal to the linewidth of the extension lines of the gate line 104 or data line 105 that overlap with this disconnection distance. Considering the influence of factors such as alignment during manufacturing, the disconnection distance between the protective portions 103' can be slightly larger than the linewidth of the extension lines of the gate line 104 or data line 105 that overlap with this disconnection distance; for example, the maximum disconnection distance between the protective portions 103' is 1.2 times the linewidth of the extension lines of the gate line 104 or data line 105 that overlap with this disconnection distance. Optionally, the minimum disconnection distance between the protective portions 103' must meet the minimum spacing achievable by the manufacturing process (e.g., 2 μm).

[0079] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 6 to 10 As shown, the protective structure 103 includes a plurality of first sub-protective structures 31 arranged sequentially at intervals in a direction away from the display area AA. In at least one of the first border area BB1, the second border area BB2, the third border area BB3, and the fourth border area BB4, at least some of the disconnection positions of the first sub-protective structures 31 are staggered. This is beneficial to make the protective parts 103' of each first sub-protective structure 31 as uniform as possible, thereby ensuring that the catalyst concentration in the area where the protective structure 103 is located is low during the development process, preventing the catalyst concentration in the area where the protective structure 103 is located from affecting the catalyst concentration in the display area AA, and ensuring the normal development effect of the display area AA.

[0080] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 6 to 10 As shown, in at least one of the first border area BB1, the second border area BB2, the third border area BB3, and the fourth border area BB4, the disconnection positions of adjacent first sub-protective structures 31 can be staggered. Considering that if the disconnection positions of adjacent first sub-protective structures 31 are directly opposite each other, the overall area of ​​the directly opposite disconnection position will be larger, and correspondingly, the catalyst density at the directly opposite disconnection position will be larger during development, which may affect the lower catalyst density in the display area AA. Therefore, to avoid affecting the display area AA, the disconnection positions of adjacent first sub-protective structures 31 are staggered in this disclosure. Optionally, as... Figure 11 As shown, the minimum distance between the staggered disconnection positions in adjacent first sub-protection structures 31 can be 200μm to 300μm, such as 250μm.

[0081] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 6 to 10 As shown, in at least one of the first border area BB1, the second border area BB2, the third border area BB3, and the fourth border area BB4, the disconnection position of the nth first sub-protective structure 31 in the direction away from the display area AA is directly opposite to each other, and the disconnection position of the nth first sub-protective structure 31 is staggered from the disconnection position of the (n+1)th first sub-protective structure 31, where n is an odd or even number. In this case, there is an even-numbered first sub-protective structure 31 between any two odd-numbered first sub-protective structures 31. Although the disconnection positions of any two odd-numbered first sub-protective structures 31 are directly opposite to each other, the even-numbered first sub-protective structure 31 between them isolates the disconnection positions, preventing the directly opposite disconnection positions from connecting into a large area without a pattern. This ensures good uniformity of catalyst concentration in the area where the protective structure 103 is located during the development process. Similarly, between any two even-numbered first sub-protective structures 31, there is an odd-numbered first sub-protective structure 31. Although the disconnection positions of any two even-numbered first sub-protective structures 31 are set opposite each other, the odd-numbered first sub-protective structure 31 located between them isolates the disconnection positions of the two, preventing the disconnection positions set opposite each other from connecting into a large area of ​​patternless region. This ensures that the catalyst concentration in the region where the protective structure 103 is located is relatively uniform during the development process.

[0082] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 7 As shown, the disconnection positions of all the first sub-protective structures 31 can be staggered in at least one of the first border area BB1, the second border area BB2, the third border area BB3 and the fourth border area BB4, so as to avoid any two disconnection positions of the first sub-protective structures 31 from connecting to form a large area of ​​patternless area, thereby ensuring that the catalyst concentration in the area where the protective structure 103 is located is relatively uniform during the development process.

[0083] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 11 to 13 As shown, the protective structure 103 can be disposed on the same layer and made of the same material as the active layer 23, and as... Figure 6 and Figure 7As shown, in the first border area BB1, the second border area BB2, the third border area BB3, and the fourth border area BB4, at least some of the disconnection positions of the first sub-protective structures 31 can be staggered, so that the protective parts 103' of each first sub-protective structure 31 are evenly distributed in the first border area BB1, the second border area BB2, the third border area BB3, and the fourth border area BB4, thereby ensuring that the catalyst concentration around the display area AA is low during the development process, preventing the catalyst concentration around the display area AA from affecting the catalyst concentration of the display area AA, and ensuring the normal development effect of the display area AA.

[0084] In some embodiments, in the display substrate provided in the present disclosure, the protective structure 103 can be in the same layer and made of the same material as the gate 21. In this case, such as Figure 8 and Figure 9 As shown, in the first border area BB1 and the second border area BB2, at least some of the disconnection positions of the first sub-protective structures 31 are staggered; in the third border area BB3 and the fourth border area BB4, at least some of the disconnection positions of each first sub-protective structure 31 are directly opposite each other, and the grid line 104 extends to the at least some of the directly opposite disconnection positions, and the grid line 104 does not contact the protective part 103', preventing different grid lines 104 from being short-circuited through the protective part 103'. This arrangement ensures good uniformity of catalyst concentration in the areas where the first sub-protective structures 31 are located in the first border area BB1 and the second border area BB2, and also minimizes the difference in catalyst concentration between the areas where the first sub-protective structures 31 are located in the third border area BB3 and the fourth border area BB4 and the areas where the first sub-protective structures 31 are located in the first border area BB1 and the second border area BB2. This results in a lower catalyst concentration around the display area AA during development, preventing the catalyst concentration around the display area AA from affecting the catalyst concentration of the display area AA, and ensuring the normal development effect of the display area AA.

[0085] In some embodiments, in the display substrate provided in the present disclosure, the protective structure 103 can be disposed on the same layer and made of the same material as the first electrode 22. In this case, such as Figure 10As shown, in the first border area BB1 and the second border area BB2, the disconnection positions of all the first sub-protective structures 31 are arranged facing each other. The data line 105 extends to at least part of the disconnection positions that are arranged facing each other, and the data line 105 does not contact the protective part 103', preventing different data lines 105 from being short-circuited through the protective part 103'. In the third border area BB3 and the fourth border area BB4, the disconnection positions of at least part of the first sub-protective structures 31 are staggered. The above arrangement can ensure that the catalyst concentration in the areas where the first sub-protective structures 31 are located in the third border area BB3 and the fourth border area BB4 is relatively uniform. At the same time, it can ensure that the difference between the catalyst concentration in the areas where the first sub-protective structures 31 are located in the first border area BB1 and the second border area BB2 and the catalyst concentration in the areas where the first sub-protective structures 31 are located in the third border area BB3 and the fourth border area BB4 is small. This makes the catalyst concentration around the display area AA low during the development process, preventing the catalyst concentration around the display area AA from affecting the catalyst concentration of the display area AA, and ensuring the normal development effect of the display area AA.

[0086] In some embodiments, in the display substrate provided in this disclosure, when the distribution density of the protective structure 103 in the frame area (e.g., BB1, BB2, BB3, BB4) is approximately the same as the distribution density of the gate 21, first electrode 22, or active layer 23 disposed in the same layer in the display area AA, the catalyst density in the area where the protective structure 103 is located is comparable to the catalyst density in the display area AA during the development process. This ensures that the catalyst in the area where the protective structure 103 is located does not penetrate into the display area AA, allowing the display area AA to be developed according to the normal catalyst density without producing line breakage defects. To facilitate the calculation of the distribution density of the protective structure 103 and simplify the manufacturing process of the protective structure 103, such as... Figures 6 to 10 As shown, the orthographic projection of the protective structure 103 within the single-sided border area (e.g., BB1, BB2, BB3, or BB4) onto the substrate 101 can be a straight line, which is equivalent to the orthographic projection shape of the protective portion 103' onto the substrate 101 being a straight line. Of course, in some embodiments, the orthographic projection shape of the protective portion 103' onto the substrate 101 can be a curve, a broken line, or any combination of straight lines, curves, and broken lines, and is not limited here.

[0087] It should be noted that in the embodiments provided in this disclosure, due to limitations of process conditions or the influence of other factors such as measurement, "approximately the same" may be completely equivalent or may have some deviation (e.g., ±5% deviation). Therefore, as long as the relationship of "approximately the same" between related features meets the allowable error, it is within the protection scope of this disclosure.

[0088] In some embodiments, in the display substrate provided in the present disclosure, the protective structure 103 and the gate 21, the first electrode 22, or the active layer 23 in the same layer satisfy the following relationship:

[0089]

[0090] Among them, S TFT S represents the projected area on the substrate 101 of the gate 21, first electrode 22, or active layer 23 of a single pixel within the display area AA, which is in the same layer as the protective structure 103. pixel W represents the area of ​​a single pixel, S represents the line width of the protection section 103', and S represents the spacing between two adjacent first sub-protection structures 31 in the direction away from the display area AA. This indicates the distribution density of the gate 21, first electrode 22, or active layer 23, which are in the same layer as the protective structure 103, in the display area AA. This indicates the distribution density of the first sub-protective structure 31 within the area where the protective structure 103 is located. Under the condition that the above relationship is satisfied, it can be ensured that the distribution density of the first sub-protective structure 31 is the same as the distribution density of the gate 21, first electrode 22, or active layer 23 disposed on the same layer as it in the display area AA.

[0091] Optionally, in this disclosure, a single pixel is a display unit, which may include three sub-pixels: red, green, and blue. The linewidth W of the protection portion 103' can be 3 μm, and the spacing S between two adjacent first sub-protective structures 31 can be 2 μm. Furthermore, to avoid an excessively large catalyst density between the display area AA and the protection structure 103 due to an excessively large distance between them, the distance from the first sub-protective structure 31 closest to the display area AA to the display area AA can be made to the smallest achievable size of 2 μm. If there are no elements interfering with the first protection structure 31 within a distance a from the display area AA, the number of first sub-protective structures 31 is (a-2) / 5, where a is the width of the display area AA affected by diffracted light. When (a-2) / 5 is a decimal, the number of first sub-protective structures 31 can be determined by rounding.

[0092] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 12 and Figure 13 As shown, it may also include an electrostatic ring 106, the orthographic projection of which onto the substrate 101 can be located within the orthographic projection of the gap of the first sub-protective structure 31 onto the substrate 101. The electrostatic ring 106 can prevent static electricity from entering the display area AA and affecting the display effect. In specific implementations, a reasonable number of first sub-protective structures 31 can be set in the space between the electrostatic ring 106 and the display area AA, depending on the size of the space. For example, Figure 12 Two first sub-protection structures 31 are set in the space between the electrostatic ring 106 and the display area AA. Figure 13 A first sub-protection structure 31 is provided in the space between the electrostatic ring 106 and the display area AA. Optionally, the electrostatic ring 106 may include a first electrostatic part disposed on the same layer as the first electrode 22, and a second electrostatic part disposed on the same layer as the active layer 23, wherein the first electrostatic part and the second electrostatic part of the same electrostatic ring 106 are electrically connected.

[0093] The four corners of the display area AA are simultaneously affected by diffraction light from both the long and short sides. This superposition of diffracted light from both directions at the same corner results in stronger light intensity at the corners compared to single-sided diffraction, causing the film layers (such as active layers) at the corners to become thinner or even fractured. Furthermore, because no active layers are designed on the outer sides of the four corners of the display area AA, large areas of development occur in these regions, resulting in high-density catalyst. During development, due to the effect of permeation, the catalyst density inside the display area AA gradually increases, and overdevelopment can also cause fractures in the active layers at these four corners.

[0094] Based on this, in the display substrate provided in the embodiments of this disclosure, such as Figure 14 and Figure 15 As shown, the border area (e.g., BB1, BB2, BB3, BB4) surrounds the display area AA, and the shape of the border area (e.g., BB1, BB2, BB3, BB4) is a rectangle with a cutout in the display area AA; the protective structure 103 is arranged around the four corners of the display area AA at the four corners of the rectangle. This allows for effective protection and isolation of the four corners of the display area AA by the protective structure 103, significantly reducing the probability of wire breakage of the active layer 23, gate 21, first electrode 22, etc., which are disposed on the same layer as the protective structure 103 within the display area AA. Optionally, since there is no active layer pattern design at the four corners of the border area (e.g., BB1, BB2, BB3, BB4) in the related art, therefore, as Figure 14 and Figure 15 As shown, the protection structure 103 located at the four corners of the frame area (e.g., BB1, BB2, BB3, BB4) can be extended to be flush with the boundary of the area where the first gate driving circuit GOA1, the second gate driving circuit GOA2, the multiplexer circuit MUX, and the test circuit CT are located, away from the boundary of the display area AA. It can even extend beyond the boundary of the area where the first gate driving circuit GOA1, the second gate driving circuit GOA2, the multiplexer circuit MUX, and the test circuit CT are located, away from the boundary of the display area AA. The larger protection structure 103 can better prevent wire breakage at the four corners of the display area AA.

[0095] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 16 As shown, the protection structure 103 includes multiple second sub-protection structures 32. The distribution density of the second sub-protection structures 32 in the area where the protection structure 103 is located is approximately the same as the distribution density of the gate 21, the first electrode 22, or the active layer 23 disposed in the same layer in the display area. In this way, during the development process, the catalyst density in the area where the protection structure 103 is located is comparable to the catalyst density in the display area AA, so that the catalyst in the area where the protection structure 103 is located will not penetrate into the display area, ensuring that the display area AA can be developed according to the normal catalyst density and will not produce line breakage defects.

[0096] In some embodiments, in the display substrate provided in the present disclosure, the shape of the second sub-protection structure 32 may be substantially the same as the shape of the gate 21, the first electrode 22, or the active layer 23 disposed in the same layer. Optionally, Figure 16 An example was given where the shape of the second sub-protective structure 32 is approximately the same as the shape of the active layer 23 disposed in the same layer. When the shape of the second sub-protective structure 32 is approximately the same as the shape of the gate 21, the first electrode 22, or the active layer 23 disposed in the same layer, the distribution density of the second sub-protective structure 32 in the area where the protective structure 103 is located, as well as the distribution density of the gate 21, the first electrode 22, or the active layer 23 disposed in the same layer in the display area AA, can be kept completely consistent. Therefore, this solution has a better anti-line breakage effect during the development process.

[0097] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 14 and Figure 15 As shown, the angle between the orthographic projection of the protective structure 103 on the substrate 101 and the side length of the four corners of the display area AA can be an obtuse angle α, so that during the development process, the catalyst density from the area where the protective structure 103 is located to the display area AA gradually increases, so as not to cause a sudden density change and cause overdevelopment at the edge of the display area AA.

[0098] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 16 As shown, the single-sided bezel area (e.g., BB1, BB2, BB3, or BB4) includes multiple rows of second sub-protective structures 32 sequentially arranged in the direction away from the display area AA. The number of each row of second sub-protective structures 32 decreases sequentially at both ends E in the extension direction of the protective structure 103 in the direction away from the display area AA, such that the orthographic projection of the protective structure 103 onto the substrate 101 forms an obtuse angle with the side length of the display area AA. In this case, as... Figure 14 and Figure 15As shown, the obtuse angle α between the orthographic projection of the protective structure 103 on the substrate 101 and the side length of the display area AA extending along the column direction is equal to (180°-β), where β = arctan(w / p). The obtuse angle α between the orthographic projection of the protective structure 103 on the substrate 101 and the side length of the display area AA extending along the row direction is equal to (180°-γ), where γ = arctan(p / w), where w represents the width of the single-row decreasing sub-protective structure 31 in the row direction, and p represents the length of a single sub-protective structure 31 in the column direction. When the shape of the second sub-protective structure 32 is the same as the shape of the gate 21, the first electrode 22, or the active layer 23 disposed in the same layer, the width w is equivalent to the width of a single sub-pixel in the row direction, and the length p is equivalent to the length of a single pixel in the column direction. Optionally, when a single pixel includes three sub-pixels: red, green, and blue, the width of a single sub-pixel in the row direction can be equal to 1 / 3 of the width of a single sub-pixel in the row direction, and the length of a single pixel in the column direction can be equal to the length of a single pixel in the column direction.

[0099] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 14 and Figure 15 The protective structure 102 has a length F in its extending direction that is greater than or equal to the width a of the display area affected by diffraction light (e.g., ...). Figure 2 The diffracted light is twice the size of the protective structure 103, so that the area affected by the diffracted light is completely located within the area where the protective structure 103 is located, effectively avoiding the influence of the diffracted light on the display area AA and avoiding the breakage of the film layer in the display area AA.

[0100] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 3 As shown, the width K of the protective structure 103 in the direction away from the display area AA is greater than or equal to the width a of the display area AA affected by diffracted light (e.g., Figure 2 As shown), the orthographic projection of the protective structure 103 on the substrate 101 does not overlap with the orthographic projections of the multiplexer circuit MUX, the test circuit CT, the first gate drive circuit GOA1, and the second gate drive circuit GOA2 on the substrate 101. This ensures that the area affected by diffraction light is entirely within the area where the protective structure 103 is located, effectively preventing the diffraction light from affecting the display area AA, the area where the multiplexer circuit MUX is located, the area where the test circuit CT is located, the area where the first gate drive circuit GOA1 is located, and the area where the second gate drive circuit GOA2 is located. This also prevents film layer breakage in the display area AA, the area where the multiplexer circuit MUX is located, the area where the test circuit CT is located, the area where the first gate drive circuit GOA1 is located, and the area where the second gate drive circuit GOA2 is located.

[0101] In some embodiments, in the display substrate provided in this disclosure, the electrostatic ring 106 may be located within the third border region BB3 and the fourth border region BB4. To facilitate the calculation of the distribution density of the first sub-protective structure 31 or the second sub-protective structure 32 in the protective structure 103, such as... Figure 16 As shown, the orthographic projection of the electrostatic ring 106 on the substrate 101 can be positioned between the orthographic projection of the protective structure 103 on the substrate 101 and the display area AA; or, as shown... Figure 17 and Figure 18 As shown, the orthogonal projection of the electrostatic ring 106 on the substrate 101 is located between the orthogonal projection of the protective structure 103 on the substrate 101 and the region where the first gate drive circuit GOA1 is located, and between the orthogonal projection of the protective structure 103 on the substrate 101 and the region where the second gate drive circuit GOA2 is located.

[0102] In some embodiments, in the display substrate provided in the present disclosure, such as Figures 11 to 13 ,as well as Figures 16 to 18 As shown, the orthographic projection shape of the active layer 23 on the substrate 101 is approximately U-shaped, making the transistor 102 a dual-gate structure and enhancing the gate control capability of the transistor 103. Of course, in some embodiments, the orthographic projection shape of the active layer 23 on the substrate 101 can also be... Figure 19 The polygonal lines shown are not limited here. Optionally, such as... Figure 19 As shown, a portion of the gate line 104 can be reused as the gate 21. Of course, in some embodiments, the gate 21 may also protrude relative to the gate line 104, which is not limited here.

[0103] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 20 and Figure 21 As shown, the display area AA includes an effective pixel area P and a virtual pixel area D surrounding the effective pixel area P. In the transistor 102 of the effective pixel area P, the first electrode 22 is electrically connected to the active layer 23; in the transistor 102 of the virtual pixel area P, the first electrode 22 is insulated from the active layer 23. In a specific implementation, the effective pixel area P can display an image, while the virtual pixel area D cannot display an image. The virtual pixel area D is used to further prevent line breaks in the film layer of the effective pixel area P.

[0104] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 4 and Figure 22As shown, the transistor 102 in the effective pixel region P may further include a second electrode 24. The effective pixel region P also includes a pixel electrode 107 electrically connected to the second electrode 24 and a common electrode 108 whose orthogonal projection overlaps with the pixel electrode 107. Optionally, it may also include a control line 109 directly contacting the side of the common electrode 108 facing the substrate 101. The control line 109 can time-division multiplex touch signals and display drive signals onto the common electrode 108, enabling the common electrode 108 to perform touch and display functions in a time-division manner. Optionally, the first electrode 22 of the transistor 102 may be the source, and the second electrode 24 may be the drain; alternatively, the first electrode 22 of the transistor 102 may be the drain, and the second electrode 24 may be the source.

[0105] Optionally, to improve transmittance, the materials of the pixel electrode 107 and the common electrode 108 may include transparent conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. To further improve transmittance, the pixel electrode 107 or the common electrode 108 may be slit electrodes. Additionally, the materials of the control line 109 and the second electrode 24 may be transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc., or they may be metallic or alloy materials. For example, the control line 109 may have a single-layer or multi-layer metallic structure formed of molybdenum, aluminum, and titanium. Exemplarily, the multi-layer metallic structure is composed of stacked titanium / aluminum / titanium metal layers.

[0106] In this disclosure, the example given is that both the pixel electrode 107 and the common electrode 108 are disposed on the display substrate. In some embodiments, the pixel electrode 107 may also be disposed on the display substrate, and the common electrode 108 may be disposed on a counter substrate opposite to the display substrate. Furthermore, this disclosure only shows the pixel electrode 107 located between the layer containing the common electrode 108 and the substrate 101. In some embodiments, the common electrode 108 may also be located between the layer containing the pixel electrode 107 and the substrate 101; this is not a limitation.

[0107] In some embodiments, in the display substrate provided in the present disclosure, such as Figure 22 As shown, the first gate drive circuit GOA1, the second gate drive circuit GOA2, the test circuit CT, or the multiplexer circuit MUX includes a switching transistor 110. Optionally, the switching transistor 110 is a bottom-gate polysilicon transistor, and the transistor 102 is a top-gate oxide transistor. In some embodiments, the switching transistor 110 and the transistor 102 can both be bottom-gate or top-gate, or one can be bottom-gate and the other top-gate; this is not limited here.

[0108] Optionally, the switch 110 and transistor 102 can be either P-type or N-type transistors. In specific implementations, the switch 110 and transistor 102 can both be P-type and both be N-type transistors, or one can be a P-type transistor and the other an N-type transistor; no limitation is made here. The voltage difference V between the gate and source of a P-type transistor is... gs Its threshold voltage V th Satisfying relation V gs <V th When it is turned on, the voltage difference V between its gate and its source is... gs Its threshold voltage V th Satisfying relation V gs ≥V th The time cutoff point. For example, transistor 102 can be a P-type transistor, then the voltage difference V between transistor 102's gate 21 and its first terminal 22 is... gs1 Its threshold voltage V th1 The relationship between them satisfies relation V gs1 <V th1 When it is turned on, the voltage difference V between its gate 21 and its first electrode 22 is... gs1 Its threshold voltage V th1 The relationship between them satisfies relation V gs ≥V th The time cutoff. The voltage difference V between the gate and source of an N-type transistor. gs Its threshold voltage V th Satisfying relation V gs >V th When it is turned on, the voltage difference V between its gate and its source is... gs Its threshold voltage V th Satisfying relation V gs ≤V th Time cutoff. For example, transistor 102 can be an N-type transistor, and the voltage difference V between its gate 21 and its first terminal 22 is... gs1 Its threshold voltage V th1 The relationship between them satisfies relation V gs1 >V th1 When it is turned on, the voltage difference V between its gate 21 and its first electrode 22 is... gs1 Its threshold voltage V th1 The relationship between them satisfies relation V gs ≤V th Deadline.

[0109] In addition, such as Figure 4 and Figure 22As shown, the display substrate provided in this disclosure may further include pads 111 for bonding with a driver chip (IC), a light-shielding layer 112 for blocking light, a support structure 113 for supporting spacers (PS), and insulating layers such as a gate insulating layer 114, a first interlayer dielectric layer 115, a second interlayer dielectric layer 116, a third interlayer dielectric layer 117, a first insulating layer 118, a planarization layer 119, a second insulating layer 120, and a buffer layer 121. Other essential components of the display substrate are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting the scope of this disclosure.

[0110] In some embodiments, the light-shielding layer 112 may be in the same layer and made of the same material as the gate of the switching transistor 110. The material of the light-shielding layer 112 may be a metal material or an alloy material. For example, the control line 109 may have a single-layer metal structure or a multi-layer metal structure formed of molybdenum, aluminum and titanium. For example, the multi-layer metal structure is composed of a stacked titanium metal layer / aluminum metal layer / titanium metal layer.

[0111] In some embodiments, the materials of the gate insulating layer 114, the first interlayer dielectric layer 115, the second interlayer dielectric layer 116, the third interlayer dielectric layer 117, the first insulating layer 118, the second insulating layer 120, and the buffer layer 121 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The materials of the support structure 113 and the planarization layer 119 may include organic insulating materials such as polyimide, polyphthalamide, polyamide, polyacrylic acid resin, polyepoxy acrylic resin, photosensitive polyimide resin, polyester acrylate, polyurethane acrylate resin, phenolic epoxy acrylic resin, benzocyclobutene, or phenolic resin.

[0112] In some embodiments, the pad 111 can be a stacked structure. Optionally, the pad 111 is composed of a first pad portion that is on the same layer and made of the same material as the light-shielding layer 112, a second pad portion that is on the same layer and made of the same material as the source / drain of the switching transistor 110, and a third pad portion that is on the same layer and made of the same material as the first electrode 22 of the transistor 102. The first pad portion is electrically connected to the third pad portion through the second pad portion.

[0113] Based on the same inventive concept, this disclosure also provides a display device, including the display substrate described above. Since the principle by which this display device solves the problem is similar to that of the display substrate, the implementation of the display device provided in this disclosure can refer to the implementation of the display substrate described above, and repeated details will not be elaborated further.

[0114] In some embodiments, the display device provided in this disclosure can be applied to any product or component with display function, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, smartwatches, fitness wristbands, and personal digital assistants. Figure 23 and Figure 24 Specifically, the display device provided in this disclosure is applied to virtual reality (VR) glasses. Optionally, Figure 23 The virtual reality glasses shown include two displays L and R, which provide different images to the left and right eyes to achieve virtual reality display; the two displays L and R respectively include the display substrates provided in the embodiments of this disclosure. Figure 24 The virtual reality glasses shown include a display screen, the effective pixel area P of which includes the left eye pixel area P. L and the right eye pixel area P R Left eye pixel area P L and the right eye pixel area P R Different images are displayed separately to achieve virtual reality display. Optionally, the left eye pixel area P L and the right eye pixel area P R The display area AA is an octagon. In some embodiments, in order to reduce the probability of line breakage in the film layer (e.g., active layer) of the display area AA, a protective structure 103 can be provided around the eight sides of the display area AA, or a protective structure 103 can be provided around the eight corners of the display area AA.

[0115] In some embodiments, the display device provided in this disclosure can be a liquid crystal display (LCD). The LCD may include a backlight module and a display panel located on the light-emitting side of the backlight module. The display panel includes a display substrate and a counter substrate placed opposite each other, a liquid crystal layer located between the display substrate and the counter substrate, a sealant surrounding the liquid crystal layer between the display substrate and the counter substrate, a first alignment layer on the display substrate near the liquid crystal layer, a second alignment layer on the counter substrate near the liquid crystal layer, a first polarizer on the display substrate away from the liquid crystal layer, and a second polarizer on the counter substrate away from the liquid crystal layer. The backlight module can be a direct-lit backlight module or an edge-lit backlight module. The backlight module may include a light source, a stacked reflector, a light guide plate, a diffuser, a prism assembly, etc. The light source can be a light-emitting diode (LED), such as a miniature LED (Mini LED, Micro LED, etc.).

[0116] Micro-LEDs, at the sub-millimeter or even micrometer scale, are self-emissive devices, just like organic light-emitting diodes (OLEDs). Like OLEDs, they offer a range of advantages, including high brightness, ultra-low latency, and ultra-wide viewing angles. Furthermore, because inorganic LEDs emit light based on more stable and lower-resistance metal semiconductors, they offer advantages over organic LEDs, such as lower power consumption, better resistance to high and low temperatures, and longer lifespan. When used as backlights, micro-LEDs can achieve more precise dynamic backlighting effects, effectively improving screen brightness and contrast while eliminating glare caused by traditional dynamic backlighting between bright and dark areas, thus optimizing the visual experience.

[0117] In some embodiments, the display device provided in this disclosure may include, but is not limited to, components such as: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip may be a central processing unit, a digital signal processor, a system-on-a-chip (SoC), etc. For example, the control chip may also include a memory, a power module, etc., and implement power supply and signal input / output functions through additionally provided wires, signal lines, etc. For example, the control chip may also include hardware circuits and computer-executable code, etc. The hardware circuit may include conventional very-large-scale integrated circuits (VLSI) or gate arrays, as well as existing semiconductors or other discrete components such as logic chips, transistors, etc.; the hardware circuit may also include field-programmable gate arrays, programmable array logic, programmable logic devices, etc.

[0118] Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0119] Although preferred embodiments have been described in this disclosure, it should be understood that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A display substrate, wherein, include: A substrate, the substrate including a display area and a border area located on at least one side of the display area; The border area includes: a first border area and a second border area placed opposite each other, and a third border area and a fourth border area placed opposite each other, wherein the third border area connects the first border area and the second border area, and the fourth border area connects the first border area and the second border area. A transistor is located on the substrate and in the display area. The transistor includes a gate, a first electrode, and an active layer. A protective structure is located on the substrate, the protective structure is disposed adjacent to the display area within the border area, and the protective structure is in the same layer and made of the same material as at least one of the active layer, the gate, and the first electrode; The display substrate further includes a gate line in the same layer and material as the gate, and a data line in the same layer and material as the first electrode. The extension direction of the gate line and the extension direction of the data line are intersected. The gate line passes through the display area and extends to the third border area and / or the fourth border area. The data line passes through the display area and extends to the first border area and the second border area. The protective structure includes a plurality of protective portions that are disconnected in their extending direction; in the first frame area and the second frame area, the orthographic projection of at least a portion of the disconnection position between each of the protective portions on the substrate overlaps with the orthographic projection of the data line on the substrate; in the third frame area and the fourth frame area, the orthographic projection of at least a portion of the disconnection position between each of the protective portions on the substrate overlaps with the orthographic projection of the gate line on the substrate.

2. The display substrate as claimed in claim 1, wherein, The shape of the orthographic projection of the protective part onto the substrate is one of a straight line, a curve, a broken line, or any combination thereof.

3. The display substrate as described in claim 1 or 2, wherein, The protective structure includes: a plurality of first sub-protective structures arranged at intervals in a direction away from the display area, wherein at least some of the disconnection positions of the first sub-protective structures are staggered in at least one of the first border area, the second border area, the third border area and the fourth border area.

4. The display substrate as described in claim 3, wherein, In at least one of the first border area, the second border area, the third border area, and the fourth border area, the disconnection positions of adjacent first sub-protective structures are staggered.

5. The display substrate as claimed in claim 4, wherein, In at least one of the first border area, the second border area, the third border area, and the fourth border area, the disconnection position of the nth first sub-protection structure in the direction away from the display area is directly opposite each other, where n is an odd or even number.

6. The display substrate as claimed in claim 5, wherein, In at least one of the first border area, the second border area, the third border area, and the fourth border area, the disconnection positions of all the first sub-protection structures are staggered.

7. The display substrate according to any one of claims 4 to 6, wherein, The protective structure is on the same layer and made of the same material as the active layer. In the first border area, the second border area, the third border area and the fourth border area, at least some of the disconnection positions of the first sub-protective structure are staggered.

8. The display substrate according to any one of claims 4 to 6, wherein, The protective structure is on the same layer and made of the same material as the gate. In the first and second border regions, at least some of the disconnection positions of the first sub-protective structures are staggered. In the third and fourth border regions, at least some of the disconnection positions of each first sub-protective structure are directly opposite each other. The gate line extends to at least some of the directly opposite disconnection positions and the gate line does not contact the protective part.

9. The display substrate according to any one of claims 4 to 6, wherein, The protective structure is on the same layer and made of the same material as the first pole. Within the first and second frame areas, all the disconnection positions of the first sub-protective structures are arranged facing each other. The data line extends to at least part of the disconnection positions that are arranged facing each other and the data line does not contact the protective part. Within the third and fourth border areas, at least some of the disconnection positions of the first sub-protective structure are staggered.

10. The display substrate according to any one of claims 4 to 6, wherein, The protective structure and the active layer, the gate, or the first electrode in the same layer satisfy the following relationship: ； Among them, S TFT S represents the projected area of ​​the active layer, the gate, or the first electrode, which are in the same layer as the protective structure, contained in a single pixel within the display area, on the substrate. pixel W represents the area of ​​a single pixel, S represents the line width of the protective portion, and S represents the spacing between two adjacent first sub-protective structures in the direction away from the display area.

11. The display substrate according to any one of claims 4 to 6, wherein, It also includes an electrostatic ring, the orthographic projection of which is located within the orthographic projection of the gap of the first sub-protective structure onto the substrate.

12. The display substrate as claimed in claim 1, wherein, The border area surrounds the display area, and the shape of the border area is a rectangle with a cutout in the display area; The protective structure is arranged around the four corners of the display area at the four corners of the rectangle.

13. The display substrate as claimed in claim 12, wherein, The protection structure includes multiple second sub-protection structures, and the distribution density of the second sub-protection structures in the area where the protection structure is located is the same as the distribution density of the active layer, the gate, or the first electrode disposed in the same layer in the display area.

14. The display substrate as claimed in claim 13, wherein, The shape of the second sub-protection structure is the same as the shape of the active layer, the gate, or the first electrode disposed in the same layer.

15. The display substrate as claimed in claim 13 or 14, wherein, The angle between the orthographic projection of the protective structure onto the substrate and the side lengths of the four corners of the display area is an obtuse angle.

16. The display substrate as claimed in claim 15, wherein, The single-sided border area includes multiple rows of second sub-protective structures arranged sequentially in the direction away from the display area, and at both ends of the extension direction of the protective structure, the number of each row of second sub-protective structures in the direction away from the display area decreases sequentially.

17. The display substrate according to any one of claims 12-14, 16, wherein, The length of the protective structure in its extending direction is greater than or equal to twice the width of the display area affected by diffracted light.

18. The display substrate according to any one of claims 1-2, 4-6, 12-14, and 16, wherein, The frame area includes: a first frame area and a second frame area placed opposite each other, and a third frame area and a fourth frame area placed opposite each other. The third frame area connects the first frame area and the second frame area, and the fourth frame area connects the first frame area and the second frame area. The first frame area includes a multiplexer circuit, the second frame area includes a test circuit, the third frame area includes a first gate drive circuit, and the fourth frame area includes a second gate drive circuit. The width of the protective structure in the direction away from the display area is greater than or equal to the width of the display area affected by diffraction light, and the orthographic projection of the protective structure on the substrate does not overlap with the orthographic projections of the multiplexing circuit, the test circuit, the first gate driving circuit, and the second gate driving circuit on the substrate.

19. The display substrate as claimed in claim 18, wherein, It also includes an electrostatic ring located in the third border area and the fourth border area, wherein the orthographic projection of the electrostatic ring on the substrate is located between the orthographic projection of the protective structure on the substrate and the display area.

20. The display substrate as claimed in claim 18, wherein, It also includes an electrostatic ring located in the third border region and the fourth border region, wherein the orthographic projection of the electrostatic ring on the substrate is located between the orthographic projection of the protective structure on the substrate and the orthographic projection of the first gate driving circuit on the substrate, and between the orthographic projection of the protective structure on the substrate and the orthographic projection of the second gate driving circuit on the substrate.

21. The display substrate according to any one of claims 1-2, 4-6, 12-14, 16, 19-20, wherein, The orthographic projection shape of the active layer on the substrate is U-shaped or zigzag-shaped.

22. A display device, wherein, Includes the display substrate as described in any one of claims 1 to 21.

23. The display device as claimed in claim 22, wherein, The display device is virtual reality glasses; The virtual reality glasses include one display substrate that provides an image to the left eye and another display substrate that provides an image to the right eye; Alternatively, the virtual reality glasses may include a display substrate, the display area of ​​which includes a left-eye pixel area for providing images to the left eye and a right-eye pixel area for providing images to the right eye.

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