Method for reducing the accuracy requirement of a sleeve

Abstract

The application discloses a method for reducing the precision requirement of sleeve deviation, and belongs to the field of semiconductor manufacturing. An SOI material sheet is provided, which comprises a silicon substrate, a buried oxygen layer and a top layer silicon which are stacked in sequence; a waveguide full-etch mask and a non-penetrating partial-etch mask are manufactured; the waveguide full-etch mask is used to perform waveguide full-etch on the SOI material sheet, so as to define the outer edges of a strip waveguide region, a transition region and a ridge waveguide region; the non-penetrating partial-etch mask is used to perform non-penetrating partial-etch on the SOI material sheet, so as to form the transition region and a ridge waveguide flat plate region; and after the non-penetrating partial-etch, the photoresist is removed. The structure prepared by the method comprises the strip waveguide, the transition region and the ridge waveguide, and effective connection and coupling of the strip waveguide and the ridge waveguide are realized; the method can effectively avoid the load effect of the corner of etching, and avoid the insufficient etching from causing the light transmission loss to become large.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for reducing the accuracy requirements of offsetting. Background Technology

[0002] Silicon-based optical waveguides are important passive devices in silicon-based optoelectronics, serving as the transmission channel for optical signals. Silicon-based optical waveguides mainly include two types: strip waveguides and ridge waveguides. Both are formed by etching the top silicon layer (Top Si) of an SOI (silicon-on-insulator) wafer. The difference lies in the cross-section: strip waveguides have a rectangular cross-section formed by a single "waveguide full etching" process on the SOI top silicon layer. Figure 1 As shown; the cross-section of the ridge waveguide is a "convex" shape formed by a "waveguide full etching" process and a "non-penetrating partial etching" process on the top silicon layer of SOI, as shown. Figure 2 As shown, the ridge waveguide comprises two regions of different thicknesses: a thicker "ridge" in the middle and thinner "slab" regions on either side. The ridge is the primary light-guiding area, while the slabs can be doped with impurities to connect electrode structures. The strip waveguide is fabricated using a single "waveguide full etching" process, with the stop layer being the buried oxide layer (BOX) of the SOI wafer, requiring only one mask. The ridge waveguide, in addition to the central ridge, also requires silicon layers of a certain thickness on both sides as slab regions. Therefore, besides a single "waveguide full etching" process to define the outer edges of the ridge and slab regions, a "non-penetrating partial etching" process is needed to define the slab regions, requiring a total of two masks.

[0003] In silicon-based optoelectronics, the connection and coupling between strip waveguides and ridge waveguides are frequently encountered. For example, silicon-based Mach-Zehnder (MZI) electro-optic modulators utilize strip waveguides as input / output (I / O) channels for optical signals and ridge waveguides as the active modulation region for optical signals. Each modulation arm involves two connections between the strip and ridge waveguides. Since the strip and ridge waveguides have different cross-sectional shapes, their connection requires a tapered transition region; otherwise, due to the mismatch in the shape and size of the optical field modes, coupling loss will be significant. Figure 3As shown, the silicon layer thickness of the transition region is the same as that of the ridge waveguide planar region. Therefore, the transition region and the ridge waveguide planar region are drawn on the same mask and implemented by the same "non-penetrating partial etching" process. Thus, connecting a strip waveguide to the ridge waveguide via the transition region requires two masks (a "waveguide full etching" mask and a "non-penetrating partial etching" mask) and two etching processes ("waveguide full etching" and "non-penetrating partial etching"). This necessitates high-precision alignment of the second mask (the "non-penetrating partial etching" mask) with the first mask (the "waveguide full etching" mask). Inaccurate alignment can easily lead to a "loading effect," causing some corners of the "non-penetrating partial etching" to be incompletely etched. This places high demands on the process.

[0004] Therefore, studying the overlay of "non-penetrating partial etching" masks and "waveguide full etching" masks, reducing incomplete etching and optical transmission loss caused by mask overlay misalignment, lowering the mask overlay accuracy requirements, and improving the feasibility of the process is an important topic that will have significant implications for the development of silicon-based optoelectronic integration processes. Summary of the Invention

[0005] The purpose of this invention is to provide a method for reducing the overlay accuracy requirement, so as to solve the problem of excessively high overlay accuracy requirements and difficult process implementation in silicon photonic waveguide etching.

[0006] To solve the above-mentioned technical problems, the present invention provides a method for reducing the accuracy requirements of misalignment, comprising: SOI material wafers are provided, comprising a silicon substrate, a buried oxide layer and a top silicon layer stacked sequentially; Fabrication of waveguide full-etch mask and non-penetrating partial-etch mask; Using a waveguide full etching mask, waveguide full etching is performed on an SOI material sheet to define the outer edges of the strip waveguide region, transition region, and ridge waveguide region; Using a non-penetrating partial etching mask, non-penetrating partial etching is performed on the SOI material sheet to form a transition region and a ridge waveguide plate region. After etching the non-penetrating areas, remove the photoresist; The non-penetrating partial etching mask includes a non-penetrating non-etched region and a non-penetrating partial etched region; the non-penetrating partial etched region includes a transition region and a flat plate region of the ridge waveguide, as well as a region where the transition region is completed into a rectangle; the "convex" shape formed by the rectangle completed by the transition region and the flat plate region of the ridge waveguide extends by 0.5-1μm except for the bottom edge, and there are right-angled trapezoidal regions on both sides; wherein, the acute angle of the right-angled trapezoid is 70-80° and the position of the acute angle is close to the junction of the strip waveguide region and the transition region.

[0007] In one embodiment, the waveguide fully etched mask includes a waveguide non-etched region and a waveguide fully etched region; The waveguide non-etched region includes a strip waveguide region, a transition region, and a ridge waveguide region.

[0008] In one embodiment, the height of the right trapezoid in the non-penetrating etched area is >2.0 μm, and the size of the acute angle is 70-80°.

[0009] In one embodiment, in the non-etched region of the waveguide, the silicon layer thickness of the strip waveguide region, the transition region, and the ridge waveguide region is the same as the top silicon thickness of the SOI material wafer; the etching depth of the fully etched region of the waveguide is the same as the top silicon thickness of the SOI material wafer, and the etching stops at the surface of the buried oxide layer.

[0010] In one implementation, the non-penetrating partial etching region only etches the top silicon of the transition region and the ridge waveguide plate region.

[0011] In one embodiment, the silicon layer thickness of the strip waveguide region and the ridge waveguide region is the top silicon thickness of the SOI material sheet, and the silicon layer thickness of the transition region and the ridge waveguide plate region is less than the top silicon thickness of the SOI material sheet.

[0012] This invention provides a method for reducing the accuracy requirements of overlay. The structure prepared by this method includes a strip waveguide, a transition region, and a ridge waveguide, achieving effective connection and coupling between the strip waveguide and the ridge waveguide. Furthermore, the "non-penetrating partial etching" mask designed in this invention has a large tolerance for overlay misalignment, reducing process requirements. Even if there is some misalignment and slight offset along the y-direction, the etching angle is still large, which can effectively avoid the load effect at the etched corners and prevent insufficient etching from causing increased optical transmission loss. Attached Figure Description

[0013] Figure 1 This is a schematic cross-sectional view of the strip waveguide structure; Figure 2 This is a schematic cross-sectional view of the ridge waveguide structure; Figure 3 This is a top view schematic diagram of the connection between the strip waveguide and the ridge waveguide via the transition region; Figure 4 This is a schematic diagram of the structural cross-section of an SOI material sheet; Figure 5 This is a schematic diagram of the waveguide fully etched mask provided by the present invention; Figure 6 This is a schematic diagram of the non-penetrating partial etching mask provided by the present invention; Figure 7 This is a schematic diagram of the shape composition of the non-penetrating partial etching mask provided by the present invention; Figure 8 This is a schematic diagram illustrating the design concept of the non-penetrating partial etching mask provided by the present invention; Figure 9 This is a schematic diagram showing the dimensions of the key geometric parameters of the non-penetrating partial etching mask provided by the present invention; Figure 10 This is a schematic diagram of waveguide full etching using a waveguide full etching mask; Figure 11 This is a schematic diagram of the structural cross-section of the SOI material sheet after the waveguide is fully etched; Figure 12 This is a schematic diagram of non-penetrating partial etching using a non-penetrating partial etching mask; Figure 13 This is a schematic diagram of the cross-sectional structure of the SOI material sheet after waveguide full etching and non-penetrating partial etching. Figure 14 This is a top view of the SOI material sheet after waveguide full etching and non-penetrating partial etching; Figure 15 This is a schematic diagram showing the alignment of the non-penetrating etching mask provided by the present invention when it is accurately aligned. Figure 16 This is a schematic diagram of the non-penetrating etching mask provided by the present invention when the alignment is inaccurate. Detailed Implementation

[0014] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a method for reducing the accuracy requirements of overlay. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0015] This invention provides a method for reducing the overlay accuracy requirements of "non-penetrating partial etching" and "waveguide full etching", comprising the following steps: Provide such as Figure 4 The SOI material sheet shown includes a silicon substrate (Si sub), a buried oxide layer (BOX), and a top silicon layer (Top Si) stacked sequentially. Fabricating a waveguide full-etch mask, such as Figure 5 As shown; the characteristics of the "waveguide full etching" mask are: the non-etched area is Dark, including the "strip waveguide area", "transition area" and "ridge waveguide area"; the waveguide full etching area is Clear; Fabricating a "non-penetrating partial etching" mask, such as Figure 6As shown in the figure, the "non-penetrating partial etching" photomask is characterized in that: the non-etching region is Dark, and the "non-penetrating partial etching" region is Clear; the shape composition of the "non-penetrating partial etching" photomask is as Figure 7 shown, the shape of the Clear region of the "non-penetrating partial etching" photomask consists of a "convex" shape and right-angled trapezoids on both sides; the design idea of the "non-penetrating partial etching" photomask is as Figure 8 shown, the "convex" shaped region in the Clear region of the "non-penetrating partial etching" photomask is formed by expanding the "convex" shape composed of the rectangle complemented by the "transition region" and the "ridge waveguide slab region" by 0.5-1.0μm except for the bottom side; the size schematic diagram of the key geometric parameters of the "non-penetrating partial etching" photomask is as Figure 9 shown, the height of the right-angled trapezoid in the Clear region of the "non-penetrating partial etching" photomask is >2.0μm, and the acute angle is 70-80°; Using the Figure 5 shown "full waveguide etching" photomask, photoresist is coated on the surface of the SOI material wafer, after development, the photoresist only covers part of the surface of the SOI material wafer (that is, the Dark region of the "full waveguide etching" photomask), exposing the region to be etched (that is, the Clear region of the "full waveguide etching" photomask); "full waveguide etching" is performed on the region of the SOI material wafer surface not covered by the photoresist (that is, the Clear region of the "full waveguide etching" photomask), and the etching stop layer is the BOX layer; as Figure 10 shown; Wherein, the unetched region (that is, the Dark region of the "full waveguide etching" photomask) defines the outer edges of the "strip waveguide region", the "transition region" and the "ridge waveguide region". After etching is completed, the thickness of the silicon layer in the "strip waveguide region", the "transition region" and the "ridge waveguide region" contained in the unetched region (that is, the Dark region of the "full waveguide etching" photomask) is the top silicon thickness of the SOI material wafer; the etching depth of the "full waveguide etching" region (that is, the Clear region of the "full waveguide etching" photomask) is the top silicon thickness of the SOI material wafer, and etching stops on the surface of the BOX layer; After "full waveguide etching", the photoresist is removed, and the cross-sectional structure of the formed SOI material wafer is as Figure 11 shown; Using the Figure 6The "non-penetrating partial etching" mask shown involves coating the surface of the SOI material wafer after "waveguide full etching" with photoresist. After development, the photoresist only covers a portion of the SOI material wafer's surface (i.e., the Dark area of ​​the "non-penetrating partial etching" mask), exposing the area to be etched (i.e., the Clear area of ​​the "non-penetrating partial etching" mask). "Non-penetrating partial etching" is then performed on the area of ​​the SOI material wafer surface not covered by photoresist (i.e., the Clear area of ​​the "non-penetrating partial etching" mask), such as... Figure 12 As shown; The etched area shape corresponds to the shape of the "non-penetrating partial etching" mask's Clear area, including the "transition region" and the "ridge waveguide plate region," as well as the area where the "transition region" is completed into a rectangle, the "convex" shape formed by the completed rectangle and the "ridge waveguide plate region" extending beyond the bottom edge, and the right-angled trapezoidal regions on both sides. After "full waveguide etching," only the silicon layer thickness of the "strip waveguide region," "transition region," and "ridge waveguide region" is the same as the top silicon thickness of the SOI material wafer. After "full waveguide etching," the etched areas, including the area where the "transition region" is completed into a rectangle, the "convex" shape formed by the completed rectangle and the "ridge waveguide plate region" extending beyond the bottom edge, and the right-angled trapezoidal regions on both sides, all have an etching depth equal to the top silicon thickness of the SOI material wafer, with etching stopping at the BOX layer surface. Due to the high selectivity of "non-penetrating partial etching", "non-penetrating partial etching" will only etch the top silicon of the "transition region" and "ridge waveguide plate region", and will not affect the thickness of the BOX layer in other areas.

[0016] After "non-penetrating partial etching" and removal of the photoresist, the cross-sectional structure of the SOI material wafer is as follows: Figure 13 As shown in the top view diagram Figure 14 As shown, the silicon layer thickness of the "strip waveguide region" and the "ridge waveguide ridge region" is the same as the top silicon thickness of the SOI material sheet, while the silicon layer thickness of the "transition region" and the "ridge waveguide flat plate region" is less than the top silicon thickness of the SOI material sheet.

[0017] In the method for reducing the accuracy requirements of "waveguide full etching" and "non-penetrating partial etching" provided by this invention, the shape of the "non-penetrating partial etching" mask is specially designed. The "non-penetrating partial etching" mask of this invention is formed by a "convex" shape composed of a rectangle completed by the "transition region" and a "ridged waveguide plate region," with an extension of 0.5-1 μm beyond the bottom edge. Conventional "non-penetrating partial etching" masks without right-angled trapezoids, if misaligned, will shift along the y-direction. Because no right-angled trapezoids are added on both sides, the etching angle is 90°, which easily leads to a load effect at the 90° corner, resulting in insufficient etching in the 90° corner area and increased optical transmission loss. The difference between the optimized "non-penetrating partial etching" mask of this invention and the conventional "non-penetrating partial etching" mask is that right-angled trapezoids are added on both sides, with a height > 2.0 μm and an acute angle of 70-80°. When the "non-penetrating partial etching" mask of this invention is accurately aligned, the shape and position distribution of the "strip waveguide region," "transition region," "ridge waveguide ridge region," and "ridge waveguide flat plate region" are as follows: Figure 15 As shown; even if there is some misalignment in the alignment, with a slight offset along the y-direction, such as Figure 16 As shown, due to the addition of a right-angled trapezoid with an acute angle of 70-80°, the etching angle remains large, at 160-170°. This effectively avoids load effects at the etched corners and prevents increased optical transmission loss due to insufficient etching. Therefore, this invention has a high tolerance for misalignment in the "non-penetrating part etching," reducing process requirements, improving process feasibility, and ensuring the transmission performance of the optical waveguide. This is of great significance for the development of silicon-based optoelectronic integration processes.

[0018] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for reducing the accuracy requirements of misalignment, characterized in that, include: SOI material wafers are provided, comprising a silicon substrate, a buried oxide layer and a top silicon layer stacked sequentially; Fabrication of waveguide full-etch mask and non-penetrating partial-etch mask; Using a waveguide full etching mask, waveguide full etching is performed on an SOI material sheet to define the outer edges of the strip waveguide region, transition region, and ridge waveguide region; Using a non-penetrating partial etching mask, non-penetrating partial etching is performed on the SOI material sheet to form a transition region and a ridge waveguide plate region. After etching the non-penetrating areas, remove the photoresist; The non-penetrating partial etching mask includes a non-penetrating non-etched region and a non-penetrating partial etched region; the non-penetrating partial etched region includes a transition region and a flat plate region of the ridge waveguide, as well as a region where the transition region is completed into a rectangle; the "convex" shape formed by the rectangle completed by the transition region and the flat plate region of the ridge waveguide extends by 0.5-1μm except for the bottom edge, and there are right-angled trapezoidal regions on both sides; wherein, the acute angle of the right-angled trapezoid is 70-80° and the position of the acute angle is close to the junction of the strip waveguide region and the transition region.

2. The method for reducing the accuracy requirement of misalignment as described in claim 1, characterized in that, The waveguide fully etched mask includes a waveguide non-etched region and a waveguide fully etched region; The waveguide non-etched region includes a strip waveguide region, a transition region, and a ridge waveguide region.

3. The method for reducing the accuracy requirement of misalignment as described in claim 1, characterized in that, The height of the right-angled trapezoid in the non-penetrating etched area is >2.0 μm.

4. The method for reducing the accuracy requirement of misalignment as described in claim 2, characterized in that, In the non-etched region of the waveguide, the silicon layer thickness of the strip waveguide region, the transition region, and the ridge waveguide region is the same as the top silicon thickness of the SOI material wafer; the etching depth of the fully etched region of the waveguide is the same as the top silicon thickness of the SOI material wafer, and the etching stops at the surface of the buried oxide layer.

5. The method for reducing the accuracy requirement of misalignment as described in claim 1, characterized in that, The non-penetrating etched area will only etch the top silicon layer of the transition region and the ridge waveguide plate region.

6. The method for reducing the accuracy requirement of misalignment as described in claim 5, characterized in that, The silicon layer thickness of the strip waveguide region and the ridge waveguide region is the same as the top silicon thickness of the SOI material wafer, while the silicon layer thickness of the transition region and the ridge waveguide plate region is less than the top silicon thickness of the SOI material wafer.

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