A method of address remapping for a memory controller

Abstract

The application is suitable for the field of digital integrated circuit design, and provides a storage controller access address remapping method, which comprises the following steps: loading a defect remapping flag bit vector of a normal data word stored in a memory and a defect remapping flag bit vector of a redundant data word into an internal register of the storage controller; acquiring the number of available redundant data words and an address offset vector according to the defect remapping flag bit vector of the redundant data word; calculating an address remapping number value of the normal data word according to the defect remapping flag bit vector of the normal data word; calculating a remapping address of the normal data word after address remapping according to the address offset vector and the address remapping number value; and performing access address remapping on the normal data word according to the number of available redundant data words and the address remapping number value.

Description

Technical Field

[0001] This application belongs to the field of digital integrated circuit design, and in particular relates to a method for remapping memory controller access addresses. Background Technology

[0002] Currently, the integrated design of non-volatile memory (a special type of computer storage device characterized by its ability to retain data for a long time in the event of power failure or power outage) such as Programmable Read-Only Memory (PROM), especially in various high-reliability and ruggedized designs, results in a relatively high resource consumption of its storage. Therefore, it is crucial to utilize its storage space as much as possible and reduce unnecessary storage capacity consumption.

[0003] To address potential manufacturing defects in the production of such memory, redundant storage data blocks are often required. This allows for the remapping of memory access addresses when manufacturing defects are detected, remapping the defective storage addresses to reserved redundant storage data blocks, thereby improving the manufacturing yield of memory products.

[0004] Current redundant storage block address remapping schemes mostly require saving the storage addresses with manufacturing defects, along with the corresponding redundant storage block enable flags, to an additional dedicated storage space. During memory access, the storage controller first needs to determine if the currently accessed address is a defective address stored in that storage space, and whether the redundant storage block enable flag is valid, before deciding whether to remap the current access address to the corresponding redundant storage block. This scheme consumes additional storage resources to store the storage addresses with manufacturing defects and the redundant storage block enable flags, and the more redundant and defective data blocks that can be remapped, the more additional storage resources are consumed. Summary of the Invention

[0005] This application provides a storage controller access address remapping method that can solve the problem of high memory consumption in traditional address remapping methods.

[0006] This application provides a memory controller access address remapping method, applied to non-volatile memory, the non-volatile memory including memory and memory controller, including:

[0007] The memory controller loads the defect remapping flag vectors of ordinary data words and redundant data words in the memory into its own internal registers, and can perform address remapping for access to defective addresses when there are manufacturing defects in the non-volatile memory.

[0008] The storage controller calculates the number of usable redundant data words and the address offset vector in the redundant data words based on the defect remapping flag bit vector of the redundant data words.

[0009] The storage controller calculates the address remapping number value of a normal data word based on the defect remapping flag bit vector of the normal data word; the address remapping number value of the normal data word is used to indicate whether the normal data word is to be accessed for address remapping, and the address of the target redundant data word to be accessed for address remapping.

[0010] The storage controller calculates the remapped address of a normal data word after address remapping based on the address offset vector and the address remapping number value;

[0011] The storage controller performs access address remapping on ordinary data words based on the number of available redundant data words and the address remapping number value.

[0012] Optionally, based on the defect remapping flag vector of the redundant data word, the number of usable redundant data words and the address offset vector in the redundant data word are obtained, including:

[0013] The state of each bit in the defect remapping flag vector of the redundant data word is determined sequentially; the defect remapping flag vector of the redundant data word includes four bits, and the state of each bit is zero or one.

[0014] The number of bits with a state of zero in the defect remapping flag bit vector of the redundant data words is counted, and the number of bits with a state of zero is taken as the number of usable redundant data words.

[0015] Obtain the address offset of each bit with a zero state, and use the address offset as an address offset vector component to obtain the address offset vector.

[0016] Optionally, based on the defect remapping flag bit vector of the ordinary data word, the address remapping number value of the ordinary data word is calculated, including:

[0017] Through calculation formula

[0018] RVAL[i]=RVAL[i-1]+RAF[i](0 <i≤31,RVAL[0]=RAF[0])

[0019] Obtain the address remapping number value RVAL[i] of the i-th ordinary data word; where RAF[i] represents the defect remapping flag bit vector of the i-th ordinary data word.

[0020] Optionally, based on the address offset vector and the address remapping number value, the remapped address of the ordinary data word after address remapping is calculated, including:

[0021] Through calculation formula

[0022] RA = RBA + ROFFSET[(RVAL-1)]

[0023] Obtain the remapped address RA of the currently accessed address; where RBA represents the base address of the redundant data word segment.

[0024] The above-mentioned solution in this application has the following beneficial effects:

[0025] The storage controller access address remapping method provided in this application, when a manufacturing defect is detected in the non-volatile memory, can remap the access to the defective remapping address to the normal redundant spare data word space. The storage controller loads the defective remapping flag vectors of ordinary data words and redundant data words into its internal registers. Then, based on the defective remapping flag vector of the redundant data words, it obtains the number of available redundant data words and the address offset vector, respectively. Next, based on the defective remapping flag vector of the ordinary data words, it calculates the address remapping number value of the ordinary data words. Subsequently, based on the address offset vector and the address remapping number value, it calculates the remapped address of the ordinary data words after address remapping. Finally, based on the number of available redundant data words and the address remapping number value, it performs access address remapping for the ordinary data words. Compared with traditional address remapping methods, this storage controller access address remapping method only saves the defective remapping flags of ordinary and redundant data words, without needing to separately save the storage address of the manufacturing defect, thus reducing memory consumption and saving storage resources.

[0026] Other beneficial effects of this application will be described in detail in the following detailed description section. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a flowchart of a storage controller access address remapping method provided in an embodiment of this application. Detailed Implementation

[0029] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0030] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0031] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0032] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0033] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0034] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0035] To address the high memory consumption of traditional address remapping methods, this application provides a storage controller address remapping method. When a manufacturing defect is detected in a non-volatile memory, the access to the defective remapping address can be remapped to the normal redundant spare data word space. The storage controller loads the defective remapping flag vectors of ordinary data words and redundant data words into its internal registers. Then, based on the defective remapping flag vector of the redundant data words, it obtains the number of available redundant data words and the address offset vector. Next, based on the defective remapping flag vector of the ordinary data words, it calculates the address remapping number value of the ordinary data words. Subsequently, based on the address offset vector and the address remapping number value, it calculates the remapped address of the ordinary data words after address remapping. Finally, based on the number of available redundant data words and the address remapping number value, it performs access address remapping on the ordinary data words. Compared to traditional address remapping methods, this storage controller address remapping method only needs to save the defective remapping flags of ordinary and redundant data words, eliminating the need to separately save the manufacturing defect storage address, thus reducing memory consumption and saving storage resources.

[0036] It should be noted that during the manufacturing process of non-volatile memory (NVM), defects may occur due to factors such as materials and processes. For example:

[0037] Bit errors can occur in memory cells in NVM due to material issues or current leakage.

[0038] Memory cell loss error: During the NVM manufacturing process, some memory cells may lose functionality, resulting in a reduction in the overall memory capacity. This loss of functionality is usually caused by errors in materials, physical structure, or manufacturing process.

[0039] Read / write latency in NVM can be affected by various manufacturing defects. For example, in some flash memory, different memory regions within the chip may have different read / write speeds. These latencies may be caused by weak circuit connections, variations in component parameters, or other reasons.

[0040] Deviations, due to variations in the manufacturing process, may exist between different NVM chips or memory cells. These differences can cause memory performance to vary between different chips / cells.

[0041] When the aforementioned manufacturing defects are detected in the memory, the memory access addresses should be remapped in a timely manner to remap the data in the memory addresses with manufacturing defects to the normal areas, thereby improving the production quality of memory products.

[0042] like Figure 1 As shown, the storage controller access address remapping method includes the following steps:

[0043] Step 11: The memory controller loads the defect remapping flag vectors of ordinary data words and redundant data words in the memory into its internal registers. When there are manufacturing defects in the non-volatile memory, address remapping can be performed on accesses to defective addresses.

[0044] The defect remapping flag bit vector for redundant data words is used, and the defect remapping flag bit vector for ordinary data words is used.

[0045] In the embodiments of this application, the aforementioned reset signal may be an electronic pulse, voltage change, or other signal, and its function is to trigger the memory to reset and release.

[0046] It should be understood that in non-volatile memory, the memory controller and the memory are connected via a system bus.

[0047] A memory controller is a hardware or software module in a computer system responsible for controlling memory operations. It performs data reading and writing operations with the processor and external devices, and coordinates memory access and data transfer. It is responsible for handling memory requests, managing the memory address space, performing memory read and write operations, and implementing functions such as memory cache management, error detection and correction, and memory mapping.

[0048] Memory is a device or component used to store and retrieve data. In computer systems, memory is typically used to store programs, data, and temporary results.

[0049] Step 12: The storage controller calculates the number of usable redundant data words and the address offset vector in the redundant data words based on the defect remapping flag vector of the redundant data words.

[0050] The specific process of step 12 is illustrated below:

[0051] Step 12.1: Sequentially determine the state of each bit in the defect remapping flag vector.

[0052] In the embodiments of this application, the defect remapping flag bit vector of the redundant data word includes four bits, and the state of each bit is zero or one.

[0053] In the embodiments of this application, the defect remapping flag vector of redundant data words can be represented as RRF[3:0], which represents a vector containing four elements (RRF[3], RRF[2], RRF[1], RRF[0]), where each element has a width of 4 bits. RRF represents Register File, and [3:0] represents the selection bit range, i.e., from bit 3 to bit 0. If the memory is in a 32-bit computer architecture, the defect remapping flag of redundant data words requires 4×32 bits of storage space.

[0054] Step 12.2: Count the number of bits with a state of zero in the defect remapping flag bit vector, and use the number of bits with a state of zero as the number of available redundant data words.

[0055] For example, in one embodiment of this application, a defect remapping flag bit vector is RRF[3:0]=4′b0010, which indicates that the second redundant data word is unavailable. At this time, the number of available redundant data words is 3 (initially 4), and the second available target redundant data word is the actual third redundant data word.

[0056] Step 12.3: Obtain the address offset of each bit with a state of zero, and use the address offset as an address offset vector component to obtain the address offset vector.

[0057] According to step 12.2 above, when the defect remapping flag bit vector is RRF[3:0]=4′b0010, the address offset of the subsequent available redundant data words is shifted one address to the right. That is, the address offset of the first available redundant data word is ROFFSET[0]=0, the address offset of the second available redundant data word is ROFFSET[1]=2, the address offset of the third available redundant data word is ROFFSET[2]=3, there is no fourth available redundant data word, and ROFFSET[3] will not be used.

[0058] Step 13: The storage controller calculates the address remapping number value of the ordinary data word based on the defect remapping flag bit vector of the ordinary data word.

[0059] The address remapping number value of a normal data word is used to indicate whether the normal data word is subject to access address remapping, and the target redundant data word address for access address remapping.

[0060] Specifically, through calculation formula

[0061] RVAL[i]=RVAL[i-1]+RAF[i](0 <i≤31,RVAL[0]=RAF[0])

[0062] Obtaining an address remapping number value RVAL[i] of the i-th ordinary data word; wherein RAF[i] represents a defect remapping flag bit vector of the i-th ordinary data word.

[0063] When RVAL[i] (i=0, 1, ..., 31) ≤ RNUM, RVAL[i] (i=0, 1, ..., 31) will be used as a pointer to ROFFSET[j] (j=0, ..., 3), indicating the target redundant data word address for access address remapping.

[0064] Step 14: the memory controller calculates the remapped address of the ordinary data word after address remapping according to the address offset vector and the address remapping number value.

[0065] Specifically, through the calculation formula

[0066] RA=RBA+ROFFSET[(RVAL-1)]

[0067] the remapped address RA is obtained; wherein RBA represents the base address of the redundant data word block.

[0068] Step 15: the memory controller performs access address remapping on the ordinary data word according to the number of available redundant data words and the address remapping number value.

[0069] For example, according to the address remapping number value, the memory controller remaps the access address of the ordinary data word to the corresponding redundant data word. In this way, the memory controller can read the redundant data word to obtain backup data.

[0070] It should be noted that, in the embodiment of the present application, when the ordinary data word defect remapping flag satisfies 0 < RVAL[i] ≤ RNUM, the memory controller preferentially remaps ordinary defective data words at lower addresses (a lower address refers to an address with a smaller address number value, for example, there are 32 word addresses from 0 to 31, if there are defective addresses at the same time, remapping is preferentially performed from address 0 to 32 to the redundant data word space until all available redundant data word space is used up). When the ordinary data word defect remapping flag exceeds the number of available redundant data words, it indicates that the redundant space data word is full at this time, and access address remapping will be temporarily stopped until a new available redundant data word appears.

[0071] As can be seen, the memory controller access address remapping method provided in this application, when a manufacturing defect is detected in the non-volatile memory, can remap the access to the defective remapped address to the normal redundant spare data word space. The memory controller loads the defective remapped flag bit vectors of the ordinary data word and the redundant data word into its internal register. Then, based on the defective remapped flag bit vector of the redundant data word, it obtains the number of available redundant data words and the address offset vector, respectively. Then, based on the defective remapped flag bit vector of the ordinary data word, it calculates the address remapped number value of the ordinary data word. Subsequently, based on the address offset vector and the address remapped number value, it calculates the remapped address of the ordinary data word after address remapping. Finally, based on the number of available redundant data words and the address remapped number value, it performs access address remapping for the ordinary data word. Compared with traditional address remapping methods, this memory controller access address remapping method only saves the defective remapped flag bits of the ordinary data word and the redundant data word, without needing to additionally save the manufacturing defect memory address, thus reducing memory consumption and saving storage resources.

[0072] The above description is the preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principles described in this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A memory controller access address remapping method, applied to a non-volatile memory, the non-volatile memory comprising a memory and a memory controller, characterized in that, The storage controller access address remapping method includes: The storage controller loads a vector consisting of defect remapping flags for each ordinary data word in the memory and a vector consisting of defect remapping flags for redundant data words into its internal register, so that when there is a manufacturing defect in the non-volatile memory, address remapping can be performed on accesses to defective addresses. The storage controller calculates the number of usable redundant data words and the address offset vector in the redundant data words based on the defect remapping flag vector of the redundant data words. The storage controller calculates the address remapping number value of the ordinary data word based on the vector formed by the defect remapping flag bits of each ordinary data word in the memory; the address remapping number value of the ordinary data word is used to indicate whether the ordinary data word is to be accessed for address remapping, and the target redundant data word address for accessing for address remapping. The storage controller calculates the remapped address of the ordinary data word after address remapping based on the address offset vector and the address remapping number value; When the address remapping number value of the ordinary data word is greater than zero and not greater than the number of available redundant data words, the storage controller remaps the access address of the ordinary data word to the remapped address.

2. The storage controller access address remapping method according to claim 1, characterized in that, The step of obtaining the number of usable redundant data words and the address offset vector in the redundant data words based on the defect remapping flag bit vector of the redundant data words includes: The state of each bit in the defect remapping flag vector is determined sequentially; the defect remapping flag vector includes four bits, and the state of each bit is zero or one. The number of bits with a state of zero in the defect remapping flag bit vector is counted, and the number of bits with a state of zero is used as the number of available redundant data words. Obtain the address offset of each bit with a state of zero, and use the address offset as an address offset vector component to obtain the address offset vector.

3. The storage controller access address remapping method according to claim 2, characterized in that, The step of calculating the address remapping number value of the ordinary data word based on the vector formed by the defect remapping flag bits of each ordinary data word in the memory includes: Through calculation formula Get the first Address remapping number value of a normal data word ;in, Indicates the first Defect remapping flag for a regular data word.

4. The storage controller access address remapping method according to claim 3, characterized in that, The step of calculating the remapped address of the ordinary data word after address remapping based on the address offset vector and the address remapping number value includes: Through calculation formula Get the remapped address of the currently accessed ordinary data word after address remapping. ; where RBA represents the base address of the redundant data word segment.

Images