Escaping wiring method, device and electronic equipment of analog circuit

Abstract

The application provides an escape routing method and device of an analog circuit and electronic equipment, and relates to the technical field of integrated circuits. The method comprises the following steps: determining a routing pin to be subjected to escape routing and a corresponding electrical node in a circuit; generating a plurality of edge rectangles in a circuit layout and assigning priorities, levels and electrical nodes to the edge rectangles; constructing a physical verification set of the circuit layout based on the circuit and the routing pin, and then verifying the routing pin based on the physical verification set; generating a routing sequence according to the routing pin and the corresponding electrical node; and performing escape routing on the routing pin in the circuit based on the routing sequence and preset routing rules. Thus, the routing efficiency can be significantly improved, and the routing process is more efficient. In the routing process, the physical verification constraint is considered, the routing result is ensured to meet the design specification and constraint condition, the subsequent physical verification problem is avoided, and the compliance of the circuit routing is ensured.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an escape wiring method, apparatus and electronic device for analog circuits. Background Technology

[0002] Integrated circuits have become a strategic industry development direction. However, integrated circuit design is costly and time-consuming. Developing a single chip often requires hundreds of specialized integrated circuit engineers to complete a year or even longer. This is because the existing integrated circuit design process is lengthy. For example, for digital integrated circuits, it requires RTL design, RTL synthesis, placement and clock tree synthesis, and routing. Each stage requires specialized engineers. The situation is similar for analog circuits. Considering that SoCs (System-on-a-Chip) include both digital and analog circuits, the combination of the two requires additional verification work. Therefore, integrated circuit companies generally need a large number of specialized engineers. On the one hand, specialized integrated circuit engineers need systematic training in electrical engineering and 3-5 years of master's or doctoral research training, thus also facing high costs and long development cycles. Furthermore, from a global perspective, emerging fields such as the internet attract a large number of outstanding graduates, making integrated circuit design not the first choice for graduates from top universities. This further exacerbates the talent shortage. The solution is to further improve the automation of integrated circuit design, thereby reducing the demand for specialized talent.

[0003] In analog circuits, under certain circumstances, due to noise and interference, routing on the upper metal layer of a sub-circuit is not permitted. In such cases, routing must be performed using channels between sub-circuits. The first step in this method is to use escape routing in analog circuits. However, the escape routing problem in analog circuits is difficult to abstract into a mathematical problem, and traditional linear programming-based approaches are no longer applicable. Summary of the Invention

[0004] This application provides an escape wiring method, apparatus, and electronic device for analog circuits, aiming to at least partially solve one of the technical problems in the related art.

[0005] In a first aspect, this application provides an escape wiring method for analog circuits, comprising:

[0006] Identify the wiring pins and corresponding electrical nodes in the circuit to be escaped;

[0007] Multiple edge rectangles are generated in the circuit layout, and priority, level and electrical nodes are assigned to the edge rectangles;

[0008] Based on the circuit and the wiring pins, a physical verification set for the circuit layout is constructed, and then the wiring pins are verified based on the physical verification set.

[0009] Generate a wiring sequence based on the wiring pins and their corresponding electrical nodes;

[0010] Based on the wiring sequence and preset wiring rules, escape wiring is performed on the wiring pins in the circuit.

[0011] Secondly, this application provides an escape wiring device for an analog circuit, comprising:

[0012] The determination module is used to determine the wiring pins and corresponding electrical nodes in the circuit to be escaped wiring;

[0013] The first generation module is used to generate multiple edge rectangles in the circuit layout and assign priority, level and electrical nodes to the edge rectangles;

[0014] The verification module is used to construct a physical verification set for the circuit layout based on the circuit and the wiring pins, and then verify the wiring pins based on the physical verification set.

[0015] The second generation module is used to generate a wiring sequence based on the wiring pins and the corresponding electrical nodes;

[0016] The wiring module is used to perform escape wiring on the wiring pins in the circuit based on the wiring sequence and preset wiring rules.

[0017] Thirdly, this application provides an electronic device, including: a processor; a memory for storing processor-executable instructions; wherein the processor is configured to execute instructions to implement an escape wiring method for analog circuits.

[0018] Fourthly, this application provides a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform an escape wiring method for analog circuits.

[0019] Fifthly, this application provides a computer program product, including a computer program, wherein the computer program is executed by a processor to implement an escape wiring method for analog circuits.

[0020] In this embodiment, the routing pins to be escaped and their corresponding electrical nodes in the circuit are first determined. Then, multiple edge rectangles are generated in the circuit layout, and priority, level, and electrical nodes are assigned to the edge rectangles. Next, a physical verification set for the circuit layout is constructed based on the circuit and the routing pins. Then, the routing pins are verified based on the physical verification set. Then, a routing sequence is generated according to the routing pins and their corresponding electrical nodes. Finally, escape routing is performed on the routing pins in the circuit based on the routing sequence and preset routing rules. Thus, routing pins in sub-circuits can be connected to the edges, allowing the aforementioned channel routing to ignore the complexity of the sub-circuit. Compared to escape routing on printed circuit boards, escape routing in analog circuits considers constraints such as different line widths, the number of vias, and design rule checks. It is more complex in circuit layouts, with significant variations in the size and spacing of routing pins, and also has characteristics such as cross-layer routing. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0022] Figure 1 This is a schematic flowchart illustrating an escape wiring method for an analog circuit according to an embodiment of this application;

[0023] Figure 2 This is a first type of circuit diagram showing the escape wiring of an analog circuit according to an embodiment of this application;

[0024] Figure 3 This is a second circuit diagram of the escape wiring of the analog circuit shown in the embodiments of this application;

[0025] Figure 4 This is a block diagram of an escape wiring device for an analog circuit according to this application;

[0026] Figure 5 A block diagram of an exemplary electronic device suitable for implementing embodiments of the present application is shown.

[0027] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0028] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Rather, the embodiments of this application include all variations, modifications, and equivalents falling within the spirit and scope of the appended claims.

[0029] Figure 1 This is a schematic flowchart of the escape wiring method for an analog circuit according to the first embodiment of this application, as shown below. Figure 1 As shown, the method includes:

[0030] S101, determine the wiring pins and corresponding electrical nodes in the circuit to be escaped.

[0031] Specifically, the connection methods and relationships of each component in the circuit can be determined first based on the circuit topology, including power supplies, signal sources, resistors, capacitors, inductors, etc. Then, the wiring pins can be determined, and their locations can be specified based on the circuit component datasheets or design documents. Typically, wiring pins correspond to the pins of circuit components, and they are used to transmit signals to other components or external connectors. In a circuit, an electrical node is a set of connection points with the same voltage. By analyzing the circuit's connection relationships, it can be determined which wiring pins belong to the same electrical node. Furthermore, wiring pins that need to be escaped can be identified by analyzing the signal transmission paths and wiring rules in the circuit. Escape typically occurs when signals need to cross long distances or connect to other circuit boards.

[0032] S102 generates multiple edge rectangles in the circuit layout and assigns priority, level and electrical nodes to the edge rectangles.

[0033] Specifically, you can first determine the size of the circuit layout, including its width (x-axis direction) and height (y-axis direction), as the basis for generating the edge rectangles. Create the top edge rectangle: Based on the width of the circuit layout, create a horizontal rectangle above the layout with the same width as the layout; the height can be adjusted as needed. Create the right edge rectangle: Based on the height of the circuit layout, create a vertical rectangle on the right side of the layout with the same height as the layout; the width can be adjusted as needed. Create the bottom edge rectangle: Based on the width of the circuit layout, create a horizontal rectangle below the layout with the same width as the layout; the height can be adjusted as needed. Create the left edge rectangle: Based on the height of the circuit layout, create a vertical rectangle on the left side of the layout with the same height as the layout; the width can be adjusted as needed.

[0034] Optionally, edge rectangles can be generated around the circuit layout according to its size. Then, the priority of the edge rectangles at the top and bottom edges of the circuit layout can be assigned horizontally, and the priority of the edge rectangles at the right and left edges can be assigned vertically. Then, the first level of each edge rectangle in the circuit layout and the priority corresponding to the first level can be determined. If the priority of any edge rectangle is opposite to the priority of the corresponding first level, the current level corresponding to any edge rectangle is determined to be the first level. Then, the number of edge rectangles assigned to the first level is updated according to the number of electrical nodes in the circuit layout.

[0035] The first level can be the level corresponding to any edge rectangle.

[0036] Specifically, the top and bottom edge rectangles can be prioritized horizontally, while the right and left edge rectangles can be prioritized vertically. Then, the first level of each edge rectangle in the circuit layout can be determined, and this first level is the opposite of its corresponding priority. In this case, the current level corresponding to any edge rectangle can be determined as the first level.

[0037] In other words, the priority direction for each layer is first determined. For example, the routing priority for layer M1 is vertical. For each planar edge rectangle, its priority direction is compared to the priority direction of the current layer. If the priority direction of the planar edge rectangle is opposite to the priority direction of the current layer, then the planar edge rectangle is assigned the information of the current layer. For example, if the routing priority for layer M1 is vertical, and the priority direction of the top and bottom edge rectangles is horizontal, then these edge rectangles will be assigned the information of layer M1 to ensure that routing is performed in accordance with the priority direction. Since the priority direction of the left and right edge rectangles is vertical, these edge rectangles will not be assigned the information of layer M1.

[0038] Furthermore, the number of rectangles assigned hierarchical information can be determined. For example, if rectangle A is not assigned hierarchical information, but rectangles B and C are, the number of rectangles B and C can be increased to N and stored in memory. Here, N is the number of electrical nodes in the circuit layout.

[0039] like Figure 2 In the circuit diagram shown, the horizontal edge rectangle of M3 refers to the edge rectangle with a horizontal priority direction at the M3 level, and the vertical edge rectangle of M2 refers to the edge rectangle with a vertical priority direction at the M2 level.

[0040] In escape routing of analog circuits, horizontal and vertical traction lines refer to wiring conductors used to connect different functional modules or signal paths. Horizontal traction lines are used to cross short distances on the circuit board, connecting different logic gates, registers, circuit elements, etc. Horizontal traction lines are primarily responsible for signal transmission and connection in the horizontal direction of the circuit board to achieve communication and data transmission between different functional units. Vertical traction lines, in contrast to horizontal traction lines, are mainly used to connect signal transmission between different areas on the circuit board. They are typically used to cross larger distances, connecting different boards, different functional areas, or different levels of signal transmission. They can effectively connect various functional modules, realizing the transmission and exchange of signals in the circuit. When performing escape routing, reasonable planning and layout of horizontal and vertical traction lines can effectively optimize the wiring structure, improve signal transmission efficiency, reduce signal interference, and ultimately achieve design requirements.

[0041] like Figure 3 In the circuit diagram shown, the vertical traction line of M3 and the horizontal traction line of M2 can be the horizontal traction line corresponding to any wiring pin of the M3 level and the vertical traction line corresponding to any wiring pin of the M2 level, respectively.

[0042] S103 constructs a physical verification set for the circuit layout based on the circuit and routing pins, and then verifies the routing pins based on the physical verification set.

[0043] Optionally, sub-circuits and routing pins in the circuit can be added to a hierarchical space index set based on RTree to address the issue of upper-level circuits being unable to access content when placing sub-circuits in the circuit layout. Adding sub-circuits and routing pins to the space index set allows for better management and retrieval, ensuring the integrity of physical verification. The physical verification set can perform short-circuit checks and design rule checks on routing pins. Short-circuit checks ensure that there are no short circuits between pins that should not be connected. Design rule checks verify that routing pins comply with process specifications and design requirements.

[0044] Furthermore, a spatial lookup can be performed on the routing pins. If a pin collides with another routing pin, and these pins have the same electrical node, and one of the lengths and widths of their intersecting rectangles conforms to the minimum linewidth of the current process (i.e., not less than the minimum linewidth of the current process), then they can be placed in the same disjoint-setup. This ensures that these pins meet good contact conditions and can be correctly connected during routing.

[0045] Optionally, each sub-circuit in the circuit and the wiring pin can be added to a hierarchical spatial index set based on RTree to form a physical verification set, and the wiring pin can be short-circuit checked and design rule checked based on the physical verification set.

[0046] Each sub-circuit and the wiring pin in the circuit can be added to a hierarchical spatial index set based on RT-Ree to form a physical verification set. Adding sub-circuits and wiring pins to the spatial index set allows for better management and retrieval, ensuring the integrity of the physical verification. Specifically, an RT-Ree-based spatial indexing algorithm can be used to organize and group all sub-circuits and wiring pins according to their location information, forming a hierarchical spatial index set. Short-circuit checks and design rule checks are performed on the wiring pins based on this physical verification set. During short-circuit checks, the location information and interrelationships in the hierarchical spatial index set are used to check for short circuits that should not exist between wiring pins. During design rule checks, known process rules and design requirements, along with the location information and interrelationships in the hierarchical spatial index set, are used to verify each wiring pin to ensure compliance with design rules and process requirements.

[0047] S104 generates a wiring sequence based on the wiring pins and their corresponding electrical nodes.

[0048] Specifically, the routing pins can be initialized by treating several routing pins belonging to the same disjoint-set data structure as one set, and all edge rectangles of the same electrical node as another set. The initialized sets are then used as nodes in the minimum spanning tree. Finally, for each pair of rectangles in the two sets, their weights are calculated using the following formula:

[0049] Weight = d / (q+l1+l2+p)+1

[0050] Where d is the Manhattan distance between the rectangles, q and p are the priorities of the current routing pins of the two rectangles, and l1 and l2 are the level indices of the current routing pins of the two rectangles.

[0051] Furthermore, a minimum spanning tree can be constructed based on the calculated weights. This can be achieved using common minimum spanning tree algorithms (such as Prim's algorithm or Kruskal's algorithm). When constructing the minimum spanning tree, edges with the minimum weights are selected to connect nodes in the set until all nodes are connected. The resulting minimum spanning tree is the routing sequence. This sequence determines the connection relationships between routing pins according to the order of the connecting edges. Pins can be routed sequentially according to the connection order of the minimum spanning tree to meet the requirements of the multi-terminal net assignment formula.

[0052] It is important to note that the priority and level index values ​​of the routing pins need to be set according to the specific configuration, and an appropriate minimum spanning tree algorithm should be selected to construct the minimum spanning tree.

[0053] Optionally, the wiring pins can be initialized first to obtain multiple sets. The wiring pins belonging to the same disjoint set are grouped into one set, and the edge rectangles belonging to the same electrical node are placed in the same set. Then, each set can be used as a node of the minimum spanning tree, and the elements between any two sets are paired. The weight of a pair of rectangles in the two sets is calculated according to a preset formula. The calculated weights are then used to construct the minimum spanning tree. The edge with the smallest weight is added to the minimum spanning tree, and this step is repeated until all nodes are connected. Then, the wiring pins in the set represented by each node are connected according to the order of the sets they belong to, in order to form a wiring sequence.

[0054] Before initializing the wiring pins to obtain multiple sets, a spatial query can be performed on each wiring pin. If the first wiring pin and the second wiring pin are in contact, and the length and width of the rectangle where the first wiring pin and the second wiring pin intersect satisfy the target linewidth corresponding to the current process, then the first wiring pin and the second wiring pin are placed in the same set of union and difference, wherein the electrical nodes corresponding to the first wiring pin and the second wiring pin are the same.

[0055] For example, given an array [(1,2),(3,4,5),(6,7)] containing various sets, (1,2) refers to one of these sets. These sets contain three elements, and their pairwise weights can be calculated to generate a minimum spanning tree. For example, (3,4,5)-(1,2)-(6,7). In this example, (1,2) is the root node of the minimum spanning tree. The sequence to be connected is (3,4,5)-(1,2)(1,2)-(6,7). In the above example, assuming (3,4,5)-(1,2) is being routed, the elements in each set must first be selected according to the algorithm, for example, 4 and 1, before routing. Since the rectangles within the sets are already connected, breaking them apart would result in meaningless routing. Therefore, it's better to select a set first and then a rectangle. This helps generate routing sequences more efficiently and optimizes the quality of the routing results. In practical applications, appropriate parameter configurations and algorithm selections are needed for different circuit designs to achieve the optimal routing effect.

[0056] S105 performs escape routing on the wiring pins in the circuit based on the wiring sequence and preset wiring rules.

[0057] Optionally, escape routing can be performed on the routing pins in the circuit based on the A* algorithm dual-ended net router and the routing sequence.

[0058] It should be noted that the A* algorithm-based two-ended net router can effectively solve the escape routing problem. After the routing sequence is generated, the A* algorithm can be used for escape routing. Escape routing refers to the process of routing pins from the core area of ​​the circuit to the surrounding edge area or other specific areas.

[0059] Here is a possible escape wiring procedure:

[0060] For routing pins that need to escape, their initial and target positions can be determined based on their set (nodes in the minimum spanning tree). The initial position can be a suitable point near the core region, while the target position can be an edge region or other specific region. A two-ended net router using the A* algorithm searches for paths simultaneously from both the initial and target positions. The A* algorithm estimates the cost from the current position to the target position using a heuristic function and selects the path with the minimum cost for expansion. During routing, different weighting factors, such as path length, line width, and impedance, can be considered to improve routing performance and quality. The interconnection relationships and constraints between routing pins need to be considered during the A* algorithm's search. This can be achieved by introducing appropriate path constraints, priority rules, and conflict handling strategies. For example, minimum distances and maximum line length limits can be set between routing pins. Once a path that meets the requirements is found, the segments along that path can be connected to complete the escape routing. Simultaneously, the set information of the routing pins needs to be updated for subsequent routing operations. Through this escape routing process, congested routing pins in the core region can be successfully routed to edge regions or other specific regions to meet design requirements and routing constraints. This can effectively improve the success rate and overall quality of routing. It should be noted that escape routing may involve different circuit designs and routing constraints; therefore, the specific implementation methods and parameter settings need to be adjusted and optimized according to the actual situation.

[0061] Specifically, pin analysis can be performed first to determine the restricted area between the routing start pin and the routing target pin, and to separate the pin from the invalid area. Then, the separated rectangles are discretized into triplet rectangles, ensuring that the discretized points are located on the routing grid. Next, two priority queues are set up: one to store the starting grid points of the routing start pin, and the other to store points generated during the routing process. The point set is then subjected to a cost function calculation and placed into the corresponding priority queue. Further, pattern routing and waveform diffusion can be performed: when a point is retrieved from the priority queue, if it is the starting point, pattern routing is performed. If pattern routing is successful, waveform diffusion is performed. If routing fails, the point is discarded. Waveform diffusion is divided into vertical and horizontal expansion. Vertical expansion traverses the via list according to the priority direction of each layer, satisfying the metal layer constraints and considering via spacing limitations. In vertical expansion, it is necessary to query the global physical verification dataset and the via set on the path to determine whether the via spacing meets the constraints. This can be queried through the physical verification API, and the vias on the path are traversed using a backtracking method for judgment.

[0062] Optionally, based on the routing sequence, a restricted routing region between the starting pin and the target pin can be detected and segmented. Then, the edge rectangles are discretized into triplet rectangles, ensuring each triplet is positioned above the routing grid. A first priority queue and a second priority queue are then established. The first priority queue stores the starting grid point of the routing starting pin, and the second priority queue stores points generated during the routing process. The A* algorithm can then be used, based on a cost function and a heuristic function, to move progressively from the routing starting pin towards the routing target pin. At each step, an optimal next point is selected to expand the search space and update the path, enabling escape routing of the pins in the circuit. After setting the first and second priority queues, the process further includes: in response to retrieving a starting grid point from the first priority queue, pattern routing is performed based on the path between the starting grid point and the routing target pin to determine if a feasible path exists. If routing is successful, waveform diffusion is performed based on the starting grid point; otherwise, the currently retrieved starting grid point is discarded. The waveform diffusion method includes vertical and horizontal expansion.

[0063] In horizontal expansion, the cost function of Algorithm A for expansion in four directions is (1-w)g+w*h. Here, w = g / (g+e*h), where g is the estimated cost, h is the historical cost, and e is the historical cost coefficient, determined by the current search point's state. Line search optimization can only be performed when the expansion direction faces the target rectangle and satisfies the priority direction. Line search optimization involves increasing the diffusion step size to the target point. However, physical verification constraints may be violated during expansion, so it's necessary to quickly find the farthest rectangle that satisfies the physical verification design constraints. In this case, a bisection method can be used for optimization, which can significantly improve runtime efficiency.

[0064] In this embodiment, the routing pins to be escaped and their corresponding electrical nodes in the circuit are first determined. Then, multiple edge rectangles are generated in the circuit layout, and priority, level, and electrical nodes are assigned to these edge rectangles. Next, a physical verification set for the circuit layout is constructed based on the circuit and the routing pins. Then, the routing pins are verified based on the physical verification set. Next, a routing sequence is generated according to the routing pins and their corresponding electrical nodes. Finally, escape routing is performed on the routing pins in the circuit based on the routing sequence and preset routing rules. Thus, routing pins in sub-circuits can be connected to the edges, allowing the aforementioned channel routing to ignore the complexity of the sub-circuit. Compared to escape routing on printed circuit boards, the escape routing of the analog circuit in this embodiment considers constraints such as different line widths, the number of vias, and design rule checks. When performing escape routing, it can achieve automated and reasonable routing even when the circuit layout is complex and the size and spacing of the routing pins vary significantly. The routing efficiency is high, the error rate is low, and it meets design requirements and various constraints in the circuit.

[0065] Employing the cost function and line search optimization of the A* algorithm, paths satisfying physical verification design constraints can be quickly found during routing, and the diffusion step size can be increased to the target point. Simultaneously, optimization using the bisection method significantly improves operational efficiency, making the routing process more efficient. Physical verification constraints are considered during routing, ensuring that the routing results conform to design specifications and constraints, avoiding subsequent physical verification problems, and ensuring the compliance of circuit routing. Utilizing the cost function and historical cost coefficients of the A* algorithm, combined with line search optimization, makes the escape routing process more intelligent, enabling it to make corresponding decisions based on the state of the current search point, thus improving the intelligence level of routing. In conclusion, escape routing in this manner can improve the efficiency, compliance, and intelligence of the routing process, bringing numerous advantages to circuit design and routing work.

[0066] Figure 4This is a block diagram of an escape wiring device for an analog circuit according to this application, such as... Figure 4 As shown, the escape wiring device 200 of the analog circuit includes:

[0067] The determination module 210 is used to determine the wiring pins and corresponding electrical nodes in the circuit to be escaped wiring.

[0068] The first generation module 220 is used to generate multiple edge rectangles in the circuit layout and assign priority, level and electrical nodes to the edge rectangles.

[0069] Verification module 230 is used to construct a physical verification set for the circuit layout based on the circuit and the wiring pins, and then verify the wiring pins based on the physical verification set.

[0070] The second generation module 240 is used to generate a wiring sequence based on the wiring pins and the corresponding electrical nodes.

[0071] The wiring module 250 is used to perform escape wiring on the wiring pins in the circuit based on the wiring sequence and preset wiring rules.

[0072] Optionally, the first generation module 220 is specifically used for:

[0073] Based on the size of the circuit layout, generate edge rectangles around the circuit layout;

[0074] Assign the priority of the edge rectangles at the top and bottom edges of the circuit layout to horizontal, and assign the priority of the edge rectangles at the right and left edges of the circuit layout to vertical.

[0075] Determine the first level of each edge rectangle in the circuit layout, and the priority corresponding to the first level;

[0076] If the priority of any edge rectangle is opposite to the priority of the corresponding first level, then the level currently corresponding to any edge rectangle is determined to be the first level.

[0077] The number of any edge rectangle assigned to the first level is updated based on the number of electrical nodes in the circuit layout.

[0078] Optionally, the verification module is specifically used for:

[0079] Each sub-circuit in the circuit and the wiring pin are added to a hierarchical spatial index set based on RTree to form a physical verification set;

[0080] The wiring pins are short-circuit checked and design rule checked based on the physical verification set.

[0081] Optionally, the second generation module includes:

[0082] The processing unit is used to initialize the wiring pins to obtain multiple sets, wherein each wiring pin belonging to the same disjoint set is placed in one set, and each edge rectangle belonging to the same electrical node is placed in the same set.

[0083] The calculation unit is used to treat each set as a node of the minimum spanning tree, and to pair the elements between any two sets, and to calculate the weight of a pair of rectangles in the two sets according to a preset formula.

[0084] A building unit is used to construct the minimum spanning tree using the calculated weights, select the edge with the smallest weight and add it to the minimum spanning tree, and repeat this step until all nodes are connected;

[0085] The generation unit is used to connect the wiring pins in the set represented by each node according to the connection order of the minimum spanning tree, so as to form a wiring sequence.

[0086] Optionally, the processing unit is further configured to:

[0087] Perform a space query for each of the aforementioned wiring pins;

[0088] If the first wiring pin and the second wiring pin are in contact, and the length and width of the rectangle where the first wiring pin and the second wiring pin intersect satisfy the target linewidth corresponding to the current process, then the first wiring pin and the second wiring pin are placed in the same set of parallel differences, wherein the electrical nodes corresponding to the first wiring pin and the second wiring pin are the same.

[0089] Optionally, the wiring module 250 is specifically used for:

[0090] Based on the A* algorithm dual-ended net router and the routing sequence, escape routing is performed on the routing pins in the circuit.

[0091] Optionally, the wiring module 250 includes:

[0092] The detection unit is used to detect the restricted wiring region between the wiring start pin and the wiring target pin based on the wiring sequence, and to segment the restricted wiring region.

[0093] A discretization processing unit is used to discretize the edge rectangles to discretize each edge rectangle into a triplet rectangle, and keep the triplet above the grid points of the wiring.

[0094] The setting unit is used to set a first priority queue and a second priority queue, wherein the first priority queue stores the starting grid point of the wiring start pin, and the second priority queue stores the points generated during the wiring process.

[0095] The moving unit is used to use the A* algorithm, based on a cost function and a heuristic function, to move step by step from the starting pin of the wiring to the target pin of the wiring, wherein, in each step, an optimal next point is selected to expand the search space and the path is updated, so as to achieve escape wiring of the wiring pin in the circuit.

[0096] Optionally, the setting unit is further configured to:

[0097] In response to retrieving a starting grid point from the first priority queue, pattern routing is performed based on the path between the starting grid point and the routing target pin to determine whether a feasible path exists;

[0098] If the wiring is successful, waveform diffusion is performed based on the starting grid point; otherwise, the currently extracted starting grid point is discarded. The waveform diffusion method includes vertical expansion and horizontal expansion.

[0099] In this embodiment, the routing pins to be escaped and their corresponding electrical nodes in the circuit are first determined. Then, multiple edge rectangles are generated in the circuit layout, and priority, level, and electrical nodes are assigned to these edge rectangles. Next, a physical verification set for the circuit layout is constructed based on the circuit and the routing pins. Then, the routing pins are verified based on the physical verification set. Next, a routing sequence is generated according to the routing pins and their corresponding electrical nodes. Finally, escape routing is performed on the routing pins in the circuit based on the routing sequence and preset routing rules. Thus, routing pins in sub-circuits can be connected to the edges, allowing the aforementioned channel routing to ignore the complexity of the sub-circuit. Compared to escape routing on printed circuit boards, the escape routing of the analog circuit in this embodiment considers constraints such as different line widths, the number of vias, and design rule checks. When performing escape routing, it can achieve automated and reasonable routing even when the circuit layout is complex and the size and spacing of the routing pins vary significantly. The routing efficiency is high, the error rate is low, and it meets design requirements and various constraints in the circuit.

[0100] Employing the cost function and line search optimization of the A* algorithm, paths satisfying physical verification design constraints can be quickly found during routing, and the diffusion step size can be increased to the target point. Simultaneously, optimization using the bisection method significantly improves operational efficiency, making the routing process more efficient. Physical verification constraints are considered during routing, ensuring that the routing results conform to design specifications and constraints, avoiding subsequent physical verification problems, and ensuring the compliance of circuit routing. Utilizing the cost function and historical cost coefficients of the A* algorithm, combined with line search optimization, makes the escape routing process more intelligent, enabling it to make corresponding decisions based on the state of the current search point, thus improving the intelligence level of routing. In conclusion, escape routing in this manner can improve the efficiency, compliance, and intelligence of the routing process, bringing numerous advantages to circuit design and routing work.

[0101] To implement the above embodiments, this disclosure also proposes a computer device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the escape wiring method for analog circuits as proposed in the foregoing embodiments of this disclosure.

[0102] To implement the above embodiments, this disclosure also proposes a non-transitory computer-readable storage medium storing a computer program, which, when executed by a processor, implements the escape wiring method for analog circuits as proposed in the foregoing embodiments of this disclosure.

[0103] To implement the above embodiments, this disclosure also proposes a computer program product that, when executed by an instruction processor, performs an escape wiring method for analog circuits as described in the foregoing embodiments of this disclosure.

[0104] Figure 5 A block diagram of an exemplary computer device suitable for implementing embodiments of the present disclosure is shown. Figure 5 The computer device 12 shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0105] like Figure 5 As shown, the computer device 12 is represented in the form of a general-purpose computing device. The components of the computer device 12 may include, but are not limited to: one or more processors or processing units 16, system memory 28, and a bus 18 connecting different system components (including system memory 28 and processing unit 16).

[0106] Bus 18 represents one or more of several bus architectures, including a memory bus or memory controller, a peripheral bus, a graphics acceleration port, a processor, or a local bus using any of the various bus architectures. Examples of these architectures include, but are not limited to, the Industry Standard Architecture (ISA) bus, the Micro Channel Architecture (MAC) bus, the Enhanced ISA bus, the Video Electronics Standards Association (VESA) local bus, and the Peripheral Component Interconnect (PCI) bus.

[0107] Computer device 12 typically includes a variety of computer system readable media. These media can be any available media that can be accessed by computer device 12, including volatile and non-volatile media, removable and non-removable media.

[0108] Memory 28 may include computer system readable media in the form of volatile memory, such as Random Access Memory (RAM) 30 and / or cache memory 32. Computer device 12 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, storage system 34 may be used to read and write non-removable, non-volatile magnetic media (…). Figure 5 Not shown; usually referred to as a "hard drive"). Although Figure 5 Not shown, a disk drive for reading and writing to a removable non-volatile disk (e.g., a "floppy disk") and an optical disc drive for reading and writing to a removable non-volatile optical disc (e.g., a compact disc read-only memory (CD-ROM), a digital video disc read-only memory (DVD-ROM), or other optical media) may be provided. In these cases, each drive may be connected to bus 18 via one or more data media interfaces. Memory 28 may include at least one program product having a set (e.g., at least one) of program modules configured to perform the functions of the embodiments of this disclosure.

[0109] A program / utility 40 having a set (at least one) of program modules 42 may be stored, for example, in memory 28. Such program modules 42 include, but are not limited to, an operating system, one or more application programs, other program modules, and program data. Each or some combination of these examples may include an implementation of a network environment. Program modules 42 typically perform the functions and / or methods described in the embodiments of this disclosure.

[0110] Computer device 12 can also communicate with one or more external devices 14 (e.g., keyboard, pointing device, display 24, etc.), and with one or more devices that enable a user to interact with computer device 12, and / or with any device that enables computer device 12 to communicate with one or more other computing devices (e.g., network card, modem, etc.). This communication can be performed via input / output (I / O) interface 22. Furthermore, computer device 12 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 20. As shown, network adapter 20 communicates with other modules of computer device 12 via bus 18. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with computer device 12, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0111] The processing unit 16 executes various functional applications and data processing by running programs stored in the system memory 28, such as implementing the methods mentioned in the foregoing embodiments.

[0112] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0113] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0114] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of preferred embodiments of this disclosure includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as will be understood by those skilled in the art to which embodiments of this disclosure pertain.

[0115] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0116] It should be understood that various parts of this disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0117] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0118] Furthermore, the functional units in the various embodiments of this disclosure can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0119] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.

Claims

1. An escape wiring method for analog circuits, characterized in that, include: Identify the wiring pins and corresponding electrical nodes in the circuit to be escaped; Multiple edge rectangles are generated in the circuit layout, and priority, hierarchy, and electrical nodes are assigned to the edge rectangles, including: Based on the size of the circuit layout, generate edge rectangles around the circuit layout; Assign the priority of the edge rectangles at the top and bottom edges of the circuit layout to horizontal, and assign the priority of the edge rectangles at the right and left edges of the circuit layout to vertical. Determine the first level of each edge rectangle in the circuit layout, and the priority corresponding to the first level; If the priority of any edge rectangle is different from the priority of the corresponding first level, the level currently corresponding to any edge rectangle is determined to be the first level; The number of any edge rectangle assigned to the first level is updated based on the number of electrical nodes in the circuit layout. Based on the circuit and the wiring pins, a physical verification set for the circuit layout is constructed, and then the wiring pins are verified based on the physical verification set. Generate a wiring sequence based on the wiring pins and their corresponding electrical nodes; Based on the wiring sequence and preset wiring rules, escape wiring is performed on the wiring pins in the circuit, including: Based on the routing sequence, a restricted routing region between the routing start pin and the routing target pin is detected, and the restricted routing region is segmented. The edge rectangles are discretized to divide each edge rectangle into a triplet rectangle, while keeping the triplet above the grid points of the wiring. A first priority queue and a second priority queue are set up, wherein the first priority queue stores the starting grid points of the wiring start pins, and the second priority queue stores the points generated during the wiring process. Using A The algorithm, based on a cost function and a heuristic function, moves step by step from the starting pin of the routing to the target pin of the routing. In each step, an optimal next point is selected to expand the search space and the path is updated to achieve escape routing of the routing pin in the circuit. After setting the first priority queue and the second priority queue, the following is also included: In response to retrieving a starting grid from the first priority queue, pattern routing is performed based on the path between the starting grid and the routing target pin to determine whether a feasible path exists; If the wiring is successful, waveform diffusion is performed based on the starting grid point; otherwise, the currently extracted starting grid point is discarded. The waveform diffusion method includes vertical expansion and horizontal expansion.

2. The method according to claim 1, characterized in that, The process of constructing a physical verification set for the circuit layout based on the circuit and the wiring pins, and then verifying the wiring pins based on the physical verification set, includes: Each sub-circuit in the circuit and the wiring pin are added to a hierarchical spatial index set based on RTree to form a physical verification set; The wiring pins are short-circuit checked and design rule checked based on the physical verification set.

3. The method according to claim 1, characterized in that, The step of generating a wiring sequence based on the wiring pins and corresponding electrical nodes includes: The wiring pins are initialized to obtain multiple sets, wherein each wiring pin belonging to the same disjoint set is placed in one set, and each edge rectangle belonging to the same electrical node is placed in the same set. Each set is used as a node of the minimum spanning tree, and the elements between any two sets are paired. The weight of a pair of rectangles in the two sets is calculated according to a preset formula. For each pair of rectangles in the two sets, the weight is calculated as follows: weight = d / (q+l1+l2+p)+1, where d is the Manhattan distance between the rectangles, q and p are the priorities of the current routing pins of the two rectangles, and l1 and l2 are the level indices of the current routing pins of the two rectangles. The minimum spanning tree is constructed using the calculated weights. The edge with the smallest weight is selected and added to the minimum spanning tree. This selection and addition process is repeated until all nodes are connected. According to the connection order of the minimum spanning tree, the wiring pins in the set represented by each node are connected in the order of their respective sets to form a wiring sequence.

4. The method according to claim 3, characterized in that, Before initializing the wiring pins to obtain multiple sets, the method further includes: Perform a space query for each of the aforementioned wiring pins; If the first wiring pin and the second wiring pin are in contact, and the length and width of the rectangle where the first wiring pin and the second wiring pin intersect satisfy the target linewidth corresponding to the current process, then the first wiring pin and the second wiring pin are placed in the same disjoint-set data structure, wherein the electrical nodes corresponding to the first wiring pin and the second wiring pin are the same.

5. The method according to claim 1, characterized in that, The step of performing escape routing on the wiring pins in the circuit based on the wiring sequence and preset wiring rules includes: Based on A The algorithm uses a two-ended net router and the routing sequence to perform escape routing on the routing pins in the circuit.

6. An escape wiring device for an analog circuit, characterized in that, The apparatus implements the method as described in claim 1, the apparatus comprising: The determination module is used to determine the wiring pins and corresponding electrical nodes in the circuit to be escaped wiring; The first generation module is used to generate multiple edge rectangles in the circuit layout and assign priority, level and electrical nodes to the edge rectangles; The verification module is used to construct a physical verification set for the circuit layout based on the circuit and the wiring pins, and then verify the wiring pins based on the physical verification set. The second generation module is used to generate a wiring sequence based on the wiring pins and the corresponding electrical nodes; The wiring module is used to perform escape wiring on the wiring pins in the circuit based on the wiring sequence and preset wiring rules.

7. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1-5.

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