A multi-chip interconnection implementation method

Abstract

This invention discloses a method for implementing multi-chip interconnection, comprising the following steps: S1: A glass layer is mounted on a glass substrate and a cavity is formed; S2: Multiple conductor pillars are formed in the cavity; S3: A chip is placed in the cavity, multiple conductor pillars are formed on the top surface of the chip, and an organic dielectric layer is used to fill the chip and bury the cavity; S4: An upper redistribution layer and an upper connection point layer are formed on the glass layer, and the connection points of the connection point layer are connected to the top of the conductor pillars; S5: The chip is flip-chip mounted on the upper connection point layer; S6: The glass substrate is debonded, and multiple glass vias are formed below the glass layer; S7: A lower redistribution layer and a lower connection point layer are formed below the glass vias of the glass layer, and the connection points on the lower connection point layer are connected to the bottom of the conductor pillars or the metal bumps of the buried chip through the pins of the lower redistribution layer; S8: Balls are implanted on the connection points of the lower connection point layer to complete the multi-chip interconnection. This application simplifies the TGV process and enhances the high-frequency characteristics of the product.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, and specifically relates to a method for implementing multi-chip interconnection. Background Technology

[0002] Chip packaging is typically used to house semiconductor integrated circuits, serving to place, fix, seal, and protect the chip, as well as enhance its electrical and thermal performance. The package structure also acts as a bridge between the chip's internal world and external circuitry—the contacts on the chip are connected to the pins of the package via wires, and these pins, in turn, connect to other devices via wires on the printed circuit board. Therefore, packaging plays a crucial role in CPUs and other LSI integrated circuits.

[0003] However, existing technologies for achieving multi-chip interconnection have the following problems:

[0004] 1. The packaging industry uses glass layers to create through-holes to achieve chip interconnection, which is extremely difficult to implement and has a very low yield.

[0005] 2. In the packaging industry, glass layers are used as chip embedding carriers. Connecting chips or intermediate layers is often limited to single-sided conductivity, which cannot maximize the use of the physical space of the package. Summary of the Invention

[0006] To address the problems mentioned in the background art, the present invention provides a method for implementing multi-chip interconnection, which solves the problems of the existing technology of using glass substrates to make through holes to achieve chip interconnection, which is extremely difficult to implement and has a very low yield, as well as the problem that it is limited to single-sided conduction and cannot maximize the utilization of the physical space of the package.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] A method for implementing multi-chip interconnection includes the following steps:

[0009] S1: The glass layer is fixedly mounted on the glass substrate by an adhesive, and the glass layer has a chip buried cavity;

[0010] S2: Fill the chip buried cavity with filler adhesive, and perform dry film operation, exposure operation and electroplating operation on the filler adhesive in sequence to obtain multiple first conductor pillars;

[0011] S3: Place at least one buried chip in the chip buried cavity, with the side of the buried chip with metal bumps facing the bottom of the chip buried cavity. After setting multiple second conductor pillars on the top surface of the buried chip, fill the chip buried cavity with an organic dielectric layer.

[0012] S4: After grinding the glass layer to a predetermined thickness, expose the tops of all conductor pillars. Use a semi-additive method to generate at least one upper redistribution layer RDL on the glass layer. Then, set an upper micro connection point layer on the upper redistribution layer RDL. The pins on the bottom surface of the upper redistribution layer RDL are connected to the top of each conductor pillar, and the pins on the top surface of the upper redistribution layer RDL are connected to the connection points of the upper micro connection point layer.

[0013] S5: Flip multiple chips, connect the metal bumps of multiple chips to the connection points on the upper micro connection point layer one by one, and then fill the bottom of each flip chip;

[0014] S6: Debond the glass substrate, and after laser induction, etching, physical vapor deposition (PVD), and electroplating at the bottom of the conductor pillar, create multiple glass vias (TGV) under the glass layer.

[0015] S7: At least one lower redistribution layer RDL is generated below the glass via TGV of the glass layer using a semi-additive method. A lower micro connection point layer is set on the bottom surface of the lower redistribution layer. The connection points on the lower micro connection point layer are connected to the bottom end of the first conductor pillar or the metal bump on the bottom surface of the buried chip through the pins of the lower redistribution layer RDL and the glass via TGV.

[0016] S8: Place balls on the connection points of the lower micro connection point layer to complete the multi-chip interconnection.

[0017] Preferably, the thickness of the glass layer is 0.4mm-0.6mm.

[0018] Preferably, the thickness of the glass substrate is 0.8mm-1.5mm.

[0019] Preferably, the chip buried cavity is manufactured using laser-induced etching technology, with a thickness of 0.3-0.5 mm.

[0020] Preferably, in S2, the filler is 100nm-10um AL glue.

[0021] Preferably, in S2, the height of the conductor post is 80um-300um.

[0022] Preferably, the predetermined thickness in S4 is 0.3-0.5 mm.

[0023] Preferably, the organic dielectric layer used in S3 includes a resin substrate ABF and a polyimide film PI.

[0024] Compared with the prior art, the beneficial effects of the present invention are:

[0025] This invention discloses a method for implementing multi-chip interconnection. By placing the chips in a chip-buried cavity within a glass layer, and then connecting them to the flip chips and the connection points of the connection point layer via conductor pillars, this application simplifies the TGV process. It combines thin glass through-hole interconnection technology and bridge die three-dimensional interconnection technology, simplifying the process difficulty while achieving three-dimensional chip stacking. This greatly improves the engineering yield, enhances the high-frequency characteristics of the product, and ensures that both sides of the chips in the chip-buried cavity are connected to the connection points of the connection point layer, maximizing the utilization of the physical space of the package. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the method flow of this application;

[0027] Figure 2 This is a schematic diagram of the product structure of this application. Detailed Implementation

[0028] To facilitate understanding of the technical content of this invention by those skilled in the art, the invention will be further described in detail below with reference to the accompanying drawings and specific examples. It should be understood that the specific examples described herein are merely illustrative and not intended to limit the scope of the invention.

[0029] Example 1

[0030] like Figure 1 , Figure 2 As shown, a method for implementing multi-chip interconnection includes the following steps:

[0031] S1: The glass layer is fixedly mounted on the glass substrate by an adhesive, and the glass layer has a chip buried cavity;

[0032] S2: Fill the chip buried cavity with filler adhesive, and perform dry film operation, exposure operation and electroplating operation on the filler adhesive in sequence to obtain multiple first conductor pillars;

[0033] S3: Place a buried chip in a chip buried cavity, with the side of the buried chip with metal bumps facing the bottom of the chip buried cavity. After setting multiple second conductor pillars on the top surface of the buried chip, fill the chip buried cavity with an organic dielectric layer.

[0034] S4: After grinding the glass layer to the predetermined thickness, expose the tops of all conductor pillars. Use a semi-additive method to generate three upper redistribution layers RDL on the glass layer. Then, set an upper micro connection point layer on the upper redistribution layers RDL. The pins on the bottom surface of the upper redistribution layers RDL are connected to the top of each conductor pillar, and the pins on the top surface of the upper redistribution layers RDL are connected to the connection points of the upper micro connection point layer.

[0035] S5: Flip multiple chips, connect the metal bumps of multiple chips to the connection points on the upper micro connection point layer one by one, and then fill the bottom of each flip chip;

[0036] S6: Debond the glass substrate, and after laser induction, etching, physical vapor deposition (PVD), and electroplating at the bottom of the conductor pillar, create multiple glass vias (TGV) under the glass layer.

[0037] S7: A three-layer lower redistribution layer RDL is generated below the glass via TGV of the glass layer using a semi-additive method. A lower micro connection point layer is set on the bottom surface of the lower redistribution layer RDL. The connection points on the lower micro connection point layer are connected to the bottom end of the first conductor pillar or the metal bumps on the bottom surface of the buried chip through the pins of the lower redistribution layer RDL and the glass via TGV.

[0038] S8: Place balls on the connection points of the lower micro connection point layer to complete the multi-chip interconnection.

[0039] In this embodiment, the present invention discloses a method for implementing multi-chip interconnection. By placing the chip in the chip buried cavity of the glass layer, and then setting conductor pillars to connect with the connection points of the flip chip and the connection point layer, this application simplifies the difficulty of TGV process, combines thin glass through-hole interconnection process and bridge die three-dimensional interconnection process, and simplifies the process difficulty on the basis of realizing three-dimensional stacking of chips, greatly improves the engineering yield, enhances the high frequency characteristics of the product, and the chip in the chip buried cavity is connected to the connection points of the connection point layer on both sides, which can maximize the use of the physical space of the package.

[0040] Example 2

[0041] The difference between this embodiment and Embodiment 1 is that the thickness of the glass layer is 0.4mm-0.6mm.

[0042] Example 3

[0043] The difference between this embodiment and Embodiment 1 is that the thickness of the glass substrate is 0.8mm-1.5mm.

[0044] Example 4

[0045] The difference between this embodiment and Embodiment 1 is that the chip buried cavity is manufactured using laser-induced etching technology, with a thickness of 0.3-0.5mm.

[0046] Example 5

[0047] The difference between this embodiment and embodiment 1 is that in S2, the filler is 100nm-10um AL adhesive.

[0048] Example 6

[0049] The difference between this embodiment and embodiment 1 is that in S2, the height of the conductor post is 80um-300um.

[0050] Example 7

[0051] The difference between this embodiment and embodiment 1 is that the predetermined thickness in S4 is 0.3-0.5 mm.

[0052] Example 8

[0053] The difference between this embodiment and Embodiment 1 is that the organic dielectric layer used in S3 includes a resin substrate ABF and a polyimide film PI.

[0054] Those skilled in the art will recognize that the embodiments described herein are intended to help the reader understand the principles of the invention and should be understood as not limiting the scope of protection of this application to such specific statements and embodiments. Those skilled in the art can make various other specific modifications and combinations based on the technical teachings disclosed in this application without departing from the essence of the invention, and these modifications and combinations are still within the scope of protection of this application.

Claims

1. A method for implementing multi-chip interconnection, characterized in that, Includes the following steps: S1: The glass layer is fixedly mounted on the glass substrate by an adhesive, and the glass layer has a chip buried cavity; S2: Fill the chip buried cavity with filler adhesive, and perform dry film operation, exposure operation and electroplating operation on the filler adhesive in sequence to obtain multiple first conductor pillars; S3: Place at least one buried chip in the chip buried cavity, with the side of the buried chip with metal bumps facing the bottom of the chip buried cavity. After setting multiple second conductor pillars on the top surface of the buried chip, fill the chip buried cavity with an organic dielectric layer. S4: After grinding the glass layer to a predetermined thickness, expose the tops of all conductor pillars. Use a semi-additive method to generate at least one upper redistribution layer RDL on the glass layer. Then, set an upper micro connection point layer on the upper redistribution layer RDL. The pins on the bottom surface of the upper redistribution layer RDL are connected to the top of each conductor pillar, and the pins on the top surface of the upper redistribution layer RDL are connected to the connection points of the upper micro connection point layer. S5: Flip multiple chips, connect the metal bumps of multiple chips to the connection points on the upper micro connection point layer one by one, and then fill the bottom of each flip chip; S6: Debond the glass substrate, and after laser induction, etching, physical vapor deposition (PVD), and electroplating at the bottom of the conductor pillar, create multiple glass vias (TGV) under the glass layer. S7: At least one lower redistribution layer RDL is generated below the glass via TGV of the glass layer using a semi-additive method. A lower micro connection point layer is set on the bottom surface of the lower redistribution layer RDL. The connection points on the lower micro connection point layer are connected to the bottom end of the first conductor pillar or the metal bump on the bottom surface of the buried chip through the pins of the lower redistribution layer RDL and the glass via TGV. S8: Place balls on the connection points of the lower micro connection point layer to complete the multi-chip interconnection.

2. The multi-chip interconnection implementation method according to claim 1, characterized in that, The thickness of the glass layer is 0.4mm-0.6mm.

3. The multi-chip interconnection implementation method according to claim 1, characterized in that, The thickness of the glass substrate is 0.8mm-1.5mm.

4. The multi-chip interconnection implementation method according to claim 1, characterized in that, The chip buried cavity is manufactured using laser-induced etching technology, with a thickness of 0.3-0.5mm.

5. The multi-chip interconnection implementation method according to claim 1, characterized in that, In S2, the filler is 100nm-10um AL resin.

6. The multi-chip interconnection implementation method according to claim 1, characterized in that, In S2, the height of the conductor pillar is 80um-300um.

7. The multi-chip interconnection implementation method according to claim 1, characterized in that, The predetermined thickness in S4 is 0.3-0.5 mm.

8. The multi-chip interconnection implementation method according to claim 1, characterized in that, The organic dielectric layer used in S3 includes a resin substrate ABF and a polyimide film PI.

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