Electrostatic discharge protection device

Abstract

The present application discloses an electrostatic discharge protection device, which includes a P-type substrate, an N-type well region, a first P-type heavily doped region, an N-type doped region and a first N-type heavily doped region. The N-type well region is disposed in the P-type substrate, the first P-type heavily doped region is disposed in the N-type well region, and the N-type doped region and the first N-type heavily doped region are disposed in the P-type substrate. The N-type doped region is coupled to the N-type doped region through an external wire, and the external wire is decoupled from the first P-type heavily doped region. Alternatively, the P-type substrate and the N-type well region are replaced by an N-type substrate and a P-type well region respectively.

Description

Technical Field

[0001] This invention relates to a protective device, and more particularly to an electrostatic discharge protection device. Background Technology

[0002] As integrated circuit (IC) devices shrink to the nanometer scale, consumer electronics such as laptops and mobile devices are designed to be much smaller than ever before. Without proper protection, the functionality of these electronic devices can be reset or even damaged in electrostatic discharge (ESD) events. Currently, all consumer electronics are expected to meet the ESD testing requirements of the IEC 61000-4-2 standard. Transient voltage suppressors (TVS) are typically designed to bypass ESD energy, thereby preventing ESD damage to electronic systems.

[0003] The working principle of electrostatic discharge protection device is as follows: Figure 1 As shown, on the integrated circuit chip, the transient voltage suppression device 10 is connected in parallel with the protection circuit 12. When an ESD event occurs, the transient voltage suppression device 10 is triggered instantaneously. At the same time, the transient voltage suppression device 10 can also provide a low-resistance path for the transient ESD current to discharge, allowing the energy of the ESD transient current to be released through the transient voltage suppression device 10. Figure 2As shown, a conventional low-voltage silicon controlled rectifier (LVTSCR) includes a P-type substrate 14, an N-type doped well region 16, three heavily doped N-type regions 18, 20, and 22, and two heavily doped P-type regions 24 and 26. The N-type doped well region 16 is formed in the P-type substrate 14. The heavily doped N-type regions 18 and 24 are formed in the N-type doped well region 16 and coupled to a first pin 28. The heavily doped N-type region 20 is formed in the N-type doped well region 16 and the P-type substrate 14. The heavily doped N-type regions 22 and 26 are formed in the P-type substrate 14. The heavily doped N-type regions 22 and 26 are coupled to a second pin. The second pin is also coupled to the gate 32 of an N-channel metal-oxide-semiconductor field-effect transistor (NMOSFET). The gate 32 is formed through a dielectric layer in the region between the heavily doped N-type regions 20 and 22. The LVTSCR primarily exhibits parasitic capacitance formed by a P-type substrate 14, an N-type doped well region 16, and an N-type heavily doped region 20. Because the N-type doped well region 16 is coupled to the first pin via the N-type heavily doped region 18, and the interface area between the P-type substrate 14 and the N-type doped well region 16 is large, the parasitic capacitance is very large. The LVTSCR turns on due to a breakdown event occurring at the interface between the N-type heavily doped region 20 and the P-type substrate 14. An N-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) formed by the N-type heavily doped regions 20 and 22 and the gate 32 is formed on the path for the LVTSCR to turn on, thereby increasing the path between the first pin 28 and the second pin 30, as well as the clamping voltage of the LVTSCR. Furthermore, the P-type heavily doped region 26, coupled to the second pin 30, is located away from the breakdown interface between the N-type heavily doped region 20 and the P-type substrate 14. Therefore, the LVTSCR requires only a relatively low trigger voltage to turn on. Low trigger current LVTSCRs are easily triggered by noise or surges in the external environment, which can cause electronic systems or integrated circuits (ICs) to malfunction.

[0004] Therefore, the present invention addresses the aforementioned problems by proposing an electrostatic discharge protection device to solve the issues arising from the prior art. Summary of the Invention

[0005] The purpose of this invention is to provide an electrostatic discharge protection device having low parasitic capacitance, low clamping voltage, low trigger voltage and high trigger current.

[0006] An embodiment of the present invention provides an electrostatic discharge protection device, comprising: a P-type substrate, an N-type well region, a first heavily doped P-type region, an N-type doped region, and a first heavily doped N-type region. The N-type well region is disposed in the P-type substrate, and the first heavily doped P-type region is disposed in the N-type well region. The N-type doped region and the first heavily doped N-type region are disposed in the P-type substrate. The N-type doped region is coupled to the N-type well region via an external wire, and the external wire is decoupled from the first heavily doped P-type region.

[0007] In one embodiment of the present invention, the first P-type heavily doped region is coupled to a first pin, the first pin is decoupled from an external conductor, and the first N-type heavily doped region is coupled to a second pin of the P-type substrate.

[0008] In one embodiment of the present invention, the first N-type heavily doped region is disposed between the N-type doped region and the N-type well region.

[0009] In one embodiment of the present invention, the electrostatic discharge protection device further includes a second heavily doped N-type region disposed within the N-type well region. The second heavily doped N-type region is coupled to the N-type doped region via an external wire.

[0010] In one embodiment of the present invention, the electrostatic discharge protection device further includes a second P-type heavily doped region disposed in a P-type substrate. An N-type doped region is disposed between the first N-type heavily doped region and the second P-type heavily doped region.

[0011] In one embodiment of the present invention, the electrostatic discharge protection device further includes a P-type well region disposed in a P-type substrate. The doping concentration of the P-type well region is greater than the doping concentration of the P-type substrate and less than the doping concentration of the second heavily doped P-type region, which is disposed in the P-type well region and is directly adjacent to the N-type doped region.

[0012] In one embodiment of the present invention, the P-type substrate has a region located between an N-type doped region and a first N-type heavily doped region, on which a dielectric layer and a conductive gate are sequentially disposed, and the conductive gate is coupled to an external wire.

[0013] In one embodiment of the present invention, the P-type substrate has a region located between an N-type doped region and a first heavily N-type doped region, on which a dielectric layer and a conductive gate are sequentially disposed, and the conductive gate is coupled to the first heavily N-type doped region.

[0014] In one embodiment of the present invention, the electrostatic discharge protection device further includes an electrostatic discharge detection circuit. The P-type substrate has a region located between an N-type doped region and a first heavily doped N-type region. A dielectric layer and a conductive gate are sequentially disposed on this region. The electrostatic discharge detection circuit is coupled to an external conductor, the conductive gate, and the first heavily doped N-type region. The first heavily doped P-type region is coupled to a first pin, and the first heavily doped N-type region is coupled to a second pin and receives a reference voltage. When the first pin receives a positive electrostatic discharge voltage higher than the reference voltage, the electrostatic discharge detection circuit responds to the positive electrostatic discharge voltage to conduct the parasitic field-effect transistor formed by the dielectric layer, the conductive gate, the N-type doped region, the P-type substrate, and the first heavily doped N-type region.

[0015] In one embodiment of the present invention, the electrostatic discharge detection circuit includes an inverter, a resistor, and a capacitor. The output terminal of the inverter is coupled to a conductive gate, the resistor is coupled between an external wire and the input terminal of the inverter, and the capacitor is coupled between the input terminal of the inverter and a reference voltage.

[0016] Another embodiment of the present invention provides an electrostatic discharge protection device, comprising: an N-type substrate, a P-type well region, a first P-type heavily doped region, an N-type doped region, and a first N-type heavily doped region. The P-type well region is disposed in the N-type substrate, and the first P-type heavily doped region is disposed in the N-type substrate. The N-type doped region and the first N-type heavily doped region are disposed in the P-type well region, wherein the N-type doped region is coupled to the N-type substrate via an external wire, and the external wire is decoupled from the first P-type heavily doped region.

[0017] In one embodiment of the present invention, the first P-type heavily doped region is coupled to a first pin, the first pin is decoupled from an external conductor, and the first N-type heavily doped region and the P-type well region are coupled to a second pin.

[0018] In one embodiment of the present invention, a first N-type heavily doped region is disposed between an N-type doped region and a first P-type heavily doped region.

[0019] In one embodiment of the present invention, the electrostatic discharge protection device further includes a second N-type heavily doped region disposed in an N-type substrate, wherein the second N-type heavily doped region is coupled to the N-type doped region through an external wire.

[0020] In one embodiment of the present invention, the electrostatic discharge protection device further includes a second P-type heavily doped region disposed in the P-type well region, wherein the N-type doped region is disposed between the first N-type heavily doped region and the second P-type heavily doped region.

[0021] In one embodiment of the present invention, the P-type well region has a region located between the N-type doped region and the first N-type heavily doped region, on which a dielectric layer and a conductive gate are sequentially disposed, and the conductive gate is coupled to an external wire.

[0022] In one embodiment of the present invention, the P-type well region has a region located between the N-type doped region and the first N-type heavily doped region, on which a dielectric layer and a conductive gate are sequentially disposed, and the conductive gate is coupled to the first N-type heavily doped region.

[0023] In one embodiment of the present invention, the electrostatic discharge protection device further includes an electrostatic discharge detection circuit. The P-type well region has a region located between the N-type doped region and the first heavily doped N-type region. A dielectric layer and a conductive gate are sequentially disposed on this region. The electrostatic discharge detection circuit is coupled to an external conductor, the conductive gate, and the first heavily doped N-type region. The first heavily doped P-type region is coupled to a first pin, and the first heavily doped N-type region is coupled to a second pin and receives a reference voltage. When the first pin receives a positive electrostatic discharge voltage higher than the reference voltage, the electrostatic discharge detection circuit responds to the positive electrostatic discharge voltage to conduct the parasitic field-effect transistor formed by the dielectric layer, the conductive gate, the N-type doped region, the P-type well region, and the first heavily doped N-type region.

[0024] In one embodiment of the present invention, the electrostatic discharge detection circuit includes an inverter, a resistor, and a capacitor. The output terminal of the inverter is coupled to a conductive gate, the resistor is coupled between an external wire and the input terminal of the inverter, and the capacitor is coupled between the input terminal of the inverter and a reference voltage.

[0025] Based on the above, the electrostatic discharge protection device is coupled to the N-type well region or N-type substrate to the N-type doped region to have low parasitic capacitance, low clamping voltage, low trigger voltage and high trigger current. Attached Figure Description

[0026] Figure 1 This is a schematic diagram showing the connection of a transient voltage suppression device in the prior art to the circuit to be protected on an integrated circuit chip.

[0027] Figure 2 This is a cross-sectional view of the structure of a low-voltage silicon controlled rectifier in the prior art.

[0028] Figure 3 This is a structural cross-sectional view of the electrostatic discharge protection device according to the first embodiment of the present invention.

[0029] Figure 4 for Figure 2 Low-voltage silicon controlled rectifier and Figure 3 The current and voltage curves of the electrostatic discharge protection device.

[0030] Figure 5 This is a structural cross-sectional view of the electrostatic discharge protection device according to the second embodiment of the present invention.

[0031] Figure 6 This is a structural cross-sectional view of the electrostatic discharge protection device according to the third embodiment of the present invention.

[0032] Figure 7 This is a structural cross-sectional view of the electrostatic discharge protection device according to the fourth embodiment of the present invention.

[0033] Figure 8This is a schematic diagram of an electrostatic discharge detection circuit according to an embodiment of the present invention.

[0034] Figure 9 This is a structural cross-sectional view of the electrostatic discharge protection device according to the fifth embodiment of the present invention.

[0035] Figure 10 This is a structural cross-sectional view of the electrostatic discharge protection device according to the sixth embodiment of the present invention.

[0036] Figure 11 This is a structural cross-sectional view of the electrostatic discharge protection device according to the seventh embodiment of the present invention.

[0037] Figure 12 This is a structural cross-sectional view of the electrostatic discharge protection device according to the eighth embodiment of the present invention.

[0038] Figure 13 This is a structural cross-sectional view of the electrostatic discharge protection device according to the ninth embodiment of the present invention.

[0039] Figure 14 This is a structural cross-sectional view of the electrostatic discharge protection device according to the tenth embodiment of the present invention.

[0040] Figure 15 This is a structural cross-sectional view of the electrostatic discharge protection device according to the eleventh embodiment of the present invention.

[0041] Figure 16 This is a structural cross-sectional view of the electrostatic discharge protection device according to the twelfth embodiment of the present invention.

[0042] Figure 17 This is a structural cross-sectional view of the electrostatic discharge protection device according to the thirteenth embodiment of the present invention.

[0043] Figure 18 This is a schematic diagram of an electrostatic discharge detection circuit according to another embodiment of the present invention.

[0044] Figure 19 This is a structural cross-sectional view of the electrostatic discharge protection device according to the fourteenth embodiment of the present invention.

[0045] Figure 20 This is a structural cross-sectional view of the electrostatic discharge protection device according to the fifteenth embodiment of the present invention.

[0046] Figure 21 This is a structural cross-sectional view of the electrostatic discharge protection device according to the sixteenth embodiment of the present invention.

[0047] Figure reference numerals: 10 - Transient voltage suppression device; 12 - Circuit to be protected; 14 - P-type substrate; 16 - N-type doped well region; 18, 20, 22 - N-type heavily doped regions; 24, 26 - P-type heavily doped regions; 28 - First pin; 30 - Second pin; 32 - Gate; 34 - P-type substrate; 34' - N-type substrate; 36 - N-type well region; 36' - P-type well region; 38 - First P-type heavily doped region; 40 - N-type doped region; 42 - First N-type heavily doped region; 44 - External conductor; 46 - First pin; 48 - Second pin; 50 - Second P-type heavily doped region; 52 - Second N-type heavily doped region; 54 - Dielectric layer; 56 - Conductive gate; 58 - Electrostatic discharge detection circuit; 60 - Inverter; 62 - Resistor; 64 - Capacitor; 66, 66' - P-type well regions; a - Distance; b - Distance; R Psub R PW 、R' PW1 、R' PW2 - Parasitic resistance; V t - Trigger voltage; I t - Trigger current; Vc - Clamping voltage. Detailed Implementation

[0048] Embodiments of the present invention will be further explained below with reference to the accompanying drawings. Wherever possible, the same reference numerals represent the same or similar components in the drawings and description. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It is understood that elements not specifically shown in the drawings or described in the description are forms known to those skilled in the art. Those skilled in the art can make various changes and modifications based on the content of this invention.

[0049] Unless otherwise specified, certain conditional clauses or words, such as "can," "could," "might," or "may," are generally intended to express features, elements, or steps that are present in the embodiments of this invention, but may also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may be unnecessary.

[0050] In the following description of "one embodiment" or "an embodiment," the term refers to a specific element, structure, or feature associated with at least one embodiment. Therefore, the multiple descriptions of "one embodiment" or "an embodiment" appearing in various places below do not refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in a suitable manner.

[0051] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. The specification and claims do not distinguish elements by differences in name, but by differences in function. The word "comprising" in the specification and claims is an open-ended term and should be interpreted as "including but not limited to". Furthermore, "coupled" here includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or signal connection methods such as wireless transmission or light guiding, or indirectly electrically or signal connected to the second element through other elements or connection means.

[0052] This invention is described in particular by way of the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this invention. Therefore, the scope of protection of this invention is determined by the appended claims. Throughout the specification and claims, unless explicitly specified, the words “a” and “described” encompass this type of description, including “a or at least one” of the described elements or components. Furthermore, as used herein, the singular article also includes descriptions of a plurality of elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and all the claims, unless explicitly specified, “in which” may include both “in which” and “therein”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the art, in the context of this invention, and in the specific context. Certain terms used to describe the invention will be discussed below or elsewhere in this specification to provide additional guidance to practitioners in describing the invention. Examples throughout this specification, including examples of any terms discussed herein, are for illustrative purposes only and do not limit the scope or meaning of the invention or any of the illustrative terms. Similarly, the invention is not limited to the various embodiments set forth in this specification.

[0053] Traditional low-trigger-current silicon-controlled rectifiers (SCRs) are easily triggered accidentally by external environmental noise or surges. When the SCR is turned on, its low holding voltage and low holding current can affect signal integrity, leading to electronic system or integrated circuit (IC) failures. Therefore, increasing the trigger current of the SCR can effectively reduce the chance of false triggering. In the following description, an electrostatic discharge (ESD) protection device is described. This ESD protection device couples an N-type well region or N-type substrate to an N-type doped region to achieve low parasitic capacitance, low clamping voltage, low trigger voltage, and high trigger current.

[0054] Figure 3 This is a cross-sectional view of the electrostatic discharge protection device according to the first embodiment of the present invention. Please refer to [link / reference]. Figure 3 The following describes a first embodiment of an electrostatic discharge (ESD) protection device. The ESD protection device includes a P-type substrate 34, an N-type well region 36, a first heavily doped P-type region 38, an N-type doped region 40, and a first heavily doped N-type region 42. The N-type well region 36 is disposed in the P-type substrate 34, the first heavily doped P-type region 38 is disposed in the N-type well region 36, and the N-type doped region 40 and the first heavily doped N-type region 42 are disposed in the P-type substrate 34. The N-type doped region 40 is coupled to the N-type well region 36 via an external conductor 44, and the external conductor 44 decouples the first heavily doped P-type region 38. The first heavily doped P-type region 38 can be coupled to a first pin 46, the first pin 46 decouples the external conductor 44, and the first heavily doped N-type region 42 and the P-type substrate 34 can be coupled to a second pin 48. The first P-type heavily doped region 38, the N-type well region 36, the P-type substrate 34, and the first N-type heavily doped region 42 form a silicon controlled rectifier.

[0055] Because the N-type well region 36 is a lightly doped N-type well region, the interface between the N-type well region 36 and the P-type substrate 34 has a high breakdown voltage. To reduce the trigger voltage of the silicon controlled rectifier (SCR), the doping concentration of the N-type doped region 40 is increased, or the distance 'a' between the N-type doped region 40 and the first heavily doped N-type region 42 is decreased. In a preferred embodiment, the doping concentration of the N-type doped region 40 is higher than that of the N-type well region 36. When the doping concentration of the N-type doped region 40 is increased or the distance 'a' between the N-type doped region 40 and the first heavily doped N-type region 42 is decreased, the punch-through voltage of the bicarrier junction transistor formed by the N-type doped region 40, the P-type substrate 34, and the first heavily doped N-type region 42 is reduced, thereby lowering the trigger voltage of the SCR. When the first pin 46 receives a positive electrostatic discharge voltage and the second pin 48 is grounded, the electrostatic discharge current first flows from the first pin 46 through the first heavily doped P-type region 38, the N-type well region 36, the external conductor 44, the N-type doped region 40, the P-type substrate 34, and the first heavily doped N-type region 42 to the second pin 48. The positive electrostatic discharge voltage causes the interface between the N-type doped region 40 and the P-type substrate 34 to break down, thereby first turning on the parasitic bicarrier junction transistor formed by the N-type well region 36, the P-type substrate 34, and the first heavily doped N-type region 42. Then, the parasitic silicon-controlled rectifier formed by the first heavily doped P-type region 38, the N-type well region 36, the P-type substrate 34, and the first heavily doped N-type region 42 is subsequently turned on. Finally, the electrostatic discharge current is released from the first pin 46 through the first heavily doped P-type region 38, the N-type well region 36, the P-type substrate 34, and the first heavily doped N-type region 42 to the second pin 48. In some embodiments of the present invention, a first heavily doped N-type region 42 is disposed between the P-type substrate 34 and the N-type well region 36, thus providing a short conduction distance for the silicon controlled rectifier (SCR) between the first pin 46 and the second pin 48. In this embodiment, the first heavily doped N-type region 42 is positioned as close as possible to the N-type well region 36. When the SCR stably releases the electrostatic discharge current, the electrostatic discharge current does not flow through the N-type doped region 40. Furthermore, the total parasitic capacitance of the SCR is dominated by the parasitic capacitance formed by the first heavily doped P-type region 38 and the N-type well region 36. Because the interface between the first heavily doped P-type region 38 and the N-type well region 36 has a small area, and the N-type well region 36 has a low doping concentration, a low parasitic capacitance is formed by the first heavily doped P-type region 38 and the N-type well region 36. Therefore, the SCR has a low clamping voltage, low on-resistance, and low parasitic capacitance.

[0056] To stabilize the voltage of the P-type substrate 34, the P-type substrate 34 can be coupled to a second pin 48. In some embodiments of the present invention, the electrostatic discharge protection device may further include a second heavily doped P-type region 50 disposed in the P-type substrate 34. An N-type doped region 40 is disposed between the first heavily doped N-type region 42 and the second heavily doped P-type region 50. The second heavily doped P-type region 50 is coupled to the second pin 48 to form an ohmic contact. When a positive electrostatic discharge voltage causes the interface between the N-type doped region 40 and the P-type substrate 34 to break down, the electrostatic discharge current also flows through the second heavily doped P-type region 50 to the second pin 48. Because the second heavily doped P-type region 50 is close to the interface between the N-type doped region 40 and the P-type substrate 34, the parasitic resistance R of the P-type substrate 34 between the N-type doped region 40 and the second heavily doped P-type region 50 is... Psub It is low. That is, the silicon controlled rectifier requires a higher trigger current to turn on. In fact, the distance b between the N-type doped region 40 and the second heavily P-type doped region 50 is adjustable. When the distance b between the N-type doped region 40 and the second heavily P-type doped region 50 is short, the parasitic resistance R... Psub It is low. When the distance b between the N-type doped region 40 and the second P-type heavily doped region 50 is long, the parasitic resistance R is low. Psub It is high. Therefore, the silicon controlled rectifier has an adjustable trigger current. In this embodiment, the parasitic resistance R... Psub The low current required for the silicon controlled rectifier (SCR) to turn on effectively reduces the chance of false triggering. In some embodiments of the invention, the electrostatic discharge protection device may further include a second heavily doped N-type region 52 disposed in the N-type well region 36. The second heavily doped N-type region 52 is coupled to the N-type doped region 40 via an external conductor 44 to form an ohmic contact. The second heavily doped N-type region 52 is used to allow electrostatic discharge current to pass through.

[0057] Figure 4 for Figure 2 Low-voltage silicon controlled rectifier and Figure 3 The current and voltage curves of the electrostatic discharge protection device are shown below. Please refer to [link / reference]. Figure 4 Solid lines represent Figure 3 Electrostatic discharge protection device, the dashed line represents Figure 2 Low-voltage silicon controlled rectifier. From Figure 4 It can be seen that both electrostatic discharge protection devices and low-voltage silicon controlled rectifiers have low trigger voltage V. t Compared to low-voltage silicon controlled rectifiers, electrostatic discharge protection devices have a higher trigger current I. t With a lower clamping voltage Vc.

[0058] Figure 5 This is a structural cross-sectional view of the electrostatic discharge protection device according to a second embodiment of the present invention. Please refer to [link / reference]. Figure 5The following describes a second embodiment of the electrostatic discharge protection device. The difference between the second and first embodiments is that the P-type substrate 34 in the second embodiment has a region between the N-type doped region 40 and the first heavily doped N-type region 42. A dielectric layer 54 and a conductive gate 56 are sequentially disposed on this region of the P-type substrate 34. The conductive gate 56 is coupled to the second pin 48 and the first heavily doped N-type region 42. When a positive electrostatic discharge voltage is applied to the first pin 46 and the second pin 48 is grounded, leakage current can be prevented from passing through the region of the P-type substrate 34 between the N-type doped region 40 and the first heavily doped N-type region 42. The remaining features of the second embodiment have been described in the first embodiment and will not be repeated here.

[0059] Figure 6 This is a cross-sectional view of the electrostatic discharge protection device according to a third embodiment of the present invention. Please refer to [link / reference]. Figure 6 The following describes a third embodiment of the electrostatic discharge protection device. The difference between the third and first embodiments is that the P-type substrate 34 in the third embodiment has a region between the N-type doped region 40 and the first heavily doped N-type region 42. A dielectric layer 54 and a conductive gate 56 are sequentially disposed on this region of the P-type substrate 34. The conductive gate 56 is coupled to an external conductor 44. When a positive electrostatic discharge voltage is applied to the first pin 46 and the second pin 48 is grounded, the positive electrostatic discharge voltage helps to conduct the parasitic field-effect transistor formed by the dielectric layer 54, the conductive gate 56, the N-type doped region 40, the P-type substrate 34, and the first heavily doped N-type region 42, thereby reducing the trigger voltage of the silicon controlled rectifier. The remaining features of the third embodiment have been described in the first embodiment and will not be repeated here.

[0060] Figure 7 This is a structural cross-sectional view of the electrostatic discharge protection device according to the fourth embodiment of the present invention. Please refer to [link / reference]. Figure 7The following describes a fourth embodiment of the electrostatic discharge (ESD) protection device. The fourth embodiment differs from the first embodiment in that the P-type substrate 34 of the third embodiment has a region between the N-type doped region 40 and the first heavily doped N-type region 42, and a dielectric layer 54 and a conductive gate 56 are sequentially disposed on this region of the P-type substrate 34. Furthermore, the fourth embodiment includes an ESD detection circuit 58, which is coupled to an external conductor 44, the conductive gate 56, and the first heavily doped N-type region 42. The first heavily doped P-type region 38 is coupled to a first pin 46. The first heavily doped N-type region 42 is coupled to a second pin 48 and receives a reference voltage. In the fourth embodiment, a positive ESD voltage is applied to the first pin 46, and the second pin 48 is grounded. When the first pin 46 receives a positive electrostatic discharge voltage higher than the ground voltage used as a reference voltage, the electrostatic discharge detection circuit 58 responds to the positive electrostatic discharge voltage to turn on the parasitic field-effect transistor formed by the dielectric layer 54, the conductive gate 56, the N-type doped region 40, the P-type substrate 34, and the first heavily doped N-type region 42, thereby reducing the trigger voltage of the silicon controlled rectifier. The electrostatic discharge detection circuit 58 can improve the sensitivity of releasing electrostatic discharge current. When the first heavily doped P-type region 38 receives an input voltage via the first pin 46, and its input voltage is less than or equal to the ground voltage used as a reference voltage, the electrostatic discharge detection circuit 58 responds to the input voltage to turn off the parasitic field-effect transistor formed by the dielectric layer 54, the conductive gate 56, the N-type doped region 40, the P-type substrate 34, and the first heavily doped N-type region 42. The remaining features of the fourth embodiment have been described in the first embodiment and will not be repeated here.

[0061] Figure 8 This is a schematic diagram of an electrostatic discharge detection circuit according to an embodiment of the present invention. Please refer to [link / reference]. Figure 7 and Figure 8 The electrostatic discharge detection circuit 58 may include an inverter 60, a resistor 62, and a capacitor 64. The output of the inverter 60 is coupled to a conductive gate 56, and the resistor 62 is coupled between an external conductor 44 and the input of the inverter 60. The capacitor 64 is coupled between the input of the inverter 60 and a ground voltage, which serves as a reference voltage. In this embodiment, the capacitor 64 is coupled to a second pin 48. To release the electrostatic discharge current, the time constant formed by the resistor 62 and the capacitor 64 is 0.1 to 1 microsecond (μs).

[0062] Figure 9 This is a structural cross-sectional view of the electrostatic discharge protection device according to the fifth embodiment of the present invention. Please refer to [link / reference]. Figure 9 and Figure 3The following describes a fifth embodiment of the electrostatic discharge protection device. The fifth embodiment differs from the first embodiment in that it further includes a P-type well region 66, which is disposed within the P-type substrate 34. The doping concentration of the P-type well region 66 is greater than the doping concentration of the P-type substrate 34, but less than the doping concentration of the second heavily doped P-type region 50, which is disposed within the P-type well region 66. The P-type well region 66 is directly adjacent to the N-type doped region 40. The parasitic resistance R of the P-type well region 66 between the N-type doped region 40 and the second heavily doped P-type region 50 is... PW The parasitic resistance R of the P-type substrate 34 below the N-type doped region 40 and the second P-type heavily doped region 50 Psub To reduce the parasitic resistance R in P-type well region 66. PW The bottom of the P-type well region 66 can be deeper than the bottom of the N-type doped region 40 and the second heavily P-type doped region 50. Compared with the silicon-controlled rectifier of the first embodiment, due to the parasitic resistance R... PW Below the parasitic resistance R Psub Therefore, the silicon-controlled rectifier of the fifth embodiment requires a higher trigger current to turn on. Other features of the fifth embodiment have been described in the first embodiment and will not be repeated here.

[0063] Figure 10 This is a cross-sectional view of the electrostatic discharge protection device according to the sixth embodiment of the present invention. Please refer to [link / reference]. Figure 10 and Figure 6 The following describes a sixth embodiment of the electrostatic discharge protection device. The sixth embodiment differs from the third embodiment in that it further includes a P-type well region 66, which is disposed within the P-type substrate 34. The doping concentration of the P-type well region 66 is greater than the doping concentration of the P-type substrate 34, but less than the doping concentration of the second heavily doped P-type region 50, which is disposed within the P-type well region 66. The P-type well region 66 is directly adjacent to the first heavily doped N-type region 42. The parasitic resistance R of the P-type well region 66 between the N-type doped region 40 and the second heavily doped P-type region 50 is... PW The parasitic resistance R of the P-type substrate 34 below the N-type doped region 40 and the second P-type heavily doped region 50 Psub To reduce the parasitic resistance R in P-type well region 66. PW The bottom of the P-type well region 66 can be deeper than the bottom of the N-type doped region 40 and the second heavily P-type doped region 50. Compared with the silicon-controlled rectifier of the third embodiment, due to the parasitic resistance R... PW Below the parasitic resistance R Psub Therefore, the silicon-controlled rectifier of the sixth embodiment requires a higher trigger current to turn on. Other features of the sixth embodiment have been described in the third embodiment and will not be repeated here.

[0064] Figure 11 This is a structural cross-sectional view of the electrostatic discharge protection device according to the seventh embodiment of the present invention. Please refer to [link / reference]. Figure 11 and Figure 7 The following describes a seventh embodiment of the electrostatic discharge protection device. The seventh embodiment differs from the fourth embodiment in that it further includes a P-type well region 66, which is disposed within the P-type substrate 34. The doping concentration of the P-type well region 66 is greater than the doping concentration of the P-type substrate 34, but less than the doping concentration of the second heavily doped P-type region 50, which is disposed within the P-type well region 66. The P-type well region 66 is directly adjacent to the first heavily doped N-type region 42. The parasitic resistance R of the P-type well region 66 between the N-type doped region 40 and the second heavily doped P-type region 50 is... PW The parasitic resistance R of the P-type substrate 34 below the N-type doped region 40 and the second P-type heavily doped region 50 Psub To reduce the parasitic resistance R in P-type well region 66. PW The bottom of the P-type well region 66 can be deeper than the bottom of the N-type doped region 40 and the second heavily P-type doped region 50. Compared with the silicon-controlled rectifier of the fourth embodiment, due to the parasitic resistance R... PW Below the parasitic resistance R Psub Therefore, the silicon-controlled rectifier of the seventh embodiment requires a higher trigger current to turn on. Other features of the seventh embodiment have been described in the fourth embodiment and will not be repeated here.

[0065] Figure 12 This is a structural cross-sectional view of the electrostatic discharge protection device according to the eighth embodiment of the present invention. Please refer to [link / reference]. Figure 12 The following describes an eighth embodiment of the electrostatic discharge protection device. The difference between the eighth and sixth embodiments lies in the P-type well region 66. In the eighth embodiment, the N-type doped region 40 and the first heavily N-type doped region 42 are located within the P-type well region 66. Other features of the eighth embodiment have been described in the sixth embodiment and will not be repeated here.

[0066] Figure 13 This is a cross-sectional view of the electrostatic discharge protection device according to the ninth embodiment of the present invention. Please refer to [link / reference]. Figure 13 The following describes a ninth embodiment of the electrostatic discharge protection device. The difference between the ninth and seventh embodiments lies in the P-type well region 66. In the ninth embodiment, the N-type doped region 40 and the first heavily N-type doped region 42 are located within the P-type well region 66. Other features of the ninth embodiment have been described in the seventh embodiment and will not be repeated here.

[0067] Figure 14 This is a cross-sectional view of the electrostatic discharge protection device according to the tenth embodiment of the present invention. Please refer to [link / reference]. Figure 14The following describes a tenth embodiment of an electrostatic discharge (ESD) protection device. The ESD protection device includes an N-type substrate 34', a P-type well region 36', a first heavily doped P-type region 38, an N-type doped region 40, and a first heavily doped N-type region 42. The P-type well region 36' is disposed in the N-type substrate 34', the first heavily doped P-type region 38 is disposed in the N-type substrate 34', and the N-type doped region 40 and the first heavily doped N-type region 42 are disposed in the P-type well region 36'. The N-type doped region 40 is coupled to the N-type substrate 34' via an external conductor 44, and the external conductor 44 decouples the first heavily doped P-type region 38. The first heavily doped P-type region 38 can be coupled to a first pin 46, and the first pin 46 decouples the external conductor 44. The first heavily doped N-type region 42 can be coupled to a second pin 48. The first P-type heavily doped region 38, the N-type substrate 34', the P-type well region 36' and the first N-type heavily doped region 42 form a silicon controlled rectifier.

[0068] Because the N-type substrate 34' is a lightly doped N-type substrate, the interface between the N-type substrate 34' and the P-type well region 36' has a high breakdown voltage. To reduce the trigger voltage of the silicon controlled rectifier, the doping concentration of the N-type doped region 40 is increased, or the distance 'a' between the N-type doped region 40 and the first heavily doped N-type region 42 is decreased. In a preferred embodiment, the doping concentration of the N-type doped region 40 is higher than the doping concentration of the N-type substrate 34'. When the doping concentration of the N-type doped region 40 is increased or the distance 'a' between the N-type doped region 40 and the first heavily doped N-type region 42 is decreased, the punch-through voltage of the bicarrier junction transistor formed by the N-type doped region 40, the P-type well region 36', and the first heavily doped N-type region 42 is reduced, thereby reducing the trigger voltage of the silicon controlled rectifier. When the first pin 46 receives a positive electrostatic discharge voltage and the second pin 48 is grounded, the electrostatic discharge current flows from the first pin 46 through the first heavily doped P-type region 38, the N-type substrate 34', the external conductor 44, the N-type doped region 40, the P-type well region 36', and the first heavily doped N-type region 42 to the second pin 48. The positive electrostatic discharge voltage causes the interface between the N-type doped region 40 and the P-type well region 36' to break down, thereby first turning on the parasitic bicarrier junction transistor formed by the N-type doped region 40, the P-type well region 36', and the first heavily doped N-type region 42. Then, the parasitic silicon-controlled rectifier formed by the first heavily doped P-type region 38, the N-type substrate 34', the P-type well region 36', and the first heavily doped N-type region 42 is turned on. Finally, the electrostatic discharge current is released from the first pin 46 through the first P-type heavily doped region 38, the N-type substrate 34', the P-type well region 36', and the first N-type heavily doped region 42 to the second pin 48. In some embodiments of the present invention, the first N-type heavily doped region 42 is located between the N-type doped region 40 and the first P-type heavily doped region 38, thus providing a short conduction distance for the silicon controlled rectifier between the first pin 46 and the second pin 48. In this embodiment, the first N-type heavily doped region 42 is as close as possible to the first P-type heavily doped region 38. When the silicon controlled rectifier stably releases the electrostatic discharge current, the electrostatic discharge current does not flow through the N-type doped region 40. Furthermore, the total parasitic capacitance of the silicon controlled rectifier is dominated by the parasitic capacitance formed by the first P-type heavily doped region 38 and the N-type substrate 34'. Because the interface between the first heavily doped P-type region 38 and the N-type substrate 34' has a small area, and the N-type substrate 34' has a low doping concentration, a low parasitic capacitance is formed by the first heavily doped P-type region 38 and the N-type substrate 34'. Therefore, the silicon controlled rectifier has low clamping voltage, low on-resistance, and low parasitic capacitance.

[0069] To stabilize the voltage of the P-type well region 36', the P-type well region 36' may be coupled to the second pin 48. In some embodiments of the present invention, the electrostatic discharge protection device may further include a second heavily doped P-type region 50 disposed in the P-type well region 36'. An N-type doped region 40 is disposed between the first heavily doped N-type region 42 and the second heavily doped P-type region 50. The second heavily doped P-type region 50 is coupled to the second pin 48 to form an ohmic contact. When a positive electrostatic discharge voltage causes the interface between the N-type doped region 40 and the P-type well region 36' to break down, the electrostatic discharge current also flows through the second heavily doped P-type region 50 to the second pin 48. Because the second heavily doped P-type region 50 is close to the interface between the N-type doped region 40 and the P-type well region 36', the parasitic resistance R' of the P-type well region 36' between the N-type doped region 40 and the second heavily doped P-type region 50 is... PW1 It is low. That is, the silicon controlled rectifier requires a higher trigger current to turn on. In fact, the distance b between the N-type doped region 40 and the second heavily P-type doped region 50 is adjustable. When the distance b between the N-type doped region 40 and the second heavily P-type doped region 50 is short, the parasitic resistance R' is low. PW1 It is low. When the distance b between the N-type doped region 40 and the second P-type heavily doped region 50 is long, the parasitic resistance R' is low. PW1 It is high. Therefore, the silicon controlled rectifier has an adjustable trigger current. In this embodiment, the parasitic resistance R' PW1 The low current required for the silicon controlled rectifier (SCR) to turn on effectively reduces the chance of false triggering. In some embodiments of the invention, the electrostatic discharge protection device may further include a second heavily doped N-type region 52 disposed in the N-type substrate 34'. The second heavily doped N-type region 52 is coupled to the N-type doped region 40 via an external conductor 44 to form an ohmic contact. The second heavily doped N-type region 52 is used to allow electrostatic discharge current to pass through.

[0070] Figure 15 This is a structural cross-sectional view of the electrostatic discharge protection device according to the eleventh embodiment of the present invention. Please refer to [link / reference]. Figure 15 The following describes an eleventh embodiment of the electrostatic discharge protection device. The difference between the eleventh and tenth embodiments is that the eleventh embodiment's P-type well region 36' has a region between the N-type doped region 40 and the first heavily doped N-type region 42, and the dielectric layer 54 and the conductive gate 56 are sequentially disposed on this region of the P-type well region 36'. The conductive gate 56 is coupled to the second pin 48 and the first heavily doped N-type region 42. When a positive electrostatic discharge voltage is applied to the first pin 46 and the second pin 48 is grounded, leakage current can be prevented from passing through the region of the P-type well region 36' between the N-type doped region 40 and the first heavily doped N-type region 42. The remaining features of the eleventh embodiment have been described in the tenth embodiment and will not be repeated here.

[0071] Figure 16This is a structural cross-sectional view of the electrostatic discharge protection device according to the twelfth embodiment of the present invention. Please refer to [link / reference]. Figure 16 The following describes a twelfth embodiment of the electrostatic discharge protection device. The difference between the twelfth and tenth embodiments is that the twelfth embodiment has a P-type well region 36' located between the N-type doped region 40 and the first heavily doped N-type region 42. A dielectric layer 54 and a conductive gate 56 are sequentially disposed in this region of the P-type well region 36'. The conductive gate 56 is coupled to an external conductor 44. When a positive electrostatic discharge voltage is applied to the first pin 46 and the second pin 48 is grounded, the positive electrostatic discharge voltage helps to conduct the parasitic field-effect transistor formed by the dielectric layer 54, the conductive gate 56, the N-type doped region 40, the P-type well region 36', and the first heavily doped N-type region 42, thereby reducing the trigger voltage of the silicon controlled rectifier. The remaining features of the twelfth embodiment have been described in the tenth embodiment and will not be repeated here.

[0072] Figure 17 This is a structural cross-sectional view of the electrostatic discharge protection device according to the thirteenth embodiment of the present invention. Please refer to [link / reference]. Figure 17 The following describes a thirteenth embodiment of the electrostatic discharge protection device. The difference between the thirteenth and tenth embodiments is that the thirteenth embodiment's P-type well region 36' has a region between the N-type doped region 40 and the first heavily doped N-type region 42, with the dielectric layer 54 and the conductive gate 56 sequentially disposed on this region of the P-type well region 36'. Furthermore, the thirteenth embodiment includes an electrostatic discharge detection circuit 58 coupled to an external conductor 44, the conductive gate 56, and the first heavily doped N-type region 42. The first heavily doped P-type region 38 is coupled to a first pin 46. The first heavily doped N-type region 42 is coupled to a second pin 48 and receives a reference voltage. In the thirteenth embodiment, a positive electrostatic discharge voltage is applied to the first pin 46, and the second pin 48 is grounded. When the first pin 46 receives a positive electrostatic discharge voltage higher than the ground voltage used as a reference voltage, the electrostatic discharge detection circuit 58 responds to the positive electrostatic discharge voltage to turn on the parasitic field-effect transistor formed by the dielectric layer 54, the conductive gate 56, the N-type doped region 40, the P-type well region 36', and the first heavily doped N-type region 42, thereby reducing the trigger voltage of the silicon controlled rectifier. The electrostatic discharge detection circuit 58 can improve the sensitivity of releasing electrostatic discharge current. When the first heavily doped P-type region 38 receives an input voltage via the first pin 46, and its input voltage is less than or equal to the ground voltage used as a reference voltage, the electrostatic discharge detection circuit 58 responds to the input voltage to turn off the parasitic field-effect transistor formed by the dielectric layer 54, the conductive gate 56, the N-type doped region 40, the P-type well region 36', and the first heavily doped N-type region 42. The remaining features of the thirteenth embodiment have been described in the tenth embodiment and will not be repeated here.

[0073] Figure 18 This is a schematic diagram of an electrostatic discharge detection circuit according to another embodiment of the present invention. Please refer to [link / reference]. Figure 17 and Figure 18 The electrostatic discharge detection circuit 58 may include an inverter 60, a resistor 62, and a capacitor 64. The output of the inverter 60 is coupled to a conductive gate 56, and the resistor 62 is coupled between an external conductor 44 and the input of the inverter 60. The capacitor 64 is coupled between the input of the inverter 60 and a ground voltage, which serves as a reference voltage. In this embodiment, the capacitor 64 is coupled to a second pin 48. To release the electrostatic discharge current, the time constant formed by the resistor 62 and the capacitor 64 is 0.1 to 1 microsecond (μs).

[0074] Figure 19 This is a structural cross-sectional view of the electrostatic discharge protection device according to the fourteenth embodiment of the present invention. Please refer to [link / reference]. Figure 14 and Figure 19 The following describes the fourteenth embodiment of the electrostatic discharge protection device. The fourteenth embodiment differs from the tenth embodiment in that it further includes a P-type well region 66', which is disposed within the P-type well region 36'. The doping concentration of the P-type well region 66' is greater than that of the P-type well region 36', but less than that of the second heavily doped P-type region 50, which is disposed within the P-type well region 66'. The P-type well region 66' is directly adjacent to the N-type doped region 40. The parasitic resistance R' of the P-type well region 66' between the N-type doped region 40 and the second heavily doped P-type region 50... PW2 The parasitic resistance R' of the P-type well region 36' between the N-type doped region 40 and the second heavily P-type doped region 50 is lower than that of the P-type well region 36'. PW1 To reduce the parasitic resistance R' in the P-type well section 66'. PW2 The bottom of the P-type well region 66' can be deeper than the bottom of the N-type doped region 40 and the second heavily P-type doped region 50. Compared to the silicon-controlled rectifier of the tenth embodiment, due to the parasitic resistance R... PW2 Below the parasitic resistance R PW1 Therefore, the silicon-controlled rectifier of the fourteenth embodiment requires a higher trigger current to turn on. Other features of the fourteenth embodiment have been described in the tenth embodiment and will not be repeated here.

[0075] Figure 20 This is a structural cross-sectional view of the electrostatic discharge protection device according to the fifteenth embodiment of the present invention. Please refer to [link / reference]. Figure 15 and Figure 20The following describes the fifteenth embodiment of the electrostatic discharge protection device. The fifteenth embodiment differs from the eleventh embodiment in that it further includes a P-type well region 66', which is disposed within the P-type well region 36'. The doping concentration of the P-type well region 66' is greater than that of the P-type well region 36', but less than that of the second heavily doped P-type region 50, which is disposed within the P-type well region 66'. The P-type well region 66' is directly adjacent to the N-type doped region 40. The parasitic resistance R' of the P-type well region 66' between the N-type doped region 40 and the second heavily doped P-type region 50... PW2 The parasitic resistance R' of the P-type well region 36' between the N-type doped region 40 and the second heavily P-type doped region 50 is lower than that of the P-type well region 36'. PW1 To reduce the parasitic resistance R' in the P-type well section 66'. PW2 The bottom of the P-type well region 66' can be deeper than the bottom of the N-type doped region 40 and the second heavily P-type doped region 50. Compared to the silicon-controlled rectifier of the eleventh embodiment, due to the parasitic resistance R... PW2 Below the parasitic resistance R PW1 Therefore, the silicon controlled rectifier of the fifteenth embodiment requires a higher trigger current to turn on. Other features of the fifteenth embodiment have been described in the eleventh embodiment and will not be repeated here.

[0076] Figure 21 This is a structural cross-sectional view of the electrostatic discharge protection device according to the sixteenth embodiment of the present invention. Please refer to [link / reference]. Figure 16 and Figure 21 The following describes the sixteenth embodiment of the electrostatic discharge protection device. The sixteenth embodiment differs from the twelfth embodiment in that it further includes a P-type well region 66', which is disposed within the P-type well region 36'. The doping concentration of the P-type well region 66' is greater than that of the P-type well region 36', but less than that of the second heavily doped P-type region 50, which is disposed within the P-type well region 66'. The P-type well region 66' is directly adjacent to the N-type doped region 40. The parasitic resistance R' of the P-type well region 66' between the N-type doped region 40 and the second heavily doped P-type region 50... PW2 The parasitic resistance R' of the P-type well region 36' between the N-type doped region 40 and the second heavily P-type doped region 50 is lower than that of the P-type well region 36'. PW1 To reduce the parasitic resistance R' in the P-type well section 66'. PW2 The bottom of the P-type well region 66' can be deeper than the bottom of the N-type doped region 40 and the second heavily P-type doped region 50. Compared to the silicon-controlled rectifier of the twelfth embodiment, due to the parasitic resistance R... PW2 Below the parasitic resistance R PW1 Therefore, the silicon controlled rectifier of the sixteenth embodiment requires a higher trigger current to turn on. Other features of the sixteenth embodiment have been described in the twelfth embodiment and will not be repeated here.

[0077] According to the above embodiments, the electrostatic discharge protection device is coupled to the N-type well region or N-type substrate to the N-type doped region to have low parasitic capacitance, low clamping voltage, low trigger voltage and high trigger current.

[0078] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the present invention.

Claims

1. An electrostatic discharge protection device, characterized in that, include: A P-type substrate; An N-type well region is disposed in the P-type substrate; A first P-type heavily doped region is located within the N-type well region; An N-type doped region and a first N-type heavily doped region are disposed in the P-type substrate, wherein the N-type doped region is coupled to the N-type well region through an external wire, and the external wire is decoupled from the first P-type heavily doped region. as well as A second N-type heavily doped region is disposed in the N-type well region, wherein the second N-type heavily doped region is coupled to the N-type doped region through the external wire.

2. The electrostatic discharge protection device as described in claim 1, characterized in that, The first P-type heavily doped region is coupled to a first pin, the first pin is decoupled from the external conductor, and the first N-type heavily doped region is coupled to the P-type substrate to a second pin.

3. The electrostatic discharge protection device as described in claim 1, characterized in that, The first N-type heavily doped region is located between the N-type doped region and the N-type well region.

4. The electrostatic discharge protection device as described in claim 1, characterized in that, It also includes a second P-type heavily doped region disposed in the P-type substrate, wherein the N-type doped region is disposed between the first N-type heavily doped region and the second P-type heavily doped region.

5. The electrostatic discharge protection device as described in claim 4, characterized in that, It also includes a P-type well region disposed in the P-type substrate, wherein the doping concentration of the P-type well region is greater than the doping concentration of the P-type substrate and less than the doping concentration of the second P-type heavily doped region, the second P-type heavily doped region is disposed in the P-type well region, and the P-type well region is directly adjacent to the N-type doped region.

6. The electrostatic discharge protection device as described in claim 1, characterized in that, The P-type substrate has a region located between the N-type doped region and the first heavily N-type doped region. A dielectric layer and a conductive gate are sequentially disposed on the region, and the conductive gate is coupled to the external wire.

7. The electrostatic discharge protection device as described in claim 1, characterized in that, The P-type substrate has a region located between the N-type doped region and the first heavily N-type doped region. A dielectric layer and a conductive gate are sequentially disposed on the region, and the conductive gate is coupled to the first heavily N-type doped region.

8. The electrostatic discharge protection device as described in claim 1, characterized in that, It also includes an electrostatic discharge detection circuit. The P-type substrate has a region located between the N-type doped region and the first heavily doped N-type region. A dielectric layer and a conductive gate are sequentially disposed on the region. The electrostatic discharge detection circuit is coupled to the external wire, the conductive gate and the first heavily doped N-type region. The first heavily doped P-type region is coupled to a first pin and the first heavily doped N-type region is coupled to a second pin and receives a reference voltage. When the first pin receives a positive electrostatic discharge voltage higher than the reference voltage, the electrostatic discharge detection circuit responds to the positive electrostatic discharge voltage to conduct the parasitic field-effect transistor formed by the dielectric layer, the conductive gate, the N-type doped region, the P-type substrate and the first heavily doped N-type region.

9. The electrostatic discharge protection device as described in claim 8, characterized in that, The electrostatic discharge detection circuit includes: An inverter whose output is coupled to the conductive gate; A resistor is coupled between the external lead and the input terminal of the inverter; and A capacitor is coupled between the input terminal of the inverter and the reference voltage.

10. An electrostatic discharge protection device, characterized in that, include: an N-type substrate; A P-type well region is disposed in the N-type substrate; A first P-type heavily doped region is disposed in the N-type substrate; An N-type doped region and a first N-type heavily doped region are disposed in the P-type well region, wherein the N-type doped region is coupled to the N-type substrate through an external wire, and the external wire is decoupled from the first P-type heavily doped region. as well as A second heavily doped N-type region is disposed in the N-type substrate, wherein the second heavily doped N-type region is coupled to the N-type doped region through the external wire.

11. The electrostatic discharge protection device as described in claim 10, characterized in that, The first P-type heavily doped region is coupled to a first pin, the first pin is decoupled from the external conductor, and the first N-type heavily doped region is coupled to the P-type well region to a second pin.

12. The electrostatic discharge protection device as described in claim 10, characterized in that, The first N-type heavily doped region is located between the N-type doped region and the first P-type heavily doped region.

13. The electrostatic discharge protection device as described in claim 10, characterized in that, It also includes a second P-type heavily doped region disposed in the P-type well region, wherein the N-type doped region is disposed between the first N-type heavily doped region and the second P-type heavily doped region.

14. The electrostatic discharge protection device as described in claim 10, characterized in that, The P-type well region has a region located between the N-type doped region and the first N-type heavily doped region. A dielectric layer and a conductive gate are sequentially disposed on the region, and the conductive gate is coupled to the external wire.

15. The electrostatic discharge protection device as described in claim 10, characterized in that, The P-type well region has a region located between the N-type doped region and the first N-type heavily doped region. A dielectric layer and a conductive gate are sequentially disposed on the region, and the conductive gate is coupled to the first N-type heavily doped region.

16. The electrostatic discharge protection device as described in claim 10, characterized in that, It also includes an electrostatic discharge detection circuit. The P-type well region has a region located between the N-type doped region and the first heavily doped N-type region. A dielectric layer and a conductive gate are sequentially disposed on the region. The electrostatic discharge detection circuit is coupled to the external wire, the conductive gate and the first heavily doped N-type region. The first heavily doped P-type region is coupled to a first pin and the first heavily doped N-type region is coupled to a second pin and receives a reference voltage. When the first pin receives a positive electrostatic discharge voltage higher than the reference voltage, the electrostatic discharge detection circuit responds to the positive electrostatic discharge voltage to conduct the parasitic field-effect transistor formed by the dielectric layer, the conductive gate, the N-type doped region, the P-type well region and the first heavily doped N-type region.

17. The electrostatic discharge protection device as described in claim 16, characterized in that, The electrostatic discharge detection circuit includes: An inverter whose output is coupled to the conductive gate; A resistor is coupled between the external lead and the input terminal of the inverter; and A capacitor is coupled between the input terminal of the inverter and the reference voltage.

Images