A monolithic silicon light integrated device based on white light and a preparation method thereof

Abstract

The application provides a monolithic silicon light integrated device based on white light and a preparation method thereof, and belongs to the field of optoelectronic integration, and the structure comprises a MOS structure light emitting device, a control electrode, an inclined surface coupling device, a planar light waveguide, a light receiving device, a detection electrode and a shared bottom electrode. The monolithic silicon light integrated device based on white light is designed, the 350nm-950nm continuous spectrum white light emitted by the MOS structure light emitting device prepared on the Si substrate is used as the basis, the control electrode, the light source, the light coupling device, the light waveguide and the light receiving device are prepared on the same Si substrate through the COMS process, special packaging is not needed, and the device directly works in the atmospheric environment. The monolithic silicon light integrated device based on white light and the preparation method thereof simplify the process flow, reduce the preparation cost, and realize the monolithic integrated silicon-based optoelectronic device which is easy to prepare.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a monolithic silicon photonic integrated device based on white light and its fabrication method. Background Technology

[0002] Silicon photonics integration technology integrates photonic devices and microelectronic devices onto a single chip using CMOS processes, employing light as the signal transmission medium to achieve on-chip optical interconnects. Compared to electrical interconnects, optical interconnects offer advantages such as higher interconnect integration, wider bandwidth, lower power consumption, and minimal signal delay and crosstalk. Optoelectronic integration technology represents a new research direction in modern integrated circuit technology and is poised to lead a new revolution in integrated circuit technology.

[0003] Currently, the main technical challenges in achieving silicon photonics integration lie in silicon-based light source devices. Existing solutions for silicon-based light sources include: external laser sources; bonding III-V group light-emitting diodes onto a silicon wafer; and monolithic integration of silicon-based light-emitting devices. However, external lasers cannot meet the requirements for large-scale integration; hybrid integration has extremely high requirements for fabrication and packaging processes, poor CMOS compatibility, and high fabrication costs, which are not conducive to large-scale integration; existing monolithically integrateable silicon-based light-emitting devices, such as silicon nanowire light-emitting devices, superlattice quantum well material silicon-based light-emitting devices, and misaligned ring light-emitting devices, still suffer from poor luminous stability, complex structures, and high fabrication and packaging costs, hindering the development of monolithic silicon photonics integration technology.

[0004] Therefore, it is particularly important to fabricate a monolithic silicon photonic integrated device that can fabricate light source devices and electronic devices on the same Si substrate. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a monolithic silicon photonic integrated device based on white light and its fabrication method, so as to provide a novel silicon-based monolithic optoelectronic integrated device.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A white light monolithic silicon photonic integrated device includes:

[0008] p-type doped Si substrate;

[0009] A SiO2 dielectric isolation layer is located on a p-type doped Si substrate.

[0010] A MOS structure light-emitting device is located on a p-type doped Si substrate;

[0011] A silicon photodiode light receiver device located on a p-type doped Si substrate;

[0012] The Mo control electrode is located on top of the SiO2 dielectric isolation layer;

[0013] The Mo detection electrode is located on top of the SiO2 dielectric isolation layer;

[0014] Si3N4 wedge optical coupling device, MOS structure light-emitting device and silicon photodiode light-receiving device;

[0015] Si3N4 planar optical waveguide, connecting two Si3N4 wedge-shaped optical coupling devices at both ends, is located on top of the SiO2 dielectric isolation layer;

[0016] The Mo-shared bottom electrode is located beneath the p-type doped Si substrate.

[0017] A further improvement of the technical solution of the present invention is that: the MOS structure light-emitting device sequentially comprises a p-type doped silicon substrate, an HfO2 high-k dielectric layer, and an ITO transparent top electrode; wherein, the doping concentration of the p-type doped silicon substrate is 10. 14 pcs / cm 3 ~ 10 18 pcs / cm 3 The thickness of the HfO2 high-k dielectric layer is 3nm~30nm; the thickness of the ITO transparent top electrode is 80nm~120nm.

[0018] A further improvement of the technical solution of the present invention is that the voltage applied to the MOS structure light-emitting device is in the range of 100mV to 60V, and the emission spectrum range is 350nm to 950nm.

[0019] A further improvement of the technical solution of the present invention is that the angle between the inclined surface of the Si3N4 wedge optical coupling device and the horizontal is 30°~60°.

[0020] A further improvement of the technical solution of the present invention is that the thickness of the Si3N4 planar optical waveguide is 200nm~300nm.

[0021] A further improvement of the technical solution of the present invention is that the thickness of the Mo control electrode, the Mo detection electrode and the Mo common bottom electrode is 80nm~120nm.

[0022] A method for fabricating a white-light monolithic silicon photonic integrated device includes the following steps:

[0023] A SiO2 dielectric isolation layer is grown epitaxially on a p-type doped Si substrate;

[0024] The region for fabricating a MOS light-emitting device is etched at a designated location in the SiO2 dielectric isolation layer using photolithography, exposing the p-type doped Si substrate in this region. At this location, an HfO2 light-emitting dielectric layer and an ITO transparent top electrode layer are sequentially deposited using magnetron sputtering, and the MOS structure light-emitting device is formed by etching.

[0025] In a designated location of the SiO2 dielectric isolation layer, a region for fabricating a silicon photodiode light receiver device is etched out using photolithography. In this region, a p-type doped Si substrate is exposed, and an n-type doped region is formed at this location using ion implantation. This process fabricates a silicon photodiode light receiver device.

[0026] Mo metal is deposited on the SiO2 dielectric isolation layer by magnetron sputtering, and a Mo control electrode is formed by photolithography, which is connected to the ITO transparent top electrode but does not block the light-emitting area.

[0027] Mo metal is deposited on the SiO2 dielectric isolation layer by magnetron sputtering, and a Mo detection electrode is formed by photolithography. The electrode is connected to the n-type region of the silicon photodiode without blocking the photosensitive area.

[0028] Si3N4 was deposited on the completed structure using PECVD, and a planar optical waveguide was formed using photolithography to connect the MOS structure light-emitting device and the silicon photodiode light-receiving device.

[0029] The Si3N4 planar waveguide above the MOS structure light-emitting device and the silicon photodiode light-receiving device is exposed by photolithography to expose the Si3N4 waveguide that needs to be etched. By controlling the temperature of the buffer oxide etchant and the baking time after the photoresist, the rate of lateral etching at different depths of the etchant is controlled to form a wedge-shaped optical coupling device.

[0030] Mo is deposited on the bottom of the completed Si substrate using a magnetron sputtering process to form a common bottom electrode, which is used as the circuit electrode for the MOS structure light-emitting device and the circuit electrode for the silicon photodiode light-receiving device.

[0031] A further improvement of the technical solution of the present invention is that the composition of the buffer oxide etching solution is HF: NH4F = 15:2, and the etching temperature is 25℃~80℃.

[0032] A further improvement to the technical solution of the present invention is that: before etching the inclined optical coupling device, the photoresist hardening temperature is 120℃ and the time is 60s~150s.

[0033] The technological advancements achieved by this invention due to the adoption of the above technical solutions are as follows:

[0034] 1. The present invention proposes a monolithic silicon photonic integrated device based on white light and its fabrication method. It uses a white light emitting device with a MOS structure that can be directly fabricated on a Si substrate as the light source. The control electrode, light source, optical coupler, optical waveguide and light receiving device are fabricated on the same Si substrate. The fabrication process meets the requirements of CMOS process and does not require the introduction of external light.

[0035] 2. Compared with existing technologies, it eliminates the high-cost bonding process for III-V group light-emitting devices, enabling low-cost and easy-to-fabricate monolithic silicon photonic integrated devices.

[0036] 3. The MOS structure light-emitting device based on this invention does not require packaging and can directly emit white light in air. Stable signal control can be achieved using control electrodes. The structure and characteristics of this invention's device eliminate the need for special packaging of the light-emitting device, further expanding its application range and scenarios.

[0037] 4. This invention proposes a novel monolithic silicon photonic integrated device and its fabrication method, which simplifies the silicon photonic integration process, reduces the fabrication cost, and realizes a low-cost monolithic integrated silicon-based optoelectronic device. Attached Figure Description

[0038] Figure 1 A schematic diagram of a monolithic silicon photonic integrated device structure based on white light is provided for an embodiment of the present invention;

[0039] Figure 2 This is a schematic cross-sectional view of a MOS structure light-emitting device provided in an embodiment of the present invention;

[0040] Figure 3 This is a schematic cross-sectional view of a silicon photodiode optical receiver device provided in an embodiment of the present invention;

[0041] Figure 4 The emission spectrum of the MOS structure light-emitting device provided in the embodiment of the present invention;

[0042] Figure 5 A flowchart illustrating the fabrication process of a monolithic silicon photonic integrated device based on white light, provided for an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of the oblique surface etching of the wedge-shaped optical coupling device provided in an embodiment of the present invention;

[0044] Among them, 101 is a p-type doped Si substrate, 102 is a Mo common bottom electrode, 103 is a SiO2 dielectric isolation layer, 104 is a Mo control electrode, 105 is a MOS structure light-emitting device, 106 is a first Si3N4 oblique wedge optical coupler, 107 is a Si3N4 planar optical waveguide, 108 is a silicon photodiode optical receiving device, 109 is a second Si3N4 oblique wedge optical coupler, 110 is a detection electrode, 201 is a HfO2 high-k dielectric layer, 202 is an ITO transparent top electrode, 301 is an n-type doped region, 601 is a photoresist, and S702 is a buffered oxide etchant. Detailed implementation manners

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments:

[0046] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0047] In addition, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", etc. may explicitly or implicitly include at least one such feature.

[0048] The core idea of the present invention is that the present invention utilizes a MOS structure light-emitting device directly prepared on a Si substrate and the continuous spectrum white light emitted therefrom, and proposes a monolithic silicon photonics integrated device in which optical and electrical devices such as a light source device, an optical waveguide, and an optical receiving device for realizing silicon photonics integration are prepared on the same Si substrate. Moreover, the device provided by the present invention does not require special packaging and can directly operate in an atmospheric environment. At the same time, the present invention also provides a preparation method for a monolithic silicon photonics integrated device based on white light. By preparing an oblique wedge-shaped inclined surface coupler, the coupling of a broadband light source can be realized, and a monolithic silicon photonics integration is achieved in cooperation with a silicon photodiode optical receiver. All the photon devices and electronic devices involved in the present invention meet the CMOS preparation process. Compared with the prior art, the bonding process of III-V group LED light source devices is omitted, the preparation process is simplified, the preparation cost is reduced, and low-cost and easy-to-prepare monolithic integrated silicon-based optoelectronic devices are realized.

[0049] Refer Figure 1 as shown Figure 1 Schematic diagram of a monolithic silicon photonics integrated device based on white light provided by an embodiment of the present invention. The monolithic silicon photonics integrated device based on white light provided by an embodiment of the present invention includes:

[0050] A p-type doped Si substrate 101, serving as a substrate for device fabrication;

[0051] A SiO2 dielectric isolation layer 103, located above the p-type doped Si substrate 101, used for electrical isolation;

[0052] A MOS structure light-emitting device 105, located above the p-type doped Si substrate 101, serving as a light source;

[0053] A silicon photodiode optical receiving device 108, located above the p-type doped Si substrate 101, used for receiving an optical signal and converting it into an electrical signal;

[0054] A Mo control electrode 104, located above the SiO2 dielectric isolation layer 103, used for regulating the generation of an optical signal by electrical excitation;

[0055] A Mo detection electrode 110, located above the SiO2 dielectric isolation layer 103, used for detecting the converted electrical signal;

[0056] A first Si3N4 wedge-shaped optical coupler 106, located above the MOS structure light-emitting device 105, used for coupling the optical signal generated by the MOS structure light-emitting device 105 into the planar optical waveguide 107;

[0057] A second Si3N4 wedge-shaped optical coupler 109, located above the silicon photodiode optical receiving device 108, coupling the optical signal in the planar optical waveguide 107 into the silicon photodiode optical receiving device 108;

[0058] A Si3N4 planar optical waveguide 107, connecting the first Si3N4 wedge-shaped optical coupler 106 and the second Si3N4 wedge-shaped optical coupler 109 at both ends, located above the SiO2 dielectric isolation layer 103, used for optical signal transmission;

[0059] A Mo common bottom electrode 102, located below the p-type doped Si substrate 101, serving as a loop electrode for exciting the MOS structure light-emitting device 105 to emit light and a detection loop electrode for the silicon photodiode optical receiving device 108.

[0060] Refer Figure 2 as shown Figure 2 Schematic cross-sectional view of the MOS structure light-emitting device 105. The main structure of the MOS structure light-emitting device 105 mainly includes: a p-type doped silicon substrate 101; a HfO2 high-k dielectric layer 201; an ITO transparent top electrode 202.

[0061] Refer Figure 3 As shown Figure 3 Figure 150 is a schematic cross-sectional view of the silicon photodiode optical receiving device 108. The silicon photodiode optical receiving device 108 mainly includes, in sequence, a p-type doped Si substrate 101 and an n-type ion implantation doped region 301.

[0062] Figure 4 Figure 154 is a luminescence spectrum diagram of the MOS structure light-emitting device. When a voltage of 100 mV to 60 V is applied to the MOS structure light-emitting device, continuous spectrum white light with a wavelength of 350 nm to 950 nm can be excited.

[0063] Further, the MOS structure light-emitting device sequentially includes a p-type doped silicon substrate with a doping concentration of 10 14 per cm 3 ~ 10 18 per cm 3 ; a HfO2 high-k dielectric layer with a thickness of 3 nm to 30 nm; and an ITO transparent top electrode with a thickness of 80 nm to 120 nm.

[0064] Further, the included angle between the inclined plane of the Si3N4 inclined wedge optical coupling device and the horizontal plane is 30° to 60°.

[0065] Further, the Si3N4 planar optical waveguide has a thickness of 200 nm to 300 nm.

[0066] Further, all the Mo electrodes have a thickness of 80 nm to 120 nm.

[0067] Refer Figure 5 As shown Figure 5 Figure 166 is a flowchart of the preparation of a monolithic silicon photonics integrated device based on white light provided by the present invention. Combining Figure 5 The preparation method of a monolithic silicon photonics integrated device based on white light provided by an embodiment of the present invention includes the following steps:

[0068] S1: Provide a p-type doped Si substrate 101, and epitaxially grow a 1000-nm SiO2 dielectric isolation layer 103 on the p-type doped Si substrate by low-temperature CVD.

[0069] S2: Through photolithography, etch out the region for preparing the MOS light-emitting device 105 at a specified position on the SiO2 dielectric isolation layer 103, expose the p-type doped Si substrate 101 in this region, and deposit a HfO2 light-emitting dielectric layer 201 at this position by magnetron sputtering. Sputtering parameters: using a hafnium (Hf) metal target, an argon-oxygen ratio of Ar / O2 (20 sccm: 20 sccm), and a pressure of 2.3 × 10 −1Pa, power 150 W; ITO transparent top electrode layer 202; sputtering parameters: ceramic target indium tin oxide (ITO), argon / oxygen ratio Ar / O2 (20 sccm: 0 sccm), pressure 1.3 × 10⁻⁶ .... −1 Pa, power 70 W; ITO top electrode 202 is etched by photolithography to form a MOS structure light-emitting device 105 of a specified pattern and size;

[0070] S3: At a designated location on the SiO2 dielectric isolation layer 103, a region for fabricating a silicon photodiode light receiver device 109 is etched out using a photolithography process. In this region, a p-type doped Si substrate 101 is exposed, and an n-type doped region 301 is formed at this location using an ion implantation process, so that a pn junction is formed between the n-type doped silicon substrate 101 and the p-type doped silicon substrate 101, ultimately forming a silicon photodiode light receiver device 108.

[0071] S4: Mo metal was deposited on the SiO2 dielectric isolation layer 103 by magnetron sputtering. The sputtering parameters were: molybdenum (Mo) target, Ar / O2 ratio (20 sccm: 0 sccm), and pressure 1.3 × 10⁻⁶. −1 Pa, power 100 W. The Mo metal layer is etched by photolithography to form a control electrode 104, which is connected to the ITO transparent top electrode 202 but does not block the light-emitting area;

[0072] S5: Mo metal was deposited on the SiO2 dielectric isolation layer 103 by magnetron sputtering. The sputtering parameters were: molybdenum (Mo) target, Ar / O2 ratio (20 sccm: 0 sccm), and pressure 1.3 × 10⁻⁶. −1 Pa, power 100 W. The Mo metal layer is etched by photolithography to form the detection electrode 110, which is connected to the n-type region of the silicon photodiode 108 without blocking the photosensitive area;

[0073] S6: Si3N4 is deposited on the completed structure using PECVD. The preparation parameters are: ammonia (NH3) and Si alkane (SiH4), mixed gas (NH3:SiH4 = 50 sccm: 10 sccm), reaction temperature 250 ℃, and discharge power 100 W. The layer is then etched using photolithography to form a Si3N4 planar optical waveguide 107, which connects the MOS structure light-emitting device 105 to the silicon photodiode light-receiving device 108.

[0074] S7: The Si3N4 planar waveguide above the MOS structure light-emitting device 105 and the silicon photodiode light-receiving device 108 is exposed by photolithography to expose the Si3N4 waveguide portion to be etched. By controlling the temperature of the buffer oxide etchant S702 (BOE, HF: NH4F = 15: 2) and the baking time after photoresist, the rate of lateral etching at different depths of the etchant is controlled to form the wedge-shaped optical coupling devices 106 and 109.

[0075] Furthermore, firstly, temperature can change the etching rate of the BOE solution, and then... Figure 6 As shown, by controlling the baking time after photoresist curing, the adhesion between photoresist 601 and Si3N4 planar optical waveguide layer 107 can be controlled, thereby allowing BOE etching solution to penetrate into the gap between photoresist and Si3N4 layer. This allows the penetrating BOE etching solution and the external BOE etching solution to work together to produce lateral and longitudinal etching, ultimately etching out a bevel to form the first wedge Si3N4 optical coupler device 106 and the second wedge Si3N4 optical coupler device 109.

[0076] Step S8: Mo is deposited on the bottom of the completed Si substrate using magnetron sputtering. The sputtering parameters are: a molybdenum (Mo) target, an argon / oxygen ratio of Ar / O2 (20 sccm: 0 sccm), and a pressure of 1.3 × 10⁻⁶. −1 Pa and 100 W power form a common bottom electrode 102, which is used as the circuit electrode of the MOS structure light-emitting device and the detection circuit electrode of the silicon photodiode light-receiving device.

[0077] In summary, this invention proposes a monolithic silicon photonic integrated device based on white light. Utilizing a MOS structure light-emitting device that can be directly fabricated on a Si substrate and the continuous-spectrum white light it emits, this invention proposes a method for fabricating photoelectric devices such as light source devices, optical waveguides, and light receivers on the same Si substrate. Furthermore, the device provided by this invention does not require special packaging and can operate directly in atmospheric environments. Simultaneously, this invention also provides a method for fabricating a monolithic silicon photonic integrated device based on white light, fabricating a wedge-shaped inclined coupler to achieve coupling to a broadband light source, and using it in conjunction with a silicon photodiode light receiver to achieve monolithic silicon photonic integration. All photonic and electronic devices involved in this invention meet CMOS fabrication process requirements. Compared with existing technologies, it eliminates the bonding process for III-V group LED light source devices, simplifies the fabrication process, reduces fabrication costs, and realizes a low-cost, easily fabricated monolithic integrated silicon-based optoelectronic device.

Claims

1. A white light monolithic silicon photonic integrated device, characterized in that, include: p-type doped Si substrate; A SiO2 dielectric isolation layer is located on a p-type doped Si substrate. A MOS structure light-emitting device is located on a p-type doped Si substrate; A silicon photodiode light receiver device located on a p-type doped Si substrate; The Mo control electrode is located on top of the SiO2 dielectric isolation layer; The Mo detection electrode is located on top of the SiO2 dielectric isolation layer; Si3N4 wedge optical coupling device, MOS structure light-emitting device and silicon photodiode light-receiving device; Si3N4 planar optical waveguide, connecting two Si3N4 wedge-shaped optical coupling devices at both ends, is located on top of the SiO2 dielectric isolation layer; The Mo-shared bottom electrode is located beneath the p-type doped Si substrate.

2. The white light monolithic silicon photonic integrated device according to claim 1, characterized in that, The MOS structure light-emitting device sequentially comprises a p-type doped silicon substrate, an HfO2 high-k dielectric layer, and an ITO transparent top electrode; wherein, the doping concentration of the p-type doped silicon substrate is 10. 14 pcs / cm 3 ~ 10 18 pcs / cm 3 The thickness of the HfO2 high-k dielectric layer is 3nm~30nm; the thickness of the ITO transparent top electrode is 80nm~120nm.

3. The white light monolithic silicon photonic integrated device according to claim 1, characterized in that, The MOS structure light-emitting device has an applied voltage range of 100mV to 60V and an emission spectrum range of 350nm to 950nm.

4. The white light monolithic silicon photonic integrated device according to claim 1, characterized in that, The angle between the inclined plane of the Si3N4 wedge optical coupling device and the horizontal plane is 30°~60°.

5. A white-light monolithic silicon photonic integrated device according to claim 1, characterized in that, The thickness of the Si3N4 planar optical waveguide is 200nm~300nm.

6. A white-light monolithic silicon photonic integrated device according to claim 1, characterized in that, The thickness of the Mo control electrode, Mo detection electrode, and Mo shared bottom electrode is 80 nm to 120 nm.

7. A method for fabricating a white monolithic silicon photonic integrated device, characterized in that, The method for fabricating a white light monolithic silicon photonic integrated device as described in any one of claims 1 to 6 includes the following steps: A SiO2 dielectric isolation layer is grown epitaxially on a p-type doped Si substrate; The region for fabricating a MOS light-emitting device is etched at a designated location in the SiO2 dielectric isolation layer using photolithography, exposing the p-type doped Si substrate in this region. At this location, an HfO2 light-emitting dielectric layer and an ITO transparent top electrode layer are sequentially deposited using magnetron sputtering, and the MOS structure light-emitting device is formed by etching. In a designated location of the SiO2 dielectric isolation layer, a region for fabricating a silicon photodiode light receiver device is etched out using photolithography. In this region, a p-type doped Si substrate is exposed, and an n-type doped region is formed at this location using ion implantation. This process fabricates a silicon photodiode light receiver device. Mo metal is deposited on the SiO2 dielectric isolation layer by magnetron sputtering, and a Mo control electrode is formed by photolithography, which is connected to the ITO transparent top electrode but does not block the light-emitting area. Mo metal is deposited on the SiO2 dielectric isolation layer by magnetron sputtering, and a Mo detection electrode is formed by photolithography. The electrode is connected to the n-type region of the silicon photodiode without blocking the photosensitive area. Si3N4 was deposited on the completed structure using PECVD, and a planar optical waveguide was formed using photolithography to connect the MOS structure light-emitting device and the silicon photodiode light-receiving device. The Si3N4 planar waveguide above the MOS structure light-emitting device and the silicon photodiode light-receiving device is exposed by photolithography to expose the Si3N4 waveguide that needs to be etched. By controlling the temperature of the buffer oxide etchant and the baking time after the photoresist, the rate of lateral etching at different depths of the etchant is controlled to form a wedge-shaped optical coupling device. Mo is deposited on the bottom of the completed Si substrate using a magnetron sputtering process to form a common bottom electrode, which is used as the circuit electrode for the MOS structure light-emitting device and the circuit electrode for the silicon photodiode light-receiving device.

8. The method for fabricating a white monolithic silicon photonic integrated device according to claim 7, characterized in that, The composition of the buffer oxide etching solution is HF: NH4F = 15: 2, and the etching temperature is 25℃~80℃.

9. The method for fabricating a white monolithic silicon photonic integrated device according to claim 7, characterized in that, Before etching the inclined optical coupling device, the photoresist hardening temperature is 120℃ and the time is 60s~150s.

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