Integrated schottky diode separate gate VDMOS and manufacturing method thereof

Abstract

The application discloses a separated gate VDMOS integrated with a Schottky diode and a preparation method, and relates to the field of semiconductor devices.The VDMOS comprises a substrate of a first conductive type and an active region prepared in the central region of the substrate, and the active region comprises a plurality of parallel distributed planar cells.For any planar cell, the planar cell comprises a planar gate unit prepared on the substrate and a virtual gate unit matched with the planar gate unit;on the cross section of the active region, the virtual gate unit is arranged in the planar gate unit, and the planar gate unit is at least divided into a first separated gate subunit and a second separated gate subunit; the virtual gate unit is insulated and separated from the first separated gate subunit and the second separated gate subunit; the virtual gate unit is in Schottky contact with a front first electrode metal above the substrate for forming a front first electrode, so as to form a Schottky diode.The VDMOS optimizes the reverse recovery characteristic of the device, reduces the switching loss of the device, and improves the switching performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and in particular to a split-gate VDMOS with integrated Schottky diode and its fabrication method. Background Technology

[0002] VDMOS is one of the most widely used power devices in power semiconductors. It has advantages such as easy driving, fast switching speed, integrability, and simple process.

[0003] On the one hand, during the turn-on process of existing VDMOS devices, the reverse recovery process of the body diode may cause current and voltage overshoot, leading to dynamic failure of the device. Furthermore, the manufacturing technology of VDMOS devices typically results in a high carrier lifetime, which in turn generates a high stored charge and a large peak reverse current in the diode, resulting in poor reverse recovery characteristics and affecting the switching performance of the device.

[0004] On the other hand, existing VDMOS devices have a large Cgd capacitance. A large Cgd capacitance will lead to high switching power consumption. At high frequency operation, the large switching loss will cause the device to heat up and cause product failure, reducing the stability of the device. Summary of the Invention

[0005] To address the aforementioned problems and technical requirements, the inventors have proposed a split-gate VDMOS with integrated Schottky diode and its fabrication method. The technical solution of this invention is as follows: A split-gate VDMOS with integrated Schottky diode includes a substrate of a first conductivity type and an active region fabricated in the central region of the substrate. The active region includes a plurality of planar cells arranged in parallel, wherein... For any planar cell, including planar gate cells fabricated on a substrate and cells adapted to planar gate cells... The virtual gate unit is configured; On the cross-section of the active region, the virtual gate unit is disposed in the planar gate unit, and the planar gate unit is divided into at least a first separated gate sub-unit and a second separated gate unit along the first direction; The virtual gate unit is insulated from and isolated from the first separate gate unit and the second separate gate unit; The first separation gate unit and the second separation gate unit are in ohmic contact with the front second electrode metal above the substrate for forming the front second electrode; The virtual gate unit makes a Schottky contact with the front first electrode metal Schottky above the substrate to form a front first electrode, thereby forming a Schottky diode.

[0006] A further technical solution is that the virtual gate unit includes a virtual gate trench and virtual gate polysilicon filling the virtual gate trench, wherein, The bottom of the virtual gate trench is located in a lightly doped region of the first conductivity type fabricated on the front side of the substrate; The virtual gate polysilicon is in contact with the front first electrode metal Schottky.

[0007] A further technical solution involves fabricating a voltage-resistant dielectric layer above the substrate, the voltage-resistant dielectric layer comprising an oxide layer and / or a protective layer, wherein... The pressure-resistant dielectric layer at least covers the inner wall of the virtual grid trench; The virtual gate polysilicon is insulated from the virtual gate trench by a voltage-resistant dielectric layer.

[0008] A further technical solution includes an insulating dielectric layer covering the front side of the substrate, and a barrier layer located above the insulating dielectric layer, wherein... The insulating dielectric layer covers the first separation gate unit and the second separation gate unit, and the front first electrode metal and the front second electrode metal are supported on the insulating dielectric layer; The barrier layer is in contact with the insulating dielectric layer and at least covers the virtual gate polysilicon. The virtual gate polysilicon is in contact with the front first electrode metal Schottky through a barrier layer.

[0009] A further technical solution is that the planar cell further includes a lightly doped region of a second conductivity type, a heavily doped region of a first conductivity type, and a heavily doped region of a second conductivity type, wherein, The second conductivity type lightly doped region is located below and in contact with the first conductivity type heavily doped region; The first heavily doped region of conductivity type is in contact with the second heavily doped region of conductivity type, and the first heavily doped region of conductivity type and the second heavily doped region of conductivity type penetrate the first lightly doped region of conductivity type; The junction depth of the heavily doped region of the first conductivity type is greater than the junction depth of the lightly doped region of the first conductivity type. The first conductivity type heavily doped region is in ohmic contact with the front first electrode metal.

[0010] A further technical solution is that, in any planar cell, the virtual gate unit is located between two lightly doped regions of the second conductivity type, wherein, The lightly doped region of the second conductivity type located on one side of the virtual gate cell overlaps with the corresponding first separate gate cell, and the lightly doped region of the second conductivity type located on the other side of the virtual gate cell overlaps with the corresponding second separate gate cell.

[0011] The first conductivity type heavily doped region corresponding to the first separated gate unit overlaps with the first separated gate unit, and the first conductivity type heavily doped region corresponding to the second separated gate unit overlaps with the second separated gate unit; The doping concentration of the heavily doped region of the first conductivity type is greater than the doping concentration of the lightly doped region of the first conductivity type, and the doping concentration of the heavily doped region of the second conductivity type is greater than the doping concentration of the lightly doped region of the second conductivity type.

[0012] A method for fabricating a split-gate VDMOS of an integrated Schottky diode, wherein the method comprises: A substrate of a first conductivity type is provided, and a planar cellular structure is fabricated within the active region; A method for fabricating a planar cellular structure includes fabricating a planar gate cell above a substrate corresponding to an active region, and fabricating a virtual gate cell within the planar gate cell, wherein the virtual gate cell divides the planar gate cell into a first separated gate sub-cell and a second separated gate cell along a first direction; When a metal layer is fabricated on the front side of the substrate, the front second electrode metal used to form the front second electrode is ohmically contacted with the first separation gate unit and the second separation gate unit. The front first electrode metal used to form the front first electrode is made into a Schottky contact with the virtual gate cell to form a Schottky diode.

[0013] A further technical solution is that the method for preparing planar cellular structures includes: A lightly doped region of the first conductivity type is prepared within the substrate, traversing the front side of the substrate. A planar gate cell is fabricated on the front side of the above-mentioned substrate. The planar gate cell includes a planar gate oxide layer and a planar gate polysilicon located on the planar gate oxide layer. A second conductivity type lightly doped region located below the first conductivity type lightly doped region is prepared in the above substrate; A virtual gate trench is fabricated in the above-mentioned planar gate polysilicon, wherein the bottom of the virtual gate trench is located in a lightly doped region of the first conductivity type; A voltage-resistant dielectric layer is prepared on the inner wall of a virtual gate trench and then filled with virtual gate polysilicon. The virtual gate polysilicon is insulated from the inner wall of the virtual gate trench by the voltage-resistant dielectric layer. An insulating dielectric layer covering the front side of the substrate is formed, and a second contact hole is prepared within the insulating dielectric layer; A barrier layer is formed on the insulating dielectric layer that forms the second contact hole, the barrier layer being at least covered by the second contact hole over the virtual gate polysilicon. A front first electrode metal for forming a front first electrode is prepared on the insulating dielectric layer on which the barrier layer is deposited. The front first electrode metal is in Schottky contact with the virtual gate polysilicon through the barrier layer above the virtual gate polysilicon.

[0014] A further technical solution is that the pressure-resistant dielectric layer includes an oxide layer and / or a protective layer, and the method for preparing the pressure-resistant dielectric layer includes: An oxide layer is prepared on the front side of the substrate where the virtual gate trench is formed, the oxide layer at least covering the inner wall of the virtual gate trench; When the voltage-resistant dielectric layer includes both an oxide layer and a protective layer, the method for preparing the voltage-resistant dielectric layer further includes preparing a protective layer on the front side of the substrate on which the oxide layer is formed, the protective layer covering the oxide layer.

[0015] A further technical solution is to prepare the first contact hole in the insulating dielectric layer before preparing the second contact hole; The depth of the first contact hole is greater than the depth of the second contact hole.

[0016] For N-type VDMOS devices, the first conductivity type refers to N-type and the second conductivity type refers to P-type; for P-type VDMOS devices, the first conductivity type and the second conductivity type refer to the opposite types as those for N-type devices.

[0017] The beneficial technical effects of this invention are: A dummy gate cell disposed in the planar gate cell is made in contact with the front first electrode metal Schottky to form the front first electrode, thereby forming a Schottky diode. During VDMOS operation, the Schottky diode formed based on the dummy gate cell shares part of the reverse current, thereby reducing the reverse current in the body diode and optimizing the reverse recovery characteristics of the device.

[0018] The virtual gate unit divides the planar gate unit into a first separated gate sub-unit and a second separated gate unit. The separated gate structure reduces the overlapping capacitance Cox, thereby reducing the Miller capacitance Cgd of the device, reducing switching losses and increasing switching speed, thus improving the stability and switching performance of the device. Attached Figure Description

[0019] Figure 1 This is a cross-sectional schematic diagram of an embodiment of the split-gate VDMOS with integrated Schottky diode provided by the present invention.

[0020] Figures 2-6 This is a cross-sectional view of the process steps in an embodiment of the fabrication method of the split-gate VDMOS of the integrated Schottky diode provided by the present invention, wherein... Figure 2 This is a cross-sectional view of an embodiment of the P-type lightly doped region prepared according to the present invention.

[0021] Figure 3 This is a cross-sectional view of one embodiment of the virtual grid trench prepared according to the present invention.

[0022] Figure 4 This is a cross-sectional view of one embodiment of the pressure-resistant dielectric layer prepared according to the present invention.

[0023] Figure 5 This is a cross-sectional view of one embodiment of the insulating dielectric layer prepared according to the present invention.

[0024] Figure 6 This is a cross-sectional view of one embodiment of the metal layer prepared according to the present invention.

[0025] Reference numerals: 1-Substrate, 2-P-type lightly doped region, 3-First separated gate polysilicon, 4-Second separated gate polysilicon, 5-Virtual gate trench, 6-Virtual gate polysilicon, 7-First separated gate oxide layer, 8-Second separated gate oxide layer, 9-P-type heavily doped region, 10-N-type heavily doped region, 11-Oxide layer, 12-Protective layer, 13-Insulating dielectric layer, 14-Barrier layer, 15-First electrode metal on the front side, 16-N-type lightly doped region, 17-Planar gate polysilicon, 18-Planar gate oxide layer, 19-First contact hole, 20-Second contact hole. Detailed Implementation

[0026] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0027] To optimize the reverse recovery characteristics of VDMOS devices, reduce switching losses, and improve switching performance, taking N-type as an example, one embodiment of the present invention includes an N-type substrate 1 and an active region fabricated in the central region of the substrate 1. The active region includes a plurality of planar cells arranged in parallel, wherein... For any planar cell, there are planar gate cells fabricated on substrate 1 and virtual gate cells adapted to the planar gate cells; On the cross-section of the active region, the virtual gate unit is disposed in the planar gate unit, and the planar gate unit is divided into at least a first separated gate sub-unit and a second separated gate unit along the first direction; The virtual gate unit is insulated from and isolated from the first separate gate unit and the second separate gate unit; The first separation gate unit and the second separation gate unit are in ohmic contact with the front second electrode metal above the substrate for forming the front second electrode; The virtual gate cell makes a Schottky contact with the front first electrode metal 15 above the substrate for forming the front first electrode to form a Schottky diode.

[0028] Specifically, the substrate 1 can be made of commonly used materials, such as silicon substrates or SiC substrates, to meet application requirements. Substrate 1 generally has a front side and a corresponding back side. For a VDMOS device, it generally includes an active region located in the center of substrate 1 and a termination protection region surrounding the active region. The specific functions and distribution of the active region and termination protection region can be consistent with existing technologies. Generally, the active region includes several cells arranged in parallel. In one embodiment of the present invention, the cells are planar cells, that is, the active region includes several planar cells. Within the active region, the planar cells generally adopt the same structural form.

[0029] To reduce switching losses in devices, in one embodiment of the present invention, for any planar cell, a virtual gate cell is prepared in the planar gate cell, the virtual gate cell dividing the planar gate cell into a first separated gate cell and a second separated gate cell along a first direction. Figure 1 As shown, the first direction is the direction from the active region to the field region. The planar gate structure between the first and second split-gate units is replaced by a virtual gate unit, reducing the length of the planar gate unit and lowering switching losses, thus resulting in better switching performance. When the device operates at high frequencies, the reduced switching losses lead to less heat generation, making the device less susceptible to damage from overheating and improving the stability of the VDMOS device. The specific principle behind the reduced switching losses of the split-gate VDMOS device can be found in the following explanation.

[0030] For VDMOS devices, metal layers are generally disposed on the front and back sides of the substrate 1. The metal layer on the front side of the substrate 1 includes a front first electrode metal 15 for forming a front first electrode and a front second electrode metal for forming a front second electrode. The metal layer on the back side of the substrate 1 includes a back electrode metal for forming a back electrode. In one embodiment of the present invention, the front first electrode is the source, the front second electrode is the gate, and the back electrode is the drain.

[0031] Specifically, the front second electrode metal is ohmically connected to the first and second separated gate units, and the front first electrode metal 15 is in Schottky contact with the virtual gate unit to form a Schottky diode, thus integrating the Schottky diode into the VDMOS device. In this case, the virtual gate polysilicon 6 serves as the cathode ground of the Schottky diode. During reverse recovery, the Schottky diode integrated in the VDMOS device and the body diode in the VDMOS device conduct simultaneously, sharing part of the reverse current. This reduces the current flowing through the body diode, correspondingly reducing the minority carrier holes injected into the body diode, and consequently reducing the charge during reverse recovery, thereby optimizing the reverse recovery characteristics of the VDMOS device. The specific form of the VDMOS device body diode is consistent with existing technology and will not be described further here.

[0032] Furthermore, the virtual gate unit includes a virtual gate trench 5 and virtual gate polysilicon 6 filled within the virtual gate trench, wherein, The bottom of the virtual gate trench 5 is located in the N-type lightly doped region 16 prepared on the front side of the substrate 1; The virtual gate polysilicon 6 is in Schottky contact with the front first electrode metal 15.

[0033] Specifically, the virtual gate trench 5 vertically penetrates the planar gate cell in the active region cross-section and extends into the N-type lightly doped region 16 on the front side of the substrate 1. This allows for adjustment of the reverse current magnitude by adjusting the carrier concentration in the epitaxial region, thereby optimizing the reverse recovery characteristics of the device. The definition of the epitaxial region is described below. The N-type lightly doped region 16 extends vertically from the front side of the substrate 1 to the back side of the substrate 1; this verticality means the virtual gate trench 5 is perpendicular to the front side of the substrate 1. The virtual gate polysilicon 6 makes Schottky contact with the front first electrode metal 15 to form a Schottky diode. The specific manner in which the virtual gate polysilicon 6 makes contact with the front first electrode metal 15 is described below. Preferably, the virtual gate trench is a U-shaped trench. The U-shaped trench enhances the voltage withstand capability of the Schottky diode formed based on the virtual gate cell. The specific principle behind this enhanced voltage withstand capability is described below. Since the virtual gate cell replaces part of the planar gate cell, the length of the planar gate structure that contributes to the formation of the overlapping capacitance Cox is reduced, thus decreasing the overlapping capacitance Cox. The overlapping capacitance Cox is a capacitor formed by overlapping planar gate polysilicon 17 and N-type doped region 16, with the planar gate oxide layer 18 as the dielectric layer. Since the Miller capacitance Cgd is mainly composed of the overlapping capacitance Cox, the Miller capacitance Cgd of the device decreases as the overlapping capacitance Cox decreases, thereby reducing the switching loss of the device, increasing the switching speed, and thus providing better switching performance.

[0034] like Figure 1 and Figure 6As shown, the virtual gate trench 5 divides the planar gate cell into a first separated gate cell and a second separated gate cell. Generally, the planar gate cell includes a planar gate oxide layer 18 fabricated on the front side of the substrate 1 and a planar gate polysilicon layer 17 fabricated on the planar gate oxide layer 18. The virtual gate trench 5 divides both the planar gate polysilicon layer 17 and the planar gate oxide layer 18 into two parts to obtain the first separated gate cell and the second separated gate cell. The first separated gate cell includes a first separated gate oxide layer 7 fabricated on the substrate 1 and a first separated gate polysilicon layer 3 disposed on the first separated gate oxide layer 7; the second separated gate cell includes a second separated gate oxide layer 8 fabricated on the substrate 1 and a second separated gate polysilicon layer 4 disposed on the second separated gate oxide layer 8. The first separated gate polysilicon layer 3 and the second separated gate polysilicon layer 4 are in ohmic contact with the front second electrode metal.

[0035] Furthermore, a voltage-resistant dielectric layer is also formed above the substrate 1, the voltage-resistant dielectric layer comprising an oxide layer 11 and / or a protective layer 12, wherein, The pressure-resistant dielectric layer at least covers the inner wall of the virtual grid trench 5; The virtual gate polysilicon 6 is insulated from the virtual gate trench 5 by a withstand dielectric layer.

[0036] Specifically, the withstand voltage dielectric layer at least covers the inner wall of the virtual gate trench 5, so that the virtual gate polysilicon 6 in the virtual gate unit is insulated from the first and second separate gate units on both sides of the virtual gate unit. When the virtual gate trench 5 is a U-shaped trench, due to the arc-shaped structure of the bottom of the U-shaped trench, the thickness of the withstand voltage dielectric layer filling the bottom of the virtual gate trench 5 is relatively large, making the electric field distribution at the bottom of the U-shaped trench more dispersed, thereby enhancing the withstand voltage capability of the Schottky diode formed by the virtual gate unit.

[0037] To improve the process compatibility of fabricating split-gate VDMOS integrated Schottky diodes, the withstand voltage dielectric layer also covers the first split-gate polysilicon 3, the second split-gate polysilicon 4, and the front side of the substrate 1. Preferably, the withstand voltage dielectric layer also includes an oxide layer 11 and a protective layer 12, with the protective layer covering the oxide layer 11. The oxide layer 11 can be made of SiO2, and the protective layer can be made of Si3N4. Since Si3N4 has a lower dielectric constant than SiO2, it has better withstand voltage and insulation capabilities, which can further improve the withstand voltage and insulation capabilities of the withstand voltage dielectric layer. In specific implementations, the number of layers of the withstand voltage dielectric layer and the materials of the oxide layer and the protective layer can be selected according to actual needs.

[0038] Furthermore, the split-gate VDMOS of the integrated Schottky diode also includes an insulating dielectric layer 13 covering the front side of the substrate 1, and a barrier layer 14 located above the insulating dielectric layer 13, wherein, The insulating dielectric layer 13 covers the first separation gate unit and the second separation gate unit, and the front first electrode metal 15 and the front second electrode metal are supported on the insulating dielectric layer 13. The barrier layer 14 is in contact with the insulating dielectric layer 13 and at least covers the virtual gate polysilicon 6. The virtual gate polysilicon 6 is in Schottky contact with the front first electrode metal 15 through the barrier layer 14.

[0039] Specifically, the insulating dielectric layer 13 can be made of SiO2 and can be used to support the metal layer above the insulating dielectric layer 13. The barrier layer 14 can be made of TiN or Ti and is used to provide a preset barrier height for the dummy gate polysilicon 6 to make Schottky contact with the front first electrode metal 15. The dummy gate polysilicon 6 makes Schottky contact with the front first electrode metal 15 through the barrier layer 14 to integrate the Schottky diode into the VDMOS device. In specific implementation, the material and thickness of the insulating dielectric layer 13 can be selected according to actual needs, specifically to meet the requirements of insulation isolation and metal layer support. The material of the barrier layer 14 can also be selected according to actual needs, specifically to meet the barrier height of the Schottky contact. In order to be compatible with existing VDMOS fabrication processes, in one embodiment of the present invention, the barrier layer 14 covers the insulating dielectric layer 13.

[0040] Furthermore, the planar cell also includes a lightly doped P-type region 2, a heavily doped N-type region 10, and a heavily doped P-type region 9, wherein, The P-type lightly doped region 2 is located below and in contact with the N-type heavily doped region 10; The N-type heavily doped region 10 is in contact with the P-type heavily doped region 9, and the N-type heavily doped region 10 and the P-type heavily doped region 9 penetrate the N-type lightly doped region 16. The junction depth of the heavily doped N-type region 10 is greater than the junction depth of the lightly doped N-type region 16; The N-type heavily doped region 10 is in 15-ohm contact with the front first electrode metal 15.

[0041] In one embodiment of the present invention, the P-type lightly doped region 2 extends vertically from the side of the N-type lightly doped region 16 near the back side of the substrate 1 toward the back side of the substrate 1. The N-type heavily doped region 10 and the P-type heavily doped region 9 extend vertically from the front side of the substrate 1 toward the back side of the substrate 1 and contact the P-type lightly doped region 2. Both the N-type heavily doped region 10 and the P-type heavily doped region 9 penetrate the N-type lightly doped region 16 that traverses the front side of the substrate 1, and the junction depth of the P-type heavily doped region 9 is greater than the junction depth of the N-type heavily doped region 10. The P-type heavily doped region 9 is used to improve the avalanche resistance of the VDMOS device. The junction depth of the N-type heavily doped region 10 is greater than the junction depth of the N-type lightly doped region 16. The positional relationship and function of the N-type heavily doped region 10 and the N-type lightly doped region 16 are consistent with the prior art and will not be repeated here.

[0042] The doping concentration of the heavily doped N-type region 10 is greater than that of the lightly doped N-type region 16, and the doping concentration of the heavily doped P-type region 9 is greater than that of the lightly doped P-type region 2. The heavily doped N-type region 10 is in 15-ohm contact with the front first electrode metal 16. Figure 1 and Figure 6 This is a cross-sectional view of a VDMOS device, so the contact between the N-type heavily doped region 10 and the first electrode metal 15 on the front side is not shown in the figure.

[0043] Furthermore, in any planar cell, the virtual gate unit is located between two lightly doped P-type regions 2, wherein, The P-type lightly doped region 2 located on one side of the virtual gate unit overlaps with the corresponding first separate gate unit, and the P-type doped region 2 located on the other side of the virtual gate unit overlaps with the corresponding second separate gate unit.

[0044] The N-type heavily doped region 10 corresponding to the first separated gate unit overlaps with the first separated gate unit, and the N-type heavily doped region 10 corresponding to the second separated gate unit overlaps with the second separated gate unit.

[0045] Specifically, in any planar cell, the width of the virtual gate unit is less than the distance between two P-type lightly doped regions 2. The first separation gate sub-unit corresponding to the P-type lightly doped region 2 on one side of the virtual gate unit is the first separation gate sub-unit located above the P-type lightly doped region 2 on one side of the virtual gate unit. The P-type lightly doped region 2 on one side of the virtual gate unit overlaps with the corresponding first separation gate unit. That is, the projection of the P-type lightly doped region 2 on one side of the virtual gate unit onto the corresponding first separation gate unit overlaps with the corresponding first separation gate unit.

[0046] The second separate gate cell corresponding to the P-type doped region 2 on the other side of the virtual gate cell is the second separate gate cell located above the P-type doped region 2 on the other side of the virtual gate cell. The overlap between the P-type doped region 2 on the other side of the virtual gate cell and the corresponding second separate gate cell is defined as the overlap between the lightly doped P-type region 2 on one side of the virtual gate cell and the corresponding first separate gate cell, as described above. Please refer to the above description for details.

[0047] In any planar cell, the aforementioned epitaxial region is the region formed by the N-type lightly doped region 16 located between the two P-type lightly doped regions 2 and the N-type substrate 1 located below it.

[0048] In any planar cell, two N-type heavily doped regions 10 are also provided on both sides of the virtual gate unit, corresponding to the N-type heavily doped region 10 of the first separated gate unit, that is, the N-type heavily doped region 10 located below the first separated gate unit. The N-type heavily doped region 10 corresponding to the first separated gate unit overlaps with the first separated gate unit, that is, the projection of the N-type heavily doped region 10 corresponding to the first separated gate unit onto the first separated gate unit overlaps with the first separated gate unit. Moreover, on the cell cross-section, the length of the overlap between the N-type heavily doped region 10 corresponding to the first separated gate unit and the first separated gate unit is less than the length of the overlap between the P-type lightly doped region 2 below the N-type heavily doped region 10 of the first separated gate unit and the first separated gate unit.

[0049] The N-type heavily doped region 10 corresponding to the second separated gate unit is the N-type heavily doped region 10 located below the second separated gate unit. The N-type heavily doped region 10 corresponding to the second separated gate unit overlaps with the first separated gate unit. The definition of this overlap corresponds to the situation described above where the N-type heavily doped region 10 corresponding to the first separated gate unit overlaps with the first separated gate unit; please refer to the above description for details. In the cell cross-section, the length of the overlap between the N-type heavily doped region 10 corresponding to the second separated gate unit and the second separated gate unit is less than the length of the overlap between the P-type lightly doped region 2 below the N-type heavily doped region 10 and the second separated gate unit.

[0050] Regarding the aforementioned split-gate VDMOS device with integrated Schottky diode, this invention provides a method for fabricating the split-gate VDMOS device with integrated Schottky diode, the method comprising: An N-type substrate 1 is provided, and a planar cellular structure is fabricated within the active region; The method for fabricating a planar cellular structure includes fabricating a planar gate cell above a substrate 1 corresponding to the active region, and fabricating a virtual gate cell in the planar gate cell, wherein the virtual gate cell divides the planar gate cell into a first separated gate sub-cell and a second separated gate cell along a first direction; When a metal layer is fabricated on the front side of substrate 1, the front second electrode metal used to form the front second electrode is made into ohmic contact with the first separation gate unit and the second separation gate unit. The front first electrode metal 15, used to form the front first electrode, is made into a Schottky contact with the virtual gate cell to form a Schottky diode.

[0051] Specifically, a planar gate cell is first prepared, and a virtual gate cell is prepared in the planar gate cell. When a metal layer is prepared on the front side of the substrate 1, the front first electrode metal 15 used to form the front first electrode is made into a Schottky contact with the virtual gate cell so as to integrate the Schottky diode into the discrete gate VDMOS device.

[0052] Furthermore, methods for preparing planar cellular structures include: An N-type lightly doped region 16 is prepared in substrate 1, traversing the front side of substrate 1; A planar gate cell is fabricated on the front side of the above-mentioned substrate 1. The planar gate cell includes a planar gate oxide layer 18 and a planar gate polysilicon 17 located on the planar gate oxide layer 18. A lightly doped P-type region 2 located below the lightly doped N-type region 16 is prepared in the above substrate 1; A virtual gate trench 5 is prepared in the above-mentioned planar gate polysilicon 17, and the bottom of the virtual gate trench 5 is located in the N-type lightly doped region 16; A voltage-resistant dielectric layer is prepared on the inner wall of the virtual gate trench 5 and filled with virtual gate polysilicon 6. The virtual gate polysilicon 6 is insulated and isolated from the inner wall of the virtual gate trench 5 through the voltage-resistant dielectric layer. An insulating dielectric layer 13 is formed on the front side of the substrate 1, covering the front side of the substrate 1, and a second contact hole 20 is formed in the insulating dielectric layer 13. A barrier layer 14 is formed on the insulating dielectric layer 13 on which the second contact hole 20 is formed, and the barrier layer 14 is at least covered by the second contact hole 20 above the virtual gate polysilicon 6. A front first electrode metal 15 for forming a front first electrode is prepared on the insulating dielectric layer 13 on which the barrier layer 14 is deposited. The front first electrode metal 15 is in Schottky contact with the virtual gate polysilicon 6 through the barrier layer 14 above the virtual gate polysilicon 6.

[0053] Specifically, Figures 2 to 6This paper illustrates one embodiment of the process steps for the split-gate VDMOS device with integrated Schottky diodes described above. The process steps of the above embodiment are explained below using a planar cell structure in a VDMOS device as an example: like Figure 2 As shown, an N-type silicon wafer is selected as substrate 1. An N-type lightly doped region 16 is prepared across the front side of substrate 1 through ion implantation and high-temperature push-junction processes. An oxidation process is performed on the front side of substrate 1 where the N-type lightly doped region 16 is prepared to grow an oxide layer of a predetermined thickness. Polysilicon is deposited on the front side of substrate 1, and a planar gate cell is prepared using photolithography. The planar gate cell includes a planar gate oxide layer 18 located on the front side of substrate 1 and a planar gate polysilicon layer 17 located on the planar gate oxide layer 18. A P-type lightly doped region 2 is prepared below the N-type lightly doped region 16 through ion implantation and high-temperature push-junction processes, and the P-type lightly doped region 2 is in contact with the N-type lightly doped region 16. In specific implementation, the process conditions of the ion implantation and high-temperature push-junction processes can be selected according to actual needs, specifically to meet the requirements for the preparation of the N-type lightly doped region 16 and the P-type lightly doped region 2. The process conditions of the oxidation process and the predetermined thickness of the oxide layer growth can be selected according to actual needs, specifically to meet the requirements for the preparation of the planar gate oxide layer 18.

[0054] like Figure 3 As shown, virtual gate trenches 5 are etched in the aforementioned planar gate cells to separate the planar gate cells into a first separated gate cell and a second separated gate cell. Preferably, the virtual gate trench 5 is a U-shaped trench, and the bottom of the U-shaped trench is located in the N-type lightly doped region 16. In specific implementation, the trench etching process can be selected according to actual needs, specifically to meet the etching requirements of the virtual gate trench 5.

[0055] like Figure 4 As shown, a voltage-resistant dielectric layer is deposited on the front side of the substrate 1. In order to reduce the number of fabrication steps and lower costs, in one embodiment of the present invention, the voltage-resistant dielectric layer covers the virtual gate trench 5, the front side of the substrate 1, the first separation gate unit, and the second separation gate unit.

[0056] Further, the pressure-resistant dielectric layer includes an oxide layer 11 and / or a protective layer 12, and the method for preparing the pressure-resistant dielectric layer includes: An oxide layer 11 is prepared on the front side of the substrate 1 where the virtual gate trench 5 is formed, the oxide layer 11 at least covering the inner wall of the virtual gate trench 5; When the voltage-resistant dielectric layer includes both an oxide layer 11 and a protective layer 12, the method for preparing the voltage-resistant dielectric layer further includes preparing a protective layer 12 on the front side of the substrate 1 on which the oxide layer 11 is formed, and the protective layer 12 covers the oxide layer 11.

[0057] like Figure 4As shown, in one embodiment of the present invention, the withstand voltage dielectric layer includes both an oxide layer 11 and a protective layer 12. When preparing the withstand voltage dielectric layer, an oxide layer 11 of a predetermined thickness is first deposited on the front side of the substrate 1 where the virtual gate trench 5 is formed. Then, a protective layer 12 of a predetermined thickness is deposited on the front side of the substrate 1 where the oxide layer 11 is formed, and the protective layer 12 covers the oxide layer 11. The materials and functions of the oxide layer 11 and the protective layer 12 can be referred to the above description and will not be repeated here. In specific implementations, the materials and thicknesses of the oxide layer 11 and the protective layer 12 can be selected according to actual needs.

[0058] like Figure 5 As shown, polysilicon is deposited within the virtual gate trench 5, and virtual gate polysilicon 6 is prepared by polysilicon etching. N-type impurities are implanted into the substrate 1, and an N-type heavily doped region 10 is prepared by a high-temperature push-junction process. An insulating dielectric layer 13 is deposited on the front side of the substrate 1. A first contact hole 19 is etched within the insulating dielectric layer 13, extending through the insulating dielectric layer 13 to the front side of the substrate 1 in the cell cross-section. A P-type heavily doped region 9 is prepared within the substrate 1 through the first contact hole 19 by ion implantation and a high-temperature push-junction process. The structural relationship between the P-type heavily doped region 9 and the N-type heavily doped region 10 is consistent with the above description and will not be repeated here. In specific implementation, the process conditions of the ion implantation and high-temperature push-junction processes can be selected according to actual needs, specifically to meet the requirements for the preparation of the P-type heavily doped region 9 and the N-type heavily doped region 10.

[0059] like Figure 6 As shown, etching is performed again within the insulating dielectric layer 13 to prepare the second contact hole 20. The second contact hole 20 penetrates the insulating dielectric layer 13 above the virtual gate polysilicon 6, exposing the virtual gate polysilicon 6. The depth of the second contact hole 20 is less than the depth of the first contact hole 19. A barrier layer 14 of a predetermined thickness is deposited on the insulating dielectric layer 13. The material of the barrier layer 14 can be Ti or TiN. To improve process compatibility, in one embodiment of the present invention, the barrier layer 14 covers the virtual gate polysilicon 6, the inner wall of the first contact hole 19, the inner wall of the second contact hole 20, and the insulating dielectric layer 13. The etching process of the second contact hole 20 can be selected according to actual needs, specifically to meet the etching requirements of the second contact hole 20.

[0060] Metal is deposited over the insulating dielectric layer 13 to form a metal layer, which includes a front first electrode metal 15 and a front second electrode metal. The front first electrode metal 15 is also disposed within a first contact hole 19 and a second contact hole 20, and is in ohmic contact with the N-type heavily doped region 10. The front first electrode metal is in ohmic contact with the virtual gate polysilicon 6 Schottky through a barrier layer 14 to form a Schottky diode. The front second electrode metal is in ohmic contact with the first split gate cell and the second split gate cell.

[0061] The above descriptions are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations that can be directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.

Claims

1. A split-gate VDMOS with integrated Schottky diode, characterized in that, It includes a substrate of a first conductivity type and an active region fabricated in the central region of the substrate. The active region includes several planar cells arranged in parallel, wherein... For any planar cell, there are planar gate cells fabricated on a substrate and virtual gate cells adapted to the planar gate cells; On the cross-section of the active region, the virtual gate unit is disposed in the planar gate unit, and the planar gate unit is divided into at least a first separated gate sub-unit and a second separated gate unit along the first direction; The virtual gate unit is insulated from and isolated from the first separate gate unit and the second separate gate unit; The first separation gate unit and the second separation gate unit are in ohmic contact with the front second electrode metal above the substrate for forming the front second electrode; The virtual gate unit makes a Schottky contact with the front first electrode metal Schottky contact above the substrate for forming the front first electrode, thereby forming a Schottky diode; The virtual gate unit includes a virtual gate trench and virtual gate polysilicon filling the virtual gate trench, wherein... The bottom of the virtual gate trench is located in a lightly doped region of the first conductivity type fabricated on the front side of the substrate; The virtual gate polysilicon is in contact with the front first electrode metal Schottky; A voltage-resistant dielectric layer is also fabricated above the substrate, the voltage-resistant dielectric layer comprising an oxide layer and / or a protective layer, wherein, The pressure-resistant dielectric layer at least covers the inner wall of the virtual grid trench; The virtual gate polysilicon is insulated from the virtual gate trench by a voltage-resistant dielectric layer.

2. The split-gate VDMOS with integrated Schottky diode according to claim 1, characterized in that, It also includes an insulating dielectric layer covering the front side of the substrate, and a barrier layer located above the insulating dielectric layer, wherein, The insulating dielectric layer covers the first separation gate unit and the second separation gate unit, and the front first electrode metal and the front second electrode metal are supported on the insulating dielectric layer; The barrier layer is in contact with the insulating dielectric layer and at least covers the virtual gate polysilicon. The virtual gate polysilicon is in contact with the front first electrode metal Schottky through a barrier layer.

3. The split-gate VDMOS with integrated Schottky diode according to claim 1, characterized in that, The planar cell further includes a lightly doped region of the second conductivity type, a heavily doped region of the first conductivity type, and a heavily doped region of the second conductivity type, wherein... The second conductivity type lightly doped region is located below and in contact with the first conductivity type heavily doped region; The first heavily doped region of conductivity type is in contact with the second heavily doped region of conductivity type, and the first heavily doped region of conductivity type and the second heavily doped region of conductivity type penetrate the first lightly doped region of conductivity type; The junction depth of the heavily doped region of the first conductivity type is greater than the junction depth of the lightly doped region of the first conductivity type. The first conductivity type heavily doped region is in ohmic contact with the front first electrode metal.

4. The split-gate VDMOS with integrated Schottky diode according to claim 3, characterized in that, In any planar cell, the virtual gate unit is located between two lightly doped regions of the second conductivity type, wherein, The lightly doped region of the second conductivity type located on one side of the virtual gate unit overlaps with the corresponding first separate gate unit, and the lightly doped region of the second conductivity type located on the other side of the virtual gate unit overlaps with the corresponding second separate gate unit; The first conductivity type heavily doped region corresponding to the first separated gate unit overlaps with the first separated gate unit, and the first conductivity type heavily doped region corresponding to the second separated gate unit overlaps with the second separated gate unit; The doping concentration of the heavily doped region of the first conductivity type is greater than the doping concentration of the lightly doped region of the first conductivity type, and the doping concentration of the heavily doped region of the second conductivity type is greater than the doping concentration of the lightly doped region of the second conductivity type.

5. A method for fabricating a split-gate VDMOS with integrated Schottky diode, characterized in that, The method for fabricating the split-gate VDMOS of the integrated Schottky diode according to claim 1 includes: A substrate of the first conductivity type is provided, and a planar cellular structure is fabricated within the active region; A method for fabricating a planar cellular structure includes fabricating a planar gate cell above a substrate corresponding to an active region, and fabricating a virtual gate cell within the planar gate cell, wherein the virtual gate cell divides the planar gate cell into a first separated gate sub-cell and a second separated gate cell along a first direction; When a metal layer is fabricated on the front side of the substrate, the front second electrode metal used to form the front second electrode is ohmically contacted with the first separation gate unit and the second separation gate unit. The front first electrode metal used to form the front first electrode is made into a Schottky contact with the virtual gate cell to form a Schottky diode.

6. The method for fabricating a split-gate VDMOS with an integrated Schottky diode according to claim 5, characterized in that, Methods for preparing planar cellular structures include: A lightly doped region of the first conductivity type is prepared within the substrate, traversing the front side of the substrate. A planar gate cell is fabricated on the front side of the above-mentioned substrate. The planar gate cell includes a planar gate oxide layer and a planar gate polysilicon located on the planar gate oxide layer. A second conductivity type lightly doped region located below the first conductivity type lightly doped region is prepared in the above substrate; A virtual gate trench is fabricated in the above-mentioned planar gate polysilicon, wherein the bottom of the virtual gate trench is located in a lightly doped region of the first conductivity type; A voltage-resistant dielectric layer is prepared on the inner wall of the virtual gate trench and then filled with virtual gate polysilicon. The virtual gate polysilicon is insulated from the inner wall of the virtual gate trench by the voltage-resistant dielectric layer. An insulating dielectric layer covering the front side of the substrate is formed, and a second contact hole is formed within the insulating dielectric layer; A barrier layer is formed on the insulating dielectric layer that forms the second contact hole, the barrier layer being at least covered by the second contact hole over the virtual gate polysilicon. A front first electrode metal for forming a front first electrode is prepared on the insulating dielectric layer on which the barrier layer is deposited. The front first electrode metal is in Schottky contact with the virtual gate polysilicon through the barrier layer above the virtual gate polysilicon.

7. The method for fabricating a split-gate VDMOS with an integrated Schottky diode according to claim 6, characterized in that, The pressure-resistant dielectric layer includes an oxide layer and / or a protective layer, and the method for preparing the pressure-resistant dielectric layer includes: An oxide layer is prepared on the front side of the substrate where the virtual gate trench is formed, the oxide layer at least covering the inner wall of the virtual gate trench; When the voltage-resistant dielectric layer includes both an oxide layer and a protective layer, the method for preparing the voltage-resistant dielectric layer further includes preparing a protective layer on the front side of the substrate on which the oxide layer is formed, the protective layer covering the oxide layer.

8. The method for fabricating a split-gate VDMOS with an integrated Schottky diode according to claim 6, characterized in that, Before preparing the second contact hole, the first contact hole is prepared in the insulating dielectric layer; The depth of the first contact hole is greater than the depth of the second contact hole.

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