A low-power pre-buck circuit applied to a wide input range DC-DC chip

Abstract

The application belongs to the technical field of integrated circuits, and particularly relates to a low-power pre-buck circuit applied to a wide-input-range DC-DC chip, which comprises a high-voltage switch tube NMOS1, a high-voltage switch tube NMOS2, a high-voltage power tube NMOS3, a high-voltage current bias tube PMOS1, a high-voltage current bias tube PMOS2, a bipolar transistor NPN1, a bipolar transistor NPN2, a Zener diode Z1, a capacitor C1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, and a resistor R6. Compared with the prior art, the Zener diode and the bipolar transistor arranged in the circuit can clamp and lock the output voltage, and the pre-buck function can be realized at extremely low power consumption.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically, to a low-power pre-buck circuit for use in wide-input-range DC-DC chips. Background Technology

[0002] The input voltage of a wide-range DC-DC converter typically ranges from a few volts to several hundred volts. This wide-range input voltage cannot be directly used as the power supply for the various modules inside the DC-DC chip. It needs to be pre-stepped down by a pre-voltage circuit to obtain a relatively stable voltage (hereinafter referred to as VDD) with a significantly reduced correlation to the input voltage.

[0003] However, VDD is generally used simultaneously as the power bias for the gate drive module of the off-chip power switch, and is typically set to 7V or higher to increase the gate-source overdrive voltage of the off-chip power switch and reduce its on-resistance. Due to factors such as process technology and temperature, VDD will still fluctuate slightly when the input voltage changes. However, VDD usually needs to be stepped down to below 5V to serve as the power supply for the various modules inside the DC-DC chip. Therefore, the small fluctuations in VDD have little impact on the on-chip modules of the DC-DC chip.

[0004] In existing technologies, the pre-buck modules introduced into DC-DC chips typically consume tens of microamps, resulting in relatively high power consumption. Therefore, this invention provides a pre-buck circuit that achieves a significant reduction in power consumption through a simple structure. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the present invention aims to provide a low-power pre-buck circuit for wide-input-range DC-DC chips that solves the aforementioned technical problems.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A low-power pre-buck circuit for wide input range DC-DC chips includes high-voltage switching transistor NMOS1, high-voltage switching transistor NMOS2, high-voltage power transistor NMOS3, high-voltage current bias transistor PMOS1, high-voltage current bias transistor PMOS2, bipolar transistor NPN1, bipolar transistor NPN2, Zener diode Z1, capacitor C1, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, and resistor R6. One end of resistor R1 is grounded, and the other end of resistor R1 is connected to the source of high-voltage switching transistor NMOS1. The gate of the high-voltage switch NMOS1 is connected to the pre-buck enable signal EN, and the drain of the high-voltage switch NMOS1 is connected to the drain of PMOS1. The drain and gate of the high-voltage current bias transistor PMOS1 are connected together, and the drain of the high-voltage current bias transistor PMOS1 is connected to the drain of the high-voltage switching transistor NMOS1 and the gate of the high-voltage current bias transistor PMOS2. The source of the high-voltage current bias transistor PMOS1 is connected to the input terminal VIN. The source of the high-voltage current bias transistor PMOS2 is connected to VIN. The drain of the high-voltage current bias transistor PMOS2, the collector of the bipolar transistor NPN1, the collector of the bipolar transistor NPN2, the gate of the high-voltage power transistor NMOS3, and the drain of the high-voltage switching transistor NMOS2 are connected together. The emitter of the bipolar transistor NPN1 is connected to the cathode of the Zener diode Z1, and the anode of the Zener diode Z1 is grounded. The base of the bipolar transistor NPN1 is connected to one end of capacitor C1 and one end of resistor R6. The gate of the high-voltage switch NMOS2 is connected to the inverted pre-buck enable signal -EN, and the source of the high-voltage switch NMOS2 is grounded. The base of the bipolar transistor NPN2 is connected to the source of the high-voltage power transistor NMOS3 and one end of the resistor R5, and the emitter of the bipolar transistor NPN2 is connected to one end of the resistor R2. The other end of resistor R2, the other end of resistor R5, the other end of capacitor C1, one end of resistor R3, and the output terminal VDD are connected together. The other end of resistor R6 is connected to one end of resistor R3 and one end of resistor R4, and the other end of resistor R4 is connected to GND.

[0007] Furthermore, when the pre-dropout enable signal EN is high, the channel of the high-voltage switch NMOS1 is turned on, and the input terminal VIN will generate a voltage divider between the drain and source of the high-voltage current bias transistor PMOS1, between the drain and source of the high-voltage switch NMOS1, and across resistor R1, and generate current in this branch.

[0008] Furthermore, by setting the width-to-length ratio of the high-voltage current bias transistor PMOS2 to twice that of the transistor, the high-voltage current bias transistor PMOS2 is mirrored to obtain the corresponding drain and source currents, and provides bias current for the bipolar transistor NPN1.

[0009] Furthermore, the voltage at the emitter of the bipolar transistor NPN1 is regulated by the Zener diode Z1, and the base voltage of the bipolar transistor NPN1 is divided by resistors R3 and R4.

[0010] Furthermore, the bipolar transistor NPN2, resistor R5, and resistor R2 provide overcurrent protection, and when the output current VDD increases, an increased voltage difference will be generated across resistor R5.

[0011] Furthermore, the branch current can be adjusted by setting a resistor R1 with a corresponding resistance value.

[0012] Furthermore, by setting the corresponding resistance values ​​of resistors R3 and R4, the magnitude of the branch current at the high-voltage power transistor NMOS3 can be adjusted.

[0013] By adopting the above technical solution, the beneficial effects of the present invention are as follows: By incorporating Zener diodes and bipolar transistors in the circuit, the output voltage can be clamped and locked, enabling pre-buck operation with extremely low power consumption. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0017] like Figure 1 As shown, the low-power pre-step-down circuit includes high-voltage switching transistor NMOS1, high-voltage switching transistor NMOS2, high-voltage power transistor NMOS3, high-voltage current bias transistor PMOS1, high-voltage current bias transistor PMOS2, bipolar transistor NPN1, bipolar transistor NPN2, Zener diode Z1, capacitor C1, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, and resistor R6.

[0018] The specific connection relationships of the components in this pre-step-down circuit are as follows: One end of resistor R1 is grounded to the ground potential GND, and the other end is connected to the source of the high-voltage switching transistor NMOS1; The source of the high-voltage switching transistor NMOS1 is connected to one end of the resistor R1, the gate is connected to the pre-buck enable signal EN, and the drain is connected to the drain of the high-voltage current bias transistor PMOS1. The drain and gate of the high-voltage current bias transistor PMOS1 are connected together and connected to the drain of the high-voltage switching transistor NMOS1, and also connected to the gate of the high-voltage current bias transistor PMOS2; the source of the high-voltage current bias transistor PMOS1 is connected to the input terminal VIN. The gate of the high-voltage current bias transistor PMOS2 is connected to the gate of the high-voltage current bias transistor PMOS1, the source is connected to the input terminal VIN, the drain is connected to the collector of the bipolar transistor NPN1, the collector of the bipolar transistor NPN2, the gate of the high-voltage power transistor NMOS3, and the drain of the high-voltage switching transistor NMOS2. The collector of bipolar transistor NPN1 is connected to the collector of bipolar transistor NPN2, and simultaneously connected to the drain of high-voltage current bias transistor PMOS2, the gate of high-voltage power transistor NMOS3, and the drain of high-voltage switching transistor NMOS2; the base of bipolar transistor NPN1 is connected to one end of capacitor C1 and one end of resistor R6; the emitter of bipolar transistor NPN1 is connected to the cathode of Zener diode Z1. The anode of Zener diode Z1 is connected to GND, and the cathode is connected to the emitter of bipolar transistor NPN1; The gate of the high-voltage switching transistor NMOS2 is connected to the inverted pre-buck enable signal -EN, and the source is connected to GND. The drain of the high-voltage switching transistor NMOS2 is connected to the collector of the bipolar transistor NPN1, the collector of the bipolar transistor NPN2, the drain of the high-voltage current bias transistor PMOS2, and the gate of the high-voltage power transistor NMOS3. The collector of bipolar transistor NPN2 is connected to the collector of bipolar transistor NPN1, and simultaneously connected to the drain of high-voltage current bias transistor PMOS2, the gate of high-voltage power transistor NMOS3, and the drain of high-voltage current bias transistor NMOS2; the base of bipolar transistor NPN2 is connected to the source of high-voltage power transistor NMOS3, and simultaneously connected to one end of resistor R5; the emitter of bipolar transistor NPN2 is connected to one end of resistor R2. One end of resistor R2 is connected to the emitter of bipolar transistor NPN2; the other end of resistor R2 is connected to one end of resistor R5, one end of capacitor C1, one end of resistor R3, and the output terminal VDD of the pre-buck circuit. One end of resistor R6 is connected to one end of capacitor C1 and also to the base of bipolar transistor NPN1; the other end of resistor R6 is connected to one end of resistor R3 and also to one end of resistor R4. One end of resistor R4 is connected to resistor R3 and also to one end of R6; the other end of resistor R4 is connected to GND. One end of capacitor C1 is connected to the base of bipolar transistor NPN1 and one end of resistor R6; the other end of capacitor C1 is connected to one end of resistor R2, one end of resistor R3, one end of resistor R5, and is also connected to the output terminal VDD. One end of resistor R5 is connected to the base of bipolar transistor NPN1 and the source of high-voltage power transistor NMOS3; the other end of resistor R5 is connected to one end of resistor R2, one end of resistor R3, one end of capacitor C1, and the output terminal VDD. One end of resistor R3 is connected to one end of resistor R2, one end of resistor R4, one end of resistor R5, one end of resistor R6, one end of capacitor C1, and the output terminal VDD.

[0019] The circuit works as follows: When the pre-buck enable signal EN is high, the channel of the high-voltage switch NMOS1 is turned on. The input terminal VIN will generate a voltage divider between the drain and source of the high-voltage current bias transistor PMOS1, between the drain and source of the high-voltage switch NMOS1, and across resistor R1, and generate current in this branch. Here, R1 can be set as large as possible so that the current in this branch is about 1uA.

[0020] By setting the width-to-length ratio of the high-voltage current bias transistor PMOS2 to twice that of the transistor, the high-voltage current bias transistor PMOS2 is mirrored to obtain a drain and source current of 2uA, which provides bias current for the bipolar transistor NPN1.

[0021] The emitter of the bipolar transistor NPN1 is regulated to about 6V by the Zener diode Z1. At this time, the base voltage of the bipolar transistor NPN1 is clamped to about 7V by the voltage division of resistors R3 and R4. At this time, resistors R3 and R4 can be set as large as possible to minimize the current in the branch of the high-voltage power transistor NMOS3.

[0022] Capacitor C1 performs frequency compensation on the loop, ensuring a phase margin of over 40 degrees.

[0023] The bipolar transistor NPN2, resistors R5 and R2 provide overcurrent protection. When the output current VDD increases, an increased voltage difference is generated across resistor R5. When this voltage difference exceeds the base-emitter turn-on voltage of the bipolar transistor NPN2, NPN2 turns on, locking the voltage across resistor R5. This prevents the output current of the high-voltage power transistor NMOS3 from increasing, thus achieving overcurrent protection.

[0024] In summary, the current consumption of this circuit can be kept below 5uA.

[0025] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any ordinary changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-power pre-step-down circuit for wide-input-range DC-DC chips, characterized in that, Including high-voltage switching transistor NMOS1, high-voltage switching transistor NMOS2, high-voltage power transistor NMOS3, high-voltage current bias transistor PMOS1, high-voltage current bias transistor PMOS2, bipolar transistor NPN1, bipolar transistor NPN2, Zener diode Z1, capacitor C1, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, and resistor R6; One end of the resistor R1 is grounded, and the other end of the resistor R1 is connected to the source of the high-voltage switching transistor NMOS1. The gate of the high-voltage switch NMOS1 is connected to the pre-buck enable signal EN, and the drain of the high-voltage switch NMOS1 is connected to the drain of PMOS1. The drain and gate of the high-voltage current bias transistor PMOS1 are connected together, and the drain of the high-voltage current bias transistor PMOS1 is connected to the drain of the high-voltage switching transistor NMOS1 and the gate of the high-voltage current bias transistor PMOS2. The source of the high-voltage current bias transistor PMOS1 is connected to the input terminal VIN. The source of the high-voltage current bias transistor PMOS2 is connected to VIN, and the drain of the high-voltage current bias transistor PMOS2, the collector of the bipolar transistor NPN1, the collector of the bipolar transistor NPN2, the gate of the high-voltage power transistor NMOS3, and the drain of the high-voltage switching transistor NMOS2 are connected. The emitter of the bipolar transistor NPN1 is connected to the cathode of the Zener diode Z1, and the anode of the Zener diode Z1 is grounded. The base of the bipolar transistor NPN1 is connected to one end of capacitor C1 and one end of resistor R6. The gate of the high-voltage switch NMOS2 is connected to the inverted pre-buck enable signal -EN, and the source of the high-voltage switch NMOS2 is grounded. The base of the bipolar transistor NPN2 is connected to the source of the high-voltage power transistor NMOS3 and one end of the resistor R5, and the emitter of the bipolar transistor NPN2 is connected to one end of the resistor R2. The other end of resistor R2, the other end of resistor R5, the other end of capacitor C1, one end of resistor R3, and the output terminal VDD are connected together. The other end of resistor R6 is connected to one end of resistor R3 and one end of resistor R4, and the other end of resistor R4 is connected to GND.

2. The low-power pre-step-down circuit for a wide input range DC-DC chip according to claim 1, characterized in that, When the pre-dropout enable signal EN is high, the channel of the high-voltage switch NMOS1 is turned on. The input terminal VIN will generate a voltage divider between the drain and source of the high-voltage current bias transistor PMOS1, between the drain and source of the high-voltage switch NMOS1, and across resistor R1, and generate current in this branch.

3. The low-power pre-step-down circuit for a wide input range DC-DC chip according to claim 1, characterized in that, By setting the width-to-length ratio of the high-voltage current bias transistor PMOS2, the high-voltage current bias transistor PMOS2 is mirrored to obtain the corresponding drain and source currents, and provides bias current for the bipolar transistor NPN1.

4. The low-power pre-step-down circuit for a wide input range DC-DC chip according to claim 1, characterized in that, The voltage at the emitter of the bipolar transistor NPN1 is regulated by the Zener diode Z1, and the base voltage of the bipolar transistor NPN1 is divided by resistors R3 and R4.

5. A low-power pre-step-down circuit for a wide input range DC-DC chip according to claim 1, characterized in that, The bipolar transistor NPN2, resistor R5, and resistor R2 provide overcurrent protection. When the output current VDD increases, an increased voltage difference will be generated across resistor R5.

6. A low-power pre-step-down circuit for a wide input range DC-DC chip according to claim 2, characterized in that, The branch current can be adjusted by setting a resistor R1 with the appropriate resistance value.

7. A low-power pre-step-down circuit for a wide input range DC-DC chip according to claim 4, characterized in that, The magnitude of the branch current at the high-voltage power transistor NMOS3 can be adjusted by setting the corresponding resistance values ​​of resistors R3 and R4.

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