Scanning circuit and display device

Abstract

A scan circuit having a plurality of stages is provided. Each scan unit of each stage of the plurality of stages of the scan circuit includes an input sub-circuit (ISC), an output sub-circuit (OSC), a first processing sub-circuit (PSC1), a second processing sub-circuit (PSC2), and a third processing sub-circuit (PSC3). The second processing sub-circuit (PSC2) includes a first capacitor (C1); the third processing sub-circuit (PSC3) includes a third capacitor (C3); the first processing sub-circuit (PSC1) includes an eighth transistor (T8); and the output sub-circuit (OSC) includes a ninth transistor (T9) and a tenth transistor (T10). In a first direction (DR1), the eighth transistor (T8) is located on a side of the ninth transistor (T9) and the tenth transistor (T10) away from the first capacitor (C1), the third capacitor (C3), and other transistors of the each scan unit.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a scanning circuit and a display device. Background Technology

[0002] The image display device includes a driver for controlling the display of an image in each of a plurality of pixels. The driver is a transistor-based circuit that includes gate drive circuitry and data drive circuitry. The gate drive circuitry is formed by cascading multiple shift register units. Each shift register unit outputs a gate drive signal to one of a plurality of gate lines. The gate drive signal from the gate drive circuitry is scanned row by row through the gate lines to control the transistors in each row to be in an on / off state. The gate drive circuitry can be integrated into a gate-on-array (GOA) circuitry, which can be directly formed in the array substrate of the display panel. Summary of the Invention

[0003] On one hand, this disclosure provides a scanning circuit including multiple stages; wherein each scanning unit of each stage of the multiple stages of the scanning circuit includes an input sub-circuit, an output sub-circuit, a first processing sub-circuit, a second processing sub-circuit, and a third processing sub-circuit; wherein the second processing sub-circuit includes a first capacitor; the third processing sub-circuit includes a third capacitor; the first processing sub-circuit includes an eighth transistor; and the output sub-circuit includes a ninth transistor and a tenth transistor; wherein, along a first direction, the eighth transistor is located on the side of the ninth transistor and the tenth transistor that is away from the first capacitor, the third capacitor, and the other transistors of each scanning unit.

[0004] Optionally, each scanning unit includes a first connecting line located in a first signal line layer and a second connecting line located in a first conductive layer; the first overall structure includes the first connecting line, and the first overall structure is electrically connected to the first electrode of the sixth transistor in the second processing sub-circuit, the gate of the seventh transistor in the second processing sub-circuit, the gate of the fourth transistor in the third processing sub-circuit, and the second capacitor electrode of the third capacitor; the second overall structure includes the second connecting line and the first capacitor electrode of the first capacitor, the second connecting line electrically connecting the first capacitor electrode of the first capacitor to the second electrode of the third transistor in the third processing sub-circuit; and the first connecting line intersects with the second connecting line.

[0005] Optionally, each scanning unit further includes a third connection line located in the first signal line layer, the third connection line being electrically connected to the second connection line, the second electrode of the third transistor, and the second electrode of the second transistor in the third processing sub-circuit.

[0006] Optionally, each scanning unit further includes a fourth connecting line located in the first conductive layer, the third overall structure includes the fourth connecting line and the first capacitor electrode of the third capacitor, the fourth connecting line is electrically connected to the first capacitor electrode of the third capacitor, the second electrode of the first transistor in the input sub-circuit and the second electrode of the fourth transistor; and the third connecting line intersects with the fourth connecting line.

[0007] Optionally, each scanning unit further includes a branch extending away from the fourth connection line; the third overall structure includes the branch line, the fourth connection line, and the first capacitor electrode of the third capacitor; and the dual-gate structure of the second transistor in the third processing sub-circuit includes a portion of the fourth connection line and a portion of the branch line.

[0008] Optionally, each scanning unit further includes a fifth connection line located in the first signal line layer, the fifth connection line being electrically connected to the second electrode of the first transistor, the second electrode of the fourth transistor, and the fourth connection line; the fourth connection line extending along the first direction; and the fifth connection line extending along a second direction different from the first direction.

[0009] Optionally, the scanning circuit further includes: a second clock signal line located in the first signal line layer; and a sixth connection line located in the first conductive layer; wherein the sixth connection line is electrically connected to the first connection line and the second clock signal line; and the sixth connection line includes the gate of the fourth transistor.

[0010] Optionally, the scanning circuit further includes: a first clock signal line located in the first signal line layer; and a seventh connection line located in the first conductive layer; wherein the seventh connection line is electrically connected to the first electrode of the second transistor in the third processing sub-circuit and the first clock signal line; and the seventh connection line includes the gate of the first transistor in the input sub-circuit and the gate of the third transistor.

[0011] Optionally, each scanning unit further includes an eighth connection line located in the first signal line layer, the eighth connection line being electrically connected to the first electrode of the second transistor along with the seventh connection line; the seventh connection line extending along the first direction; and the eighth connection line extending along a second direction different from the first direction.

[0012] Optionally, each scanning unit further includes a ninth connection line located in the first signal line layer, the ninth connection line being electrically connected to the second capacitor electrode of the first capacitor and the second electrode of the sixth transistor and the first electrode of the seventh transistor; and the orthographic projection of the ninth connection line on the substrate partially overlapping the orthographic projection of the second capacitor electrode of the first capacitor on the substrate.

[0013] Optionally, the orthographic projection of the first connecting line on the substrate overlaps with the orthographic projection of the second capacitor electrode of the third capacitor on the substrate.

[0014] Optionally, the second overall structure includes the second connecting line, the first capacitor electrode of the first capacitor, the gate of the fifth transistor in the third processing sub-circuit, and the gate of the sixth transistor.

[0015] Optionally, each scanning unit includes a second capacitor in the first processing sub-circuit; wherein the ninth transistor and the tenth transistor are arranged along a second direction; the first capacitor, the third capacitor, and the second capacitor are arranged sequentially along the first direction; and along the first direction, the second capacitor is located on the side of the ninth transistor and the tenth transistor away from the first capacitor and the third capacitor.

[0016] Optionally, the scanning circuit further includes a first voltage signal line and a second voltage signal line located in the first signal line layer; wherein, along the first direction, the first voltage signal line and the second voltage signal line are located on opposite sides of the transistor and capacitor of each scanning unit; the first voltage signal line is electrically coupled to the first electrode of the fifth transistor in the third processing sub-circuit, the first electrode of the eighth transistor in the first processing sub-circuit, and the first electrode of the ninth transistor in the output sub-circuit; and the second voltage signal line is electrically coupled to the first electrode of the tenth transistor in the output sub-circuit.

[0017] Optionally, the channel length of the active layer of the ninth transistor is less than or equal to 3.8 μm; the channel length of the active layer of the tenth transistor is less than or equal to 3.8 μm; the channel width of the active layer of the ninth transistor is greater than 180 μm; and the channel width of the active layer of the tenth transistor is greater than 180 μm.

[0018] Optionally, the fourth overall structure includes the active layer of the fourth transistor in the third processing sub-circuit and the active layer of the fifth transistor in the third processing sub-circuit; and the ratio of the channel width of the active layer of the fourth transistor to the channel width of the active layer of the fifth transistor is in the range of 1.5:1 to 2.5:1.

[0019] Optionally, each scanning unit further includes a fifth connection line located in the first signal line layer, the fifth connection line being electrically connected to the second electrode of the first transistor, the second electrode of the fourth transistor, and the fourth connection line; the active layer of the first transistor, the fifth connection line, the active layer of the fourth transistor in the third processing sub-circuit, and the active layer of the fifth transistor in the third processing sub-circuit are collinear and arranged sequentially along the second direction.

[0020] Optionally, the active layer of the first transistor and the active layer of the third transistor are parallel and extend along a second direction.

[0021] On the other hand, this disclosure provides a display device including a scanning circuit described in or manufactured by the methods described in this disclosure, and a display panel.

[0022] Optionally, the display device further includes a second scanning circuit; wherein the scanning circuit is configured to provide a first type of control signal; the second scanning circuit is configured to provide a second type of control signal; the scanning circuit and the second scanning circuit are arranged along the first direction; along the first direction, the display device further includes a first voltage signal line and a second voltage signal line configured to provide a first voltage signal and a second voltage signal to the scanning circuit respectively, and a third voltage signal line and a fourth voltage signal line configured to provide the first voltage signal and the second voltage signal to the second scanning circuit respectively; wherein each scanning unit further includes a tenth connecting line, the tenth connecting line connecting the second capacitor electrode of the second capacitor in each scanning unit to the third voltage signal line; the tenth connecting line intersects with a plurality of signal lines extending along the second direction and configured to provide signals to the second scanning circuit; and the fifth overall structure includes the tenth connecting line and the second capacitor electrode of the second capacitor in each scanning unit. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 These are circuit diagrams of various scanning units according to some embodiments of this disclosure.

[0025] Figure 2 It is shown Figure 1 The timing diagram shows the operation of the scanning unit at the indicated level.

[0026] Figure 3A The structure of each scanning unit in a scanning circuit according to some embodiments of the present disclosure is shown.

[0027] Figure 3B It shows Figure 3A The structure of the semiconductor material layer in each scanning unit is shown in the figure.

[0028] Figure 3C It shows Figure 3A The structure of the first conductive layer in each scanning unit is shown in the figure.

[0029] Figure 3D It shows Figure 3A The structure of the second conductive layer in each scanning unit is shown in the figure.

[0030] Figure 3E It shows Figure 3A The structure of the interlayer dielectric layer in each scanning unit is shown in the figure.

[0031] Figure 3F It shows Figure 3A The structure of the first signal line layer in each scanning unit is shown in the figure.

[0032] Figure 3G It shows Figure 3A The structure of the second signal line layer in each scanning unit is shown in the figure.

[0033] Figure 3H The structure of the first signal line layer in the scanning circuit and the second scanning circuit according to some embodiments of the present disclosure is shown.

[0034] Figure 4 This is a schematic diagram illustrating the display area and surrounding area in a display device according to some embodiments of the present disclosure.

[0035] Figure 5A Detailed structures in display areas of a display panel according to some embodiments of the present disclosure are shown.

[0036] Figure 5B Detailed structures in display areas of a display panel according to some embodiments of the present disclosure are shown. Specific Implementation

[0037] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented in this disclosure is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0038] This disclosure provides, in particular, a scanning circuit and a display device that substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a scanning circuit. In some embodiments, the scanning circuit includes multiple stages. Each scanning unit in each of the multiple stages of the scanning circuit includes an input sub-circuit, an output sub-circuit, a first processing sub-circuit, a second processing sub-circuit, and a third processing sub-circuit. Optionally, each scanning unit includes a first connecting line located in a first signal line layer, a second connecting line located in a first conductive layer, a first capacitor in the second processing sub-circuit, and a third capacitor in the third processing sub-circuit. Optionally, the first connecting line is a first integral structure electrically connected to a first electrode of a sixth transistor in the second processing sub-circuit, a gate of a seventh transistor in the second processing sub-circuit, a gate of a fourth transistor in the third processing sub-circuit, and a second capacitor electrode of the third capacitor. Optionally, a second integral structure includes a second connecting line and a first capacitor electrode of the first capacitor, the second connecting line electrically connecting the first capacitor electrode of the first capacitor to a second electrode of the third transistor in the third processing sub-circuit. Optionally, the first connecting line intersects with the second connecting line.

[0039] Various suitable structures can be implemented in this scanning circuit. Figure 1 This is a circuit diagram of each scanning unit according to some embodiments of this disclosure. (Refer to...) Figure 1 In some embodiments, each scanning unit includes an input sub-circuit ISC, an output sub-circuit OSC, a first processing sub-circuit PSC1, a second processing sub-circuit PSC2, and a third processing sub-circuit PSC3.

[0040] In some embodiments, the output sub-circuit OSC is configured to provide a first power supply VGH or a second power supply VGL to the output terminal TM4 in response to the voltages of the fourth node N4 and the first node N1. Optionally, the output sub-circuit OSC includes a ninth transistor T9 and a tenth transistor T10.

[0041] The ninth transistor T9 is coupled between the first power supply VGH and the output terminal TM4. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the first power supply VGH is provided to the output terminal TM4, and the voltage of the first power supply VGH (in...) Figure 1 The signal marked as Outc can be transmitted to the nth gate line and used as a gate drive signal with a gate on level.

[0042] The tenth transistor T10 is coupled between the output terminal TM4 and the second power supply VGL. The gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off according to the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the second power supply VGL is provided to the output terminal TM4, and the voltage of the second power supply VGL (in the...) Figure 1 The signal marked Outc can be provided to the nth gate line and used as a gate drive signal with a gate cutoff level. In one example, when the gate drive signal has a gate cutoff level, it can be understood that no gate drive signal is provided.

[0043] In some embodiments, the input sub-circuit ISC is configured to control the voltages of the first node N1 and the fifth node N5 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input sub-circuit ISC includes a first transistor T1.

[0044] The first transistor T1 is coupled between the first input terminal TM1 and the fifth node N5. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 is turned on to be electrically coupled to the first input terminal TM1 and the fifth node N5.

[0045] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1. Optionally, the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2.

[0046] The eighth transistor T8 is coupled between the first power supply VGH and the fourth node N4. The gate of the eighth transistor T8 is coupled to the first node N1. The eighth transistor T8 can be turned on or off depending on the voltage of the first node N1. Optionally, when the eighth transistor T8 is turned on, the voltage of the first power supply VGH can be supplied to the fourth node N4.

[0047] The second capacitor C2 is coupled between the first power supply VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge the voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to maintain the voltage of the fourth node N4.

[0048] In some embodiments, the second processing sub-circuit PSC2 is coupled to the sixth node N6 and configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0049] The first terminal of the first capacitor C1 is coupled to the sixth node N6, and the second terminal of the first capacitor C1 is coupled to the third node N3, which is the common node between the sixth transistor T6 and the seventh transistor T7.

[0050] The sixth transistor T6 is coupled between the third node N3 and the sixth node N6. The gate of the sixth transistor T6 is coupled to the sixth node N6. The sixth transistor T6 can be turned on according to the voltage of the sixth node N6, so that the voltage corresponding to the second clock signal CB provided to the third input terminal TM3 can be applied to the third node N3.

[0051] A seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 can be turned on in response to the effective voltage of the second clock signal CB provided to the third input terminal TM3. As used in this disclosure, the effective voltage refers to a low voltage in the case of a p-type transistor and a high voltage in the case of an n-type transistor; the ineffective voltage refers to a high voltage in the case of a p-type transistor and a low voltage in the case of an n-type transistor.

[0052] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.

[0053] The first electrode of the third capacitor C3 is coupled to the first node N1, and the second electrode of the third capacitor C3 is coupled to the third input terminal TM3. The third capacitor C3 is configured to stabilize the voltage level at either the first node N1 or the fifth node N5.

[0054] The fifth transistor T5 is coupled between the first power supply VGH and the seventh node N7. The gate of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 can be turned on or off according to the voltage of the second node N2.

[0055] The fourth transistor T4 is coupled between the seventh node N7 and the first node N1. The gate of the fourth transistor T4 is coupled to the third input terminal TM3. The fourth transistor T4 can be turned on or off in response to the second clock signal CB provided to the third input terminal TM3.

[0056] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. The gate of the second transistor T2 is coupled to the fifth node N5.

[0057] The third transistor T3 is coupled between the second node N2 and the second power supply VGL. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the third transistor T3 can be turned on, so that the voltage of the second power supply VGL can be provided to the second node N2.

[0058] In some embodiments, each of the first transistor T1 to the tenth transistor T10 may be formed of a p-type transistor. In some embodiments, in the case of p-type transistors, the gate on-state voltage of the first transistor T1 to the tenth transistor T10 may be set to a low level, while its gate off-state voltage may be set to a high level.

[0059] In some embodiments, each of the first to tenth transistors T1 to T10 may be formed of an n-type transistor. In some embodiments, in the case of n-type transistors, the gate on-state voltage of the first transistor T1 to the tenth transistor T10 may be set to a high level, while its gate off-state voltage may be set to a low level.

[0060] Figure 2 It is shown Figure 1 The timing diagram shows the operation of the scanning unit at the indicated level. (Refer to...) Figure 2 The first clock signal CK and the second clock signal CB each have two horizontal time periods (2H) and have a gate on level during different horizontal time periods. Optionally, the second clock signal CB can be set to a signal offset from the first clock signal CK by half a period (i.e., one horizontal time period (1H)).

[0061] In some embodiments, when clock signals CK and CB are provided, the second input terminal TM2 and the third input terminal TM3 can be set to a low level, i.e., the voltage of the second power supply VGL. When clock signals CK and CB are not provided, the second input terminal TM2 and the third input terminal TM3 can be set to a high level, i.e., the voltage of the first power supply VGH.

[0062] In some embodiments, when a start signal STV or an output signal Outp from the output terminal of a previous scan unit (e.g., a previous scan unit in the same stage or a previous scan unit in the previous stage) is provided, the first input terminal TM1 can be set to a high level, i.e., the voltage of the first power supply VGH. When the start signal STV or the output signal Outp from the output terminal of a previous scan unit is not provided, the first input terminal TM1 can be set to a low level, i.e., the voltage of the second power supply VGL.

[0063] In some embodiments, the start signal STV provided to the first input terminal TM1 or the output signal Outp from the output terminal of the previous scan unit may be configured to overlap with the first clock signal CK provided to the second input terminal TM2 at least once. Optionally, the width of the start signal STV or the output signal Outp from the output terminal of the previous scan unit may be greater than the width of the first clock signal CK, for example, provided during four horizontal time periods (4H). In this case, the output signal provided to the first input terminal TM1 of the next stage may also overlap with the second clock signal CB provided to the second input terminal TM2 of the next stage at least once.

[0064] In some embodiments, during the first time period t1, the first clock signal CK is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned on. Furthermore, during the first time period t1, the second clock signal CB is not provided to the third input terminal TM3, and the seventh transistor T7 is turned off.

[0065] In some embodiments, when the first transistor T1 is turned on, the first input terminal TM1 is electrically coupled to the fifth node N5. The first input terminal TM1 is electrically coupled to the first node N1 through the fifth node N5.

[0066] In some embodiments, during the first time period t1, the start signal STV provided to the first input terminal TM1 or the output signal Outp from the output terminal of the previous scan unit has a low level, and a low voltage (e.g., the voltage of the second power supply VGL) can be applied to the fifth node N5 and the first node N1. When the fifth node N5 and the first node N1 are set to a low voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned on.

[0067] In some embodiments, during the first time period t1, the second clock signal CB is not provided to the third input terminal TM3, and a high voltage is provided to the third capacitor C3.

[0068] In some embodiments, when the fourth transistor T4 is off, the fifth transistor T5 is connected as a diode between the second node N2 and the first power supply VGH. When the fifth transistor T5 is on during the first time period t1, the voltage of the first power supply VGH is not transmitted to the second node N2, and the voltage of the second node N2 remains at the voltage of the previous state, for example, a high voltage. The high voltage of the second node N2 is applied to the sixth node N6, and the sixth node N6 is set to a high voltage. The sixth transistor T6 is off.

[0069] In some embodiments, when the eighth transistor T8 is turned on, the voltage of the first power supply VGH is provided to the fourth node N4. The ninth transistor T9 is turned off.

[0070] In some embodiments, when the tenth transistor T10 is turned on, the voltage of the second power supply VGL is provided to the output terminal TM4. During the first time period t1, the gate drive signal is not provided to the nth gate line.

[0071] In some embodiments, during the second time period t2, the supply of the first clock signal CK to the second input terminal TM2 is interrupted. The first transistor T1 and the fifth transistor T5 are turned off. The fourth node N4 and the first node N1 maintain the voltage of the previous time period through the second capacitor C2 and the third capacitor C3, respectively. Since the fourth node N4 remains in a high voltage state, the ninth transistor T9 remains off. Since the first node N1 remains in a low voltage state, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 remain in a conducting state.

[0072] In some embodiments, during the second time period t2, a second clock signal CB is provided to the third input terminal TM3. The seventh transistor T7 is turned on by the second clock signal CB provided to the third input terminal TM3. When the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. The third node N3 is set to a high voltage.

[0073] In some embodiments, during the second time period t2, the second clock signal CB is provided to the gate of the fourth transistor T4, thereby turning on the fourth transistor T4. A low voltage is provided to the seventh node N7 via the fourth transistor T4. Through the coupling of the third capacitor C3, the voltage of the first node N1 is maintained at a voltage lower than the second power supply voltage VGL (second-order low voltage).

[0074] In some embodiments, during the third time period t3, the supply of the second clock signal CB to the third input terminal TM3 is interrupted. When the supply of the second clock signal CB is interrupted, the seventh transistor T7 is turned off.

[0075] In some embodiments, during the third time period t3, the start signal STV or the output signal Outp from the output terminal of the previous scan unit is provided to the first input terminal TM1, and the first clock signal CK is provided to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on.

[0076] In some embodiments, when the first transistor T1 is turned on, the first input terminal TM1 and the fifth node N5 are electrically coupled to each other. The first input terminal TM1 is electrically coupled to the first node N1 through the fifth node N5. The fifth node N5 and the first node N1 are set to a high voltage by a start signal STV provided to the first input terminal TM1 or an output signal Outp from the output terminal of the previous scan unit. When the fifth node N5 and the first node N1 are set to a high voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0077] In some embodiments, when the third transistor T3 is turned on, a low voltage of the second power supply VGL is applied to the second node N2, causing the second node N2 and the sixth node N6 to be set to a low voltage. The fifth transistor T5 and the sixth transistor T6 can then be turned on.

[0078] In some embodiments, when the sixth transistor T6 is turned on, the third input terminal TM3 is electrically coupled to the third node N3. Since the second clock signal CB is not provided to the third input terminal TM3 during the third time period t3, the third node N3 remains at a high voltage. Since the seventh transistor T7 remains off, the voltage of the third node N3 does not affect the voltage of the fourth node N4. The first capacitor C1 is configured to store a voltage corresponding to the on-level of the sixth transistor T6.

[0079] In some embodiments, during the fourth time period t4, the second clock signal CB may be provided to the third input terminal TM3. When the second clock signal CB is provided to the third input terminal TM3, the seventh transistor T7 is turned on.

[0080] In some embodiments, when the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. A low voltage of the second clock signal CB, provided to the third input terminal TM3, is provided to the third node N3 and the fourth node N4 via the sixth transistor T6, which remains on. When a low voltage is provided to the fourth node N4, the ninth transistor T9 is turned on.

[0081] In some embodiments, when the ninth transistor T9 is turned on, the voltage of the first power supply VGH is provided to the output terminal TM4. The voltage of the first power supply VGH provided to the output terminal TM4 is provided to the nth gate line as a gate drive signal.

[0082] In some embodiments, during the fifth time period t5, the supply of the second clock signal CB to the third input terminal TM3 is interrupted. When the supply of the second clock signal CB is interrupted, the seventh transistor T7 is turned off. The fourth node N4 is stably maintained at a high voltage through the second capacitor C2. The ninth transistor T9 remains on, and the voltage of the first power supply VGH is provided to the nth gate line as a gate drive signal.

[0083] Figure 3A The structure of each scanning unit in a scanning circuit according to some embodiments of the present disclosure is shown. Figure 3B It shows Figure 3A The structure of the semiconductor material layer in each scanning unit is shown in the figure. Figure 3C It shows Figure 3A The structure of the first conductive layer in each scanning unit is shown in the figure. Figure 3D It shows Figure 3A The structure of the second conductive layer in each scanning unit is shown in the figure. Figure 3E It shows Figure 3A The structure of the interlayer dielectric layer in each scanning unit is shown in the figure. Figure 3F It shows Figure 3A The structure of the first signal line layer of each scanning unit is shown in the figure. Figure 3G It shows Figure 3A The diagram shows the structure of the second signal line layer for each scanning unit. (Refer to...) Figures 3A to 3G In some embodiments, as described above... Figure 1 and Figure 2 The scanning unit of the scanning circuit in each of the multiple stages includes ten transistors (T1 to T10) and three capacitors (C1 to C3).

[0084] Reference Figure 3A and Figure 3B In some embodiments, the semiconductor material layer includes the active layer of each scanning unit, including the active layer ACT1 of the first transistor T1, the active layer ACT2 of the second transistor T2, the active layer ACT3 of the third transistor T3, the active layer ACT4 of the fourth transistor T4, the active layer ACT5 of the fifth transistor T5, the active layer ACT6 of the sixth transistor T6, the active layer ACT7 of the seventh transistor T7, the active layer ACT8 of the eighth transistor T8, the active layer ACT9 of the ninth transistor T9, and the active layer ACT10 of the tenth transistor T10.

[0085] In some embodiments, the active layer ACT1 of the first transistor T1 and the active layer ACT3 of the third transistor T3 are arranged along a first direction DR1. (Refer to...) Figures 3A to 3C In some embodiments, the seventh connection line Cl7 in the first conductive layer includes the gate G1 of the first transistor T1 and the gate G3 of the third transistor T3. In one embodiment, the seventh connection line Cl7 is an integral structure.

[0086] In some embodiments, the active layer ACT1 of the first transistor T1, the active layer ACT4 of the fourth transistor T4, and the active layer ACT5 of the fifth transistor T5 are arranged along the second direction DR2. Optionally, at least a portion of the active layer ACT4 of the fourth transistor T4 and at least a portion of the active layer ACT5 of the fifth transistor T5 are collinear along the second direction DR2.

[0087] In some embodiments, the second transistor T2 has a dual-gate structure, and the active layer ACT2 of the second transistor T2 comprises two parts.

[0088] In some embodiments, the ninth transistor T9 has a multi-gate structure, and the active layer ACT9 of the ninth transistor T9 includes multiple portions arranged in multiple columns and rows, such as two columns and three rows.

[0089] In some embodiments, the tenth transistor T10 has a multi-gate structure, and the active layer ACT10 of the tenth transistor T10 includes multiple portions arranged in multiple columns and rows, such as two columns and three rows.

[0090] In some embodiments, the overall structure extending along the second direction DR2 includes an active layer ACT4 of a fourth transistor T4 and an active layer ACT5 of a fifth transistor T5. Optionally, the ratio of the channel width of the active layer ACT4 of the fourth transistor T4 to the channel width of the active layer ACT5 of the fifth transistor T5 is in the range of 1.5:1 to 2.5:1, for example, 1.5:1 to 1.6:1, 1.6:1 to 1.7:1, 1.7:1 to 1.8:1, 1.8:1 to 1.9:1, 1.9:1 to 2.0:1, 2.0:1 to 2.1:1, 2.1:1 to 2.2:1, 2.2:1 to 2.3:1, 2.3:1 to 2.4:1, or 2.4:1 to 2.5:1.

[0091] Optionally, the ratio of the channel width of the active layer ACT4 of the fourth transistor T4 to the channel width of the active layers of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, or the eighth transistor T8 is in the range of 1.5:1 to 2.5:1, for example, 1.5:1 to 1.6:1, 1.6:1 to 1.7:1, 1.7:1 to 1.8:1, 1.8:1 to 1.9:1, 1.9:1 to 2.0:1, 2.0:1 to 2.1:1, 2.1:1 to 2.2:1, 2.2:1 to 2.3:1, 2.3:1 to 2.4:1, or 2.4:1 to 2.5:1.

[0092] Optionally, the channel width of the active layer ACT9 of the ninth transistor T9 is greater than 180 μm, for example, 180 μm to 200 μm, 200 μm to 220 μm, 220 μm to 240 μm, 240 μm to 260 μm, 260 μm to 280 μm, or 280 μm to 300 μm. Optionally, the channel width of the active layer ACT10 of the tenth transistor T10 is greater than 180 μm, for example, 180 μm to 200 μm, 200 μm to 220 μm, 220 μm to 240 μm, 240 μm to 260 μm, 260 μm to 280 μm, or 280 μm to 300 μm. Optionally, the channel width of the active layer ACT10 of the tenth transistor T10 is greater than the channel width of the active layer ACT9 of the ninth transistor T9.

[0093] Optionally, the channel length of the active layer ACT9 of the ninth transistor T9 is less than or equal to 3.8 μm, for example, 3.0 μm to 3.1 μm, 3.1 μm to 3.2 μm, 3.2 μm to 3.3 μm, 3.3 μm to 3.4 μm, 3.4 μm to 3.5 μm, 3.5 μm to 3.6 μm, 3.6 μm to 3.7 μm, or 3.7 μm to 3.8 μm. Optionally, the channel length of the active layer ACT10 of the tenth transistor T10 is less than or equal to 3.8 μm, for example, 3.0 μm to 3.1 μm, 3.1 μm to 3.2 μm, 3.2 μm to 3.3 μm, 3.3 μm to 3.4 μm, 3.4 μm to 3.5 μm, 3.5 μm to 3.6 μm, 3.6 μm to 3.7 μm, or 3.7 μm to 3.8 μm.

[0094] Optionally, the ratio of the channel width to the channel length of the active layer ACT4 of the fourth transistor T4 is in the range of 1.75 to 2. Optionally, the ratio of the channel width to the channel length of the active layer of the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, or the eighth transistor T8 is in the range of 0.92 to 0.95.

[0095] In some embodiments, the overall structure includes an active layer ACT6 of a sixth transistor T6 and an active layer ACT7 of a seventh transistor T7. The overall structure includes a first portion extending along a first direction DR1 and a second portion extending along a second direction DR2, wherein the first portion includes the active layer ACT7 of the seventh transistor T7, and the second portion includes the active layer ACT6 of the sixth transistor T6. Optionally, the angle between the first portion and the second portion is in the range of 85 degrees to 95 degrees, for example, 90 degrees.

[0096] Reference Figure 3A and Figure 3CIn some embodiments, the first conductive layer includes the gates of each scanning unit, including the gate G1 of the first transistor T1, the gate G2 of the second transistor T2, the gate G3 of the third transistor T3, the gate G4 of the fourth transistor T4, the gate G5 of the fifth transistor T5, the gate G6 of the sixth transistor T6, the gate G7 of the seventh transistor T7, the gate G8 of the eighth transistor T8, the gate G9 of the ninth transistor T9, and the gate G10 of the tenth transistor T10. In some embodiments, the first conductive layer also includes the first capacitor electrode Ce1-1 of the first capacitor C1, the first capacitor electrode Ce1-2 of the second capacitor C2, and the first capacitor electrode Ce1-3 of the third capacitor C3. In some embodiments, the first conductive layer also includes a second connection line Cl2, a fourth connection line Cl4, a sixth connection line Cl6, and a seventh connection line Cl7. In some embodiments, for example, when the scanning units are not in the first stage, the first conductive layer also includes an output signal line LOUTp from the output terminal of the previous scanning unit. The output signal line LOUTp is electrically connected to the first electrode of the first transistor T1.

[0097] Reference Figure 3A and Figure 3D In some embodiments, the second conductive layer includes the second capacitor electrode Ce2-1 of the first capacitor C1, the second capacitor electrode Ce2-2 of the second capacitor C2, and the second capacitor electrode Ce2-3 of the third capacitor C3. In some embodiments, the second conductive layer further includes a tenth connecting line Cl10.

[0098] Reference Figure 3E This shows a via extending through the interlayer dielectric layer.

[0099] Reference Figure 3A and Figure 3F In some embodiments, the first signal line layer includes a plurality of signal lines extending along a second direction DR2. The plurality of signal lines include a first voltage signal line LVGH, a second voltage signal line LVGL, a start signal line LSTV, a first clock signal line CLK, and a second clock signal line CLB. Figure 3F A plurality of signal lines configured to provide signals to a second scan circuit adjacent to the scan circuit are also shown. The plurality of signal lines configured to provide signals to the second scan circuit include a third voltage signal line LVGH', a fourth voltage signal line LVGL', a second start signal line LSTV', a third clock signal line CLK', and a fourth clock signal line CLB'. In some embodiments, the first signal line layer further includes an output signal line LOutc, which is configured to output control signals to one or more rows of sub-pixels in a corresponding level. In some embodiments, the first signal line layer further includes a first connection line Cl1, a third connection line Cl3, a fifth connection line Cl5, an eighth connection line Cl8, and a ninth connection line Cl9.

[0100] Reference Figure 3A and Figure 3G In some embodiments, the second signal line layer includes an anode material layer AML.

[0101] Reference Figure 1 , Figure 2 and Figures 3A to 3G In some embodiments, each scanning unit includes a first connection line Cl1 in a first signal line layer, a second connection line Cl2 in a first conductive layer, a first capacitor C1 in a second processing sub-circuit PSC2, and a third capacitor C3 in a third processing sub-circuit PSC3. A first overall structure includes the first connection line Cl1, which is electrically connected to the first electrode of the sixth transistor T6 in the second processing sub-circuit PSC2, the gate G7 of the seventh transistor T7 in the second processing sub-circuit PSC2, the gate G4 of the fourth transistor T4 in the third processing sub-circuit PSC3, and the second capacitor electrode Ce2-3 of the third capacitor C3. A second overall structure includes the second connection line Cl2 and the first capacitor electrode Ce1-1 of the first capacitor C1. The second connection line Cl2 electrically connects the first capacitor electrode Ce1-1 of the first capacitor C1 to the second electrode of the third transistor T3 in the third processing sub-circuit PSC3. Optionally, the first connection line Cl1 intersects with the second connection line Cl2.

[0102] In some embodiments, each scanning unit further includes a third connection line Cl3 located in the first signal line layer. The third connection line Cl3 is electrically connected to the second connection line Cl2, the second electrode of the third transistor T3 in the third processing sub-circuit PSC3, and the second electrode of the second transistor T2 in the third processing sub-circuit PSC3.

[0103] In some embodiments, each scanning unit further includes a fourth connection line Cl4 located in the first conductive layer. The third overall structure includes the fourth connection line Cl4 and the first capacitor electrode Ce1-3 of the third capacitor C3. The fourth connection line Cl4 is electrically connected to the first capacitor electrode Ce1-3 of the third capacitor C3, the second electrode of the first transistor T1 in the input sub-circuit ISC, and the second electrode of the fourth transistor T4 in the third processing sub-circuit PSC3. Optionally, the third connection line Cl3 intersects with the fourth connection line Cl4.

[0104] In some embodiments, each scanning unit further includes a branch line B1 extending away from the fourth connection line Cl4. The third overall structure includes the branch line B1, the fourth connection line Cl4, and the first capacitor electrode Ce1-3 of the third capacitor C3. A portion of the fourth connection line Cl4 and a portion of the branch line B1 form the dual-gate structure of the second transistor T2 in the third processing sub-circuit PSC3.

[0105] In some embodiments, each scanning unit further includes a fifth connection line Cl5 located in the first signal line layer. The fifth connection line Cl5 is electrically connected to the second electrode of the first transistor T1 in the input sub-circuit ISC, the second electrode of the fourth transistor T4 in the third processing sub-circuit PSC3, and the fourth connection line Cl4. Optionally, the fourth connection line Cl4 extends along a first direction DR1. Optionally, the fifth connection line Cl5 extends along a second direction DR2, which is different from the first direction DR1.

[0106] In some embodiments, the scanning circuit further includes a second clock signal line CLB located in the first signal line layer; and a sixth connection line Cl6 located in the first conductive layer. Optionally, the sixth connection line Cl6 is electrically connected to the first connection line Cl1 and the second clock signal line CLB. Optionally, the sixth connection line Cl6 includes the gate of the fourth transistor T4 in the third processing sub-circuit PSC3.

[0107] In some embodiments, the scanning circuit further includes: a first clock signal line CLK located in the first signal line layer; and a seventh connection line Cl7 located in the first conductive layer. Optionally, the seventh connection line is electrically connected to the first electrode of the second transistor T2 in the third processing sub-circuit PSC3 and the first clock signal line CLK. Optionally, the seventh connection line Cl7 includes the gate of the first transistor T1 in the input sub-circuit ISC and the gate of the third transistor T3 in the third processing sub-circuit PSC3.

[0108] In some embodiments, each scanning unit further includes an eighth connection line Cl8 located in the first signal line layer, which is electrically connected to the first electrode of the second transistor T2 in the third processing sub-circuit PSC3, along with the seventh connection line Cl7. Optionally, the seventh connection line Cl7 extends along a first direction DR1. Optionally, the eighth connection line Cl8 extends along a second direction DR2, which is different from the first direction DR1.

[0109] In some embodiments, each scanning unit further includes a ninth connection line Cl9 located in the first signal line layer. The ninth connection line Cl9 electrically connects the second capacitor electrode Ce2-1 of the first capacitor C1 to the second electrode of the sixth transistor T6 and the first electrode of the seventh transistor T7 in the second processing sub-circuit PSC2. Optionally, the orthographic projection of the ninth connection line Cl9 on the substrate partially overlaps with the orthographic projection of the second capacitor electrode Ce2-1 of the first capacitor C1 on the substrate.

[0110] In some embodiments, the orthographic projection of the first connecting line Cl1 on the substrate partially overlaps with the orthographic projection of the second capacitor electrode Ce2-3 of the third capacitor C3 on the substrate.

[0111] In some embodiments, the second overall structure includes a second connection line Cl2, a first capacitor electrode Ce1-1 of a first capacitor C1, the gate of a fifth transistor T5 in a third processing sub-circuit PSC3, and the gate of a sixth transistor T6 in a second processing sub-circuit.

[0112] In some embodiments, each scanning unit includes: a second capacitor C2 in the first processing sub-circuit PSC1; and a ninth transistor T9 and a tenth transistor T10 in the output sub-circuit OSC. In some embodiments, the ninth transistor T9 and the tenth transistor T10 are arranged along a second direction DR2. Optionally, the first capacitor C1, the third capacitor C3, and the second capacitor C2 are arranged sequentially along a first direction DR1. Optionally, along the first direction DR1, the second capacitor C2 is located on the side of the ninth transistor T9 and the tenth transistor T10 away from the first capacitor C1 and the third capacitor C3.

[0113] In some embodiments, each scanning unit includes an eighth transistor T8 in the first processing sub-circuit PSC1. Optionally, along the first direction DR1, the eighth transistor T8 is located on the side of the ninth transistor T9 and the tenth transistor T10 away from the first capacitor C1, the third capacitor C3, and the other transistors of each scanning unit.

[0114] In some embodiments, each scanning unit further includes a first voltage signal line LVGH and a second voltage signal line LVGL located in the first signal line layer. Optionally, along the first direction DR1, the first voltage signal line LVGH and the second voltage signal line LVGL are located on opposite sides of the transistor and capacitor of each scanning unit, respectively. Optionally, the first voltage signal line LVGH is electrically coupled to the first electrode of the fifth transistor T5 in the third processing sub-circuit PSC3, the first electrode of the eighth transistor T8 in the first processing sub-circuit PSC1, and the first electrode of the ninth transistor T9 in the output sub-circuit OSC. Optionally, the second voltage signal line LVGL is electrically coupled to the first electrode of the tenth transistor T10 in the output sub-circuit OSC.

[0115] In some embodiments, the scanning circuit includes a plurality of signal lines extending along a second direction DR2 in a first signal line layer. Among the plurality of signal lines, the first voltage signal line LVGH and the second voltage signal line LVGL are closest to the transistors and capacitors of each scanning unit.

[0116] In some embodiments, the fourth overall structure includes the active layer of the fourth transistor T4 in the third processing sub-circuit PSC3 and the active layer of the fifth transistor T5 in the third processing sub-circuit PSC3. Optionally, the ratio of the channel width of the active layer of the fourth transistor T4 to the channel width of the active layer of the fifth transistor T5 is in the range of 1.5:1 to 2.5:1.

[0117] In some embodiments, each scanning unit further includes a fifth connection line Cl5 located in the first signal line layer. The fifth connection line Cl5 is electrically connected to the second electrode of the first transistor T1 in the input sub-circuit ISC, the second electrode of the fourth transistor T4 in the third processing sub-circuit PSC3, and the fourth connection line Cl5. Optionally, the active layer of the first transistor T1 in the input sub-circuit ISC, the fifth connection line Cl5, the active layer of the fourth transistor T4 in the third processing sub-circuit PSC3, and the active layer of the fifth transistor T5 in the third processing sub-circuit PSC3 are collinear and arranged sequentially along the second direction DR2.

[0118] In some embodiments, the active layers of the first transistor T1 and the third transistor T3 are parallel and extend along the second direction DR2.

[0119] On the other hand, the present invention provides a display device including a scanning circuit manufactured according to or by methods described in this disclosure, and a display panel having a plurality of light-emitting elements. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS devices, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a quantum dot display device.

[0120] In some embodiments, the display device further includes a second scanning circuit. The scanning circuit described herein is configured to provide a first type of control signal; the second scanning circuit is configured to provide a second type of control signal. The first type of control signal and the second type of control signal are different from each other. In one example, the first type of control signal is a light emission control signal. In another example, the second type of control signal is a reset control signal. Optionally, the scanning circuit and the second scanning circuit are arranged along a first direction DR1. Figure 3H The structure of the first signal line layer in the scanning circuit and the second scanning circuit according to some embodiments of the present disclosure is shown. (Refer to...) Figure 3H In some embodiments, along the first direction DR1, the display device further includes a first voltage signal line LVGH and a second voltage signal line LVGL configured to provide a first voltage signal and a second voltage signal to the scanning circuit SC, respectively, and a third voltage signal line LVGH' and a fourth voltage signal line LVGL' configured to provide the first voltage signal and the second voltage signal to the scanning circuit SC2, respectively.

[0121] In some embodiments, each scanning unit further includes a tenth connection line Cl10, which connects the second capacitor electrode Ce2-2 of the second capacitor C2 in the scanning unit to a third voltage signal line LVGH'. Optionally, the tenth connection line Cl10 intersects with a plurality of signal lines extending along the second direction DR2 and configured to provide signals to the second scanning circuit. Optionally, the fifth overall structure includes the tenth connection line Cl10 in the scanning unit and the second capacitor electrode Ce2-2 of the second capacitor C2.

[0122] The scanning circuit described in this disclosure can be used to generate various suitable control signals to sub-pixels in a display panel. In one example, the scanning circuit described in this disclosure is a light emission control signal generation circuit configured to generate light emission control signals to sub-pixels in a display panel. In another example, the scanning circuit described in this disclosure is a gate scan signal generation circuit configured to generate gate scan signals to sub-pixels in a display panel. In yet another example, the scanning circuit described in this disclosure is a reset control signal generation circuit configured to generate reset control signals to sub-pixels in a display panel.

[0123] Figure 4 A schematic diagram showing the display area and surrounding area in a display device according to some embodiments of the present disclosure is provided. (Refer to...) Figure 4 In some embodiments, the display device includes a display area DA and a peripheral area PA. As used herein, the term "display area" refers to the area of ​​the display panel that actually displays an image. Optionally, the display area may include subpixel areas and inter-subpixel areas. A subpixel area refers to the light-emitting area of ​​a subpixel, for example, the area corresponding to a pixel electrode in a liquid crystal display or the area corresponding to a light-emitting layer in an organic light-emitting diode display panel. An inter-subpixel area refers to the area between adjacent subpixel areas, for example, the area corresponding to a black matrix in a liquid crystal display or the area corresponding to a pixel defining layer in an organic light-emitting diode display panel. Optionally, the inter-subpixel area is the area between adjacent subpixel areas within the same pixel. Optionally, the inter-subpixel area is the area between two adjacent subpixel areas from two adjacent pixels.

[0124] In some embodiments, the scanning circuitry is located in the peripheral region. As used herein, the term "peripheral region" refers to an area of ​​the display panel in which various circuits (e.g., scanning circuitry) and wires are provided to transmit signals to the display panel. To increase the transparency of the display panel, opaque or light-blocking components of the display panel (e.g., batteries, printed circuit boards, metal frames, etc.) may be located in the peripheral region instead of the display region.

[0125] Various implementations of this display panel can be carried out. Figure 5ADetailed structures in display areas of a display panel according to some embodiments of the present disclosure are shown. (Refer to...) Figure 5A In some embodiments, the display panel includes in the display area: a substrate BS (e.g., a flexible substrate); an active layer ACT of a corresponding thin-film transistor among a plurality of thin-film transistors (TFTs) located on the substrate BS; a gate insulating layer GI located on the side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both portions of a first conductive layer) located on the side of the gate insulating layer GI away from the substrate BS; an insulating layer IN located on the side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (a portion of a second conductive layer) located on the side of the insulating layer IN away from the gate insulating layer GI; an interlayer dielectric layer ILD located on the side of the second capacitor electrode Ce2 away from the gate insulating layer GI; a first electrode S and a second electrode D (a portion of a first SD metal layer) located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; a planarization layer PLN located on the side of the first electrode S and the second electrode D away from the interlayer dielectric layer ILD; a pixel defining layer PDL defining a sub-pixel opening and located on the side of the planarization layer PLN away from the substrate BS; and a light-emitting element LE located in the sub-pixel opening. The light-emitting element LE includes: an anode AD, located on the side of the planarization layer PLN away from the interlayer dielectric layer ILD; a light-emitting layer EL, located on the side of the anode AD away from the planarization layer PLN; and a cathode layer CD, located on the side of the light-emitting layer EL away from the anode AD. The display panel also includes an encapsulation layer EN within the display area, which encapsulates the light-emitting element LE and is located on the side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 located on the side of the cathode layer CD away from the substrate BS, an organic encapsulation sublayer IJP located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS, and a second inorganic encapsulation sublayer CVD2 located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. The display panel also includes, in the display area: a buffer layer BUF located on the side of the encapsulation layer EN away from the substrate BS; a plurality of second electrode bridges BR located on the side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI located on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 located on the side of the touch insulating layer TI away from the buffer layer BUF; and an overcoat layer OC located on the side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI.

[0126] Reference Figure 5AThe display panel includes a semiconductor material layer SML, a first conductive layer Gate1, a second conductive layer Gate2, and a first signal line layer SLL1. The display panel also includes an insulating layer IN located between the first conductive layer Gate1 and the second conductive layer Gate2; and an interlayer dielectric layer ILD located between the second conductive layer Gate2 and the first signal line layer SLL1.

[0127] Figure 5B Detailed structures in display areas of a display panel according to some embodiments of the present disclosure are shown. (Refer to...) Figure 5BIn some embodiments, the display panel includes, in the display area: a substrate BS (e.g., a flexible substrate); an active layer ACT of a corresponding thin-film transistor among a plurality of thin-film transistors (TFTs) located on the substrate BS; a gate insulating layer GI located on the side of the active layer ACT away from the substrate BS; a gate G and a first capacitor electrode Ce1 (both portions of a first conductive layer) located on the side of the gate insulating layer GI away from the substrate BS; an insulating layer IN located on the side of the gate G and the first capacitor electrode Ce1 away from the gate insulating layer GI; a second capacitor electrode Ce2 (a portion of a second conductive layer) located on the side of the insulating layer IN away from the gate insulating layer GI; and an interlayer located on the side of the second capacitor electrode Ce2 away from the gate insulating layer GI. The interlayer dielectric layer (ILD); a first electrode S and a second electrode D (part of the first SD metal layer) located on the side of the interlayer dielectric layer ILD away from the gate insulating layer GI; a passivation layer PVX located on the side of the first electrode S and the second electrode D away from the interlayer dielectric layer ILD; a first planarization layer PLN1 located on the side of the passivation layer PVX away from the interlayer dielectric layer ILD; a relay electrode RE (part of the second SD metal layer) located on the side of the first planarization layer PLN1 away from the passivation layer PVX; a second planarization layer PLN2 located on the side of the relay electrode RE away from the first planarization layer PLN1; a pixel defining layer PDL defining a sub-pixel opening and located on the side of the second planarization layer PLN2 away from the substrate BS; and a light-emitting element LE located in the sub-pixel opening. The light-emitting element LE includes: an anode AD located on the side of the second planarization layer PLN2 away from the first planarization layer PLN1; a light-emitting layer EL located on the side of the anode AD away from the second planarization layer PLN2; and a cathode layer CD located on the side of the light-emitting layer EL away from the anode AD. The display panel further includes an encapsulation layer EN in the display area, which encapsulates the light-emitting element LE and is located on the side of the cathode layer CD away from the substrate BS. In some embodiments, the encapsulation layer EN includes a first inorganic encapsulation sublayer CVD1 located on the side of the cathode layer CD away from the substrate BS, an organic encapsulation sublayer IJP located on the side of the first inorganic encapsulation sublayer CVD1 away from the substrate BS, and a second inorganic encapsulation sublayer CVD2 located on the side of the organic encapsulation sublayer IJP away from the first inorganic encapsulation sublayer CVD1. The display panel also includes, in the display area: a buffer layer BUF located on the side of the encapsulation layer EN away from the substrate BS; a plurality of second electrode bridges BR2 located on the side of the buffer layer BUF away from the encapsulation layer EN; a touch insulating layer TI located on the side of the plurality of second electrode bridges BR2 away from the buffer layer BUF; a plurality of first touch electrodes TE1 located on the side of the touch insulating layer TI away from the buffer layer BUF; and a protective layer OC located on the side of the plurality of first touch electrodes TE1 away from the touch insulating layer TI.Optionally, the display panel does not include a passivation layer PVX in the display area, for example, the interlayer dielectric layer ILD is in direct contact with the first planarization layer PLN1.

[0128] Reference Figure 5B The display panel includes a semiconductor material layer SML, a first conductive layer Gate1, a second conductive layer Gate2, a first signal line layer SLL1, and a second signal line layer SLL2. The display panel also includes: an insulating layer IN located between the first conductive layer Gate1 and the second conductive layer Gate2; an interlayer dielectric layer ILD located between the second conductive layer Gate2 and the first signal line layer SLL1; and at least a passivation layer PVX or a planarization layer PLN located between the first signal line layer SLL1 and the second signal line layer SLL2.

[0129] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A scanning circuit comprising multiple stages; in, Each scanning unit of each of the plurality of stages of the scanning circuit includes an input sub-circuit, an output sub-circuit, a first processing sub-circuit, a second processing sub-circuit, and a third processing sub-circuit. The second processing sub-circuit includes a first capacitor; The third processing sub-circuit includes a third capacitor; The first processing sub-circuit includes an eighth transistor; and The output sub-circuit includes a ninth transistor and a tenth transistor; Wherein, along the first direction, the eighth transistor is located on the side of the ninth transistor and the tenth transistor that is away from the first capacitor, the third capacitor and the other transistors of each scanning unit; Each scanning unit includes a first connecting line located in the first signal line layer and a second connecting line located in the first conductive layer; The first overall structure includes the first connecting line, and the first overall structure is electrically connected to the first electrode of the sixth transistor in the second processing sub-circuit, the gate of the seventh transistor in the second processing sub-circuit, the gate of the fourth transistor in the third processing sub-circuit, and the second capacitor electrode of the third capacitor. The second overall structure includes the second connecting line and the first capacitor electrode of the first capacitor, wherein the second connecting line electrically connects the first capacitor electrode of the first capacitor to the second electrode of the third transistor in the third processing sub-circuit; and The first connecting line intersects with the second connecting line.

2. The scanning circuit according to claim 1, wherein, Each scanning unit further includes a third connection line located in the first signal line layer, the third connection line being electrically connected to the second connection line, the second electrode of the third transistor, and the second electrode of the second transistor in the third processing sub-circuit.

3. The scanning circuit according to claim 2, wherein, Each scanning unit further includes a fourth connection line located in the first conductive layer. The third overall structure includes the fourth connection line and the first capacitor electrode of the third capacitor. The fourth connection line is electrically connected to the first capacitor electrode of the third capacitor, the second electrode of the first transistor in the input sub-circuit, and the second electrode of the fourth transistor. The third connecting line intersects with the fourth connecting line.

4. The scanning circuit according to claim 3, wherein, Each scanning unit also includes a branch extending away from the fourth connecting line; The third overall structure includes the branch line, the fourth connecting line, and the first capacitor electrode of the third capacitor; as well as The dual-gate structure of the second transistor in the third processing sub-circuit includes a portion of the fourth connection line and a portion of the branch line.

5. The scanning circuit according to claim 3, wherein, Each scanning unit further includes a fifth connection line located in the first signal line layer, the fifth connection line being electrically connected to the second electrode of the first transistor, the second electrode of the fourth transistor, and the fourth connection line; The fourth connecting line extends along the first direction; and The fifth connecting line extends along a second direction different from the first direction.

6. The scanning circuit according to claim 1, further comprising: The second clock signal line is located in the first signal line layer; as well as The sixth connecting line located in the first conductive layer; The sixth connecting line is electrically connected to the first connecting line and the second clock signal line; and The sixth connection line includes the gate of the fourth transistor.

7. The scanning circuit according to claim 1, further comprising: The first clock signal line located in the first signal line layer; as well as The seventh connection line located in the first conductive layer; Wherein, the seventh connecting line is electrically connected to the first electrode of the second transistor in the third processing sub-circuit and to the first clock signal line; and The seventh connection line includes the gate of the first transistor and the gate of the third transistor in the input sub-circuit.

8. The scanning circuit according to claim 7, wherein, Each scanning unit further includes an eighth connection line located in the first signal line layer, and the eighth connection line and the seventh connection line are electrically connected to the first electrode of the second transistor; The seventh connecting line extends along the first direction; and The eighth connecting line extends along a second direction different from the first direction.

9. The scanning circuit according to claim 1, wherein, Each scanning unit further includes a ninth connection line located in the first signal line layer, wherein the ninth connection line is electrically connected to the second capacitor electrode of the first capacitor, the second electrode of the sixth transistor, and the first electrode of the seventh transistor; as well as The orthographic projection of the ninth connecting line on the substrate overlaps with the orthographic projection of the second capacitor electrode of the first capacitor on the substrate.

10. The scanning circuit according to any one of claims 1 to 9, wherein, The orthographic projection of the first connecting line on the substrate overlaps with the orthographic projection of the second capacitor electrode of the third capacitor on the substrate.

11. The scanning circuit according to claim 1, wherein, The second overall structure includes the second connecting line, the first capacitor electrode of the first capacitor, the gate of the fifth transistor in the third processing sub-circuit, and the gate of the sixth transistor.

12. The scanning circuit according to claim 1, wherein, Each scanning unit includes: The second capacitor in the first processing sub-circuit; The ninth transistor and the tenth transistor are arranged along the second direction; The first capacitor, the third capacitor, and the second capacitor are arranged sequentially along the first direction; and Along the first direction, the second capacitor is located on the side of the ninth transistor and the tenth transistor away from the first capacitor and the third capacitor.

13. The scanning circuit according to claim 1, further comprising a first voltage signal line and a second voltage signal line located in the first signal line layer; in, Along the first direction, the first voltage signal line and the second voltage signal line are located on opposite sides of the transistor and capacitor of each scanning unit; The first voltage signal line is electrically coupled to the first electrode of the fifth transistor in the third processing sub-circuit, the first electrode of the eighth transistor in the first processing sub-circuit, and the first electrode of the ninth transistor in the output sub-circuit; as well as The second voltage signal line is electrically coupled to the first electrode of the tenth transistor in the output sub-circuit.

14. The scanning circuit according to claim 1, wherein, The channel length of the active layer of the ninth transistor is less than or equal to 3.8 μm; The channel length of the active layer of the tenth transistor is less than or equal to 3.8 μm; The channel width of the active layer of the ninth transistor is greater than 180 μm; and The channel width of the active layer of the tenth transistor is greater than 180 μm.

15. The scanning circuit according to claim 1, wherein, The fourth overall structure includes the active layer of the fourth transistor in the third processing sub-circuit and the active layer of the fifth transistor in the third processing sub-circuit; and The ratio of the channel width of the active layer of the fourth transistor to the channel width of the active layer of the fifth transistor is in the range of 1.5:1 to 2.5:

1.

16. The scanning circuit according to claim 3, wherein, Each scanning unit further includes a fifth connection line located in the first signal line layer, the fifth connection line being electrically connected to the second electrode of the first transistor, the second electrode of the fourth transistor, and the fourth connection line; as well as The active layer of the first transistor, the fifth connection line, the active layer of the fourth transistor in the third processing sub-circuit, and the active layer of the fifth transistor in the third processing sub-circuit are collinear and arranged sequentially along the second direction.

17. The scanning circuit according to claim 1, wherein, The active layers of the first transistor and the third transistor in the input sub-circuit are parallel and extend along the second direction.

18. A display device comprising a scanning circuit according to any one of claims 1 to 17, and a display panel.

19. The display device according to claim 18, further comprising a second scanning circuit; in, The scanning circuit is configured to provide a first type of control signal; The second scanning circuit is configured to provide a second type of control signal; The scanning circuit and the second scanning circuit are arranged along the first direction; Along the first direction, the display device further includes a first voltage signal line and a second voltage signal line configured to provide a first voltage signal and a second voltage signal to the scanning circuit respectively, and a third voltage signal line and a fourth voltage signal line configured to provide the first voltage signal and the second voltage signal to the second scanning circuit respectively; Each scanning unit further includes a tenth connecting line, which connects the second capacitor electrode of the second capacitor in each scanning unit to the third voltage signal line. The tenth connecting line intersects with a plurality of signal lines extending along the second direction and configured to provide signals to the second scanning circuit; and The fifth overall structure includes the tenth connecting line and the second capacitor electrode of the second capacitor in each scanning unit.

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