single ended memory

Abstract

The application provides a single-end memory, relates to the technical field of storage, and can solve the problem of slow reading speed of the existing single-end memory. The single-end memory comprises array-distributed storage units, the storage units are connected with a reading bit line and a reading word line, the reading bit line is connected with a pre-charging unit through a column selection unit, the reading bit line is connected with an output end of a leakage current compensation unit through the column selection unit, the reading bit line is also connected with a control end of the leakage current compensation unit through a feedback circuit, and the feedback circuit outputs a feedback signal to the control end of the leakage current compensation unit to stop the leakage current compensation unit from charging the reading bit line through the output end when it is determined that the level of the reading bit line is lower than a first predetermined value.

Description

Technical Field

[0001] This application relates to the field of storage technology, and more particularly to a single-ended memory. Background Technology

[0002] Single-ended memory (SUM) is a common type of memory that consists of arrayed memory cells. In a single-ended memory, multiple cells in a row are connected to the same read bit line (RBL), and each cell in that row is also connected to a read word line (RWL). During a read operation, the read bit line RBL is initially set to a high level. When a cell is selected by the read word line RWL connected to any cell, the selected cell outputs stored information to the read bit line RBL. This stored information affects the level of the read bit line RBL, allowing the storage information of the selected cell to be determined based on the level changes on the read bit line RBL.

[0003] Reference Figure 1 The diagram shows a circuit structure diagram of a single-ended memory with a row of memory cells. The single-ended memory includes memory cell 1, memory cell 2, and memory cell 3. Memory cell 1 is also connected to read word line RWL1, memory cell 2 is also connected to read word line RWL2, and memory cell 3 is also connected to read word line RWL3. Read bit line RBL is also connected to power supply Vdd via a pre-charge unit. Figure 1 The pre-charge unit (taking transistor M11 as an example) is connected to the power supply Vdd via a leakage current compensation unit. Figure 1 (Taking transistor M12 as an example, the leakage current compensation unit is used in the middle).

[0004] When reading the stored information from memory cell 1, transistor M11 is first turned on. The read bit line RBL is connected to the power supply Vdd through transistor M11, and the power supply Vdd charges the read bit line RBL, causing RBL to go high. Subsequently, transistor M11 is turned off, and the read bit line RBL remains high. The read word line RWL1 selects memory cell 1, while memory cells 2 and 3 are not selected. Therefore, memory cell 1 outputs stored information to the read bit line RBL. If the stored information in memory cell 1 is high at this time, memory cell 1 outputs a high level to the read bit line RBL, and the read bit line RBL remains high. However, memory cells 2 and 3 will generate leakage current. The presence of this leakage current will lower the level of the read bit line RBL, and in severe cases, it will directly affect the accuracy of reading the stored information from memory cell 1. Therefore, the single-ended memory incorporates a leakage current compensation unit (i.e., transistor M12) in its circuit design. Transistor M12 is initially turned on, and the read bit line RBL is connected to the power supply Vdd through transistor M12. The power supply Vdd charges the read bit line RBL, causing the level of the read bit line RBL to rise, compensating for the decrease in the level of the read bit line RBL due to leakage current. Therefore, the read bit line RBL remains at a high level, and the high level of the read bit line RBL can accurately determine that the stored information of memory cell 1 is at a high level.

[0005] If the stored information in memory cell 1 is low, memory cell 1 outputs a low level to the read bit line RBL, causing the level of read bit line RBL to begin to decrease. However, transistor M12 does not turn off in time; it remains on, and read bit line RBL is still connected to the power supply Vdd through transistor M12. Power supply Vdd continues to charge read bit line RBL, causing its level to rise. This results in a slow decrease in the level of read bit line RBL. To accurately determine the stored information in memory cell 1, it is necessary to wait for the level of read bit line RBL to become low, thus slowing down the read speed of this single-ended memory. Summary of the Invention

[0006] The embodiments of this application provide a single-ended memory, relating to the field of storage technology, which can solve the problem of slow read speed of existing single-ended memories.

[0007] To achieve the above objectives, embodiments of this application provide the following technical solutions:

[0008] Firstly, a single-ended memory is provided, comprising arrayed memory cells connected to read bit lines and read word lines. The read bit lines are connected to a pre-charge unit via a column select unit, and also connected to the output of a leakage current compensation unit via the column select unit. The read bit lines are further connected to the control terminal of the leakage current compensation unit via a feedback circuit. When the feedback circuit determines that the level of the read bit line is lower than a first predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit to stop the leakage current compensation unit from charging the read bit line through its output terminal. In the aforementioned single-ended memory, when the column select unit selects a read bit line, the pre-charge unit charges the read bit line through the column select unit, and the read bit line remains at a high level. If a read word line selects a memory cell at this time, the memory cell outputs stored information to the read bit line. When the stored information is at a low level, the level of the read bit line also begins to decrease. After determining that the level of the read bit line is lower than a certain predetermined value, the feedback circuit outputs a feedback signal to the control terminal of the leakage current compensation unit, which stops the leakage current compensation unit from charging the read bit line through its output terminal. Since the leakage current compensation unit of the single-ended memory is controlled by the feedback signal output by the feedback circuit, and the feedback signal output by the feedback circuit changes in a timely manner according to the level change of the read bit line, the leakage current compensation unit can be turned off more promptly. Because the leakage current compensation unit stops charging the read bit line in time, the level of the read bit line can decrease more quickly when the stored information is at a low level. This allows the single-ended memory to read the stored information on the read bit line more quickly, thus increasing the read speed of the single-ended memory.

[0009] Optionally, when the feedback circuit determines that the level of the read bit line is higher than the second predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit to control the leakage current compensation unit to charge the read bit line through its output terminal, wherein the first predetermined value is less than or equal to the second predetermined value. In this scheme, when the stored information of the selected memory cell is high, the read bit line will remain high. When the feedback circuit determines that the level of the read bit line is higher than the second predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit. This feedback signal can control the leakage current compensation unit to charge the read bit line through its output terminal, compensating for the leakage current generated by other memory cells on the read bit line. Since the feedback signal output by the feedback circuit can also control the leakage current compensation unit to turn on in a timely manner, the read performance of the single-ended memory when the stored information is read at a high level can also be guaranteed.

[0010] Optionally, the feedback circuit includes an inverter. The input of the inverter is connected to the read line, and the output of the inverter is connected to the control terminal of the leakage current compensation unit. The inverter is used to generate a feedback signal based on the level of the read line.

[0011] Optionally, embodiments of this application also provide a specific structure for an inverter. The inverter includes a first transistor and a second transistor. A first terminal of the first transistor is connected to a power supply, a second terminal of the first transistor is connected to the first terminal of the second transistor, and a second terminal of the second transistor is connected to ground. The control terminals of the first and second transistors are connected to the input terminal of the inverter, and the second terminal of the first transistor is also connected to the output terminal of the inverter. Furthermore, the first and second transistors are of different types.

[0012] Optionally, embodiments of this application also provide another specific structure for an inverter, comprising: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; the first terminal of the third transistor is connected to a power supply, the second terminal of the third transistor is connected to the first terminal of the fourth transistor, and the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor; the second terminal of the fifth transistor is connected to ground; the first terminal of the sixth transistor is connected to the second terminal of the fourth transistor, the control terminal of the sixth transistor is connected to the second terminal of the third transistor, and the second terminal of the sixth transistor is connected to a power supply; the control terminals of the third transistor, the fourth transistor, and the fifth transistor are connected to the input terminal of the inverter; the second terminal of the third transistor is also connected to the output terminal of the inverter; the fourth, fifth, and sixth transistors are of the same type, while the third and fourth transistors are of different types.

[0013] Optionally, the feedback circuit described above can also generate a feedback signal based on the level of the read bit line by setting a logic gate circuit. This feedback circuit would then include: a first NOR gate and a first NOT gate. The input of the first NOT gate is connected to the control terminal of the column selection unit, the output of the first NOT gate is connected to the first input of the first NOR gate, the second input of the first NOR gate is connected to the read bit line, and the output of the first NOR gate is connected to the control terminal of the leakage current compensation unit.

[0014] Optionally, after the precharge unit charges the read bit line through the column selection unit, if the read word line selects the memory unit, the memory unit outputs the storage information to the read bit line.

[0015] Optionally, the feedback circuit is connected to the transmission path between the storage unit and the column selection unit.

[0016] Optionally, the single-ended memory further includes: a first switching unit, through which the leakage current compensation unit is connected to the read bit line, and the control terminal of the first switching unit is connected to the control terminal of the column selection unit. In this scheme, it is ensured that when the column selection unit is activated by a signal from its control terminal to select a read bit line, the first switching unit can be simultaneously activated to connect the leakage current compensation unit to the read bit line. This allows the leakage current compensation unit to promptly compensate for or stop compensating the level of the read bit line when it is selected, achieving adaptive operation of the leakage current compensation unit in response to the selection of the read bit line.

[0017] Optionally, to enable faster reading of stored information from the single-ended memory when it reaches a low level, the single-ended memory further includes a discharge unit. The control terminal of the discharge unit is connected to the control terminal of the leakage current compensation unit. The first terminal of the discharge unit is connected to the read bit line via a column selection unit, and the second terminal of the discharge unit is connected to ground. In this scheme, when the stored information is at a low level, after receiving a feedback signal, the discharge unit can connect the read bit line to ground via the column selection unit and the discharge unit, thereby accelerating the reduction of the read bit line's level and ensuring that the read bit line's level drops to a low level as quickly as possible, thus improving the reading speed of the single-ended memory.

[0018] Optionally, the discharge unit may include a seventh transistor and an eighth transistor; the control terminal of the seventh transistor is connected to the control terminal of the leakage current compensation unit, and the first terminal of the seventh transistor is connected to the read bit line through the column selection unit; the second terminal of the seventh transistor is connected to the control terminal of the eighth transistor, and the second terminal of the seventh transistor is also connected to the first terminal of the eighth transistor, and the second terminal of the eighth transistor is connected to ground. In this scheme, the connection method of the seventh and eighth transistors will make the equivalent resistance of the current discharge unit higher, so the discharge speed of the discharge unit will be slower. If the level of the current read bit line is reduced due to the presence of leakage current, the discharge unit configured in this way will not directly connect the read bit line to ground, causing the problem of reading stored information errors, thus making the read performance of the single-ended memory more stable.

[0019] Optionally, the discharge unit may further include a ninth transistor. The control terminal of the leakage current compensation unit is connected to the control terminal of the ninth transistor via a second NOT gate. The first terminal of the ninth transistor is connected to the read bit line via a column select unit; the second terminal of the ninth transistor is connected to ground. In this scheme, the ninth transistor is a P-type transistor. P-type transistors experience threshold loss when transmitting voltage levels, which slows down the discharge speed of the discharge unit.

[0020] Optionally, a second switching unit is further provided between the first end of the discharge unit and the column selection unit. In this scheme, the presence of the second switching unit is to control the discharge unit to adaptively operate or not operate as needed.

[0021] Optionally, the single-ended memory further includes a second NOR gate and a third NOT gate. The input of the third NOT gate is connected to the control terminal of the column selection unit, and the output of the third NOT gate is connected to the first input of the second NOR gate; the second input of the second NOR gate is connected to the read bit line; and the output of the second NOR gate is connected to the control terminal of the discharge unit. Attached Figure Description

[0022] Figure 1 A schematic diagram of the structure of a single-ended memory provided for the prior art;

[0023] Figure 2 A schematic diagram of the structure of a single-ended memory provided in Embodiment 1 of this application;

[0024] Figure 3 for Figure 2 A typical structural diagram of a storage unit in a computer.

[0025] Figure 4 Schematic diagram of current flow of the single-ended memory provided in Embodiment 2 of this application Figure 1 ;

[0026] Figure 5 Schematic diagram of current flow of the single-ended memory provided in Embodiment 2 of this application Figure 2 ;

[0027] Figure 6 A schematic diagram of the structure of a single-ended memory provided in Embodiment 3 of this application;

[0028] Figure 7 A schematic diagram of the structure of a single-ended memory provided in Embodiment 4 of this application;

[0029] Figure 8 A schematic diagram of the structure of a single-ended memory provided in Embodiment 5 of this application;

[0030] Figure 9 A schematic diagram of the structure of a single-ended memory provided in Embodiment Six of this application;

[0031] Figure 10 A schematic diagram of the structure of a single-ended memory provided in Embodiment 7 of this application;

[0032] Figure 11 A schematic diagram of the structure of a single-ended memory provided in Embodiment 8 of this application;

[0033] Figure 12 A schematic diagram of the structure of a single-ended memory provided in Embodiment 9 of this application;

[0034] Figure 13 A schematic diagram of the structure of a single-ended memory provided in Embodiment 10 of this application;

[0035] Figure 14 A schematic diagram of the structure of a single-ended memory provided in Embodiment Eleven of this application;

[0036] Figure 15 A schematic diagram of the structure of a single-ended memory provided in Embodiment Twelve of this application;

[0037] Figure 16 Performance simulation of single-ended memory provided for embodiments of this application Figure 1 ;

[0038] Figure 17 Performance simulation of single-ended memory provided for embodiments of this application Figure 2 . Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0040] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to those skilled in the art. In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, in the embodiments of this application, the words "first," "second," etc., do not limit the quantity or order.

[0041] Furthermore, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0042] It should be noted that, in this application, the terms "exemplary" or "for example" are used to indicate that something is being described as an example, illustration, or illustration. Any embodiment or design described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0043] The technical terms used in the embodiments of this application are explained below:

[0044] In the embodiments of this application, the transistor can be a metal-oxide-semiconductor field-effect transistor (MOSFET). Transistors are classified into two types: N-type (negative) transistors and P-type (positive) transistors. A transistor includes a source, a drain, and a gate. The transistor can be turned on or off by controlling the level of the input gate. When the transistor is on, the source and drain conduct, generating an on-state current. When the transistor is off, although the source and drain do not conduct, a small leakage current is generated between them due to the transistor's structural characteristics. In the embodiments of this application, the transistor's gate is also referred to as the control terminal, the source as the first terminal, and the drain as the second terminal; or, the gate is referred to as the control terminal, the drain as the first terminal, and the source as the second terminal. Furthermore, an N-type transistor turns on when the control terminal is high, with both terminals conducting and generating an on-state current between them. When the control terminal is low, the N-type transistor turns off, with neither terminal conducting and a leakage current existing between them. Similarly, a P-type transistor turns on when the control terminal is low, with both terminals conducting and generating an on-state current. When the control terminal is high, the P-type transistor turns off, with neither terminal conducting and a leakage current existing.

[0045] In the embodiments of this application, a high level indicates that the data stored in the memory cell is "1" (also referred to as logic "1"); a low level indicates that the data stored in the memory cell is "0" (also referred to as logic "0"). Additionally, a high level also indicates that the current voltage is higher than a predetermined value; a low level also indicates that the current voltage is lower than a predetermined value (the predetermined value can change according to circuit variations). Furthermore, a high level signal indicates that the current signal is logic high (sometimes referred to as HIGH); a low level signal indicates that the current signal is logic low (sometimes referred to as LOW).

[0046] Reference Figure 2 As shown in the figure, the embodiments of this application provide a schematic diagram of a single-ended memory structure. The single-ended memory includes a memory array 20, an input / output (I / O) circuit 21, a reference circuit 22, and a decoder 23, which are respectively coupled to the memory array 20, and a control logic circuit 24 coupled to the input / output circuit 21 and the decoder 23.

[0047] Reference Figure 2As shown, the memory array 20 includes multiple memory cells arranged in an array within the memory array 20, and each memory cell includes multiple transistors. Figure 2 As shown, storage cells 201 and 202 are arranged in row a, and storage cells 203 and 204 are arranged in row b; storage cells 201 and 203 are arranged in column A, and storage cells 202 and 204 are arranged in column B. Each storage cell is used to store one bit of data, i.e., data "1" or data "0". When the data stored in the storage cell is "1", it can also be said that the stored information of the storage cell is high level (in the following embodiments of this application, the stored information of the storage cell is high level to represent the data stored in the storage cell is "1"). When the data stored in the storage cell is "0", it can also be said that the stored information of the storage cell is low level (in the following embodiments of this application, the stored information of the storage cell is low level to represent the data stored in the storage cell is "0"). In addition, the memory array 20 includes multiple bit lines (BLs) (which can be read bit lines (RBLs) or write bit lines (WBLs)) and / or bit barlines (which can be write bit barlines (WBBLs)) arranged along corresponding columns, and multiple word lines (WLs) (which can be read word lines (RWLs) or write word lines (WWLs) arranged along corresponding rows. For clarity, Figure 2 Each column in the table shows only one read line, such as Figure 2 The read lines RBL-A in column A and RBL-B in column B are shown.

[0048] Input / output circuit 21 includes multiple sense amplifiers (SA) (such as...) Figure 2 The sensitive amplifiers SA-A and SA-B shown are illustrated. The reference circuit (RC) 22 includes multiple sub-reference circuits (such as...). Figure 2 The sub-reference circuits RC-A and RC-B are shown. Each column of memory cells in the memory array 20 described above is coupled to the corresponding sensitive amplifier and sub-reference circuit via a read line RBL. Figure 2As shown, memory cells 201 and 203 in column A are coupled to sensitive amplifier SA-A and sub-reference circuit RC-A via read line RBL-A; memory cells 202 and 204 in column B are coupled to sensitive amplifier SA-B and sub-reference circuit RC-B via read line RBL-B. For example, when a corresponding column is added to the memory array 20, the input / output circuit 21 adds a sensitive amplifier corresponding to the column in the memory array 20, and the reference circuit 22 adds a sub-reference circuit corresponding to the column in the memory array 20.

[0049] The decoder 23 coupled to the memory array 20 can be used to receive address information (e.g., row address) provided by the control logic circuit 24 to assert one or more word lines of the memory array 20. Furthermore, the control logic circuit 24 can be coupled to the input / output circuit 21 to retrieve data read by a sensitive amplifier (e.g., sensitive amplifier SA-A, sensitive amplifier SA-B, etc.) during a read operation.

[0050] in, Figure 2 The single-ended memory shown may also include other memory arrays and / or one or more other functional circuits (such as buffer circuits, timing circuits, etc.), and each memory array may include more or fewer memory cells.

[0051] Reference Figure 3 The illustration shows an embodiment of this application. Figure 2 A typical structural diagram of the storage cell 201 is shown below. The storage cell 201 includes eight transistors (the storage cell composed of these eight transistors is also called an eight-transistor static random access memory cell). The eight transistors are transistor M1, transistor M2, transistor M3, transistor M4, transistor M5, transistor M6, transistor M7, and transistor M8. Figure 3 As shown, transistors M1 and M3 are P-type transistors, while the other transistors are N-type transistors. Furthermore, the memory cell 201 also includes a write word line WWL, a write bit line WBL, a write bit bar line WBBL, a read bit line RBL-A, and a read word line RWL.

[0052] like Figure 3As shown, the first terminal of transistor M1 is connected to the power supply Vdd, the second terminal of transistor M1 is connected to the first terminal of transistor M2, and the second terminal of transistor M2 is connected to ground GND. The first terminal of transistor M3 is connected to the power supply Vdd, the second terminal of transistor M3 is connected to the first terminal of transistor M4, the second terminal of transistor M4 is connected to ground GND, and the second terminal of transistor M3 is also connected to the control terminal of transistor M1, which in turn is connected to the control terminal of transistor M2. The write bit line WBL is connected to the first terminal of transistor M5, the second terminal of transistor M5 is connected to the second terminal of transistor M1, and the second terminal of transistor M5 is also connected to the control terminal of transistor M3, which in turn is connected to the control terminal of transistor M4. The write word line WWL is connected to the control terminal of transistor M5, and the write word line WWL is also connected to the control terminal of transistor M6. The first terminal of transistor M6 is connected to the second terminal of transistor M3, and the second terminal of transistor M6 is connected to the write bit bar line WBBL. Specifically, the second terminal of transistor M3 is also connected to the control terminal of transistor M7, the second terminal of transistor M7 is connected to ground, the first terminal of transistor M7 is connected to the first terminal of transistor M8, the second terminal of transistor M8 is connected to the read bit line RBL-A, and the control terminal of transistor M8 is connected to the read word line RWL. The second terminal of transistor M1 is also coupled to the first node 2011 of the memory cell 201, and the second terminal of transistor M3 is also coupled to the second node 2012 of the memory cell 201.

[0053] Transistors M1-M6 constitute the core of memory cell 201, which is mainly used to perform write operations (i.e., the core includes a write interface). Transistors M1 and M2 are connected to form a first inverter, while transistors M3 and M4 are connected to form a second inverter. The first and second inverters are cross-coupled with each other (e.g., ...). Figure 3(As shown). More specifically, the first inverter and the second inverter are each coupled between the power supply Vdd and ground GND. Furthermore, the first inverter is coupled to transistor M5, and the second inverter is coupled to transistor M6. Transistors M5 and M6 are also coupled to the write word line WWL of the memory cell; transistor M5 is also coupled to the write bit line WBL, and transistor M6 is also coupled to the write bit bar line WBBL. The switching on and off of transistors M5 and M6 is controlled by the write word line WWL. The core of memory cell 201 makes its storage function more stable. Transistors M7 and M8 constitute the read buffer of memory cell 201, which is mainly used to perform read operations (i.e., the read buffer provides a read interface). The read word line RWL controls the switching on or off of transistor M8. A high level on the read word line RWL indicates that the current memory cell 201 is selected for information output, and a low level on the read word line RWL indicates that the current memory cell 201 is not selected. The storage information control transistor M7 of storage cell 201 is turned on or off. When the storage information of storage cell 201 is high, the high-level storage information control transistor M7 is turned off, and when the storage information of storage cell 201 is low, the low-level storage information control transistor M7 is turned on.

[0054] The following is combined with Figure 2 The single-ended memory shown and Figure 3 The process of writing storage information into storage unit 201 and reading storage information from storage unit 201 using the storage unit shown is explained.

[0055] When writing storage information into storage unit 201, refer to Figure 2 As shown, firstly, the input / output circuit 21 receives the current write command. The input / output circuit 21 obtains the address information (e.g., row address) of the memory cell corresponding to the memory cell in the write command through the control logic circuit 24. Then, the decoder 23 sets (asserts) one or more word lines of the memory cell in the memory array 20 corresponding to the memory cell in the memory array 20. (Refer to...) Figure 3As shown, when the write word line WWL is set to a high level, transistors M5 and M6 are turned on. The write bit line WBL transmits the corresponding low / high level storage information to the memory cell 201. At the same time, the bit bar line WBBL receives the inverse signal of the storage information (for example, when the storage information received by WBL is high, the bit bar line receives a low level; when the storage information received by WBL is low, the bit bar line receives a high level). Assuming that the storage information transmitted by the current write bit line WBL is low, transistors M3 and M2 in the corresponding memory cell 201 are turned on, transistors M1 and M4 are turned off, the first node 2011 in the memory cell 201 is low, and the second node 2012 is high. The low level storage information transmitted by the write bit line WBL is accurately written into the core of the memory cell 201. Assuming the current write bit line WBL transmits a high-level storage information, transistors M3 and M2 in the corresponding storage cell 201 are turned off, while transistors M1 and M4 are turned on. The first node 2011 within storage cell 201 is at a high level, and the second node 2012 is at a low level. The high-level storage information transmitted by the write bit line WBL is accurately written into the core of storage cell 201. In other words, a high level at the first node 2011 and a low level at the second node 2012 in storage cell 201 indicates that the current storage information in storage cell 201 is high; conversely, a low level at the first node 2011 and a high level at the second node 2012 indicate that the storage information in storage cell 201 is low.

[0056] When reading the stored information of storage unit 201, refer to Figure 2 As shown, firstly, the input / output circuit 21 receives the current read instruction. The input / output circuit 21 obtains the address information (e.g., row address) of the memory cell corresponding to the memory information to be read from the read instruction through the control logic circuit 24. Then, the decoder 23 sets one or more word lines of the memory cell corresponding to the memory information to be read in the memory array 20, and also sets the read bit line to a high level. (Refer to...) Figure 3As shown, this means setting the read word line RWL and the read bit line RBL-A to a high level. Setting the read word line RWL to a high level selects memory cell 201, turning on transistor M8 in memory cell 201. At this time, a current I1 is formed between transistor M8 and read bit line RBL-A. Assuming the stored information in memory cell 201 is currently high, then the first node 2011 within memory cell 201 is high, the second node 2012 is low, transistor M7 is off, and read bit line RBL-A will not connect to ground GND through transistors M7 and M8. Therefore, no current I2 will flow through transistors M7 and M8, and memory cell 201 outputs a high level to read bit line RBL-A, maintaining the initial high level of read bit line RBL-A. (Refer to...) Figure 2 The input / output circuit 21 receives the level of the read bit line RBL-A and the level of the sub-reference circuit RC-A, determines that the level of the read bit line RBL-A is greater than the level of the sub-reference circuit RC-A, and therefore determines that the information stored in the storage unit 201 is at a high level. (Refer to...) Figure 3 Assuming the stored information in memory cell 201 is currently at a low level, then the first node 2011 within memory cell 201 is at a low level, the second node 2012 is at a high level, transistor M7 is turned on, and the read bit line RBL-A is connected to ground GND through transistors M7 and M8, generating a current I2 flowing through transistors M7 and M8. Therefore, memory cell 201 outputs a low level to read bit line RBL-A, and the level of read bit line RBL-A begins to decrease. (Refer to...) Figure 2 The input / output current 21 receives the level of the read bit line RBL-A and the level of the sub-reference circuit RC-A. If it determines that the level of the read bit line RBL-A is less than the level of the sub-reference circuit RC-A, it determines that the stored information in the storage unit 201 is at a low level at this time.

[0057] It should be noted that, depending on the actual needs of the single-ended memory, reference circuit 21 may or may not be provided. When reference circuit 21 is not provided, input / output circuit 22 only receives the level on the read bit line and determines whether the stored information of the current memory cell is high or low based on the level on the read bit line.

[0058] When reading the stored information of a selected memory cell in the aforementioned single-ended memory, the selected memory cell outputs the stored information to the read bit line, which affects the level of the read bit line. At this time, other memory cells in the same column as the selected memory cell will generate leakage current, which will also affect the level of the read bit line, causing abnormal changes in the level of the read bit line. For this reason, most single-ended memories are equipped with leakage current compensation units.

[0059] For details, please refer to Figure 4As shown in the diagram, an embodiment of this application provides a schematic diagram of a single-ended memory. This single-ended memory includes a read bit line RBL-1 and other read bit lines RBL-n. Each read bit line includes multiple memory cells. Taking read bit line RBL-1 as an example, read bit line RBL-1 is connected to three memory cells (memory cell c1, memory cell c2, and memory cell c3). The stored information in these three memory cells can be read through read bit line RBL-1. Memory cell c1 is also connected to read word line RWL-1, memory cell c2 is also connected to read word line RWL-2, and memory cell c3 is also connected to read word line RWL-3. Read bit line RBL-1 is also connected to a power supply Vdd via a pre-charge unit. Figure 4 Taking transistor M41 as an example, the first terminal of transistor M41 is connected to the power supply Vdd, and the second terminal of transistor M41 is connected to the read line RBL-1. The read line RBL-1 is connected to the power supply Vdd through a leakage current compensation unit. Figure 4 Taking transistor M42 as an example, the leakage current compensation unit has its first terminal connected to the power supply Vdd and its second terminal connected to the read bit line RBL-1. The read bit line RBL-1 is coupled to the first input terminal of NAND gate 401. The memory cells in other columns are coupled to the second input terminal of NAND gate 401 via other read bit lines RBL-n. The output terminal of NAND gate 401 is coupled to the control terminal of transistor M45. The first terminal of transistor M45 is connected to ground GND, and its second terminal is connected to the global bit line (GBL). The output terminal of NAND gate 401 is also coupled to the control terminal of transistor M42. Here, transistors M41 and M42 are P-type transistors, and transistor M45 is an N-type transistor.

[0060] in addition, Figure 4 The structure of the three memory cells in the single-ended memory shown can be referred to Figure 3 The schematic diagram of the storage unit 201 shown is as follows: Figure 4 The core cc within the storage unit is equivalent to Figure 3 The transistors M1-M6 in the memory cell 201 are used to store information and perform write operations. Figure 4 The transistor M44 in the middle is equivalent to Figure 3 In the storage cell 201, transistor M7 is used. The core cc in each storage cell is coupled to transistor M44. When the stored information stored in the core cc of the storage cell is high, transistor M44 is turned off. When the stored information stored in the core cc of the storage cell is low, transistor M44 is turned on. Figure 4 The transistor M43 in the memory cell is equivalent to Figure 3In the memory cell 201, transistor M8 is controlled by a high level read word line RWL to turn on transistor M43 in the memory cell, and a low level read word line RWL controls transistor M43 in the memory cell to turn off.

[0061] Reference Figure 4 As shown, when this single-ended memory reads stored information, firstly, the precharge signal S1 switches from high level to low level, thereby controlling the control terminal level of transistor M41 to low level, transistor M41 is turned on, the power supply Vdd is connected to the read bit line RBL-1, the power supply Vdd charges the read bit line RBL-1, making the level of the read bit line RBL-1 high level. Then, the precharge signal S1 changes from low level to high level, controlling the control terminal level of transistor M41 to high level, transistor M41 is turned off, the power supply Vdd stops charging the read bit line RBL-1, and the read bit line RBL-1 remains at a high level. In this configuration, the other read bit lines RBL-n connected to the memory cells of other columns are connected to the power supply Vdd via switch 1, and the global bit line GBL is also connected to the power supply Vdd via switch 2. When the precharge signal S1 switches from high to low to control the level of read bit line RBL-1 to high, switches 1 and 2 are also turned on, so that the other read bit lines RBL-n and the global bit line GBL are connected to the power supply Vdd. Therefore, the other read bit lines RBL-n and the global bit line GBL are also set to high. And because the transistor M45 is turned off (because the high level on read bit line RBL-1 and other read bit lines RBL-n is NAND gate 401, which outputs a low level and controls M45 to turn off), the global bit line GBL remains at a high level.

[0062] Taking the reading of stored information from memory cell c1 as an example, the reading process of this single-ended memory is explained. When the read word line RWL-1 connected to memory cell c1 is high, the control terminal of transistor M43 is at a high level, selecting memory cell c1, and memory cell c1 outputs stored information to read bit line RBL-1. When the read word line RWL-2 connected to memory cell c2 is low, the control terminal of transistor M43 is at a low level, and memory cell c2 is not selected. When the read word line RWL-3 connected to memory cell c3 is low, the control terminal of transistor M43 is at a low level, and memory cell c3 is not selected.

[0063] Reference Figure 4As shown, if the stored information in the storage cell c1 is high, the transistor M44 controlled by the stored information in the storage cell c1 will be turned off. The read bit line RBL-1 will not be connected to ground GND because of the transistors M43 and M44 in the storage cell c1. The level of the read bit line RBL-1 will remain high, which is equivalent to the storage cell c1 outputting a high level to the read bit line RBL-1. Since other read lines RBL-n are set to high level, the high levels on read line RBL-1 and other read lines RBL-n are ANDed by NAND gate 401, resulting in a low level output. This low level is transmitted to the control terminal of the leakage current compensation unit (i.e., transistor M42), causing transistor M42 to turn on. Read line RBL-1 is connected to power supply Vdd through transistor M42, and power supply Vdd charges read line RBL-1. The output of NAND gate 401 is also low, controlling transistor M45 to turn off. The global bit line GBL is not connected to ground through transistor M45. Therefore, the input / output circuit coupled to the global bit line GBL can determine that the level of the global bit line GBL is high, and can also determine that the stored information in the currently selected memory cell c1 is high. Although transistors M43 and M44 in memory cell c2 will generate leakage current, i.e., ... Figure 4 The read line RBL-1 is connected to ground GND through transistors M43 and M44 in memory cell c2. Memory cell c2 generates a leakage current Ic2 flowing through transistors M43 and M44. Read line RBL-1 is also connected to ground GND through transistors M43 and M44 in memory cell c3. Memory cell c3 generates a leakage current Ic3 flowing through transistors M43 and M44. The leakage currents Ic2 and Ic3 cause the level of read line RBL-1 to decrease. However, because the single-ended memory has a leakage current compensation unit (i.e., transistor M42), when transistor M42 is turned on, read line RBL-1 is connected to the power supply Vdd through transistor M42, increasing the level of read line RBL-1 and compensating for the decrease in level caused by the leakage currents Ic2 and Ic3.

[0064] Reference Figure 5As shown, if the stored information in memory cell c1 is low, the transistor M44 controlling the stored information in memory cell c1 is turned on. The read bit line RBL-1 is connected to ground (GND) because of the turn-on of transistors M43 and M44 in memory cell c1. An on-state current Ic1 is generated in memory cell c1 flowing through transistors M43 and M44. Therefore, memory cell c1 outputs a low level to read bit line RBL-1, and the level of read bit line RBL-1 begins to decrease. When the level of read bit line RBL-1 decreases to low, NAND gate 401 performs a NAND operation on the levels of read bit line RBL-1 and other read bit lines RBL-n, outputting a high level to transistor M45. Transistor M45 is turned on, and the global bit line GBL is connected to ground (GND) through transistor M45. The level of global bit line GBL begins to decrease. As the level of global bit line GBL gradually decreases to low, the input / output circuit coupled to this global bit line GBL can determine that the stored information in memory cell c1 is low. Simultaneously, when the NAND gate 401 outputs a high level, the control terminal of transistor M42 also receives a high level, turning off transistor M42 and stopping the power supply Vdd from charging read line RBL-1. However, during the period from when the level of read line RBL-1 begins to decrease until it decreases to a low level, transistor M42 remains on, and the power supply Vdd continues to charge read line RBL-1. This affects the rate at which the level of read line RBL-1 decreases, resulting in a slower read speed for this single-ended memory.

[0065] It should be noted that the single-ended memory may also include leakage current compensation units, precharge units, and NAND gates corresponding one-to-one with other read bits RBL-n. When reading the stored information in the memory cell connected to a read bit line, the leakage current compensation unit, precharge unit, and NAND gate corresponding to that read bit line are activated. Alternatively, the single-ended memory may also include leakage current compensation units and precharge units corresponding one-to-one with other read bits RBL-n. The control terminal of each leakage current compensation unit is connected to the output terminal of NAND gate 401 through a switch. When reading the stored information in the memory cell connected to a read bit line, the switch connected to the leakage current compensation unit corresponding to that read bit line is turned on, and the leakage current compensation unit corresponding to that read bit line is activated.

[0066] To address the slow read speed of single-ended memory, embodiments of this application provide a single-ended memory that can be applied to... Figure 2 In the memory array 20 shown. (Refer to...) Figure 6 As shown, Figure 6This is a schematic diagram of the structure of a single-ended memory provided in an embodiment of the present application. The single-ended memory includes arrayed memory cells 601, which are connected to read bit lines RBL-1 and read word lines; the read bit lines RBL-1 are connected to column selection units ( Figure 6 The column selection unit (taking transistor M61 as an example) is connected to the precharge unit ( Figure 6 The pre-charge unit in the example uses transistor M62; the read bit line RBL-1 is connected to the leakage current compensation unit through the column select unit. Figure 6 The output terminal of the leakage current compensation unit (taking transistor M63 as an example); the read line RBL-1 is also connected to the control terminal of the leakage current compensation unit through the feedback circuit 602; when the feedback circuit 602 determines that the level of the read line is lower than the first predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit to stop the leakage current compensation unit from charging the read line RBL-1 through the output terminal.

[0067] In one example, refer to Figure 6 As shown, the column selection unit of this single-ended memory includes transistor M61, the precharge unit includes transistor M62, and the leakage current compensation unit includes transistor M63. The read bit line RBL-1 is connected to the memory cell 601. The power supply Vdd is connected to the first terminal of transistor M62, the second terminal of transistor M62 is connected to the second terminal of transistor M61, and the first terminal of transistor M61 is connected to the read bit line RBL-1. The read bit line RBL-1 is connected to the control terminal of transistor M63 through a feedback circuit 602, which is connected to the transmission path between the memory cell 601 and transistor M61. The first terminal of transistor M63 is connected to the power supply Vdd, and the second terminal of transistor M63 is connected to the second terminal of transistor M61. The read bit line RBL-1 is also connected to the first input terminal of the NAND gate 603. The storage cells of other columns are connected to the second input terminal of the NAND gate 603 through other read bit lines RBL-n. The output terminal of the NAND gate 603 is connected to the control terminal of the transistor M64. The first terminal of the transistor M64 is connected to ground GND, and the second terminal of the transistor M64 is connected to the global bit line GBL.

[0068] It should be noted that the column selection unit, precharge unit, and leakage current compensation unit mentioned above may also contain more or fewer other electronic components, and their connection relationships may be simpler or more complex. The read bit line RBL-1 may also connect to more memory cells.

[0069] Reference Figure 6As shown, when this single-ended memory reads the stored information from memory cell 601, since memory cell 601 is connected to read bit line RBL-1, the column selection signal S2 needs to be changed from low to high to turn on transistor M61, indicating that read bit line RBL-1 is selected. Then, the precharge signal S3 changes from high to low to turn on transistor M62. Read bit line RBL-1 is connected to power supply Vdd through transistors M61 and M62. Power supply Vdd charges read bit line RBL-1, making read bit line RBL-1 high. Subsequently, the precharge signal S3 changes from low to high to turn off transistor M62, power supply Vdd stops charging read bit line RBL-1, and read bit line RBL-1 remains high. Meanwhile, other read bit lines RBL-n connected to memory cells in other columns will be set to high, and the global bit line GBL will also be pre-set to high (see details). Figure 4 The steps shown are: the other read bit lines RBL-n and the global bit line GBL are set to high level), and because transistor M64 is turned off (because the high level on read bit line RBL-1 and the other read bit line RBL-n is NAND gate 603 NAND operation to output a low level, controlling M64 to turn off), the global bit line GBL remains high.

[0070] Next, the read word line selects the storage unit 601, and the storage unit 601 outputs the storage information to the read bit line RBL-1.

[0071] When the stored information in storage cell 601 is at a low level (for example, refer to...), Figure 5As shown, when transistor M44 in memory cell c1 is turned on, and memory cell c1 outputs a low level to read line RBL-1 (memory cell 601 is the same as memory cell c1), the level of read line RBL-1 will start to drop. At this time, after the feedback circuit 602 determines that the level of read line RBL-1 has dropped to a first predetermined value, it outputs a feedback signal S4 to the control terminal of transistor M63 to control transistor M63 to turn off (for example, when transistor M63 is a P-type transistor, the feedback signal S4 is high; when transistor M63 is an N-type transistor, the feedback signal S4 is low). Transistor M63 disconnects read line RBL-1 from power supply Vdd, power supply Vdd stops charging read line RBL-1, and the level of read line RBL-1 will drop to a low level. The level of read bit line RBL-1 is low, while the other read bit lines RBL-n remain high. After NAND processing by NAND gate 603, the output of NAND gate 603 outputs a high level, thereby controlling transistor M64 to turn on. The global bit line GBL is connected to ground GND through transistor M64. The level of global bit line GBL will gradually decrease to a low level. The input / output circuit coupled to the global bit line GBL can determine that the level of global bit line GBL is low, and can also determine that the stored information in the currently selected memory cell 601 is low.

[0072] In the aforementioned single-ended memory, when the column selection unit selects a read bit line, the pre-charge unit charges the read bit line through the column selection unit, keeping the read bit line at a high level. If the read word line selects a memory cell at this time, that memory cell outputs stored information to the read bit line. When the stored information is at a low level, the level of the read bit line also begins to decrease. After determining that the level of the read bit line is lower than a predetermined value, the feedback circuit outputs a feedback signal to the control terminal of the leakage current compensation unit. This feedback signal can stop the leakage current compensation unit from charging the read bit line through its output terminal. Since the leakage current compensation unit of the single-ended memory is controlled by the feedback signal output by the feedback circuit, and the feedback signal output by the feedback circuit changes in a timely manner according to the level change of the read bit line, the leakage current compensation unit can be turned off more promptly. Because the current compensation unit stops charging the read bit line in a timely manner, the level of the read bit line can decrease more quickly under the influence of the stored information being at a low level. This allows the single-ended memory to read the stored information on the read bit line more quickly, thus increasing the read speed of the single-ended memory.

[0073] Still refer to Figure 6 As shown, when the stored information in storage cell 601 is at a high level (for example, refer to...), Figure 4As shown, when transistor M44 in memory cell c1 is off, and memory cell c1 outputs a high level to read line RBL-1 (memory cell 601 is the same as memory cell c1), read line RBL-1 remains high. However, other unselected memory cells connected to read line RBL-1 will experience leakage current. At this time, feedback circuit 602 connected to read line RBL-1, upon determining that the level of read line RBL-1 is higher than a second predetermined value, outputs feedback signal S4 to the control terminal of transistor M63, controlling transistor M63 to turn on (for example, when transistor M63 is a P-type transistor, feedback signal S4 is low; when transistor M63 is an N-type transistor, feedback signal S4 is high). Read line RBL-1 is connected to power supply Vdd through transistors M63 and M61. Power supply Vdd charges read line RBL-1, compensating for the leakage current generated by the unselected memory cells on read line RBL-1, thus keeping read line RBL-1 high. Since the other read bit lines RBL-n remain high, after NAND processing by NAND gate 603, the output of NAND gate 603 outputs a low level, thereby controlling transistor M64 to turn off. The global bit line GBL will not be connected to ground GND through transistor M64, and the level of the global bit line GBL remains at the initial high level. The input / output circuit coupled to the global bit line GBL can determine that the level of the global bit line GBL is high, and can also determine that the stored information in the currently selected memory cell 601 is high.

[0074] Specifically, the first predetermined value is less than or equal to the second predetermined value. The first predetermined value must also be greater than a low level. Only when the first predetermined value is greater than a low level can the feedback circuit 602 output a feedback signal to the transistor M63 before the level of the read line RBL-1 drops to a low level, thus stopping the power supply Vdd from charging the read line RBL-1 through the transistor M63. The second predetermined value must also be less than a high level. Only when the second predetermined value is less than a high level can the feedback circuit 602 output a feedback signal to the transistor M63 when the level of the read line RBL-1 drops due to leakage current, thus controlling the power supply Vdd to charge the read line RBL-1 through the transistor M63.

[0075] In the aforementioned single-ended memory, when the stored information of the selected memory cell is high, the read bit line remains high. When the feedback circuit determines that the level of the read bit line is higher than a second predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit. This feedback signal controls the leakage current compensation unit to charge the read bit line through its output terminal, compensating for the leakage current generated by other memory cells on the read bit line. Since the feedback signal output by this feedback circuit can also control the leakage current compensation unit to turn on in a timely manner, the read performance of the single-ended memory when the stored information is high can also be guaranteed.

[0076] For example, the feedback circuit described above includes an inverter. The input terminal of the inverter is connected to the read bit line, and the output terminal of the inverter is connected to the control terminal of the leakage current compensation unit; wherein the inverter is used to generate a feedback signal according to the level of the read bit line to control the leakage current compensation unit to turn on or off in a timely manner.

[0077] Specifically, the inverter in the feedback circuit 602 includes a first transistor and a second transistor (such an inverter is also called a pull-bias inverter).

[0078] Reference Figure 7 As shown in the diagram, an embodiment of this application provides a structural schematic of a single-ended memory. Figure 7 The single-ended memory shown details the specific structure of the inverter in the feedback circuit 602, where... Figure 7 The inverter in the feedback circuit 602 shown includes transistor Mf1 (the first transistor mentioned above, assuming Mf1 is a P-type transistor) and transistor Mf2 (the second transistor mentioned above, assuming Mf2 is an N-type transistor). The first terminal of transistor Mf1 is connected to the power supply Vdd, the second terminal of transistor Mf1 is connected to the first terminal of transistor Mf2, and the second terminal of transistor Mf2 is connected to ground GND. The control terminals of transistors Mf1 and Mf2 are connected to the input terminals of the inverter included in the feedback circuit 602; the second terminal of transistor Mf1 is also connected to the output terminal of the inverter included in the feedback circuit 602.

[0079] When the single-ended memory reads the stored information in the storage cell 601, the stored information is at a high level, and the storage cell 601 outputs a high level to the read bit line RBL-1. Although the level of the read bit line RBL-1 will decrease due to the presence of leakage current, when the level of the read bit line RBL-1 is between the second predetermined value and the high level, the input level of the inverter included in the feedback circuit 602 is considered to be at a high level, so that the control terminal level of transistor Mf1 is at a high level, transistor Mf1 is turned off, and the control terminal level of transistor Mf2 is at a high level, transistor Mf2 is turned on. Since transistor Mf1 is off and transistor Mf2 is on, and the output terminal of the inverter is connected to ground GND, the output level of the inverter is low. At this time, the feedback signal S4 output by the feedback circuit 602 to the control terminal of the leakage current compensation unit (that is, transistor M63, which is a P-type transistor) is low, thereby controlling transistor M63 to turn on. The read bit line RBL-1 is connected to the power supply Vdd through transistor M63. The power supply Vdd charges the read bit line RBL-1, and the read bit line RBL-1 remains at a high level.

[0080] When the single-ended memory reads the stored information from the storage cell 601, the stored information is at a low level. The storage cell 601 outputs a low level to the read bit line RBL-1, and the level of the read bit line RBL-1 begins to decrease. When the level of the read bit line RBL-1 decreases to a first predetermined value, the input level of the inverter included in the feedback circuit 602 is considered to be at a low level, so that the control level of transistor Mf1 is at a low level and transistor Mf1 is turned on, while the control level of transistor Mf2 is at a low level and transistor Mf2 is turned off. Since transistor Mf1 is turned on and transistor Mf2 is turned off, and the output of the inverter is connected to the power supply Vdd, the output level of the inverter is high. At this time, the feedback signal S4 output by the feedback circuit 602 to the control terminal of the leakage current compensation unit (that is, transistor M63, which is a P-type transistor) is high, thereby controlling transistor M63 to turn off. The read bit line RBL-1 will not be connected to the power supply Vdd through transistor M63, the power supply Vdd will not charge the read bit line RBL-1, and the level of the read bit line RBL-1 will continue to decrease to a low level.

[0081] In some embodiments, refer to Figure 8 As shown in the diagram, an embodiment of this application provides a structural schematic of a single-ended memory. Figure 8 The single-ended memory shown in the diagram illustrates another specific structure of the inverter in the feedback circuit 602, which includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor (such an inverter is also known as a half-Smitter inverter).

[0082] Specifically, such as Figure 8 As shown, the inverter in the feedback circuit 602 includes transistor Mf3 (the third transistor mentioned above, with Mf3 being a P-type transistor), transistor Mf4 (the fourth transistor mentioned above, with Mf4 being an N-type transistor), transistor Mf5 (the fifth transistor mentioned above, with Mf5 being an N-type transistor), and transistor Mf6 (the sixth transistor mentioned above, with Mf6 being an N-type transistor). The first terminal of transistor Mf3 is connected to the power supply Vdd, the second terminal of transistor Mf3 is connected to the first terminal of transistor Mf4, and the second terminal of transistor Mf4 is connected to the first terminal of transistor Mf5; the second terminal of transistor Mf5 is connected to ground GND; the first terminal of transistor Mf6 is connected to the second terminal of transistor Mf4, the control terminal of transistor Mf6 is connected to the second terminal of transistor Mf3, and the second terminal of transistor Mf6 is connected to the power supply Vdd; the control terminals of transistors Mf3, Mf4, and Mf5 are connected to the input terminal of the inverter included in the feedback circuit 602; the second terminal of transistor Mf3 is also connected to the output terminal of the inverter included in the feedback circuit 602.

[0083] When the single-ended memory reads the stored information from memory cell 601, the stored information is at a high level, and memory cell 601 outputs a high level to read line RBL-1. Although the level of read line RBL-1 will decrease due to leakage current, when the level of read line RBL-1 is between a second predetermined value (which may be the forward threshold voltage of a half-Smitter inverter) and a high level, the input levels of the inverters included in feedback circuit 602 are all considered to be high, causing the control terminal level of transistor Mf3 to be high, turning off transistor Mf3, while the control terminals of transistors Mf4 and Mf5 are high, turning on transistors Mf4 and Mf5. Since transistor Mf3 is off and transistors Mf4 and Mf5 are on, the second terminal of transistor Mf3 is connected to ground GND, and the level of the second terminal of transistor Mf3 is low. The control terminal level of transistor Mf6, which is connected to the second terminal of transistor Mf3, is also low, turning off transistor Mf6. The output level of the inverter is low. At this time, the feedback signal S4 output by the feedback circuit 602 to the control terminal of the leakage current compensation unit (that is, transistor M63, which is a P-type transistor) is low, thereby controlling transistor M63 to turn on. The read bit line RBL-1 is connected to the power supply Vdd through transistor M63. The power supply Vdd charges the read bit line RBL-1, and the read bit line RBL-1 remains at a high level.

[0084] When the single-ended memory reads the stored information from the storage cell 601, the stored information is at a low level. The storage cell 601 outputs a low level to the read bit line RBL-1, and the level of the read bit line RBL-1 begins to decrease. When the level of the read bit line RBL-1 decreases to a first predetermined value (the first predetermined value may be the negative threshold voltage of the half-Smitter inverter), the input level of the inverter included in the feedback circuit 602 is considered to be at a low level, so that the control level of transistor Mf3 is at a low level and transistor Mf3 is turned on. When the control levels of transistors Mf4 and Mf5 are at a low level, transistors Mf4 and Mf5 are turned off. Because transistor Mf3 is turned on and transistors Mf4 and Mf5 are turned off, the second terminal of transistor Mf3 is connected to the power supply Vdd, and the voltage level of the second terminal of transistor Mf3 is high. The control terminal of transistor Mf6, which is connected to the second terminal of transistor Mf3, is also high, turning on transistor Mf6. The second terminal of transistor Mf4 is also connected to the power supply Vdd through transistor Mf6, keeping the second terminal of transistor Mf3 high. Therefore, the output voltage of the inverter is high. At this time, the feedback signal S4 output by the feedback circuit 602 to the control terminal of the leakage current compensation unit (i.e., transistor M63, which is a P-type transistor) is high, thereby controlling transistor M63 to turn off. The read line RBL-1 cannot be connected to the power supply Vdd through transistor M63, and the power supply Vdd will not charge the read line RBL-1. The voltage level of the read line RBL-1 continues to decrease to a low level.

[0085] The feedback circuit 602 can also generate a feedback signal based on the level of the read bit line by setting logic gate circuits, as shown in the reference. Figure 9 As shown in the diagram, an embodiment of this application provides a structural schematic of a single-ended memory. Figure 9 In the single-ended memory shown, the feedback circuit 602 includes a first NOR gate and a first NOT gate.

[0086] Specifically, such as Figure 9 As shown, the feedback circuit 602 of the single-ended memory includes a NOT gate 6020 (i.e., the first NOT gate mentioned above) and a NOR gate 6021 (i.e., the first NOR gate mentioned above). The input terminal of the NOT gate 6020 is connected to the control terminal of the transistor M61 (i.e., the column selection unit mentioned above, with the transistor M61 being an N-type transistor as an example). The output terminal of the NOT gate 6020 is connected to the first input terminal of the NOR gate 6021. The second input terminal of the NOR gate 6021 is connected to the read bit line RBL-1. The output terminal of the NOR gate 6021 is connected to the control terminal of the leakage current compensation unit (i.e., the transistor M63, with the transistor M63 being a P-type transistor as an example).

[0087] For example, refer to Figure 9As shown, the input terminal of NOT gate 6020 is connected to the control terminal of the column selection unit. Specifically, the control terminal of transistor M61 is input to the column selection signal S2, and the input terminal of NOT gate 6020 is also input to the column selection signal S2.

[0088] When the single-ended memory reads the stored information in the storage cell 601, the stored information is at a high level, and the storage cell 601 outputs a high level to the read bit line RBL-1. Although the level of the read bit line RBL-1 will decrease due to the presence of leakage current, when the level of the read bit line RBL-1 is between the second predetermined value and the high level, the level input to the second input terminal of the NOR gate 6021 included in the feedback circuit 602 is considered to be at a high level. Since column selection signal S2 is high when data is read, the level of column selection signal S2 output to the first input of NOR gate 6021 through NOT gate 6020 is low. NOR gate 6021 performs NOR operation, making the output of NOR gate 6021 low. At this time, the feedback signal S4 output by feedback circuit 602 to the control terminal of transistor M63 is low, transistor M63 is turned on, and read bit line RBL-1 is connected to power supply Vdd through transistor M63. Power supply Vdd charges read bit line RBL-1, and read bit line RBL-1 remains high.

[0089] When the single-ended memory reads the stored information from storage cell 601, the stored information is at a low level. Storage cell 601 outputs a low level to read line RBL-1, causing the level of read line RBL-1 to begin to decrease. When the level of read line RBL-1 decreases to a first predetermined value, the level input to the second input terminal of NOR gate 6021 included in feedback circuit 602 is considered low. Since column selection signal S2 is high when data is read, the level of column selection signal S2 output to the first input terminal of NOR gate 6021 through NOT gate 6020 is low. NOR gate 6021 performs a NOR operation, causing the output terminal of NOR gate 6021 to be high. At this time, the feedback signal S4 output by feedback circuit 602 to the control terminal of transistor M63 is high, transistor M63 is turned off, and read line RBL-1 is not connected to power supply Vdd through transistor M63. Power supply Vdd no longer charges read line RBL-1, and the level of read line RBL-1 continues to decrease to a low level.

[0090] In other embodiments, the leakage current compensation unit of the single-ended memory can be connected to the read bit line through the first switching unit, and the control terminal of the first switching unit is connected to the control terminal of the column selection unit.

[0091] Specifically, refer to Figure 10As shown in the diagram, an embodiment of this application provides a schematic diagram of a single-ended memory. This single-ended memory further includes transistor M65 (i.e., the aforementioned first switching unit, where transistor M65 is an N-type transistor). The first terminal of transistor M65 is connected to the second terminal of transistor M63 (i.e., the aforementioned leakage current compensation unit, where transistor M63 is a P-type transistor). The first terminal of transistor M63 is connected to the power supply Vdd. The second terminal of transistor M65 is connected to the second terminal of transistor M61 (i.e., the aforementioned column select unit, where transistor M61 is an N-type transistor). The first terminal of transistor M61 is connected to the read bit line RBL-1. The connection between the control terminal of the first switching unit and the control terminal of the column select unit indicates that the control terminal of the column select unit receives the column select signal S2, and the control terminal of transistor M65 also receives the column select signal S2. When the single-ended memory reads the stored information in storage cell 601, the column selection signal S2 is set to a high level. Therefore, the control terminals of transistors M61 and M65 are at a high level, and transistors M61 and M65 are turned on. The power supply Vdd is connected to the read line RBL-1 through transistors M61, M65, and M63. Since the control terminal signal of the column selection unit also controls the opening or closing of the first switching unit, it is ensured that when the column selection unit is turned on by its control terminal signal to select the read line, the first switching unit can be turned on at the same time to connect the leakage current compensation unit to the read line. This allows the leakage current compensation unit to compensate for or stop compensation of the level of the read line in a timely manner when the read line is selected, realizing the adaptive operation of the leakage current compensation unit when the read line is selected.

[0092] For example, in order to enable the single-ended memory to read stored information at a low level more quickly, embodiments of this application provide a single-ended memory. The single-ended memory further includes: a discharge unit, the control terminal of which is connected to the control terminal of a leakage current compensation unit; a first terminal of the discharge unit is connected to a read bit line via a column selection unit; and a second terminal of the discharge unit is connected to ground.

[0093] Specifically, refer to Figure 11 As shown, an embodiment of this application provides a schematic diagram of a single-ended memory. The single-ended memory further includes a discharge unit 604, which includes a transistor Md1 (taking an N-type transistor as an example). The control terminal of transistor Md1 is connected to the control terminal of a leakage current compensation unit (i.e., transistor M63, taking a P-type transistor as an example). The second terminal of transistor Md1 is connected to ground (GND), and the first terminal of transistor Md1 is connected to the second terminal of transistor M61 (i.e., the aforementioned column select unit, taking an N-type transistor as an example). The first terminal of transistor M61 is connected to the read bit line RBL-1.

[0094] When the single-ended memory reads the stored information from storage cell 601, the stored information is at a high level. Storage cell 601 outputs a high level to read line RBL-1. When feedback circuit 602 determines that the level of read line RBL-1 is higher than a second predetermined value, it outputs feedback signal S4 to the control terminal of transistor M63. Feedback signal S4 is at a low level, transistor M63 is turned on, and the power supply Vdd is controlled to charge read line RBL-1 through transistor M63, so that read line RBL-1 remains at a high level. At the same time, the control terminal of transistor Md1 also receives feedback signal S4. Because feedback signal S4 is at a low level, transistor Md1 is turned off, and read line RBL-1 is not connected to ground GND through transistor Md1, thus ensuring that read line RBL-1 remains at a high level.

[0095] When the single-ended memory reads the stored information from storage cell 601, the stored information is at a low level. Storage cell 601 outputs a low level to read line RBL-1, causing the level of read line RBL-1 to begin decreasing. When the level of read line RBL-1 decreases to a first predetermined value, feedback circuit 602 outputs feedback signal S4 to the control terminal of transistor M63. This feedback signal S4 is at a high level, and transistor M63 is turned off to stop the power supply Vdd from charging read line RBL-1 through transistor M63, causing the level of read line RBL-1 to continue decreasing to a low level. At the same time, the control terminal of transistor Md1 also receives feedback signal S4. Because feedback signal S4 is at a high level, transistor Md1 is turned on, and read line RBL-1 is connected to ground GND through transistor Md1. The level of read line RBL-1 decreases, and transistor Md1 causes the level of read line RBL-1 to decrease faster. This single-ended memory, through the synergistic action of transistors M63 and Md1, ensures that the level of the read bit line RBL-1 can be reduced to a low level as quickly as possible when the stored information is low, thereby improving the read speed of the single-ended memory.

[0096] In some embodiments, to avoid the discharge unit being too sensitive and the level of the read bit line decreasing due to leakage current, the discharge unit discharges the read bit line to ground, causing data reading errors. Embodiments of this application also provide a discharge unit for a single-ended memory, which includes a seventh transistor and an eighth transistor.

[0097] Specifically, refer to Figure 12 As shown in the diagram, an embodiment of this application provides a structural schematic of a single-ended memory. Figure 12The single-ended memory shown illustrates a specific structure of a discharge unit 604, which includes transistors Md2 (the seventh transistor mentioned above, exemplified by an N-type transistor) and Md3 (the eighth transistor mentioned above, exemplified by an N-type transistor). The control terminal of transistor Md2 is connected to the control terminal of transistor M63 (the aforementioned connection to the leakage current compensation unit, exemplified by a P-type transistor). The first terminal of transistor Md2 is connected to the second terminal of transistor M61 (the aforementioned column select unit, exemplified by an N-type transistor). The first terminal of transistor M61 is connected to the read bit line RBL-1. The second terminal of transistor Md2 is connected to the control terminal of transistor Md3, and is also connected to the first terminal of transistor Md3. The second terminal of transistor Md3 is connected to ground.

[0098] When the single-ended memory reads the stored information from storage cell 601, the stored information is at a high level. Storage cell 601 outputs a high level to read line RBL-1. When feedback circuit 602 determines that the level of read line RBL-1 is higher than a second predetermined value, it outputs feedback signal S4 to the control terminal of transistor M63. Feedback signal S4 is at a low level, and transistor M63 is turned on to control the power supply Vdd to charge read line RBL-1 through transistor M63, thus keeping read line RBL-1 at a high level. At the same time, the control terminal of transistor Md2 also receives feedback signal S4. Because feedback signal S4 is at a low level, transistor Md2 is turned off. Since the second terminal of transistor Md2 is connected to the control terminal of transistor Md3, transistor Md3 is also turned off. Read line RBL-1 is not connected to ground GND through transistors Md2 and Md3, ensuring that read line RBL-1 remains at a high level.

[0099] When the single-ended memory reads the stored information from the storage cell 601, the stored information is at a low level. The storage cell 601 outputs a low level to the read bit line RBL-1, and the level of the read bit line RBL-1 begins to decrease. When the level of the read bit line RBL-1 decreases to a first predetermined value, the feedback circuit 602 outputs a feedback signal S4 to the control terminal of the transistor M63. The feedback signal S4 is at a high level, and the transistor M63 is turned off to stop the power supply Vdd from charging the read bit line RBL-1 through the transistor M63, so that the level of the read bit line RBL-1 continues to decrease to a low level. Simultaneously, the control terminal of transistor Md2 also receives feedback signal S4. Because feedback signal S4 is high, transistor Md2 is turned on. Since the second terminal of transistor Md2 is connected to the control terminal and the first terminal of transistor Md3, and the second terminal of transistor Md3 is connected to ground (GND), it proves that the discharge unit 604 is connected to ground (GND) through transistors Md2 and Md3. This connection method between transistors Md2 and Md3 increases the equivalent resistance of the current discharge unit 604, thus slowing down the discharge speed. If the current level of read line RBL-1 is reduced due to leakage current, this configuration of the discharge unit 604 will prevent the read line RBL-1 from being directly connected to ground, thus avoiding errors in reading stored information and making the read performance of the single-ended memory more stable.

[0100] In other embodiments, the single-ended memory includes a second NOT gate, and the discharge unit includes a ninth transistor.

[0101] Specifically, refer to Figure 13 As shown in the diagram, an embodiment of this application provides a structural schematic of a single-ended memory. Figure 13 The single-ended memory shown illustrates another specific structure of the discharge unit 604, which includes transistor Md4 (the aforementioned ninth transistor, exemplified by a P-type transistor). The single-ended memory also includes a NOT gate 605 (the aforementioned second NOT gate). The control terminal of transistor M63 (the aforementioned leakage current compensation unit, exemplified by a P-type transistor) is connected to the input terminal of NOT gate 605. The output terminal of NOT gate 605 is connected to the control terminal of transistor Md4. The second terminal of transistor Md4 is connected to ground (GND), and the first terminal of transistor Md4 is connected to the second terminal of transistor M61 (the aforementioned column select unit, exemplified by an N-type transistor). The first terminal of transistor M61 is connected to the read bit line RBL-1.

[0102] When the single-ended memory reads the stored information from storage cell 601, the stored information is at a high level. Storage cell 601 outputs a high level to read line RBL-1. When feedback circuit 602 determines that the level of read line RBL-1 is higher than a second predetermined value, it outputs feedback signal S4 to the control terminal of transistor M63. Feedback signal S4 is at a low level, transistor M63 is turned on, and the power supply Vdd is controlled to charge read line RBL-1 through transistor M63, so that read line RBL-1 remains at a high level. At the same time, feedback signal S4 is turned high by NOT operation through NOT gate 605 and input to the control terminal of transistor Md4. Transistor Md4 is turned off, and read line RBL-1 is not connected to ground GND through transistor Md4, ensuring that read line RBL-1 remains at a high level.

[0103] When the single-ended memory reads the stored information from storage cell 601, the stored information is at a low level. Storage cell 601 outputs a low level to read line RBL-1, causing the level of read line RBL-1 to begin to decrease. When the level of read line RBL-1 decreases to a first predetermined value, feedback circuit 602 outputs feedback signal S4 to the control terminal of transistor M63. This feedback signal S4 is at a high level, and transistor M63 is turned off to stop the power supply Vdd from charging read line RBL-1 through transistor M63, causing the level of read line RBL-1 to continue to decrease to a low level. At the same time, feedback signal S4 becomes low through NOT gate 605 and is input to the control terminal of transistor Md4. Transistor Md4 is turned on, and read line RBL-1 is connected to ground GND through transistor Md4. However, since transistor Md4 is a P-type transistor, there is a threshold loss when P-type transistors transmit levels, which also slows down the discharge speed of discharge unit 604. If the current level of the read bit line RBL-1 is reduced due to the presence of leakage current, the discharge unit 604 configured in this way will not directly reduce the level of the read bit line RBL-1 to a low level, making the read performance of the single-ended memory more stable.

[0104] Embodiments of this application also provide a single-ended memory, which further includes a second switching unit between the first end of the discharge unit and the column selection unit.

[0105] Specifically, refer to Figure 14As shown in the diagram, an embodiment of this application provides a schematic diagram of a single-ended memory. This single-ended memory further includes a transistor M66 (i.e., the second switching unit mentioned above; transistor M66 is an N-type transistor, for example). The first terminal of the discharge unit 604 is connected to the second terminal of transistor M66, and the first terminal of transistor M66 is connected to the second terminal of transistor M61 (i.e., the column select unit mentioned above; transistor M61 is an N-type transistor, for example). The first terminal of transistor M61 is connected to the read bit line RBL-1. The control terminal of transistor M66 can be connected to the tracking circuit of the single-ended memory. This tracking circuit can track the level changes on the global bit line GBL, turning on transistor M66 before the global bit line GBL reads a low level and turning off transistor M66 before the global bit line GBL reads a high level. Specifically, a high level can be output to the control terminal of M66 δt1 time before the global bit line GBL reads a low level, to control transistor M66 to turn on. Discharge unit 604 is connected to read bit line RBL-1 through transistors M66 and M61, accelerating the discharge of read bit line RBL-1 so that it drops to a low level more quickly. Conversely, a low level can be output to the control terminal of transistor M66 δt2 time before the global bit line GBL reads a high level, to control transistor M66 to turn off. Discharge unit 604 cannot be connected to read bit line RBL-1 through transistors M66 and M61. If the current level of read bit line RBL-1 decreases due to leakage current, discharge unit 604 will not discharge read bit line RBL-1, ensuring the single-ended memory reads stored information at a high level. The aforementioned δt1 and δt2 time values ​​can be configured by default or adaptively adjusted.

[0106] Alternatively, the control terminal of transistor M66 can be connected to an external test pin of the single-ended memory. Specifically, when reading the stored information of memory cell 601, a low-level control transistor M66 can be transmitted via an external test transistor to turn it off, preventing discharge unit 604 from connecting to read line RBL-1 through transistors M66 and M61. If the current level of read line RBL-1 decreases due to leakage current, discharge unit 604 will not discharge read line RBL-1 to ground, ensuring the single-ended memory's performance of reading stored information at a high level. On the other hand, when reading the stored information of memory cell 601, a high-level control transistor M66 can be transmitted via an external test transistor to turn it on, allowing discharge unit 604 to connect to read line RBL-1 through transistors M66 and M61. Discharge unit 604 will accelerate the discharge of read line RBL-1, causing read line RBL-1 to drop to a low level more quickly.

[0107] In other embodiments, the control terminal of the discharge unit can be controlled to turn on or off via a circuit connection structure similar to feedback circuit 602. Exemplarily, the single-ended memory also includes a second NOR gate and a third NOT gate.

[0108] Specifically, refer to Figure 15 As shown, Figure 15 The schematic diagram of the single-ended memory provided in the embodiment of this application shows that the single-ended memory further includes a NOT gate 606 (that is, the third NOT gate mentioned above) and a NOR gate 607 (that is, the second NOR gate mentioned above). The input terminal of the NOT gate 606 is connected to the control terminal of the transistor M61 (that is, the column select unit mentioned above, the transistor M61 is an N-type transistor for example), the output terminal of the NOT gate 606 is connected to the first input terminal of the NOR gate 607, the read bit line RBL-1 is connected to the second input terminal of the NOR gate 607, and the output terminal of the NOR gate 607 is connected to the control terminal of the discharge unit 604.

[0109] For example, refer to Figure 15 As shown, the input terminal of NOT gate 606 is connected to the control terminal of the column selection unit. Specifically, the control terminal of transistor M61 is input to the column selection signal S2, and the input terminal of NOT gate 606 is also input to the column selection signal S2.

[0110] When the single-ended memory reads the stored information in memory cell 601, the stored information is at a high level, and memory cell 601 outputs a high level to read line RBL-1. Although the level of read line RBL-1 will decrease due to leakage current, when the level of read line RBL-1 is between the second predetermined value and the high level, the level input to the second input terminal of NOR gate 607 is considered to be high. Since column selection signal S2 is high when reading occurs, the level of column selection signal S2 output to the first input terminal of NOR gate 607 through NOT gate 606 is low. NOR gate 607 performs a NOR operation, causing the level transmitted by NOR gate 607 to the control terminal of discharge unit 604 to be low.

[0111] When the single-ended memory reads the stored information from memory cell 601, the stored information is at a low level. Memory cell 601 outputs a low level to read line RBL-1, causing the level of read line RBL-1 to begin decreasing. When the level of read line RBL-1 decreases to a first predetermined value, the level input to the second input terminal of NOR gate 607 is considered low. Since column selection signal S2 is high when a read occurs, the level of column selection signal S2 output to the first input terminal of NOR gate 607 through NOT gate 606 is low. NOR gate 607 performs a NOR operation, causing the level transmitted from NOR gate 607 to the control terminal of discharge unit 604 to be high.

[0112] It should be noted that a low level transmitted from the NOR gate 607 to the control terminal of the discharge unit 604 can either turn on the transistor in the discharge unit 604 (a P-type transistor is used in the discharge unit 604) to discharge, or turn off the transistor in the discharge unit 604 (an N-type transistor is used in the discharge unit 604) to prevent discharge. Similarly, a high level transmitted from the NOR gate 607 to the control terminal of the discharge unit 604 can either turn on the transistor in the discharge unit 604 (an N-type transistor is used in the discharge unit 604) to discharge, or turn off the transistor in the discharge unit 604 (a P-type transistor is used in the discharge unit 604) to prevent discharge.

[0113] For example, when the feedback circuit 602 of the single-ended memory includes an inverter and a discharge unit 604 is provided, the feedback signal and read time of the single-ended memory are simulated by selecting a slow N-type transistor and a fast P-type transistor process curve (slow NMOS fast PMOS concer, SNFPconcer), setting the voltage level to 0.6 volts and the temperature to -40 degrees Celsius. Alternatively, a typical process curve (tipicalconcer, TT concerr) is selected, setting the voltage level to 1.2 volts and the temperature to 25 degrees Celsius. The simulation diagram is shown below. Figure 16 and Figure 17 As shown.

[0114] It should be noted that the changes in the voltage level from high to low as described in the above embodiments are gradual. In the simulation diagram, because the time interval is very short, the gradual change is very obvious.

[0115] Simulation was performed with the read storage information of the memory cell as a low level, and the result was obtained. Figure 16 The diagram shows the level change of the Global Bit Line (GBL) in a conventional single-ended memory (curve 1), while the embodiment of this application provides the level change of the Global Bit Line (GBL) in a single-ended memory (curve 2). Specifically, considering curve 1 and... Figure 5The process of reading the stored information (low level) from a memory cell in an existing single-ended memory is described below. When the rising edge of the CLK clock (i.e., when the CLK clock initially goes high) arrives, the read bit line RBL-1 is selected. At time t1, the precharge unit M41 is activated, charging the read bit line RBL-1. Simultaneously, the levels of other read bit lines RBL-n and the global bit line GBL also continuously rise. That is, from time t1 to t2 in curve one, the level of the global bit line GBL continuously rises to a high level. Then, the read word line selects memory cell c1, and memory cell c1 outputs low-level stored information to the read bit line RBL-1. This low-level stored information causes the level of the read bit line RBL-1 to continuously decrease. However, before the level of read bit line RBL-1 drops to a low level, the level of read bit line RBL-1 received by the first terminal of NAND gate 401 is high, and the level of other read bit lines RBL-n received by the second terminal of NAND gate 401 is also high. NAND gate 401 performs a NAND operation and outputs a low level, causing the control terminal level of transistor M42 to go low. Transistor M42 is turned on, and read bit line RBL-1 is connected to power supply Vdd through transistor M42. Power supply Vdd charges read bit line RBL-1, and the level of read bit line RBL-1 drops slowly. Corresponding to time t2 to t3 in curve 1, because the level of the read bit line drops slowly and does not drop to a low level, the level output by NAND gate 401 is low, transistor M45 is off, and global bit line GBL cannot be connected to ground through transistor M45. Therefore, the level of global bit line GBL remains high from time t2 to t3. When the level of read bit line RBL-1 drops to a low level, NAND gate 401 performs a NAND operation and outputs a high level. Transistor M42 is turned off, and transistor M45 is turned on. The global bit line GBL is connected to ground through transistor M45, causing the level of the global bit line GBL to continuously decrease. That is, from time t3 to t6, the global bit line GBL continuously decreases to a low level. The input / output circuit coupled to this global bit line GBL can determine that the current level of the global bit line GBL is low, and it can also determine that the stored information of the current memory cell c1 is low.

[0116] Secondly, combining curve two and Figure 15 The process of reading the stored information (low level) of the storage cell of the single-ended memory provided in the embodiments of this application is described below. (Refer to...) Figure 16 Curve 2 and Figure 15In the single-ended memory shown, when the rising edge of the CLK clock (i.e., when the CLK clock just starts to go high) arrives, the column selection unit M61 is turned on, and the read bit line RBL-1 is selected. At time t1, the precharge unit M62 is turned on, and the precharge unit M62 charges the read bit line RBL-1, causing the level of the read bit line RBL-1 to continuously rise. At the same time, the levels of other read bit lines RBL-n and the global bit line GBL also continuously rise. That is, from time t1 to time t3 in curve 1, the level of the global bit line GBL continuously rises to a high level. When the feedback circuit 602 determines that the level of the read bit line RBL-1 is higher than a second predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit M63 to control the leakage current compensation unit M63 to charge the read bit line RBL-1 through its output terminal, so that the read bit line RBL-1 remains at a high level. At time t3, the read word line RWL selects the storage unit 601, and the storage unit 601 outputs storage information to the read bit line RBL-1. This storage information is at a low level, which causes the level of the read bit line RBL-1 to begin to decrease. Since the leakage current compensation unit M63 is not turned off at this time, the leakage current compensation unit M63 is still charging the read bit line RBL-1, which makes the level of the read bit line RBL-1 decrease slowly. When the feedback circuit 602 determines that the level of the read bit line RBL-1 is lower than the first predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit M63 to stop the leakage current compensation unit M63 from charging the read bit line RBL-1 through the output terminal. At this time, the level of the read bit line RBL-1 decreases faster. When the level of the read bit line RBL-1 decreases to a low level, the NAND gate 603 performs a NAND operation, the transistor M64 turns on, and the global bit line GBL is connected to ground through the transistor M64, causing the level of the global bit line GBL to decrease continuously. That is, from time t3 to time t5, the level of the global bit line GBL continuously decreases. At time t4, because the discharge unit 604 turns on, the level of the read bit line RBL-1 begins to decrease rapidly. This is reflected in the global bit line GBL, which can be seen to decrease at a significantly faster rate at time t4 (i.e., curve two). The input / output circuit coupled to the global bit line GBL can determine at time t5 that the level of the global bit line GBL is low, and can also determine that the stored information of the current memory cell 601 is low.

[0117] Reference Figure 16It can be seen that the time consumed by existing single-ended memories from the rising edge of the CLK clock to the global bit line GBL reading the stored information as low is t6-t1, which is 1.4 nanoseconds (this time is the read time); while the single-ended memory provided in the embodiments of this application consumes t5-t1, which is 0.8 nanoseconds (this time is the read time), from the rising edge of the CLK clock to the global bit line GBL reading the stored information as low. The read time of the single-ended memory provided in the embodiments of this application is improved by 40% compared with existing single-ended memories.

[0118] Figure 17 The diagram illustrates the level change of the feedback signal received by the leakage current compensation unit in a conventional single-ended memory (curve 3), while the embodiment of this application provides the level change of the feedback signal received by the leakage current compensation unit in a single-ended memory (curve 4). Specifically, considering curve 3 and... Figure 5 The process of reading stored information (low level) from a memory cell in an existing single-ended memory is described below. When the rising edge of the CLK clock (i.e., when the CLK clock initially goes high) arrives, read bit line RBL-1 is selected. At time t1, precharge unit M41 is activated, charging read bit line RBL-1. The level of read bit line RBL-1 continuously increases, and simultaneously, the levels of other read bit lines RBL-n and the global bit line GBL also continuously increase. The first terminal of NAND gate 401 receives a high level from read bit line RBL-1, while the second terminal of NAND gate 401 receives high levels from other read bit lines RBL-n and RBL-n. When the level of L-n is high, NAND gate 401 performs a NAND operation and outputs a low level, causing the control terminal level of transistor M42 (i.e., the feedback signal received by transistor M42) to be low, and transistor M42 to turn on. That is, at time t2', the feedback signal output by NAND gate 401 to the control terminal of transistor M42 is low, controlling transistor M42 to turn on. Power supply Vdd charges read line RBL-1 through transistor M42, so the level of the feedback signal shown in curve 3 decreases rapidly at time t2'. At time t5', the level of read line RBL-1 decreases to low, and the level of read line RBL-1 received by the first terminal of NAND gate 401 is low, while the level of other read lines RBL-n received by the second terminal of NAND gate 401 is high. NAND gate 401 performs a NAND operation and outputs a high level. That is, at time t5', referring to curve 3, NAND gate 401 outputs a feedback signal to the control terminal of transistor M42, which is high, controlling transistor M42 to turn off. At the same time, the high level output of NAND gate 401 also turns on transistor M45, and the global bit line GBL starts to discharge through transistor M45. The level of the global bit line GBL goes low. When the level of the global bit line GBL drops to a low level, the input / output circuit coupled to the global bit line GBL determines that the stored information of the memory cell c1 is low.

[0119] Secondly, combining curve four and Figure 15 The process of reading the stored information (low level) of the storage cell of the single-ended memory provided in the embodiments of this application is described below. (Refer to...) Figure 17 Curve 4 and Figure 15 In the single-ended memory shown, when the rising edge of the CLK clock (that is, when the CLK clock just starts to go high) arrives, the column selection unit M61 is turned on, and the read bit line RBL-1 is selected. At time t1, the precharge unit M62 is turned on and charges the read bit line RBL-1. During the charging process of the read bit line RBL-1, when the feedback circuit 602 determines that the level of the read bit line RBL-1 is higher than the second predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit M63. This feedback signal is low. Referring to curve four, that is, at time t3', the feedback signal becomes low and controls the leakage current compensation unit M63 to charge the read bit line RBL-1 through the output terminal. When the read word line RWL selects the storage unit 601, the storage unit 601 outputs stored information to the read bit line RBL-1. This stored information is at a low level, causing the level of the read bit line RBL-1 to begin to decrease. When the feedback circuit 602 determines that the level of the read bit line RBL-1 is lower than a first predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit M63. This feedback signal is at a high level. Referring to curve four, that is, at time t4', the feedback signal becomes high to stop the leakage current compensation unit M63 from charging the read bit line RBL-1 through the output terminal. At this time, the level of the read bit line RBL-1 decreases faster, and due to the presence of the discharge unit 604, the level of the read bit line RBL-1 quickly decreases to a low level. The NAND gate 603 performs a NAND operation and outputs a high level, then the transistor M64 turns on. The global bit line GBL is connected to ground through the transistor M64, and the level of the global bit line GBL becomes low. The input / output circuit coupled to the global bit line GBL reads the stored information of the storage unit 601 as low.

[0120] Reference Figure 17 It can be seen that for existing single-ended memories, the feedback signal transitions from high to low and then back to high after the rising edge of the CLK clock takes t5'-t1, which is 1.47 nanoseconds. In contrast, the single-ended memory provided in this application takes t4'-t1, which is 1.01 nanoseconds, for the feedback signal transitions from high to low and then back to high after the rising edge of the column select signal clock. The feedback signal change time of the single-ended memory provided in this application is improved by 46% compared to existing single-ended memories. Furthermore, the feedback signal of the single-ended memory provided in this application can become high much earlier than the feedback signal of existing single-ended memories.

[0121] It should be noted that, in order to clearly describe the various embodiments provided in this application, the types of transistors used in the embodiments of this application are shown. It is understood that, without departing from the spirit of this application, the types of transistors provided in the embodiments of this application can be adaptively changed, and the level of the corresponding control terminal of the transistor can also be adaptively changed. Such changes are considered to be within the scope of protection to be protected by this application.

[0122] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely exemplary illustrations of this application as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from the spirit and scope of this application. Thus, if such modifications and modifications of this application fall within the scope of the claims of this application and their equivalents, this application is also intended to include such modifications and modifications.

Claims

1. A single-ended memory, characterized in that, The system includes arrayed storage cells connected to read bit lines and read word lines; the read bit lines are connected to a precharge unit via a column selection unit; and the read bit lines are connected to the output of a leakage current compensation unit via the column selection unit. The read line is also connected to the control terminal of the leakage current compensation unit via a feedback circuit; The column selection unit is turned on under the action of the column selection signal; When the feedback circuit determines that the level of the read line is lower than a first predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit to stop the leakage current compensation unit from charging the read line through the output terminal.

2. The single-ended memory according to claim 1, characterized in that, When the feedback circuit determines that the level of the read line is higher than the second predetermined value, it outputs a feedback signal to the control terminal of the leakage current compensation unit to control the leakage current compensation unit to charge the read line through the output terminal, wherein the first predetermined value is less than or equal to the second predetermined value.

3. The single-ended memory according to claim 1, characterized in that, The feedback circuit includes: an inverter; The input terminal of the inverter is connected to the read line, and the output terminal of the inverter is connected to the control terminal of the leakage current compensation unit. The inverter is used to generate the feedback signal based on the level of the read bit line.

4. The single-ended memory according to claim 3, characterized in that, The inverter includes: a first transistor and a second transistor; The first terminal of the first transistor is connected to a power supply, the second terminal of the first transistor is connected to the first terminal of the second transistor, the second terminal of the second transistor is connected to ground, the control terminal of the first transistor and the control terminal of the second transistor are connected to the input terminal of the inverter; the second terminal of the first transistor is also connected to the output terminal of the inverter. The first transistor is of a different type than the second transistor.

5. The single-ended memory according to claim 3, characterized in that, The inverter includes: a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor; The first terminal of the third transistor is connected to the power supply, the second terminal of the third transistor is connected to the first terminal of the fourth transistor, the second terminal of the fourth transistor is connected to the first terminal of the fifth transistor, the second terminal of the fifth transistor is connected to ground, the first terminal of the sixth transistor is connected to the second terminal of the fourth transistor, the control terminal of the sixth transistor is connected to the second terminal of the third transistor, and the second terminal of the sixth transistor is connected to the power supply. The control terminals of the third transistor, the fourth transistor, and the fifth transistor are connected to the input terminal of the inverter; the second terminal of the third transistor is also connected to the output terminal of the inverter. The fourth transistor, the fifth transistor, and the sixth transistor are of the same type, while the third transistor is of a different type from the fourth transistor.

6. The single-ended memory according to claim 1, characterized in that, The feedback circuit includes: a first NOR gate and a first NOT gate; Wherein, the input terminal of the first NOT gate is connected to the control terminal of the column selection unit, and the output terminal of the first NOT gate is connected to the first input terminal of the first NOR gate; The second input terminal of the first NOR gate is connected to the read bit line; the output terminal of the first NOR gate is connected to the control terminal of the leakage current compensation unit.

7. The single-ended memory according to any one of claims 1-6, characterized in that, After the pre-charging unit charges the read bit line through the column selection unit, if the read word line selects the storage unit, the storage unit outputs storage information to the read bit line.

8. The single-ended memory according to any one of claims 1-6, characterized in that, The feedback circuit is connected to the transmission path between the storage unit and the column selection unit.

9. The single-ended memory according to any one of claims 1-6, characterized in that, The single-ended memory further includes: a first switching unit, wherein the leakage current compensation unit is connected to the read bit line through the first switching unit, and the control terminal of the first switching unit is connected to the control terminal of the column selection unit.

10. The single-ended memory according to any one of claims 1-6, characterized in that, The single-ended memory further includes a discharge unit, the control terminal of which is connected to the control terminal of the leakage current compensation unit. The first end of the discharge unit is connected to the read line through the column selection unit; the second end of the discharge unit is connected to ground.

11. The single-ended memory according to claim 10, characterized in that, The discharge unit includes a seventh transistor and an eighth transistor; The control terminal of the seventh transistor is connected to the control terminal of the leakage current compensation unit, and the first terminal of the seventh transistor is connected to the read bit line through the column selection unit; the second terminal of the seventh transistor is connected to the control terminal of the eighth transistor, and the second terminal of the seventh transistor is also connected to the first terminal of the eighth transistor, and the second terminal of the eighth transistor is connected to ground.

12. The single-ended memory according to claim 10, characterized in that, The discharge unit includes: a ninth transistor, the control terminal of the leakage current compensation unit is connected to the control terminal of the ninth transistor through a second NOT gate, the first terminal of the ninth transistor is connected to the read bit line through the column selection unit, and the second terminal of the ninth transistor is connected to ground.

13. The single-ended memory according to claim 10, characterized in that, A second switching unit is also provided between the first end of the discharge unit and the column selection unit.

14. The single-ended memory according to claim 10, characterized in that, The single-ended memory further includes: a second NOR gate and a third NOT gate; The input terminal of the third NOT gate is connected to the control terminal of the column selection unit, and the output terminal of the third NOT gate is connected to the first input terminal of the second NOR gate. The second input terminal of the second NOR gate is connected to the read bit line; the output terminal of the second NOR gate is connected to the control terminal of the discharge unit.

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