A data transmission apparatus, method and related device

Abstract

Embodiments of the present application provide a data transmission device, method and related equipment. Wherein a data transmission device can include: a plurality of processing units and a plurality of routers, each router is connected with one or more processing units, each router forms a communication connection relationship with any one of the plurality of routers; the plurality of routers include a first router, the first router is connected with a first processing unit. The first processing unit is used for: generating a first request; after determining that the state of receiving data of the first router is ready, determining a first clock signal based on the first request; sending target data to the first router based on the first clock signal, and sending the first clock signal to the first router. The first router is used for: receiving the target data sent by the first processing unit based on the first clock signal; according to the destination address, sending the target data to a second processing unit. By implementing the embodiments of the present application, the system performance can be improved while reducing the chip area.

Description

Technical Field

[0001] This application relates to the field of information technology, and in particular to a data transmission device, method and related equipment. Background Technology

[0002] With the deepening of internetization and industry digitalization, manufacturers of personal and industrial smart terminals are increasingly adopting system-on-chip (SoC) technology to integrate multiple types of intellectual property cores (IPs), such as microprocessors, central processing units (CPUs), digital signal processing units (DSPs), graphics processing units (GPUs), neural network processing units (NPUs), memory, network connectivity chips, etc. The number of integrated IP cores has also increased from dozens to hundreds. This necessitates greater interconnectivity and bandwidth between each IP core to support increasingly more real-time data communication.

[0003] Asynchronous circuit design technology, by inherently eliminating the need for a clock, enables a novel SoC integration architecture that achieves globally-asynchronous local-synchronous (GLS), significantly simplifying chip design complexity and reducing development investment and time. Among these, NOC (Network Over Chip) architecture is currently the mainstream bus integration technology for large-scale IP core integration. Each routing node is interconnected with other routing nodes in four directions, forming a fully interconnected mesh network. Each process entity (PE) connects to only one routing node and communicates with other PEs. Different PEs operate at different clock frequencies.

[0004] However, in existing NOC architectures, each routing node can only connect to one processing entity (i.e., PE), resulting in a large number of routers and consuming a significant amount of chip area. Furthermore, current NOC architectures employ a mesh interconnection structure, and the IP size and area of ​​the processing units that need to be integrated are very large, potentially reaching hundreds of millions of transistors. This leads to numerous and long router outgoing lines, introducing significant transmission latency, with large differences in latency across different locations, making timing analysis and convergence difficult.

[0005] Therefore, how to improve system performance while reducing chip area is a problem that needs to be solved in the embodiments of this application. Summary of the Invention

[0006] This application provides a data transmission device, method, and related equipment that reduces chip area while improving system performance.

[0007] In a first aspect, embodiments of this application provide a data transmission apparatus, which may include: multiple processing units and multiple routers, each of the routers being connected to one or more processing units, and each of the routers forming a communication connection with any one of the multiple routers; wherein the multiple routers include a first router, and the first router is connected to a first processing unit.

[0008] The first processing unit is configured to: generate a first request, the first request being used to request that target data be sent to the second processing unit, the target data including the destination address of the second processing unit; after determining that the first router is ready to receive data, determine a first clock signal based on the first request; send the target data to the first router based on the first clock signal, and send the first clock signal to the first router.

[0009] The first router is configured to: receive the first clock signal; receive the target data sent by the first processing unit based on the first clock signal; and send the target data to the second processing unit according to the destination address.

[0010] In the embodiments provided in the first aspect, after determining that the router (e.g., a first router) is ready to receive data, the data transmission device based on the asynchronous handshake mechanism causes the processing unit (e.g., a first processing unit) to generate a first clock signal based on the request to send data; and sends the first clock signal and the target data to the router according to the first clock signal, so that the router can receive the target data through the received first clock signal, and then the router sends the target data to the second processing unit according to the destination address carried in the received target data. This asynchronous handshake transmission method between the processing unit and the router can ensure that the router receives the target data completely. In addition, the processing unit also sends the clock signal (i.e., the first clock signal) when sending the target data to the router, so that the router can receive the data according to the clock signal, reducing the clock constraints within the data transmission device, making it easier to integrate multiple heterogeneous processing units or intellectual property cores within the data transmission device, and at the same time, making multiple routers not limited by synchronous clocks, making decision-making faster, and effectively improving the transmission performance of the system. Moreover, the relatively short and relatively deterministic data line connecting the processing unit and the router will further result in a small and relatively deterministic delay of the corresponding clock signal when the processing unit has a need to send data. Meanwhile, in this embodiment of the application, a router can be asynchronously connected to multiple processing units, which greatly reduces the chip area occupied by the bus.

[0011] In one possible implementation, the first router is further configured to: after the target data is received, adjust the data reception status of the first router from ready to not ready; the first processing unit is further configured to: after detecting that the data reception status of the first router has changed from ready to not ready, determine that the target data transmission is complete. In this embodiment, when the data reception status in the router changes from ready to not ready, the processing unit can determine that the data transmission is complete and stop data transmission to save communication resources. The ready and not ready states can be identified by high and low electrical signals, respectively.

[0012] In one possible implementation, each of the aforementioned processing units includes a first asynchronous handshake circuit. Specifically, the first processing unit is used to: determine a first clock signal based on the first request after determining that the first router's data reception status is ready, through the first asynchronous handshake circuit. In this embodiment, the first clock signal (also referred to as a self-timing clock) is provided by the asynchronous handshake circuit. This asynchronous handshake circuit has a simple structure and can generate a self-timing clock through a self-loop mechanism. That is, when the router's data reception status is ready and the first request exists simultaneously, a self-timing clock can be generated to drive the asynchronous message transmitter to send the target data to the router in a serial single-bit transmission manner.

[0013] In one possible implementation, each of the aforementioned processing units includes an asynchronous message transmitter; the first processing unit is specifically configured to: based on the first request, control the asynchronous message transmitter to send the target data to the first router in a serial single-bit transmission manner based on the first clock signal. In this embodiment, the asynchronous message transmitter can receive the drive of the first clock signal to send the target data to the router in a serial single-bit transmission manner, thereby realizing asynchronous transmission between the processing unit and the router.

[0014] In one possible implementation, the target data is transmitted as a variable-length or fixed-length data packet. The first processing unit is further configured to: after generating the first request, set the header of the target data and send the header and the first clock signal to the first router; after the last bit of the target data is sent, set the trailer of the target data and send it; the first router is further configured to: after receiving the header corresponding to the target data, start receiving the target data; after receiving the trailer of the target data, adjust the receiving data status of the first router from ready to not ready. In this embodiment, asynchronous transmission of the target data is achieved by setting the header and trailer of the target data, eliminating the need for clock synchronization between the processing unit and the router, and making it easier for a single router to integrate multiple heterogeneous processing units or intellectual property cores.

[0015] In one possible implementation, each of the aforementioned processing units includes a storage area based on a first-in-first-out (FIFO) storage mechanism; the first processing unit is specifically used to: write the target data into the aforementioned FIFO storage area and then generate the aforementioned first request. In this embodiment, the FIFO storage mechanism enables multiple target data sets to be sent sequentially according to a certain time order when they need to be sent, resulting in faster sending decisions and effectively improving the system's transmission performance.

[0016] In one possible implementation, the first processing unit and the first router are connected via an asynchronous message bus, wherein the asynchronous message bus includes a receive-ready signal line, a clock signal line, a message valid bit signal line, and one or more data lines. In this embodiment, the asynchronous message bus includes four signal lines: a receive-ready signal line, a clock signal line, a message valid bit signal line, and one or more data lines. The receive-ready signal line transmits a ready signal indicating that data reception is ready; the clock signal line transmits a first clock signal; the message valid bit signal line transmits the header and trailer signals of the target data; and one or more data lines transmit the valid data of the target data. These four signal lines significantly alleviate the problems of multiple and complex outgoing lines between the processing unit and the router in the prior art, reducing the chip area occupied by the entire asynchronous message bus. Optionally, depending on service requirements, the data lines can also be multiple data lines supporting multiple channels.

[0017] In one possible implementation, each of the aforementioned routers includes multiple sets of ports, each set of ports including a receiving port and a transmitting port, wherein each receiving port is used to receive data, and each transmitting port is used to transmit data. In this embodiment, the router is configured with a processing unit or other router connected to it via configurable ports. Through port-configurable routers, flexible reconfigurable network architectures are possible, such as point-to-point and multipoint-to-multipoint architectures. Furthermore, each port inside the router is connected to a receiving unit or a transmitting unit for sending and receiving data.

[0018] In one possible implementation, each of the aforementioned receiving ports corresponds to a receiving unit, and each of the aforementioned receiving units includes a storage area based on a first-in-first-out (FIFO) storage mechanism. Specifically, the first router is used to: receive the target data sent by the first processing unit through the storage area within the first receiving unit, driven by the target receiving port, based on the aforementioned first clock signal. The target receiving port is the receiving port in the first router connected to the first processing unit. In this embodiment, the FIFO storage mechanism enables the sequential transmission of multiple target data in a certain time order when they need to be sent, allowing the sending unit to make decisions faster during transmission and effectively improving the system's transmission performance. Furthermore, the storage area based on the FIFO storage mechanism can be applied to synchronous-to-asynchronous conversion methods, synchronously writing data (e.g., the processing unit synchronously writing target data to the sending unit) or reading data (e.g., the sending unit in the router synchronously reading data based on the storage area of ​​the receiving unit), and asynchronously reading data (e.g., the processing unit asynchronously sending target data from the sending unit in the processing unit to the router) or writing data (e.g., the first receiving unit in the router asynchronously writing data).

[0019] In one possible implementation, each of the aforementioned sending ports corresponds to a sending unit; the first router is specifically used to: determine the target sending port in the first router according to the destination address, wherein the target sending port is the sending port in the first router corresponding to the second processing unit; and send the target data to the second processing unit through the first sending unit corresponding to the target sending port. In this embodiment, a port-configurable router determines the target sending port corresponding to the first sending unit according to the destination address, and sends the target data to the second processing unit through that sending port. Moreover, in a communication connection formed by multiple routers, it is not necessary to determine the port number when receiving target data; data can be sent to the second processing unit according to the destination address.

[0020] In one possible implementation, each of the aforementioned routers includes a mapping table. This mapping table includes a mapping relationship between the port identifier of each of the aforementioned transmitting ports in the router and the unit identifier of the corresponding processing unit or the routing identifier of another of the aforementioned routers. The unit identifier is used to uniquely identify the processing unit, and the routing identifier is used to uniquely identify the router. Specifically, the first router is used to: determine the target transmitting port based on the destination address and the mapping table in the first router. In this embodiment, the routing forwarding mechanism by querying the mapping table simplifies the routing forwarding process and improves transmission efficiency.

[0021] In one possible implementation, when the second processing unit is connected to a second router, and the first router and the second router are two different routers among the plurality of routers, the target sending port is the sending port with the fewest hops to the second router among the first routers. Implementing this embodiment, in a communication connection formed by multiple routers, the case with the highest number of routing connection hops is one less than the number of routers. The router can automatically select the transmission path with the fewest connection hops to send the target data to the second processing unit based on the destination address.

[0022] In one possible implementation, the first router is specifically configured to: when the first sending unit receives a second request sent by the first receiving unit, control the first sending unit to retrieve the target data from the storage area of ​​the first receiving unit, wherein the second request is used to request the transmission of the target data through the first sending unit; and transmit the target data to the second processing unit through the first sending unit in a serial single-bit transmission manner based on the target transmission port. In this embodiment, by using a simple sending unit based on shared data, the storage area of ​​the receiving end's FIFO mechanism is reused, reducing data movement and improving transmission efficiency.

[0023] In one possible implementation, each of the aforementioned routers includes a channel selector; the channel selector of the first router is used to connect the data path from the first receiving unit to the first sending unit, so that the first sending unit can obtain the target data from the storage area of ​​the first receiving unit. In this embodiment, when there is a need to send data, the channel selector can connect the data path between the receiving unit and the sending unit, so that the sending unit can reuse the FIFO storage area of ​​the receiving unit through the data path, reducing data movement and greatly improving the transmission performance of the router.

[0024] In one possible implementation, each of the aforementioned routers includes an arbitrator, and each of the aforementioned sending units corresponds to one of the aforementioned arbitrators. The arbitrator of the first router is used to: when m receiving units simultaneously request data transmission from the first sending unit, determine a target receiving unit from the m receiving units according to a preset arbitration rule, where m is greater than 1 and less than or equal to the total number of receiving units included in the router. Optionally, the channel selector of the first router is further used to: after the arbitrator determines the target receiving unit, connect the data path from the target receiving unit to the first sending unit, so that the first sending unit can obtain data from the storage area of ​​the target receiving unit and send it. In this embodiment of the application, the arbitrator is used to implement a "many-to-one" fair arbitration mechanism, reducing conflicts when routing and forwarding data. To ensure the normal operation of each sending unit, there is a one-to-one correspondence between the arbitrator and the sending unit.

[0025] In one possible implementation, the arbitrator includes a second asynchronous handshake circuit. This second asynchronous handshake circuit of the first router is used to: determine a second clock signal based on the signal requesting data transmission sent by the target receiving unit to the first sending unit after determining that the data transmission status of the first sending unit is ready; the channel selector of the first router is specifically used to: connect the data path from the target receiving unit to the second sending unit based on the second clock signal. In this embodiment, the arbitrator in the router implements a fair arbitration mechanism in the data transmission device based on a simple token ring mechanism of handshake circuits such as Click circuits. Furthermore, the arbitrator achieves a high-performance data packet-based transmission mechanism by utilizing a common arbitration mechanism with timing dependencies on the receiving unit. It is understood that the arbitrator in this router is an asynchronous arbitrator.

[0026] In one possible implementation, the number of the second asynchronous handshake circuits in each of the aforementioned arbitrators is one less than the number of receiving ports in the aforementioned router. In this embodiment, to ensure that all receiving ports except the receiving port corresponding to the sending port need to send messages to the sending port, the number of the second asynchronous handshake circuits in the arbitrators is one less than the number of receiving ports in the router.

[0027] Secondly, embodiments of this application provide a data transmission method applied to a data transmission apparatus, the data transmission apparatus comprising: multiple processing units and multiple routers, each router being connected to one or more processing units, and each router forming a communication connection with any one of the multiple routers; wherein the multiple routers include a first router, the first router being connected to a first processing unit; the method comprising: generating a first request through the first processing unit, the first request being used to request that target data be sent to a second processing unit, the target data including a destination address of the second processing unit; determining a first clock signal based on the first request after the first processing unit determines that the first router is ready to receive data; sending the target data to the first router based on the first clock signal through the first processing unit, and sending the first clock signal to the first router; receiving the first clock signal through the first router; receiving the target data sent by the first processing unit based on the first clock signal through the first router; and sending the target data to the second processing unit through the first router according to the destination address.

[0028] In one possible implementation, the method further includes: after the first router finishes receiving the target data, adjusting the data receiving state of the first router from ready to not ready; and after the first processing unit detects that the data receiving state of the first router has changed from ready to not ready, determining that the target data transmission is complete.

[0029] In one possible implementation, each of the above processing units includes a first asynchronous handshake circuit; the first processing unit is specifically used to: determine the first clock signal based on the first request after determining that the first router is ready to receive data through the first asynchronous handshake circuit.

[0030] In one possible implementation, each of the above processing units includes an asynchronous message transmitter; the first processing unit is specifically configured to: based on the first request, control the asynchronous message transmitter to send the target data to the first router in a serial single-bit transmission manner based on the first clock signal.

[0031] In one possible implementation, the target data is transmitted in the form of a variable-length or fixed-length data packet. The method further includes: after generating the first request, the first processing unit sets the header of the target data and sends the header and the first clock signal to the first router; after the last bit of the target data is transmitted, the first router sets the trailer of the target data and transmits it; after receiving the header of the target data, the first router starts receiving the target data; after receiving the trailer of the target data, the first router changes its data reception status from ready to not ready.

[0032] In one possible implementation, each of the aforementioned processing units includes a storage area based on a first-in-first-out (FIFO) storage mechanism; the generation of the first request by the aforementioned first processing unit includes: generating the aforementioned first request after writing the aforementioned target data into the aforementioned FIFO storage area by the aforementioned first processing unit.

[0033] In one possible implementation, the first processing unit and the first router are connected via an asynchronous message bus, wherein the asynchronous message bus includes a receive ready signal line, a clock signal line, a message valid bit signal line, and one or more data lines.

[0034] In one possible implementation, each of the aforementioned routers includes multiple sets of ports, each set of ports including a receiving port and a transmitting port, wherein each of the aforementioned receiving ports corresponds to a receiving unit for receiving data, and each of the aforementioned transmitting ports corresponds to a transmitting unit for transmitting data.

[0035] In one possible implementation, each of the aforementioned receiving ports corresponds to a receiving unit, and each of the aforementioned receiving units includes a storage area based on a first-in-first-out (FIFO) storage mechanism; the aforementioned receiving of the target data sent by the first processing unit through the first router based on the first clock signal includes: based on the first clock signal, driving the storage area within the first receiving unit to receive the target data sent by the first processing unit through the target receiving port, wherein the target receiving port is a receiving port in the first router connected to the first processing unit.

[0036] In one possible implementation, each of the aforementioned transmission ports corresponds to a transmission unit; the aforementioned sending of the target data to the second processing unit via the first router according to the destination address includes: determining a target transmission port in the first router based on the destination address, wherein the target transmission port is a transmission port in the first router corresponding to the second processing unit; and sending the target data to the second processing unit via the first transmission unit corresponding to the target transmission port.

[0037] In one possible implementation, each of the routers includes a mapping table that includes a mapping relationship between the port identifier of each of the transmitting ports in the router and the unit identifier of the corresponding processing unit or the routing identifier of the other router, wherein the unit identifier is used to uniquely identify the processing unit and the routing identifier is used to uniquely identify the router; determining the target transmitting port in the first router according to the destination address includes: determining the target transmitting port based on the mapping table in the first router according to the destination address.

[0038] In one possible implementation, when the second processing unit is connected to the second router, and the first router and the second router are two different routers among the plurality of routers, the target sending port is the sending port with the fewest hops to the second router among the first routers.

[0039] In one possible implementation, sending the target data to the second processing unit through the first sending unit corresponding to the target sending port includes: when the first sending unit receives a second request sent by the first receiving unit, controlling the first sending unit to retrieve the target data from the storage area of ​​the first receiving unit, wherein the second request is used to request the sending of the target data through the first sending unit; and sending the target data to the second processing unit through the first sending unit in a serial single-bit transmission manner based on the target sending port.

[0040] In one possible implementation, each of the routers includes a channel selector; the method further includes: connecting the data path from the first receiving unit to the first transmitting unit via the channel selector of the first router, so that the first transmitting unit obtains the target data from the storage area of ​​the first receiving unit.

[0041] In one possible implementation, each of the routers includes an arbitrator, and each of the sending units corresponds to one of the arbitrators; the method further includes: when m receiving units simultaneously request to send data to the first sending unit, determining a target receiving unit from the m receiving units through the arbitrator of the first router according to a preset arbitration rule, where m is greater than 1 and less than or equal to the total number of the receiving units included in the router.

[0042] In one possible implementation, the method further includes: after the arbitrator determines the target receiving unit, connecting the data path from the target receiving unit to the first sending unit through the channel selector of the first router, so that the first sending unit can obtain data from the storage area of ​​the target receiving unit and send it.

[0043] In one possible implementation, the arbitrator includes a second asynchronous handshake circuit; the process of connecting the data path from the target receiving unit to the first transmitting unit via the channel selector of the first router after the arbitrator determines the target receiving unit includes: after determining that the transmitting data status of the first transmitting unit is ready, determining a second clock signal based on the signal requesting data transmission sent by the target receiving unit to the first transmitting unit via the second asynchronous handshake circuit of the first router; and connecting the data path from the target receiving unit to the second transmitting unit via the channel selector of the first router based on the second clock signal.

[0044] In one possible implementation, the number of the second asynchronous handshake circuits in each of the aforementioned arbitrators is one less than the number of receive ports in the aforementioned router.

[0045] Thirdly, embodiments of this application provide a computer-readable storage medium for storing computer software instructions used for a data transmission apparatus provided in the first aspect, which includes a program designed to execute the above aspect.

[0046] Fourthly, embodiments of this application provide a computer program product including instructions that, when executed by a computer, enable the computer to perform the processes executed by the data transmission device described in the first aspect.

[0047] Fifthly, this application provides a chip system that includes the apparatus provided in the first aspect and any implementation thereof. The chip system is used to implement the functions of the apparatus involved in the first aspect. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for data transmission. The chip system may be composed of chips or may include chips and other discrete devices.

[0048] Sixthly, embodiments of this application provide an electronic device that includes the apparatus provided in accordance with the first aspect and any implementation thereof. This electronic device is used to implement the functions involved in the first aspect.

[0049] In this embodiment, the data transmission device based on the asynchronous handshake mechanism generates a first clock signal based on the request to send data by the processing unit (first processing unit) after determining that the router (first router) is ready to receive data. The first clock signal and the target data are then sent to the router according to the first clock signal, allowing the router connected to the processing unit to receive the target data via the first clock signal. The router then sends the target data to the second processing unit based on the destination address carried in the received target data. This asynchronous handshake transmission method between the processing unit and the router ensures that the router receives the target data completely. Furthermore, the processing unit also sends the clock signal (i.e., the first clock signal) used to send the target data to the router, enabling the router to receive data based on this clock signal. This reduces clock constraints within the data transmission device, making it easier to integrate various heterogeneous processing units or intellectual property cores. It also allows multiple routers to operate without synchronization clock limitations, resulting in faster decision-making and effectively improving system transmission performance. Moreover, the relatively short and relatively deterministic data cable between the processing unit and the router further reduces the latency of the corresponding clock signal when the processing unit needs to send data, ensuring a relatively stable latency. Meanwhile, in this embodiment of the application, a router can be asynchronously connected to multiple processing units simultaneously, which greatly reduces the chip area occupied by the bus. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0051] Figure 1 This is a schematic diagram of the structure of a data packet provided in an embodiment of this application.

[0052] Figure 2 This is a schematic diagram of the structure of a data transmission device provided in an embodiment of this application.

[0053] Figure 3 This is a schematic diagram of another data transmission device provided in an embodiment of this application.

[0054] Figure 4 This is a schematic diagram of the structure of an asynchronous message transceiver provided in an embodiment of this application.

[0055] Figure 5 This is a circuit diagram of a Click unit provided in an embodiment of this application.

[0056] Figure 6 This is a schematic diagram of the working timing of a Click unit in working mode, provided in an embodiment of this application.

[0057] Figure 7 This is a schematic diagram of the structure of a transmitting unit provided in an embodiment of this application.

[0058] Figure 8 This is a schematic diagram of an asynchronous message sending process provided in an embodiment of this application.

[0059] Figure 9 This is a schematic diagram of the structure of a receiving unit provided in an embodiment of this application.

[0060] Figure 10 This is a schematic diagram of the structure of a router provided in an embodiment of this application.

[0061] Figure 11 This is a schematic diagram of a simple data transmission device provided in an embodiment of this application.

[0062] Figure 12 This is a block diagram of a router implementation provided in an embodiment of this application.

[0063] Figure 13 This is a schematic diagram of a router forwarding process provided in an embodiment of this application.

[0064] Figure 14 This is a schematic diagram of an arbitration process provided in an embodiment of this application.

[0065] Figure 15 This is a schematic diagram of the internal circuit structure of an arbitrator provided in an embodiment of this application.

[0066] Figure 16 This application provides a method based on... Figure 7 A schematic diagram of the expanded transmitting unit.

[0067] Figure 17 This application provides a method based on... Figure 7 The diagram shows the data packet transmission effect of the sending unit.

[0068] Figure 18 This application provides a method based on... Figure 16 The data packet transmission effect of the sending unit shown.

[0069] Figure 19 This application provides a method related to... Figure 16 The corresponding implementation block diagram of the extended router.

[0070] Figure 20 This is a flowchart illustrating a data transmission method provided in an embodiment of this application. Detailed Implementation

[0071] The embodiments of this application will now be described with reference to the accompanying drawings.

[0072] The terms "first" and "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0073] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0074] It should be understood that in this application, "at least one (item)" means one or more, and "more than one" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "a and / or b" can represent: only a exists, only b exists, and both a and b exist simultaneously, where a and b can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0075] As used in this specification, the terms "component," "module," "system," etc., are used to refer to computer-related entities, hardware, firmware, combinations of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. As illustrated, applications running on computing devices and computing devices can both be components. One or more components may reside in a process and / or an execution thread, and components may be located on a single computer and / or distributed among two or more computers. Furthermore, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system, and / or a network, such as the Internet, which interacts with other systems via signals).

[0076] Data transmission can be categorized into two main methods: serial transmission and parallel transmission. Serial transmission involves transmitting data bit-by-bit along a single signal line. For example, one bit might be transmitted at a time using a single data line, with multiple bits transmitted sequentially one after another. Parallel transmission, on the other hand, divides data into blocks of a predetermined number of bits. These blocks are then transmitted simultaneously via multiple data lines, each carrying a set number of bits. In other words, parallel transmission distributes data across multiple signal lines, using multiple parallel data lines to transmit multiple bits at once.

[0077] The difference between serial transmission and parallel transmission:

[0078] 1. Due to transmission characteristics, parallel transmission cables occupy much more space than serial transmission cables.

[0079] 2. In parallel transmission, if the physical properties of the parallel lines are inconsistent, such as slight differences in length or different cable materials, the bits transmitted in the parallel lines will not arrive at the receiver simultaneously, making it easy for the receiver to make mistakes when receiving data.

[0080] 3. Serial transmission has a higher transmission frequency than parallel transmission.

[0081] 4. The cost of parallel transmission lines is several times that of serial transmission lines.

[0082] Corresponding to serial and parallel transmission are asynchronous and synchronous communication methods. In asynchronous communication, the time slots between units of data transmitted can be arbitrary. However, the receiving end must be ready to receive at all times. Since the sending end can start sending characters at any time, start and stop bits must be added at the beginning and end of each character to ensure the receiving end can correctly receive each character. Synchronous communication is a bit-synchronous communication technology that requires both the sender and receiver to have synchronized clock signals of the same frequency and phase. A specific synchronization character is appended to the beginning of the transmitted message to establish synchronization between the sender and receiver, after which transmission / reception is performed bit by bit under the control of the synchronized clock. Compared to synchronous communication, asynchronous communication has the advantages of simpler and cheaper communication equipment, and most importantly, it does not require strict control clock synchronization.

[0083] With the deepening of internetization and industry digitalization, the number of integrated IP cores between chips has increased from dozens to hundreds. This necessitates more interconnections and bandwidth between IPs to support increasingly larger real-time data communications. Moreover, since current IP cores use synchronous circuit design technology, they require strict clock synchronization and are becoming increasingly large in scale. Therefore, under high clock frequencies and large data bit widths, the latency introduced by the placement and routing of IP cores within the SoC chip cannot be ignored, leading to a significant increase in the design complexity of larger SoC chips. Therefore, to simplify chip design complexity, reduce development investment and cycle time, while ensuring chip computing power, the chip architecture in this application adopts a combination of asynchronous communication and serial transmission, and connects as many processing units as possible to a single routing node, simplifying chip design complexity and reducing chip area.

[0084] First, in the data transmission device of this application embodiment, the transmitted data can be in the form of a data packet. This data packet can be of fixed length or variable length. This application embodiment takes a variable-length data packet as an example, and the data packet structure is as follows: Figure 1 Please refer to the appendix for details. Figure 1 , Figure 1 This is a schematic diagram of the structure of a data packet provided in an embodiment of this application. For example... Figure 1 As shown, the fields of this data packet are defined as follows:

[0085] The first field is the destination address of the data packet, which identifies the recipient of the data packet (the second processing unit). The length of this field can be extended according to the actual bus size. For example, a 3-bit identifier. In this embodiment, it can be the communication address of the second processing unit.

[0086] The second field is the packet length field, which indicates the effective data length of the packet, such as... Figure 1As shown, the effective data in the data packet is in 2-bit units of length. The length field indicates that the effective data is a multiple of 2 bits, i.e., 2 * length value.

[0087] The third field is the valid data of the data packet, which stores the information to be transmitted by the data packet. The specific format can be agreed upon according to design needs, and this application embodiment does not impose specific limitations.

[0088] The fourth field is the data packet transmission check bit, which checks whether errors are introduced during transmission. The check method can be selected according to the actual scenario. For example, parity checking can be used, but this application embodiment does not specifically limit it.

[0089] It should be noted that the embodiments in this application are described using the transmission of the data packet in a data transmission device as an example, and are not limited to the specific transmission form of the data in this data architecture. For example, the data can also be transmitted in the form of data frames, data blocks, etc.

[0090] Next, in this application embodiment, the transmitted data is as follows: Figure 1 Using the data packet shown as an example, this paper briefly introduces the data transmission device combining asynchronous communication and serial transmission in the embodiments of this application. Please refer to the appendix. Figure 2 , Figure 2 This is a schematic diagram of a data transmission device provided in an embodiment of this application. In the schematic diagram of the data transmission device, the circle represents the processing unit 01, and the square represents the router 02.

[0091] like Figure 2 As shown: The device includes multiple processing units 01 and multiple routers 02. The routers 02 can form connection paths, and each router 02 is connected to one or more processing units 01, with each processing unit 01 having one and only one corresponding router 02 connected to it. That is, each router 02 can connect to multiple processing units 01, but each processing unit 01 can only connect to one router 02. Furthermore, each router 02 can form a communication connection with any one of the multiple routers 02. That is, any one of the multiple routers 02 can transmit data with any other router 02; furthermore, a processing unit 01 connected to one router 02 can transmit data with a processing unit 01 connected to another router 02 through one or more routers 02. For example: Figure 2 As shown, the data in processing unit 101 can be transmitted to processing unit 103 through router 102 and router 104.

[0092] Optionally, multiple routers can be connected in a back-to-back cascade configuration to reduce router cabling, shorten the interconnection cable length, and reduce transmission latency. Back-to-back cascading involves directly connecting the receive and transmit ports of two interconnected routers via data cables, wires, or other data transmission media. In other words, the two interconnected routers are connected directly through relevant data transmission media without a communication network. For example, the transmit port of the sending router is directly connected to the receive port of the receiving router.

[0093] Optionally, the router and the processing unit can also be connected in a back-to-back cascade manner.

[0094] The first processing unit in the data transmission device is configured to: generate a first request, the first request being used to request that target data be sent to a second processing unit, the target data including the destination address of the second processing unit; after determining that the first router is ready to receive data, determine a first clock signal based on the first request; send the target data to the first router based on the first clock signal, and send the first clock signal to the first router.

[0095] The first router is configured to: receive the first clock signal; receive the target data sent by the first processing unit based on the first clock signal; and send the target data to the second processing unit according to the destination address.

[0096] In this embodiment, the data transmission device based on the asynchronous handshake mechanism generates a first clock signal based on the request to send data by the processing unit (first processing unit) after determining that the router (first router) is ready to receive data. The first clock signal and the target data are then sent to the router according to the first clock signal, allowing the router connected to the processing unit to receive the target data via the first clock signal. The router then sends the target data to the second processing unit based on the destination address carried in the received target data. This asynchronous handshake transmission method between the processing unit and the router ensures that the router receives the target data completely. Furthermore, the processing unit also sends the clock signal (i.e., the first clock signal) used to send the target data to the router, enabling the router to receive data based on this clock signal. This reduces clock constraints within the data transmission device, making it easier to integrate various heterogeneous processing units or intellectual property cores. It also allows multiple routers to operate without synchronization clock limitations, resulting in faster decision-making and effectively improving system transmission performance. Moreover, the relatively short and relatively deterministic data cable between the processing unit and the router further reduces the latency of the corresponding clock signal when the processing unit needs to send data, ensuring a relatively stable latency. Meanwhile, in this embodiment of the application, a router can be asynchronously connected to multiple processing units, which greatly reduces the chip area occupied by the bus.

[0097] It should be noted that the processing unit of the data transmission device may include intellectual property (IP) cores, microprocessors, central processing units (CPUs), digital signal processing (DSPs), graphics processing units (GPUs), neural network processing units (NPUs), and other related processing entities (PEs) capable of data processing.

[0098] It should also be noted that the data transmission device structure provided in the embodiments of this application is not limited to the one described above. Figure 2 The closed structure shown can also include non-closed structures. For example: please refer to the appendix. Figure 3 , Figure 3 This is a schematic diagram of another data transmission device provided in an embodiment of this application. Figure 3As shown, the device includes multiple processing units 01 and multiple routers 02. The routers 02 can form interconnected paths. Each router 02 is connected to at least two processing units 01, and each processing unit 01 has one and only one corresponding router 02 connected to it. Figure 2 Unlike the illustrated device, this data transmission device has multiple routers arranged in a chain, and the number of hops in the longest transmission path during data transmission is one less than the number of routers in the data transmission device. Therefore, this application embodiment does not specifically limit the connection structure of the data transmission device.

[0099] The following example, taking the processing unit sending data to the router, briefly introduces the exemplary electronic devices and related logic modules involved in the asynchronous serial transmission method in this application embodiment.

[0100] (I) Asynchronous Message Receiver

[0101] Both the processing unit 01 and the router 02 in this embodiment may include an asynchronous transceiver, which can transmit and receive target data in an asynchronous serial transmission mode.

[0102] The asynchronous transceiver includes a transmitting unit and a receiving unit. The transmitting unit includes an asynchronous handshake circuit and an asynchronous message transmitter. The asynchronous handshake circuit is used to provide a self-timing clock signal (equivalent to the first clock signal in this application) to the asynchronous message transmitter so that the asynchronous message transmitter transmits the target data in a serial single-bit transmission manner according to the self-timing clock signal.

[0103] The receiving unit is used to receive target data.

[0104] Taking the example of the processing unit sending data to the router, please refer to the appendix. Figure 4 , Figure 4 This is a schematic diagram of the structure of an asynchronous message transceiver provided in an embodiment of this application. Figure 4 As shown: The sending end includes a sending unit tx (also known as an asynchronous message sending unit, second sending unit, etc.) and a message packet management unit of the processing unit; the receiving end includes a receiving unit rx (also known as an asynchronous message receiving unit, first receiving unit, etc.) of the router and a message packet management unit.

[0105] The sending end's message packet management unit (msg) uses a FIFO-based message packet management mechanism to drive asynchronous message sending and receiving units to transmit data packets, thus implementing an asynchronous message packet transmission mechanism. FIFO stands for First-In-First-Out (FIFO), meaning the target data that enters this message packet management unit first is sent first. Furthermore, this sending end's message packet management unit can synchronously receive target data sent by the processing unit, including one or more of the following: data transmission indicator bits (start bit (msg_bn) and end bit (msg_end)), valid data, and a synchronization clock. It can also send receive indicator bits (indicating data received) and feedback on the data transmission status (success or failure) to the processing unit.

[0106] The receiver's message packet management unit (msg) is also based on the FIFO message packet management mechanism. Furthermore, this receiver's message packet management unit can send target data to the router or processing unit, including data transmission indication bits (start bit (msg_bn) and end bit (msg_end) of the data packet), valid data, and an asynchronous self-clock, etc. It can also receive receive indication bits (data received) and feedback on data transmission status (success or failure) sent by the router or processing unit.

[0107] Transmitting and receiving units: They can implement 1. a serial single-bit transmission mechanism. Because the router and processing unit are connected back-to-back in a cascaded transmission architecture, transmitting and receiving units at different ends (e.g., between different processing units and routers, or between different routers) can send or receive data (e.g., ...) through one or more data lines. Figure 4 (e.g., sending data), for example: the serial single-bit transmission mechanism of this application can be implemented through a single data line. 2. Shortening data transmission delay. Since the smallest transmission unit of data between the sending unit and the receiving unit in this application embodiment can be a data packet, that is, this application embodiment adopts a packet-based asynchronous handshake mechanism instead of the asynchronous single-bit handshake mechanism, thus shortening the transmission delay (e.g., as...). Figure 4 The message sends an indication bit, and the start bit (msg_bn) and end bit (msg_end) of the packet are determined by signals transmitted through the message validity bit signal line. 3. Simplify timing analysis for integration and interfacing. Because asynchronous timing is used between different ends (such as... Figure 4 It features a self-synchronizing timing mechanism (self-clocking), and eliminates the need for strict clock synchronization between different receiving units of a router, further simplifying timing analysis for integration and interfacing, and making it easy to expand according to business needs.

[0108] It should be noted that the specific implementation process between the above-mentioned sending unit and receiving unit can be found in the relevant descriptions of the following embodiments of the sending unit and receiving unit device and method, which will not be repeated here.

[0109] a. Transmitting unit

[0110] The sending unit includes an asynchronous handshake circuit and an asynchronous message transmitter. The asynchronous handshake circuit provides a self-timing clock for the asynchronous message transmitter, and the asynchronous message transmitter sends the target data to the router in a serial single-bit transmission mode according to the self-timing clock signal.

[0111] Asynchronous handshake circuit

[0112] First, let me briefly introduce the asynchronous handshake circuit involved in the embodiments of this application. This handshake circuit can be called a click element, hereinafter referred to as the Click unit. The Click unit can provide a self-timing clock for the asynchronous message transmitter. Moreover, due to its simple design, the Click unit can greatly simplify the design complexity of converting a synchronous circuit into an asynchronous circuit. Specifically, the Click unit generates a self-timing clock through a self-loop to drive the asynchronous message transmitter to continuously send serial data. The delay of the self-loop is determined by the maximum delay from the sending unit to the receiving unit.

[0113] Please refer to the attached document. Figure 5 , Figure 5 This is a circuit diagram of a Click unit provided in an embodiment of this application. The Click unit includes: two AND gates, one OR gate, and a phase-locked register.

[0114] An AND gate is a basic logic gate that performs the AND operation. This circuit has multiple inputs and one output. The output is high only when all inputs are simultaneously high (logic 1); otherwise, the output is low (logic 0).

[0115] An OR gate is a circuit that performs logical addition, also known as a logical AND circuit. This circuit has two or more inputs and one output. The output of the OR gate is high (logic 1) as long as one or more inputs are high (logic 1). The output is low (logic 0) only when all inputs are low (logic 0).

[0116] A phase-locked register (PLC) is used to toggle the level of the signal corresponding to B.ack in this embodiment of the application. That is, when the level of B.ack changes, the changed level is toggled back. For example, if B.ack changes from low to high, the PLC can change the high level back to low.

[0117] That is, the final output of the Click unit is Fire = -A.req * A.ack * B.ack + A.req * -A.ack * -B.ack. Here, -A.req is the inverted signal of A.req. For example, when A.req is high, -A.req is low. Similarly, -A.ack and -B.ack are the inverted signals of A.ack and B.ack, respectively. Generally, a high level is 1, and a low level is 0.

[0118] The Click unit handshake circuit includes: a forward handshake signal line, a backward handshake signal line, and a self-clock signal line.

[0119] 1. The forward handshake signal lines consist of two signal lines: request and response, such as... Figure 5 In A.req, A.ack;

[0120] 2. The backward handshake signal lines consist of two signal lines: request and response, such as... Figure 5 B.req, B.ack;

[0121] 3. Self-clock signal line, such as Figure 5 Fire.

[0122] The self-clock signal line Fire can drive data storage devices based on the first-in-first-out mechanism (such as registers, serial FIFO memories, and FIFO queues) to output data according to the self-clock signal Fire.

[0123] Please refer to the attached document. Figure 6 , Figure 6 This is a timing diagram illustrating the operation of a Click unit in its working mode, as provided in an embodiment of this application. The circuit operating mode of the Click unit includes, for example... Figure 6 As shown: the signal in_req is as described above. Figure 5 The signal output from the A.req signal line, in_ack is as described above. Figure 5 The signal output from the B.ack signal line, out_req is as described above. Figure 5 The signal output from the B.req signal line, out_ack is as described above. Figure 5 The signal output from the A.ack signal line.

[0124] That is, Fire=-in_req*out_ack*in_ack+in_req*-out_ack*-in_ack.

[0125] In this Click unit, the forward handshake signal line A.req and the backward handshake signal line B.ack are the two input signal lines, and the forward handshake signal line A.ack and the backward handshake signal line B.req are the two output signal lines. In this embodiment, when a request to send target data is received, the input signal in_req changes from low level to high level (rising edge), which triggers the Click unit to self-clock Fire and send data.

[0126] At the same time, by Figure 6 As shown in the timing diagram, this Click unit implements a 4-phase handshake protocol, where both the rising and falling edges of the request can be generated from the timing clock, i.e. Figure 6 The Fire shown.

[0127] It should be noted that other circuits may also be used to provide a self-timing clock in the embodiments of this application, and the embodiments of this application do not make specific limitations on this.

[0128] It should also be noted that the specific application process of the Click unit in this application embodiment should be referred to the relevant description of the device embodiment below, which will not be described in this application embodiment.

[0129] Secondly, based on the above Figure 4 Taking the sending end as an example, this section describes the implementation methods of the sending unit on the processing unit side when the processing unit sends target data to the router. Please refer to the appendix. Figure 7 , Figure 7 This is a schematic diagram of the structure of a transmitting unit provided in an embodiment of this application. For example... Figure 7 As shown: The sending unit may include a Click unit and an asynchronous message sender, and may also include an asynchronous message bus. Among them,

[0130] An asynchronous message bus refers to the data lines connecting the receiving unit and the transmitting unit. The transmitting unit side includes four signal lines: a receive-ready signal line, a self-clock signal line, a message valid bit signal line, and a data line (signal lines for transmitting data). The receive-ready signal line is used to transmit the indicator bit, the self-clock signal line is used to transmit the self-clock timer, the message valid bit signal line is used to transmit the packet header and trailer, and the data line is used to transmit valid data.

[0131] The Click unit (equivalent to the first asynchronous handshake circuit in this application) generates its own timing clock via a self-loop mechanism to drive the asynchronous message transmitter to continuously send serial data. The self-loop delay in the Click unit is determined by the maximum delay from the sending unit on the processing unit side to the receiving unit on the router side. It should be noted that the maximum delay can be determined by physical quantities affecting data transmission time, such as the length and material of the data cable connecting the sending unit on the processing unit side and the receiving unit on the router side. It should also be noted that the method by which the Click unit generates its own timing clock can be referenced to the above. Figures 5 to 6 The descriptions of the relevant embodiments are not repeated here.

[0132] The asynchronous message transmitter, driven by the self-timing clock provided by the Click unit, reads the serial FIFO (based on FIFO storage medium) and the valid bits of the data packet, outputs data to the data lines and message valid bits of the asynchronous message bus, and simultaneously outputs its own self-timing clock to the asynchronous message bus's self-timing clock after a certain delay. For example, Figure 7 As shown: The asynchronous message sender includes an asynchronous message sending and processing flow, message length len, asynchronous serial FIFO, packet encapsulation module M, and valid data D. Please refer to the appendix. Figure 8 , Figure 8 This is a schematic diagram of an asynchronous message sending and processing flow provided in an embodiment of this application. For example... Figure 8 As shown, the asynchronous message sending process can start message packet sending, call `message_len` to check if the message length is greater than 0; if so, set the send request signal `A.req`; set the message validity bit to valid; wait for sending to complete and set `A.ack`, shift out one bit of data in the asynchronous serial FIFO, and simultaneously decrement `message_len` by 1; repeat this process until the message length `message_len` is 0, then set the message sending to complete and set the message validity bit to invalid. Here, `message_len` is used to count the packet length of the target data, and `valid data D` is the valid data in the target data.

[0133] Taking the sending unit sending target data to the router as an example, the specific steps of the asynchronous message transceiver sending data in the sending unit on the processing unit side are as follows:

[0134] 1. Write the message to be sent. The processing unit first writes the data packet to be sent from the data interface to the asynchronous serial FIFO in the asynchronous message sender.

[0135] 2. Initiate transmission. The processing unit notifies its asynchronous message transmission unit to initiate the asynchronous message transmission process and start sending data.

[0136] 3. Set packet header and wait for reception. The asynchronous message sending unit sets the packet header in the packet encapsulation module M and waits for the receiving end of the routing node to become ready for reception.

[0137] 4. Request to send. If the receive readiness status becomes valid, a request to send is sent to the Click unit in the asynchronous message sending unit.

[0138] 5. Send Bits. The Click unit triggers the clock to send the packet header, the first bit of data, and the corresponding clock pulse to the asynchronous message bus.

[0139] 6. This bit transmission is complete. According to the preset delay circuit, the Click unit reports back to itself whether the transmission of this bit is complete. It should be noted that the delay duration determined by this delay circuit is determined by the distance between the data transmission unit and the receiving unit.

[0140] 7. Next bit. Once transmission is detected as complete, the Click unit notifies the asynchronous message sending unit that the first bit can be sent. If the message is not finished, steps 4 to 7 above are repeated until the last bit of the message.

[0141] 8. Set the packet trailer. After detecting the last bit, the asynchronous message sending unit sets the packet trailer in the data packet module M, repeating steps 4-7 above.

[0142] 9. Reception complete. After detecting the end of the packet, the receiving end of the routing node sets the receive ready signal to invalid, indicating that the message has been successfully received.

[0143] 10. Transmission Complete. Upon detecting a message reception completion signal, the transmitting unit of the processing unit notifies its local processing unit that transmission is complete.

[0144] b. Receiving unit

[0145] Additionally, please refer to the appendix. Figure 9 , Figure 9 This is a schematic diagram of the structure of a receiving unit provided in an embodiment of this application. Figure 9 As shown, the receiving unit may consist of two parts: an asynchronous message bus and an asynchronous message receiver.

[0146] The asynchronous message bus refers to the data lines connecting the receiving unit and the transmitting unit. The receiving unit side includes four signal lines (connected to the transmitting unit side): a receive-ready signal line, a self-timing clock signal line, a message valid bit signal line, and a data line (signal lines for transmitting data). The receive-ready signal line is used to transmit the indicator bit, the self-timing clock signal line is used to transmit the self-timing clock, the message valid bit signal line is used to transmit the packet header and trailer, and the data line is used to transmit valid data.

[0147] The asynchronous message receiver comprises an asynchronous message reception processing flow and an asynchronous serial FIFO. The asynchronous message reception processing flow monitors the data reception process and stores data packets in the asynchronous serial FIFO. Since the transmitting unit transmits its own timing clock via the asynchronous message bus, the receiving unit can directly use this clock signal to receive data transmitted by the transmitting unit. The receiving unit needs to wait for a message transmission completion signal or event to notify downstream processing units or routers to read the received data packets.

[0148] Among them, the above Figure 4 Taking the router as the receiving end as an example, this section introduces the relevant implementation methods of the router-side receiving unit when the sending unit sends target data to the router. Figure 9 As shown: The specific steps of the data receiving process of the receiving unit are as follows:

[0149] 1. Ready to receive. When a request to send data is received from the asynchronous message sending unit, the local end (the receiving unit in the router) confirms that it can receive the new data packet and sets the receive ready signal.

[0150] 2. Packet header detected. Upon detecting the packet header signal, receive data and data packet length statistics are initiated.

[0151] 3. Data reception. Based on the self-clock of the peer (the transmitting unit in the processing unit), the local FIFO receives data and updates the packet length statistics.

[0152] 4. Packet tail detected. The detection of the packet tail signal confirms that the message has been successfully received.

[0153] 5. Reception complete. The local end sets a reception complete signal to notify the other end that the message has been received. That is, the receive ready signal is set to invalid, indicating that the message has been received.

[0154] 6. Message ready. A message notifying the local processing unit (the processing unit receiving the target data) that the message is ready.

[0155] 7. Read received messages. The local processing unit reads the received data packets through the data interface.

[0156] 8. Read complete. After reading the data packet, the local processing unit sets the read complete signal. The local interface unit detects this signal and repeats step 1 to prepare to receive the next data packet.

[0157] It should be noted that steps 6-8 are the steps for two processing units to transmit target data when they are connected to the same router and there is no transmission conflict.

[0158] Since the smallest transmission unit between the sending unit and the receiving unit in this embodiment is a data packet, that is, this embodiment uses a packet-based asynchronous handshake mechanism instead of an asynchronous single-bit handshake mechanism, thus shortening the transmission delay (e.g., as shown in the example). Figure 4 The packet sends indicator bits to determine the start bit (msg_bn) and end bit (msg_end). Furthermore, asynchronous timing is used between different ends (e.g., ...). Figure 4 It features a self-synchronized timing clock, eliminating the need for strict clock synchronization, simplifying timing analysis for integration and interfacing, and making it easy to expand according to business needs.

[0159] In summary, both the router and the processing unit in this embodiment include a receiving unit and a transmitting unit. The structure and function of the receiving and transmitting units in both the router and the processing unit can be referenced from the descriptions in the above embodiments. For example, the receiving unit of the first router and the transmitting unit of the first processing unit can implement: 1. an asynchronous serial single-bit transmission mechanism; 2. reduced data transmission latency; and 3. simplified timing analysis for integration and interfacing.

[0160] (II) Router

[0161] The router is configured with multiple sets of routing ports. Each set of routing ports includes a receiving port and a transmitting port. The receiving port of each set of routing ports is also connected to a receiving unit, and the transmitting port of each set of routing ports is connected to a transmitting unit.

[0162] The router includes asynchronous transceiver units (i.e., receiving or transmitting units connected to various ports), a mapping table, route arbitration, and a channel selector. Please refer to the appendix. Figure 10 , Figure 10 This is a schematic diagram of the structure of a router provided in an embodiment of this application. Figure 10 As shown:

[0163] Asynchronous transceiver unit: Receives and sends message packets from the routing port. The asynchronous transceiver unit in a router also includes a receiving unit and a sending unit (i.e., RX and TX).

[0164] As mentioned above Figure 10 As shown: The asynchronous transceiver unit includes multiple receiving units and transmitting units. Each receiving unit and each transmitting unit corresponds to a port. For example: receiving unit RX0 corresponds to receiving port A, receiving unit RX1 corresponds to receiving port B, receiving unit RX2 corresponds to receiving port C, and receiving unit RX3 corresponds to receiving port D; transmitting unit TX0 corresponds to transmitting port A, transmitting unit TX1 corresponds to transmitting port B, transmitting unit TX2 corresponds to transmitting port C, and transmitting unit TX3 corresponds to transmitting port D.

[0165] It should be noted that the receiving and transmitting units in the router have the same transmission mechanism as the asynchronous transceiver in Embodiment (I) above, which can achieve: 1. a serial single-bit transmission mechanism; 2. reduced data transmission latency; 3. simplified timing analysis for integration and interfacing, etc., which will not be elaborated further in this embodiment.

[0166] Mapping table: This table contains the connection relationships between each sending port of this router and processing units or other routers, enabling the router to configure the mapping table according to the SoC topology and look up the sending port of a message packet. The mapping table includes the destination port number and the sending port number of this router. The destination port number includes the unit identifier of the processing unit connected to that port, the router's routing identifier, or the communication code and communication address corresponding to that port (e.g., the destination address contained in the data packet), etc. The unit identifier is used to uniquely identify the processing unit, and the routing identifier is used to uniquely identify the router.

[0167] Please refer to the attached document. Figure 11 , Figure 11 This is a schematic diagram of a simple data transmission device provided in an embodiment of this application. The data transmission device includes two routers and six processing units, wherein each router is connected to three processing units. Figure 11 The connection relationships are shown below, and the mapping table for each router of this data transmission device is as follows:

[0168] Table 1: Mapping table for Router 1

[0169] 1-Processing Unit 1 1 2-Processing Unit 2 2 3-Processing Unit 3 3 other 4

[0170] Table 2: Mapping table for Router 2

[0171] 4-Processing Unit 4 1 5-Processing Unit 5 3 6-Processing Unit 6 4 other 2

[0172] It should be noted that each router only stores the mapping table corresponding to its own local ports.

[0173] Arbitrator: Each sending port corresponds to an arbitrator. Under the condition of meeting the arbitration conditions (such as when multiple receiving ports send messages to a sending port at the same time), only one receiving port's sending request is processed at a time, and each receiving port gets a fair chance to send.

[0174] Channel selector: Connects or disconnects the data channel from the receive port to the send port. For example, if arbitration conditions are met, the data channel from the receive port to the send port is connected or disconnected based on the arbitration result of the arbitrator. Another example: disconnects the data channel from the receive port to the send port after data transmission is complete.

[0175] Based on the above Figure 10The diagram below illustrates the router's structure. Taking the example of sending a message packet from port A to port D, the router's forwarding process is described below. The specific steps are as follows: Please refer to the appendix. Figure 12 and Figure 13 , Figure 12 This is a block diagram illustrating the implementation of a router according to an embodiment of this application. Figure 13 This is a schematic diagram of a router forwarding process provided in an embodiment of this application. Wherein, as... Figure 12 As shown, ports A, B, and C can all send data requests to the arbitrator at port D; the arbitrator selects port A, B, or C to send data to port D; after the channel selector obtains the sending port determined by the arbitrator, it establishes the data channel between port A, B, or C and port D; it receives the following from port A, B, or C: 1. Sending request; 2. Message validity bit (i.e., the header or trailer of the data packet); 3. Data bits; 4. and sends feedback to continue sending the next data bit.

[0176] Taking sending data from port A to port D as an example, such as Figure 13 As shown:

[0177] 1. After receiving a message packet, the receiving unit of port A of the router extracts the encoding of the destination processing unit and finds the corresponding port, such as port D, through the encoding of the destination processing unit.

[0178] 2. The receiving unit of port A requests the arbitrator of the port to send a message packet.

[0179] 3. After confirming that port D is ready to send, the arbitrator starts arbitration. If there is no conflict, it directly decides to send a message packet to port A.

[0180] 4. The arbitrator sends a signal to the channel selection unit to select port A, thus enabling the data channel between port A and port D.

[0181] 5. After the data channel is established, the transmit ready signal of port D can be sent to port A.

[0182] 6. After detecting the transmit ready signal of port D, port A starts sending message packets.

[0183] 7. After sending the message, notify the arbitrator that the sending is complete.

[0184] 8. The receiving port A also releases the request at the same time.

[0185] 9. After receiving the completion signal of transmission from port D and the release request signal from port A, the arbitrator notifies the channel selection unit to release the data channels of port A and port D, thus completing a full transmission process.

[0186] Arbitrator in router

[0187] Since the arbitrator in this application does not have an arbitration protection window with a synchronized clock cycle, the existing synchronous arbitrator mechanism cannot be fully reused. Therefore, it is necessary to design a real-time arbitrator mechanism based on the event arrival time, which can leverage the advantages of asynchronous real-time arbitration while also achieving fair arbitration.

[0188] The following example illustrates the working principle of the arbitrator corresponding to a single transmitting port, using a conflict scenario where three receiving ports simultaneously send signals to a single transmitting port. Please refer to the appendix. Figure 14 , Figure 14 This is a schematic diagram of an arbitration process provided in an embodiment of this application. Figure 14 As shown, the steps are as follows:

[0189] 1. If the arbitrator determines that multiple preset arbitration conditions are met simultaneously, it will initiate a new round of arbitration; otherwise, it will wait for a status change. The preset arbitration conditions are as follows:

[0190] 1) At least one asynchronous message receiver on the receiving port requests the sending port of the target to send the target data.

[0191] 2) This sending port is in a ready state.

[0192] 3) This sending port is not in a completed state.

[0193] 4) This sending port is not selected.

[0194] 2. Determine whether receiving port A needs to be enabled. If port A has a request, enable receiving port A; otherwise, proceed to step 3.

[0195] 3. Determine whether receiving port B needs to be enabled. If port B has a request, enable receiving port B; otherwise, proceed to step 4.

[0196] 4. Determine whether receiving port C needs to be enabled. If port C has a request, enable receiving port C; otherwise, return to step 1.

[0197] 5. After receiving port A is selected, wait for receiving port A to finish sending. If it is not finished, wait; otherwise, release the selection signal of receiving port A and go to step 3.

[0198] 6. After receiving port B is strobed, wait for receiving port B to finish sending. If it is not finished, wait; otherwise, release the strobe signal of receiving port B and go to step 4.

[0199] 7. After the receiving port C is strobed, wait for the receiving port C to finish sending. If it is not finished, wait; otherwise, release the strobe signal of the receiving port C and go to step 1.

[0200] Please refer to the attached document. Figure 15 , Figure 15 This is a schematic diagram of the internal circuit structure of an arbitrator provided in an embodiment of this application. Figure 15 This is an implementation scheme for an asynchronous arbiter, based on multiple Click circuits (see above for corresponding solutions). Figure 5 The cyclic arbitration circuit in the described embodiment utilizes a Click circuit to implement a token ring mechanism. A decision can only be made upon receiving a token, ensuring that each port has a chance to make a decision in any time series, thereby achieving the goal of cyclic arbitration. The operating mode of this Click circuit can be referred to the relevant description in the above-described Click circuit device embodiment, and will not be repeated here. It should be noted that the number of Click circuits corresponds to the number of receive ports in the router.

[0201] Among them, the Figure 15 Chinese R A R B R C This represents the signals received from port A, port B, and port C; S A S B S C These represent the connection paths from receiving port A, receiving port B, and receiving port C to transmitting port D, respectively; T A It is a state transition indicator, T R It is the ready state of the sending port D, T C The sending port D has completed its transmission status. ClickA, ClickB, and ClickC circuits are three asynchronous handshake circuits (equivalent to the second asynchronous handshake circuit in this application), where '&' represents an AND gate logic circuit. Figure 15 ①-⑦ in the above correspond to the above Figure 14 The implementation process is described in steps ①-⑦.

[0202] It is understood that the embodiments of this application do not specifically limit the implementation scheme of the arbitrator.

[0203] Based on the internal circuit structure of the arbitrator described above, the truth table within the arbitrator is analyzed. Please refer to Tables 3-5 below.

[0204] Table 3: Cases where three requests arrive simultaneously

[0205]

[0206] Table 4: Cases with only one transmitted signal

[0207]

[0208]

[0209] Table 5: Cases where two requests arrive simultaneously

[0210]

[0211] In the truth tables of Tables 3 to 5 above, 1 represents logic 1, indicating a true, ready state, and 0 represents logic 0, indicating a false, not-ready state. PortA, PortB, and PortC under the "transmission request" represent transmission requests from receiving ports A, B, and C, respectively; PortA, PortB, and PortC under the "channel signal" represent the channel signals between transmitting port D and receiving ports A, B, and C, respectively; "transmission ready" refers to whether transmitting port D can complete the transmission task; "transmission completed" refers to whether transmitting port D has completed a transmission task. For example, if PortA is 1 at time T0 of the self-timed clock (equivalent to the second clock signal in this embodiment), it means that receiving port A has a transmission request that needs to be sent at time T0 of the self-timed clock.

[0212] Table 3 (Scenario 1) above shows the case where three sending requests arrive simultaneously, and the goal is to send to port A first, then port B, and finally port C. Table 4 (Scenario 2) shows the case where there is only one sending signal, and the goal is to achieve the shortest arbitration cycle (such as a six-click handshake cycle). Table 5 (Scenario 3) shows the case where two sending requests arrive simultaneously, and the goal is to achieve fair scheduling.

[0213] In this embodiment, the arbitrator in the router implements a fair arbitration mechanism in the data transmission device based on a simple token ring mechanism using handshake circuits such as Click circuits. Furthermore, this arbitrator achieves a high-performance data packet-based transmission mechanism by utilizing a common arbitration mechanism based on the timing dependencies of the receiving unit.

[0214] The embodiments of this application can be based on an asynchronous message bus architecture, using port-reusable routers and router cascading technology, which can be connected to multiple processing units or routers. The wiring is simple and concise, the routing algorithm is simple, the maximum number of hops is one less than the number of asynchronous routers, the latency is low and relatively deterministic, and the chip area occupied by the bus is greatly reduced. Moreover, the application of asynchronous transceiver units in routers and asynchronous transceivers in processors can reduce clock constraints and make it easier to integrate various heterogeneous processing units or IP cores. The use of asynchronous arbitrators in routers is not limited by synchronous clocks, the decision-making is faster, and the forwarding performance of the system can be effectively improved.

[0215] (III) The extended receiving and transmitting units.

[0216] Based on the above Figure 7 and Figure 9The schematic diagram shows that the data connection between the receiving unit and the transmitting unit includes four signal lines: a receive-ready signal line, a self-timing clock signal line, a message valid bit signal line, and a data line (signal line for transmitting data). This data line is used to transmit valid data serially. When transmitting large data blocks or vectors or other data requiring high-speed transmission, the transmission speed between the receiving and transmitting units is relatively slow.

[0217] Due to the implementation scheme based on asynchronous message transceivers in this application embodiment ( Figure 7 and Figure 9 By adopting a bound data transmission scheme, the number of data lines can be easily expanded, and the control lines and control logic of the receiving and transmitting units can be completely reused. This allows the data lines to be expanded as needed to support large data transmissions. Therefore, to handle large data blocks or data with high transmission speed requirements, the number of data lines between the receiving and transmitting units can be increased to achieve a multi-channel serial transmission mode.

[0218] Please refer to the attached document. Figure 16 , Figure 16 This application provides a method based on... Figure 7 A schematic diagram of the expanded transmitting unit. (See diagram below.) Figure 16 As shown, compared to Figure 7 The message bus shown, Figure 16 The expansion of the data channel includes: the addition of a new data line to the asynchronous data bus, the addition of a new valid data transmission module D to the asynchronous message transmitter, and asynchronous serial FIFO-2.

[0219] Please refer to the appendix. Figure 17 and Figure 18 , Figure 17 This application provides a method based on... Figure 7 The diagram shows the data packet transmission effect of the sending unit. Figure 18 This application provides a method based on... Figure 16 The data packet transmission effect of the sending unit is shown. A schematic diagram of the expanded circuit structure is also shown. Figure 17 As shown, when there is only one data line, data packets are transmitted serially bit by bit through one data channel. D0, D1, and D2, etc., represent the data units in the data packet, and the size of each data unit can be 1 bit. Figure 18As shown, when there are only multiple data lines (taking two as an example), data packets are transmitted serially bit by bit across multiple data channels. Here, D0, D1, and D2 represent the data units in each channel corresponding to the data packet, and each data unit can be 1 bit in size. In this case, multiple data streams can be transmitted simultaneously under the same asynchronous clock. It should be noted that when large data packets are sent in parallel, a certain algorithm, such as the odd-even splitting algorithm, can be used to convert the original parallel data into serial data across multiple channels (e.g., odd-numbered bits are transmitted and stored in the data line and serial FIFO corresponding to channel 1, and even-numbered bits are transmitted and stored in the data line and serial FIFO corresponding to channel 2).

[0220] It should be noted that, based on the transmitting unit, a serial FIFO can be added to the receiving unit to store the received data.

[0221] Please refer to the attached document. Figure 19 , Figure 19 This application provides a method related to... Figure 16 The corresponding implementation block diagram of the extended router. (Example) Figure 19 As shown, for a router, after expanding the receiving and transmitting units, it is only necessary to expand the channel selector to be consistent with the asynchronous data transceiver unit so that the channel selector can support multi-channel data transmission.

[0222] It should be noted that, Figure 19 This example of extending the data channel is merely for illustration. The specific implementation method can be customized according to business needs, and this application does not impose any specific limitations on it.

[0223] It should also be noted that the above Figure 4 -the above Figure 19 This application is merely an illustrative example of the embodiments, and its specific implementation is not limited. Moreover, the device mentioned in the embodiments of this application can be a control device or a processing module, etc., for transmitting data within the data transmission device. This application does not specifically limit the specific form of the device.

[0224] It should also be noted that the above Figure 4 -the above Figure 19The division of multiple units is merely a logical division based on function and does not constitute a limitation on the specific structure within the data transmission device. In specific implementations, some functional modules may be subdivided into more smaller functional modules, and some functional modules may be combined into a single functional module. However, regardless of whether these functional modules are subdivided or combined, the general flow executed by the data transmission device during data transmission remains the same. Typically, each unit corresponds to its own program code (or program instructions). When these program codes are run on the relevant hardware device, they cause the unit to execute the corresponding flow to achieve the corresponding function. Furthermore, the function of each unit can also be implemented through relevant hardware.

[0225] Based on the related devices provided in the above-described embodiments, and in conjunction with the data transmission method provided in this application, the technical problems raised in this application are specifically analyzed and solved.

[0226] See Figure 20 , Figure 20 This is a flowchart illustrating a data transmission method provided in an embodiment of this application. This method can be applied to the above-mentioned... Figure 2 or Figure 3 In the data transmission architecture described herein, the processing unit can be used to support and execute... Figure 3 The method flow shown consists of steps S301-S304. A router can be used to support and execute this process. Figure 3 The method flow shown includes steps S305-S308. The following example, taking the transmission of target data from the first processing unit to the target processing unit, exemplifies the data transmission method in this application embodiment. This method may include the following steps S301-S308.

[0227] Step S301: The first processing unit determines the target data.

[0228] Specifically, the first processing unit determines the target data, which includes the destination address of the second processing unit. The destination address can be the communication address of the second processing unit.

[0229] Optionally, the target data can be transmitted as variable-length or fixed-length data packets. As described above. Figure 1 The aforementioned data packet structure.

[0230] Step S302: The first processing unit generates the first request.

[0231] Specifically, the first processing unit generates a first request, which requests that the target data be sent to the second processing unit. It should be noted that this first request is equivalent to... Figure 5The A.req signal shown changes from low to high when the first request is generated. This first request can be used to trigger the first asynchronous handshake circuit (e.g., ...). Figure 5 As shown, the first clock signal is generated.

[0232] Optionally, each processing unit includes a storage area based on a first-in-first-out (FIFO) memory mechanism. After writing the target data into the FIFO-based storage area, the first processing unit generates the sending request. The FIFO-based storage area can be as described above. Figure 7 or Figure 9 The asynchronous serial FIFO module in the memory can also be other forms of storage areas, such as memory, queues, or linked lists. The first-in, first-out (FIFO) storage mechanism allows multiple target data to be sent sequentially according to a certain time order, enabling faster decision-making by the sending unit and effectively improving the system's transmission performance.

[0233] Step S303: After determining that the first router is ready to receive data, the first processing unit determines the first clock signal based on the first request.

[0234] Specifically, after determining that the first router's data reception status is ready, the first processing unit determines a first clock signal based on the first request. It should be noted that this first clock signal is triggered simultaneously by the first router's data reception readiness status and the first request. This clock signal can drive the sending unit to send data to the receiving unit, and it can also drive the receiving unit to receive data sent by the sending unit. This first clock signal is equivalent to the aforementioned... Figure 7 or Figure 9 The self-timing clock signal in the embodiment.

[0235] Optionally, each of the above processing units includes a first asynchronous handshake circuit; the first processing unit is specifically used to: determine the first clock signal based on the first request after determining that the first router's data reception status is ready through the first asynchronous handshake circuit. The first clock signal (also referred to as a self-timing clock) is provided by the asynchronous handshake circuit. This asynchronous handshake circuit has a simple structure and can generate a self-timing clock through a self-loop, that is, when the router's data reception status is ready and the first request exists simultaneously, a self-timing clock can be generated to drive the asynchronous message transmitter to send the target data to the router in a serial single-bit transmission mode.

[0236] Optionally, each of the above processing units includes an asynchronous message transmitter; the first processing unit is specifically configured to: based on the first request, control the asynchronous message transmitter to send the target data to the first router in a serial single-bit transmission manner based on the first clock signal. The asynchronous message transmitter can receive the drive of the first clock signal to send the target data to the router in a serial single-bit transmission manner, thereby realizing asynchronous transmission between the processing unit and the router.

[0237] It should be noted that this first clock signal can also be called a self-timing clock (as mentioned above). Figures 7-9 The embodiment shown is provided by an asynchronous handshake circuit, as described above. Figure 5 The Fire signal is shown. This asynchronous handshake circuit has a simple structure and can generate a self-timing clock through a self-loop mechanism. That is, when the router's data reception readiness state and the first request exist simultaneously, a self-timing clock can be generated to drive the asynchronous message transmitter to send the target data to the router in a serial single-bit transmission mode. Each of the above processing units may also include a sending unit (i.e., a second sending unit), which includes the first asynchronous handshake circuit and the asynchronous message transmitter.

[0238] Step S304: The first processing unit sends the target data to the first router based on the first clock signal, and sends the first clock signal to the first router.

[0239] Specifically, the second sending unit in the first processing unit sends target data to the first router based on the first clock signal, and sends the first clock signal to the first router.

[0240] Optionally, the first processing unit and the first router are connected via an asynchronous message bus, wherein the asynchronous message bus includes a receive-ready signal line, a clock signal line, a message valid bit signal line, and data lines. In this embodiment, the asynchronous message bus includes four signal lines: a receive-ready signal line, a clock signal line, a message valid bit signal line, and one or more data lines. The receive-ready signal line is used to transmit a ready signal, which indicates that the data reception status is ready; the clock signal line is used to transmit a first clock signal; the message valid bit signal line is used to transmit the header and trailer signals of the target data; and one or more data lines are used to transmit the valid data of the target data. When the transmitted data is small (e.g., the target data is an indication message, control message, or data smaller than a preset threshold), it can be transmitted serially bit by bit through a single data line. When the data is large (e.g., the target data is vector data, video frames, image data, voice data, or data larger than or equal to a preset threshold), it can be transmitted serially through multiple data lines supporting multiple channels. Specific implementation methods can be found in the above embodiments, and will not be elaborated upon here. These four signal lines greatly alleviate the problems of multiple and complex outgoing lines between the processing unit and the router in the prior art, and reduce the chip area occupied by the entire asynchronous message bus.

[0241] Optionally, depending on business needs, the data cable can also be multiple data cables supporting multiple channels.

[0242] Step S305: The first router receives the first clock signal.

[0243] Specifically, the first router receives the first clock signal.

[0244] Optionally, each of the aforementioned routers includes multiple sets of ports, each set of ports including a receiving port and a transmitting port, wherein each receiving port is used to receive data, and each transmitting port is used to transmit data. In this embodiment, the router is configured with a processing unit or other router connected to it via configurable ports. Through port-configurable routers, flexible reconfigurable network architectures are possible, such as point-to-point and multi-point-to-multi-point architectures. Furthermore, each port inside the router is connected to a receiving unit or a transmitting unit for sending and receiving data.

[0245] Optionally, the target data is transmitted in the form of a variable-length or fixed-length data packet; the first processing unit is further configured to: set the packet header of the target data after generating a transmission request. It is understood that this packet header needs to be sent to the router along with the first clock signal via the message validity bit signal line.

[0246] Step S306: The first router receives the target data sent by the first processing unit based on the first clock signal.

[0247] Specifically, the first router receives target data sent by the first processing unit based on a first clock signal.

[0248] Optionally, the target data is transmitted in the form of a variable-length or fixed-length data packet; the first processing unit is further configured to: after generating the first request, set the header of the target data packet, and send the header and the first clock signal to the first router; the first router is further configured to: upon receiving the header corresponding to the target data packet, initiate the reception of the target data. For example: as described above. Figure 7 As shown, when the first router detects the packet header signal, it starts receiving data and counting message packet lengths.

[0249] Optionally, each of the aforementioned receiving ports in the router corresponds to a receiving unit, and each of the aforementioned receiving units includes a storage area based on a first-in-first-out (FIFO) storage mechanism. Specifically, the first router is used to: based on the aforementioned first clock signal, drive the storage area within the first receiving unit to receive the aforementioned target data sent by the aforementioned first processing unit through the target receiving port. The aforementioned target receiving port is the receiving port in the first router connected to the aforementioned first processing unit. The FIFO storage mechanism allows multiple target data to be sent sequentially according to a certain time order when they need to be sent, enabling faster decision-making by the sending unit during the transmission process and effectively improving the system's transmission performance. Furthermore, this FIFO-based storage area can be applied to synchronous-to-asynchronous conversion methods, synchronously writing data (e.g., the processing unit synchronously writing target data to the sending unit) or reading data (e.g., the sending unit in the router synchronously reading data based on the storage area of ​​the receiving unit), and asynchronously reading data (e.g., the processing unit asynchronously sending target data from the second sending unit to the router) or writing data (e.g., the first receiving unit in the router asynchronously writing data).

[0250] Step S307: After the target data is received, change the data reception status of the first router from ready to not ready.

[0251] Specifically, the first router is further configured to: after the target data is received, adjust the data reception status of the first router from ready to not ready; the first processing unit is further configured to: after detecting that the data reception status of the first router has changed from ready to not ready, determine that the target data transmission is complete. In this embodiment, when the data reception status in the router changes from ready to not ready, the processing unit can determine that the data transmission is complete and stop data transmission to save communication resources. The ready and not ready states can be identified by high and low electrical signals, respectively.

[0252] Optionally, the first processing unit is further configured to: set the packet trailer of the target data and send it after the last bit of the target data has been sent; the first router is further configured to: adjust the data reception status of the first router from ready to not ready after receiving the packet trailer of the target data. Asynchronous transmission of the target data is achieved by setting the packet header and trailer, eliminating the need for clock synchronization between the processing unit and the router, and making it easier for a single router to integrate multiple heterogeneous processing units or intellectual property cores.

[0253] Step S308: The first router sends the target data to the second processing unit according to the destination address.

[0254] Specifically, the first router sends the target data to the target unit based on the destination address.

[0255] Optionally, each of the aforementioned transmitting ports in the router corresponds to a transmitting unit; based on the aforementioned destination address, a target transmitting port in the first router is determined, and the target transmitting port is the transmitting port in the first router corresponding to the aforementioned second processing unit; the aforementioned target data is transmitted to the aforementioned second processing unit through the first transmitting unit corresponding to the aforementioned target transmitting port. By using a port-configurable router, the target transmitting port corresponding to the first transmitting unit is determined based on the destination address, and the target data is transmitted to the second processing unit through that transmitting port. Furthermore, in a communication connection formed by multiple routers, it is not necessary to determine the port number upon receiving the target data; data can be transmitted to the second processing unit based on the destination address.

[0256] Optionally, each of the aforementioned routers includes a mapping table, which includes a mapping relationship between the port identifier of each of the aforementioned transmitting ports in the router and the unit identifier of the corresponding processing unit or the routing identifier of other routers. The unit identifier is used to uniquely identify the processing unit, and the routing identifier is used to uniquely identify the router. Specifically, the first router is used to: determine the aforementioned target transmitting port based on the aforementioned destination address and the mapping table in the first router. In this embodiment of the application, the routing forwarding mechanism by querying the mapping table simplifies the routing forwarding process and improves transmission efficiency.

[0257] Optionally, when the second processing unit is connected to the second router, and the first router and the second router are two different routers among the plurality of routers, the target sending port is the sending port with the fewest hops to the second router among the first routers. In the communication connection formed by multiple routers, the case with the most data with the most routing connection hops is one less than the number of routers. The router can choose the transmission path with the fewest connection hops to send the target data to the second processing unit based on the destination address.

[0258] Optionally, the first router is specifically configured to: when the first sending unit receives a second request sent by the first receiving unit, control the first sending unit to retrieve the target data from the storage area of ​​the first receiving unit, wherein the second request is used to request the transmission of the target data through the first sending unit; and transmit the target data to the second processing unit through the first sending unit in a serial single-bit transmission manner based on the target transmission port. By using a simple sending unit based on shared data, the storage area of ​​the receiving end's FIFO mechanism is reused, reducing data movement and improving transmission efficiency.

[0259] Optionally, each of the aforementioned routers includes a channel selector; the channel selector of the first router is used to connect the data path from the first receiving unit to the first transmitting unit, so that the first transmitting unit can obtain the target data from the storage area of ​​the first receiving unit. When there is a need to send data, the channel selector can connect the data path between the receiving unit and the transmitting unit, so that the transmitting unit can reuse the FIFO storage area of ​​the receiving unit through the data path, reducing data movement and greatly improving the transmission performance of the router.

[0260] Optionally, after transmission is complete, the channel selector releases the data path, allowing other first receiving units to send data to the first transmitting unit. That is, the first transmitting unit can only send data to one first receiving unit at a time, and the data path between the first transmitting unit and that first receiving unit will be disconnected after transmission is complete.

[0261] Optionally, each of the aforementioned routers includes an arbitrator, and each of the aforementioned sending units corresponds to one of the aforementioned arbitrators. The arbitrator of the first router is used to: when m receiving units simultaneously request data transmission from the first sending unit, determine a target receiving unit from the m receiving units according to a preset arbitration rule, where m is greater than 1 and less than or equal to the total number of the aforementioned receiving units included in the router; the channel selector of the first router is further used to: after the arbitrator determines the target receiving unit, connect the data path from the target receiving unit to the first sending unit, so that the first sending unit can obtain data from the storage area of ​​the target receiving unit and send it. In this embodiment of the application, an arbitrator is used to implement a "many-to-one" fair arbitration mechanism to reduce conflicts when routing and forwarding data. To ensure the normal operation of each sending unit, there is a one-to-one correspondence between the arbitrator and the sending unit.

[0262] Optionally, the arbitrator includes a second asynchronous handshake circuit; the second asynchronous handshake circuit of the first router is used to: after determining that the data transmission status of the first transmitting unit is ready, determine a second clock signal based on the signal requesting data transmission sent by the target receiving unit to the first transmitting unit; the channel selector of the first router is specifically used to: connect the data path from the target receiving unit to the second transmission based on the second clock signal. In this embodiment, the arbitrator in the router implements a fair arbitration mechanism in the data transmission device based on a simple token ring mechanism of handshake circuits such as Click circuits. Moreover, the arbitrator implements a data packet-based transmission mechanism by utilizing a common arbitration mechanism with timing dependencies on the receiving unit, resulting in high performance. It is understood that the arbitrator in the router is an asynchronous arbitrator.

[0263] Optionally, the number of the second asynchronous handshake circuits in each of the above-mentioned arbitrators is one less than the number of receiving ports in the above-mentioned router. In this embodiment, in order to ensure that all receiving ports except the receiving port corresponding to the sending port need to send messages to the sending port, the number of the second asynchronous handshake circuits in the arbitrator is one less than the number of receiving ports in the router.

[0264] In implementing the embodiments of this application, the data transmission device based on the asynchronous handshake mechanism, after determining that the router (e.g., the first router) is ready to receive data, generates a first clock signal based on the data transmission request of the processing unit (e.g., the first processing unit). The first clock signal and the target data are then sent to the router according to the first clock signal, allowing the router connected to the processing unit to receive the target data via the first clock signal. The router then sends the target data to the second processing unit based on the destination address carried in the received target data. This asynchronous handshake transmission method between the processing unit and the router ensures that the router receives the target data completely. Furthermore, the processing unit also sends the clock signal (i.e., the first clock signal) used to send the target data to the router, enabling the router to receive data based on this clock signal. This reduces clock constraints within the data transmission device, making it easier to integrate various heterogeneous processing units or intellectual property cores. Simultaneously, it frees multiple routers from synchronization clock limitations, resulting in faster decision-making and effectively improving system forwarding performance. Moreover, the relatively short and relatively deterministic data cable connection between the processing unit and the router further leads to a smaller and more deterministic delay in the corresponding clock signal when the processing unit needs to send data. Meanwhile, in this embodiment of the application, a router can be asynchronously connected to multiple processing units, which greatly reduces the chip area occupied by the bus.

[0265] It should be noted that both the first router and the first processing unit include a receiving unit and a transmitting unit. For example, the first router may include a first receiving unit and a first transmitting unit, and the first processing unit may include a second receiving unit and a second transmitting unit. The first receiving unit and the second receiving unit have similar functions and structures, both used to receive data via asynchronous serial single-bit transmission. Similarly, the first transmitting unit and the second transmitting unit have similar functions and structures, both used to transmit data via asynchronous serial single-bit transmission. The relevant structures and functions of the receiving and transmitting units in the first router and the first processing unit can also be referred to the relevant descriptions in the above embodiments, which will not be repeated in the embodiments of this application.

[0266] It should also be noted that the first router mentioned in the embodiments of this application can be referred to in the above-mentioned manner. Figure 4 -the above Figure 19 The routers involved, and the first processing unit mentioned in the embodiments of this application, can be referred to in the above-described manner. Figure 4 -the above Figure 19 The processing units involved in this embodiment will not be described in detail here.

[0267] This application also provides a chip system, which includes the apparatus provided in any of the above embodiments and in combination with any of the above embodiments. The chip system is used to implement the functions of the data transmission apparatus described above. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for the data transmission apparatus. The chip system may be composed of chips or may include chips and other discrete devices.

[0268] This application also provides an electronic device, which includes the apparatus provided in any of the above embodiments and in combination with any of the above embodiments. This electronic device is used to implement the functions of the data transmission apparatus described above.

[0269] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0270] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0271] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0272] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0273] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0274] If the integrated units described above are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which can be a personal computer, server, or network device, specifically a processor in the computer device) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium may include various media capable of storing program code, such as a USB flash drive, portable hard drive, magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM).

[0275] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A data transmission device, characterized in that, include: The system includes multiple processing units and multiple routers, each router being connected to one or more processing units and forming a communication connection with any one of the multiple routers; wherein the multiple routers include a first router, which is connected to a first processing unit. The first processing unit is configured to: generate a first request, the first request being used to request that target data be sent to the second processing unit, the target data including the destination address of the second processing unit; After determining that the first router is ready to receive data, a first clock signal is determined based on the first request; The target data is sent to the first router based on the first clock signal, and the first clock signal is also sent to the first router. The first router is configured to: receive the first clock signal; The target data sent by the first processing unit is received based on the first clock signal; The target data is sent to the second processing unit according to the destination address.

2. The apparatus according to claim 1, characterized in that, Each of the processing units includes a first asynchronous handshake circuit; The first processing unit is specifically used to: determine the first clock signal based on the first request after determining that the first router is ready to receive data through the first asynchronous handshake circuit.

3. The apparatus according to claim 1 or 2, characterized in that, Each of the processing units includes an asynchronous message sender; The first processing unit is specifically used to: based on the first request, control the asynchronous message sender to send the target data to the first router in a serial single-bit transmission mode based on the first clock signal.

4. The apparatus according to any one of claims 1-3, characterized in that, Each of the processing units includes a storage area based on a first-in-first-out (FIFO) memory mechanism; The first processing unit is specifically used to: write the target data into the storage area based on the first-in-first-out storage mechanism, and then generate the first request.

5. The apparatus according to any one of claims 1-4, characterized in that, The first processing unit and the first router are connected via an asynchronous message bus, wherein the asynchronous message bus includes a receive ready signal line, a clock signal line, a message valid bit signal line, and one or more data lines.

6. The apparatus according to any one of claims 1-5, characterized in that, Each router includes multiple sets of ports, each set of ports including a receive port and a send port, wherein each receive port is used to receive data and each send port is used to send data.

7. The apparatus according to claim 6, characterized in that, Each of the receiving ports corresponds to a receiving unit, and each receiving unit includes a storage area based on a first-in-first-out (FIFO) memory mechanism; The first router is specifically used to: based on the first clock signal, drive the storage area within the first receiving unit to receive the target data sent by the first processing unit through the target receiving port, wherein the target receiving port is the receiving port in the first router connected to the first processing unit.

8. The apparatus according to claim 7, characterized in that, Each of the aforementioned transmission ports corresponds to one transmission unit; The first router is specifically used to: determine the target sending port in the first router according to the destination address, wherein the target sending port is the sending port in the first router corresponding to the second processing unit; The target data is sent to the second processing unit through the first sending unit corresponding to the target sending port.

9. The apparatus according to claim 8, characterized in that, When the second processing unit is connected to the second router, and the first router and the second router are two different routers among the plurality of routers, the target sending port is the sending port with the fewest hops to the second router among the first routers.

10. The apparatus according to claim 8, characterized in that, The first router is specifically configured to: when the first sending unit receives a second request sent by the first receiving unit, control the first sending unit to obtain the target data from the storage area of ​​the first receiving unit, wherein the second request is used to request the target data to be sent through the first sending unit; The first sending unit transmits the target data to the second processing unit via a serial single-bit transmission method based on the target sending port.

11. The apparatus according to any one of claims 8-10, characterized in that, Each router includes an arbitrator, and each transmitting unit corresponds to one arbitrator; The arbitrator of the first router is used to: determine the target receiving unit from the m receiving units according to a preset arbitration rule when m receiving units simultaneously request data to be sent to the first sending unit. Here, m is greater than 1 and less than or equal to the total number of receiving units contained in the router.

12. A data transmission method, characterized in that, The method is applied to a data transmission device, the data transmission device comprising: multiple processing units and multiple routers, each router being connected to one or more processing units, and each router forming a communication connection with any one of the multiple routers; wherein the multiple routers include a first router, the first router being connected to a first processing unit; the method includes: The first processing unit generates a first request, which requests that target data be sent to the second processing unit. The target data includes the destination address of the second processing unit. After the first processing unit determines that the first router is ready to receive data, it determines the first clock signal based on the first request. The first processing unit sends the target data to the first router based on the first clock signal, and sends the first clock signal to the first router; The first clock signal is received through the first router; The first router receives the target data sent by the first processing unit based on the first clock signal; The first router sends the target data to the second processing unit according to the destination address.

13. The method according to claim 12, characterized in that, Each of the processing units includes a first asynchronous handshake circuit; After the first processing unit determines that the first router is ready to receive data, it determines a first clock signal based on the first request, including: After determining that the first router is ready to receive data, the first asynchronous handshake circuit determines the first clock signal based on the first request.

14. The method according to claim 12 or 13, characterized in that, Each of the processing units includes an asynchronous message sender; The step of sending the target data to the first router via the first processing unit based on the first clock signal includes: Based on the first request, the asynchronous message sender is controlled to send the target data to the first router in a serial single-bit transmission mode based on the first clock signal.

15. The method according to any one of claims 12-14, characterized in that, Each of the processing units includes a storage area based on a first-in-first-out (FIFO) memory mechanism; The generation of the first request through the first processing unit includes: After the first processing unit writes the target data into the storage area based on the first-in-first-out storage mechanism, the first request is generated.

16. The method according to any one of claims 12-15, characterized in that, The first processing unit and the first router are connected via an asynchronous message bus, wherein the asynchronous message bus includes a receive ready signal line, a clock signal line, a message valid bit signal line, and one or more data lines.

17. The method according to any one of claims 12-16, characterized in that, Each router includes multiple sets of ports, each set of ports including a receive port and a send port, wherein each receive port is used to receive data and each send port is used to send data.

18. The method according to claim 17, characterized in that, Each of the receiving ports corresponds to a receiving unit, and each receiving unit includes a storage area based on a first-in-first-out (FIFO) memory mechanism; The step of receiving the target data sent by the first processing unit via the first router based on the first clock signal includes: Based on the first clock signal, the target data sent by the first processing unit is received by the storage area within the first receiving unit through the target receiving port, wherein the target receiving port is the receiving port in the first router connected to the first processing unit.

19. The method according to claim 18, characterized in that, Each of the aforementioned sending ports corresponds to a sending unit; the step of sending the target data to the second processing unit via the first router according to the destination address includes: Based on the destination address, the target sending port in the first router is determined, and the target sending port is the sending port in the first router corresponding to the second processing unit; The target data is sent to the second processing unit through the first sending unit corresponding to the target sending port.

20. The method according to claim 19, characterized in that, When the second processing unit is connected to the second router, and the first router and the second router are two different routers among the plurality of routers, the target sending port is the sending port with the fewest hops to the second router among the first routers.

21. The method according to claim 19, characterized in that, Sending the target data to the second processing unit through the first sending unit corresponding to the target sending port includes: When the first sending unit receives the second request sent by the first receiving unit, it controls the first sending unit to obtain the target data from the storage area of ​​the first receiving unit. The second request is used to request the target data to be sent through the first sending unit. The first sending unit transmits the target data to the second processing unit via a serial single-bit transmission method based on the target sending port.

22. The method according to any one of claims 19-21, characterized in that, Each router includes an arbitrator, and each sending unit corresponds to one arbitrator; the method further includes: When m receiving units simultaneously request data to be sent to the first sending unit, the arbitrator of the first router determines the target receiving unit from the m receiving units according to a preset arbitration rule, where m is greater than 1 and less than or equal to the total number of receiving units contained in the router.

23. A chip system, characterized in that, The chip system includes the apparatus described in any one of claims 1-11.

24. An electronic device, characterized in that, The electronic device includes the apparatus described in any one of claims 1-11.

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