A testing device

Abstract

This invention provides a testing device comprising: a motherboard and a fixture board. The motherboard is equipped with a first baseboard management controller, which is connected to a first IPMB connector and a field-replaceable unit via I2C. The motherboard also includes a first sideband signal connector, a first MCIO connector, and a first power connector. The fixture board includes a second baseboard management controller, which is connected to a second IPMB connector via I2C. The second IPMB connector is connected to the first IPMB connector. The fixture board also includes a second sideband signal connector, a second MCIO connector, and a second power connector. The first sideband signal connector is connected to the second sideband signal connector. The first MCIO connector is connected to the second MCIO connector for data transmission between the fixture board and the motherboard. The first power connector and the second power connector are connected. The fixture board also includes a downlink connector, which includes multiple test interfaces for connecting different boards under test.

Description

Technical Field

[0001] This invention relates to the field of server testing, and more particularly to a fixture board. Background Technology

[0002] With the advancement and development of technology, servers play a vital role in people's lives. Servers can operate reliably for extended periods, possess powerful input / output external data throughput capabilities, and offer scalability, among other features. Testing and debugging the single-board hardware units during the design phase is an indispensable part of server development.

[0003] In server hardware design, different server models and configurations need to be developed to meet diverse business requirements. Each board under test (DUT) connects to the server motherboard via different connectors to complete the test; that is, different DUTs require different motherboards for testing.

[0004] The above method requires that the test of the board under test must be performed with the corresponding motherboard. When there are many boards under test, different test environments need to be set up, resulting in low testing efficiency and a cumbersome testing process. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a testing apparatus that overcomes or at least partially solves the above problems.

[0006] In a first aspect, embodiments of this application disclose a testing apparatus, comprising: The motherboard and the fixture board are provided. The motherboard is equipped with a first baseboard management controller. The first baseboard management controller is connected to a first IPMB connector and a field replaceable unit via I2C. The first baseboard management controller is used to provide the fixture board with the information stored in the field replaceable unit through the first IPMB connector. The motherboard also includes a first sideband signal connector, a first MCIO connector, and a first power connector; The fixture board includes a second baseboard management controller, which is connected to a second IPMB connector via I2C. The second IPMB connector is connected to the first IPMB connector and is used to acquire information stored in the field replaceable unit of the mainboard. The fixture plate also includes a second sideband signal connector, a second MCIO connector, and a second power connector. The first sideband signal connector is connected to the second sideband signal connector and is used to provide a sideband signal to the fixture plate; The first MCIO connector is connected to the second MCIO connector for high-speed data transmission between the fixture board and the motherboard; The first power connector and the second power connector are connected to supply power to the fixture plate; The fixture board also includes a downlink connector; the downlink connector includes multiple test interfaces for connecting different boards under test.

[0007] Optionally, the second baseboard management controller, the second MCIO connector, and the second power connector are respectively connected to the downlink connector.

[0008] Optionally, the downlink connector includes: a third power connector; The second power connector is connected to the third power connector and is used to supply power to the board under test.

[0009] Optionally, the downlink connector includes: a GEN_Z connector power supply module and a Multitrack connector power supply module; The second power connector is connected to the GEN_Z connector power supply module and the Multitrack connector power supply module respectively, and is used to supply power to the GEN_Z connector power supply module and the Multitrack connector power supply module.

[0010] Optionally, the second baseboard management controller is connected to the downlink connector via an I2C bus for performing functional verification on the board under test connected to the downlink connector.

[0011] Optionally, the second baseboard management controller is provided with a general-purpose input / output interface; The general-purpose input / output interface is connected to the downlink connector.

[0012] Optionally, the board under test is connected to the test interface of the downlink connector via a cable; and / or, the board under test is directly plugged into the test interface of the downlink connector.

[0013] Optionally, the number of the first MCIO connectors is multiple; the number of the second MCIO connectors is multiple.

[0014] Optionally, the downlink connector includes a third MCIO connector; the third MCIO connector is connected to the board under test.

[0015] Optionally, the downlink connector includes: a GEN_Z connector and a Multitrack connector; The second MCIO connector is connected to the corresponding GEN_Z connector; The second MCIO connector is connected to the corresponding Multitrack connector; The number of the second MCIO connector is the sum of the first number of MCIO connectors corresponding to the GEN_Z connector and the second number of MCIO connectors corresponding to the Multitrack connector; The GEN_Z connector is provided with a first slot, which is used to connect a board under test that is compatible with the Gen_Z interface; the board under test that is compatible with the Gen_Z interface is connected to the motherboard through four second MCIO connectors, a second power connector, and a second sideband signal connector. The Multitrack connector is provided with a second slot for connecting a board under test that is compatible with the Multitrack interface; the board under test that is compatible with the Multitrack interface is connected to the motherboard through two second MCIO connectors, a second power connector, and a second sideband signal connector.

[0016] This application discloses a testing device comprising: a motherboard and a fixture board. The motherboard is equipped with a first baseboard management controller, which is connected to a first IPMB connector and a field-replaceable unit via I2C. The first baseboard management controller is used to provide information stored in the field-replaceable unit to the fixture board through the first IPMB connector. The motherboard also includes a first sideband signal connector, a first MCIO connector, and a first power connector. The fixture board includes a second baseboard management controller, which is connected to a second IPMB connector via I2C. The second IPMB connector is connected to the first IPMB connector and is used to acquire information stored in the field-replaceable unit of the motherboard. The fixture board also includes a second sideband signal connector, a second MCIO connector, and a second power connector. The first sideband signal connector is connected to the second sideband signal connector and is used to provide sideband signals to the fixture board. The first MCIO connector is connected to the second MCIO connector and is used for high-speed data transmission between the fixture board and the motherboard. The first power connector is connected to the second power connector and is used to supply power to the fixture board. The fixture board also includes a downlink connector, which includes multiple test interfaces for connecting different boards under test. This application's solution isolates the board under test (DUT) and uses a fixture board to achieve compatible connections for DUTs with different interfaces. The high-speed bus signal from the fixture board's uplink MCIO connector can be directly transferred to the DUT via the downlink connector. Sideband signals from the mainboard can be connected to the fixture board's BMC. The IPMB connector enables communication between the fixture board's BMC and the mainboard's BMC. The fixture board's BMC can parse and process the input sideband signals and transmit them to the DUT, thus enabling functional verification of the hardware module circuits within the DUT. For DUTs in different projects / configurations, the same mainboard can be used for testing and verification, thereby reducing the complexity of test environment setup during R&D self-testing, improving testing efficiency, and reducing the time investment of R&D personnel in hardware development. Attached Figure Description

[0017] Figure 1 This is a connection method for a test board in a related technology provided by an embodiment of the present invention; Figure 2 This is a testing device provided in an embodiment of the present invention; Figure 3 This is a testing method provided by an embodiment of the present invention. Detailed Implementation

[0018] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0019] The concepts and background involved in this application are explained below.

[0020] I / O (Input / Output) is the communication between an information processing system (such as a calculator) and the external world (which could be humans or another information processing system). Input is the signals or data received by the system, and output is the signals or data sent from it.

[0021] The BMC (Baseboard Management Controller) is a dedicated controller for monitoring and managing servers. Its four main functions are: 1. Device Information Management: Recording server information (model, manufacturer, date, production and technical information of each component, chassis information, motherboard information, etc.) and BMC information (server hostname, IP address, BMC firmware version, etc.); 2. Server Status Monitoring and Management: Detecting the health status of various server components (CPU, memory, hard drive, fans, chassis, etc.) such as temperature and voltage, and adjusting fan speeds in real time based on temperature data to prevent overheating and control overall power consumption; 3. If any abnormality occurs in a single board component, the information is promptly reported to the upper-level network management system via various industry-standard protocols such as SNMP, SMTP, and Redfish; 4. Remote Control Management of the Server: Server power on / off, restart, maintenance, firmware updates, system installation, etc.; 5. Maintenance Management: Log management, user management, BIOS management, alarm management, etc.

[0022] FRU (Field Replacement Unit): It is usually stored in EEPROM (Electrically Erasable Programmable Read-Only Memory), which stores relevant asset information, serial number, manufacturer and MAC address, etc. It has a long service life and is not easily lost when power is off, and will not change with firmware upgrades such as BMC and BIOS.

[0023] I2C (Inter-Integrated Circuit, a two-wire serial bus) requires only two wires to transmit information between devices connected to the bus.

[0024] PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) SAS (Serial Attached SCSI) SATA (Serial Advanced Technology Attachment, a new standard for hard drive interfaces) GPIO (General-purpose input / output) SPEC (Specification, Specification) VR (Voltage Regulate module) CPLD (Complex Programmable Logic Device) MCU (Microcontroller Unit): Also known as a single-chip microcomputer or microcontroller, it is a control chip in a component or device.

[0025] refer to Figure 1 , Figure 1 This paper illustrates a connection method for testing a board under test (BUT) in related technologies. In related technologies, after the server motherboard and daughter cards are designed and manufactured, a test environment is set up according to testing requirements. The BUT is then connected to the motherboard via communication methods, including adapter cables or direct plug-ins. Hardware unit testing and debugging of the BUT are then performed. During the R&D self-testing phase, testing of boards with side panels mainly includes hardware signal testing, functional verification, VR testing, etc. Because the hardware interfaces of motherboards and daughter cards (i.e., BUTs) differ between different projects, testing of each BUT must be performed with its corresponding motherboard. During the testing and verification process, multiple test environments need to be set up, consuming significant time and manpower. Therefore, based on the above problems, the method proposed in this application is as follows: Firstly, reference Figure 2This application discloses a testing device, including: a motherboard and a fixture board. The motherboard is equipped with a first baseboard management controller, which is connected to a first IPMB connector and a field-replaceable unit via I2C. The first baseboard management controller is used to provide information stored in the field-replaceable unit to the fixture board through the first IPMB connector. The motherboard also includes a first sideband signal connector, a first MCIO connector, and a first power connector. The fixture board includes a second baseboard management controller, which is connected to a second IPMB connector via I2C. The second IPMB connector is connected to the first IPMB connector and is used to acquire information stored in the field-replaceable unit of the motherboard. The fixture board also includes a second sideband signal connector, a second MCIO connector, and a second power connector. The first sideband signal connector is connected to the second sideband signal connector and is used to provide sideband signals to the fixture board. The first MCIO connector is connected to the second MCIO connector and is used for high-speed data transmission between the fixture board and the motherboard. The first power connector is connected to the second power connector and is used to supply power to the fixture board. The fixture board also includes a downlink connector, which includes multiple test interfaces for connecting different boards under test.

[0026] In this embodiment of the invention, the BMC (Baseboard Management Controller) is a dedicated controller for monitoring and managing servers, with the following four main functions: Device information management: recording server information (model, manufacturer, date, production and technical information of each component, chassis information, motherboard information, etc.) and BMC information (server hostname, IP address, BMC firmware version, etc.); BMCs are installed on both the motherboard and the fixture board to enable information exchange. (Reference) Figure 2 The fixture board may include an uplink connector, a baseboard management controller, and a downlink connector. The uplink connector is used to connect to various interfaces on the motherboard, and the downlink connector is used to connect to boards under test with different interface types. In other words, the fixture board can connect two interfaces that cannot directly establish a communication connection, thereby enabling the testing of the boards under test.

[0027] Specifically, the upstream connector of the fixture board may include: a second IPMB connector, a second power connector, a second sideband signal connector, and a second MCIO connector. The high-speed bus signal of the second MCIO connector can be directly transferred to the board under test (DUT) through the downstream connector, and the DUT can communicate with the motherboard through the MCIO connector. Multiple components of the second connector can be configured to meet the testing needs of different scenarios.

[0028] The second IPMB connector of the fixture board is connected to the first IPMB connector of the motherboard. The first IPMB connector of the motherboard is connected to the first baseboard management controller of the motherboard via an I2C1 bus. The first baseboard management controller of the motherboard also communicates with the FRU module of the motherboard via an I2C2 bus. The second IPMB connector of the fixture board is connected to the second baseboard management controller of the fixture board via an I2C1 bus. Therefore, the second IPMB connector in the uplink connector can be used to establish an I2C communication connection between the baseboard management controller of the fixture board and the baseboard management controller of the motherboard. The second baseboard management controller of the fixture board can obtain the FRU information of the connected motherboard via I2C (bus). Based on the obtained platform information, it can analyze and process the sideband signals input by the second sideband signal connector and the second MCIO connector. Then, it can connect to the board under test via the I2C bus and GPIO signals (General-purpose input / output) to perform functional verification of the hardware module circuits in the board under test.

[0029] Furthermore, the second sideband signal connector of the fixture board is communicatively connected to the first sideband signal connector of the motherboard, and the second MCIO connector of the fixture board is communicatively connected to the first MCIO connector of the motherboard. The second sideband signal connector and the second MCIO connector can transmit the received sideband signals to the second baseboard management controller of the fixture board, so that the second baseboard management controller can analyze and process the sideband signals based on the communication connection between the second IPMB connector and the motherboard, thereby communicating with the board under test connected to the downlink connector.

[0030] Downlink connectors may include connectors of different interface types such as MCIO connectors, GEN_Z connectors, and Multitrack connectors, which can be used to connect compatible boards under test (DUTs). For example, MCIO connectors can be used to connect DUTs that adapt to the MCIO interface, GEN_Z connectors can be used to connect DUTs that adapt to the GEN_Z interface, and Multitrack connectors can be used to connect DUTs that adapt to the Multitrack interface. It should be noted that downlink connectors may also include connectors of other interface types for connecting DUTs of other interface types. The specific configuration can be determined according to actual needs, and this application embodiment does not limit this.

[0031] The fixture board expands the interface types of the boards under test (DUTs) that can be connected to the motherboard, enabling DUTs with different interface types to communicate with the motherboard. This allows a single motherboard to perform functional verification and other testing processes for DUTs with different interface types, saving testing time and improving testing efficiency. The steps for testing the DUT using the fixture board are as follows: 1. Select any existing motherboard and connect the fixture board's uplink connector to the corresponding interface on the motherboard using an adapter cable; 2. Connect the DUT to the fixture board's downlink connector using an adapter cable or a direct connection; 3. Based on the PCIe / SAS / SATA protocol SPEC boundary values, select one set of links with the motherboard for signal testing and functional verification. By isolating the board under test (DUT) and using a fixture board to achieve compatible connections for DUTs with different interfaces, the high-speed bus signal from the second MCIO connector can be directly transferred to the DUT via the downstream connector. The motherboard's sideband signals can be connected to the fixture board's BMC. The IPMB connector enables communication between the fixture board's BMC and the motherboard's BMC. The fixture board's BMC can parse and process the input sideband signals and transmit them to the DUT, thus enabling functional verification of the hardware module circuits within the DUT. For DUTs in different projects / configurations, the same motherboard can be used for testing and verification, reducing the complexity of test environment setup during R&D self-testing, improving testing efficiency, and reducing the time R&D personnel spend on hardware development.

[0032] In summary, this application discloses a testing device comprising: a motherboard, the motherboard having a first baseboard management controller, the first baseboard management controller being connected to a first IPMB connector and a field-replaceable unit via I2C, the first baseboard management controller being used to provide information stored in the field-replaceable unit to a fixture board via the first IPMB connector; the motherboard further comprising a first sideband signal connector, a first MCIO connector, and a first power connector; the fixture board comprising a second baseboard management controller, the second baseboard management controller being connected to a second IPMB connector via I2C, the second IPMB connector being connected to the first IPMB connector, and being used to acquire information stored in the field-replaceable unit of the motherboard; the fixture board further comprising a second sideband signal connector, a second MCIO connector, and a second power connector; the first sideband signal connector being connected to the second sideband signal connector, and being used to provide sideband signals to the fixture board; the first MCIO connector being connected to the second MCIO connector, and being used for high-speed data transmission between the fixture board and the motherboard; the first power connector being connected to the second power connector, and being used to supply power to the fixture board; the fixture board further comprising: a downlink connector; the downlink connector comprising multiple test interfaces for connecting different boards under test. This application's solution isolates the board under test (DUT) and uses a fixture board to achieve compatible connections for DUTs with different interfaces. The high-speed bus signal from the second MCIO connector can be directly transferred to the DUT via the downlink connector, and the motherboard's sideband signals can be connected to the fixture board's BMC. The IPMB connector enables communication between the fixture board's BMC and the motherboard's BMC. The fixture board's BMC can parse and process the input sideband signals and transmit them to the DUT, thereby enabling functional verification of the hardware module circuits in the DUT. For DUTs of different projects / configurations, the same motherboard can be used for testing and verification, thereby reducing the complexity of test environment setup during R&D self-testing, improving testing efficiency, and reducing the time invested by R&D personnel in hardware development.

[0033] Optionally, refer to Figure 2 The second baseboard management controller, the second MCIO connector, and the second power connector are respectively connected to the downlink connector.

[0034] In an embodiment of the present invention, reference is made to Figure 2The IPMB connector on the fixture board is connected to the baseboard management controller on the motherboard via a bus. This bus can be an I2C bus or other data bus, which is not limited to this embodiment. I2C (Inter-Integrated Circuit, two-wire serial bus) requires only two wires to transmit information between devices connected to the bus. These two wires are the serial data line (SDA) and the serial clock line (SCL). The I2C bus is a standard bidirectional interface that uses a controller called the master device to communicate with slave devices. A slave device must not transmit data unless the master has addressed it. Each device on the I2C bus has a specific device address to distinguish it from other devices on the same I2C bus. Many slave devices require configuration at startup to set their behavior. This is typically done when the master accesses the slave's internal register mappings, which have unique register addresses. A device can have one or more registers for storing, writing, or reading data. The physical I2C interface consists of a serial clock (SCL) and a serial data (SDA) line. Both the SDA and SCL lines must be connected to VCC via pull-up resistors, the size of which depends on the capacitance on the I2C lines. Data transmission can only be initiated when the bus is idle. If both the SDA and SCL lines are high after a STOP condition, the bus is considered idle. The general process for a master device to access a slave device is as follows: 1. Assuming a master wants to send data to a slave: the master transmitter sends a START condition and addresses the slave receiver; the master transmitter sends data to the slave receiver; the master transmitter terminates the transmission with a STOP condition. If the master wants to receive / read data from the slave: the master receiver sends a START condition and addresses the slave transmitter; the master receiver sends a request register to read from the slave transmitter; the master receiver receives data from the slave transmitter; the master receiver terminates the transmission with a STOP condition.

[0035] Specifically, refer to Figure 2 The second IPMB connector of the fixture board is connected to the first IPMB connector of the motherboard. The first IPMB connector of the motherboard is connected to the first baseboard management controller of the motherboard via an I2C1 bus. The first baseboard management controller of the motherboard also communicates with the FRU module of the motherboard via an I2C2 bus. The second IPMB connector of the fixture board is connected to the second baseboard management controller of the fixture board via an I2C1 bus, so that the fixture board can obtain the FRU information of the motherboard.

[0036] The second baseboard management controller, the second MCIO connector, and the second power connector of the further fixture board are respectively connected to the downlink connector for communicating with the board under test connected to the downlink connector, receiving data transmitted by the board under test, and supplying power to the board under test.

[0037] Optionally, the downlink connector includes: a third power connector; the second power connector is connected to the third power connector for supplying power to the board under test.

[0038] In an embodiment of the present invention, reference is made to Figure 2 The upstream connector also includes a second power connector, and the downstream connector also includes a third power connector. The second power connector connects to the motherboard's power connector, and the second power connector also connects to the third power connector in the downstream connector. Figure 2 (not shown in the diagram, but included in the downstream connector), so that the second power connector can power the third power connector.

[0039] Specifically, powering the third power connector via the second power connector can meet the power supply requirements for different boards under test. It should be noted that the number of second power connectors and the number of third power connectors can be multiple, depending on the number of different interface types of connectors in the downlink connector, to meet the power supply requirements for multiple third power connectors. This embodiment of the application does not impose any limitations on this.

[0040] Optionally, the downlink connector includes: a GEN_Z connector power supply module and a Multitrack connector power supply module, and a second power connector is connected to the GEN_Z connector power supply module and the Multitrack connector power supply module respectively, for supplying power to the GEN_Z connector power supply module and the Multitrack connector power supply module.

[0041] In an embodiment of the present invention, reference is made to Figure 2 The uplink connector also includes a second power connector, and the downlink connector also includes a GEN_Z connector power supply module and a Multitrack connector power supply module. Figure 2 (Not shown in the diagram, but included in the downlink connector), the GEN_Z connector power supply module is used to power the GEN_Z connector, and the Multitrack connector power supply module is used to power the Multitrack connector. If the fixture board also includes other types of downlink connectors, power supply modules for other interface types of downlink connectors can also be provided. These power supply modules can all be connected to the second power connector to enable the second power connector to power each power supply module of the downlink connector.

[0042] Specifically, the power supply to the GEN_Z connector power supply module, the Multitrack connector power supply module, and the power supply modules of other interface types via the second power connector can meet the power supply requirements of different boards under test.

[0043] It should be noted that the number of second power connectors can be multiple, and can be set according to the number of connectors of different interface types in the downlink connectors to meet the power supply requirements of multiple downlink power connectors. The downlink power connectors can be arranged in an array on the fixture board, and this embodiment does not limit the number of power connectors. Similarly, the number of third power connectors can also be multiple, and can be set according to actual needs, and this embodiment does not limit the number of power connectors.

[0044] Optionally, the second baseboard management controller is connected to the downlink connector via an I2C bus for functional verification of the board under test connected to the downlink connector.

[0045] In an embodiment of the present invention, reference is made to Figure 2 The second baseboard management controller and the downlink connector can be connected via a bus, which can be an I2C bus or other data bus. This application embodiment does not limit the specific bus.

[0046] Specifically, the first IPMB connector in the uplink connector can be used for I2C communication between the baseboard management controller of the fixture board and the baseboard management controller of the motherboard. The second baseboard management controller of the fixture board can obtain the FRU information of the connected motherboard through I2C (bus), and then analyze and process the sideband signals input by the second sideband signal connector and the second MCIO connector according to the obtained platform information. Then, it connects to the board under test through the I2C bus and GPIO signal interface (General-purpose input / output) between the downlink connector, so that the hardware module circuit in the board under test can be functionally verified.

[0047] Optionally, the second baseboard management controller is provided with a universal input / output interface, which is connected to the downlink connector.

[0048] In an embodiment of the present invention, reference is made to Figure 2 The baseboard management controller is equipped with a general-purpose input / output (GPIO) interface, which connects to the downstream connector. The GPIO interface includes multiple pins, which can output high / low levels or read the pin status (high or low). Users can interact with the hardware through the GPIO interface to control hardware operation and read hardware status signals (such as interrupt signals).

[0049] The functions of general purpose input / output (GPIO) ports include acting as controllable port pins or connecting to chip peripherals via port mapping. When acting as a controllable port pin, the pin can be configured as either an input or an output. Output functions include strong push-pull output and open-drain output. When configured as a strong push-pull output, the user can define the pin's level at any given time, either high or low. When configured as an open-drain output, an external pull-up resistor is required to output a high-level signal. Input functions allow viewing the pin's level at any given time. Input functions include pull-up, pull-down, and high-impedance modes. Pull-up and pull-down modes respectively set the input pin to a high or low level, while the high-impedance mode results in an unstable input pin level.

[0050] Optionally, the board under test is connected to the test interface of the downstream connector via a cable; and / or, the board under test is directly plugged into the test interface of the downstream connector.

[0051] In this embodiment of the invention, the connection method between the board under test and the fixture board may include: one is that the board under test is connected to the downlink connector through a compatible cable; the other is that the board under test is directly inserted into the downlink connector.

[0052] For example, if the downstream connector includes a Gen_Z x32 connector, and the board under test (DUT) is a Riser card supporting the Gen_Z x32 interface, the gold fingers of the DUT can be directly inserted into the Gen_Z x32 connector on the fixture board. In this case, the fixture board is connected to the motherboard via four second MCIO x8 connectors, a second power connector, a second sideband signal connector, and cables. Similarly, if the downstream connector includes a Multitrack x16 connector, and the DUT is a Riser card supporting the Multitrack x16 interface, the gold fingers of the DUT can be directly inserted into the Multitrack x16 connector on the fixture board. The fixture board is connected to the motherboard via two MCIO x8 connectors, a second power connector, a second sideband signal connector, and cables. This connection between the DUT and the fixture board enables communication between the DUT and the motherboard, allowing for functional verification of multiple DUTs with different interface types using a single motherboard, thus improving testing efficiency. This application's solution isolates the board under test (DUT) and uses a fixture board to achieve compatible connections for DUTs with different interfaces. The high-speed bus signal from the second MCIO connector can be directly transferred to the DUT via the downlink connector, and the motherboard's sideband signals can be connected to the fixture board's BMC. The IPMB connector enables communication between the fixture board's BMC and the motherboard's BMC. The fixture board's BMC can parse and process the input sideband signals and transmit them to the DUT, thereby enabling functional verification of the hardware module circuits in the DUT. For DUTs of different projects / configurations, the same motherboard can be used for testing and verification, thereby reducing the complexity of test environment setup during R&D self-testing, improving testing efficiency, and reducing the time invested by R&D personnel in hardware development.

[0053] Optionally, the number of the first MCIO connectors is multiple; the number of the second MCIO connectors is multiple.

[0054] In an embodiment of the present invention, reference is made to Figure 2The uplink connector may include: a second IPMB connector, a second power connector, a second sideband signal connector, and a second MCIO connector. The high-speed bus signal from the second MCIO connector can be directly transferred to the board under test (DUT) via the downlink connector. The DUT can then communicate with the motherboard via the MCIO connector. Specifically, the second sideband signal connector of the fixture board communicates with the second sideband signal connector of the motherboard, and multiple MCIO connectors on the fixture board communicate with multiple MCIO connectors on the motherboard. The second sideband signal connector and the second MCIO connector can transmit the received sideband signals to the baseboard management controller of the fixture board. This allows the baseboard management controller to parse and process the sideband signals based on the communication connection between the second IPMB connector and the motherboard, thereby enabling communication with the DUT connected to the downlink connector. There are multiple first MCIO connectors and multiple second MCIO connectors; the specific number can be set according to the required number of interfaces on the DUT to be tested.

[0055] Optionally, the downlink connector includes a third MCIO connector, which connects to the board under test.

[0056] In this embodiment of the invention, the downlink connector may further include a third MCIO connector, used to establish a communication connection with the uplink connector and the board under test.

[0057] For example, the downlink connector may include multiple third MCIO connectors. When the board under test needs to connect to the MCIO connector to transmit data, the board under test can be directly connected to the MCIO connector in the downlink connector.

[0058] Furthermore, in one scenario, if the board under test is a Riser card that has both gold fingers and needs to be connected via cable, its gold fingers can be directly inserted into the corresponding interfaces of the uplink and downlink connectors on the fixture board. The cable portion can be connected to the third MCIO X8 connector, the third power connector, and the third sideband signal connector on the fixture board via an adapter cable. The corresponding second MCIO X8 interface, the second power connector, and the second sideband signal connector can be connected to the motherboard to achieve communication between the board under test and the motherboard.

[0059] Optionally, the downlink connector includes: a GEN_Z connector and a Multitrack connector; a second MCIO connector is connected to the GEN_Z connector; the second MCIO connector is connected to the Multitrack connector; the number of second MCIO connectors is the sum of a first number of MCIO connectors corresponding to the GEN_Z connector and a second number of MCIO connectors corresponding to the Multitrack connector; the GEN_Z connector is provided with a first slot for connecting a board under test (DUT) adapted to the Gen_Z interface; the DUT adapted to the Gen_Z interface is connected to the motherboard through four second MCIO connectors, a second power connector, and a second sideband signal connector; the Multitrack connector is provided with a second slot for connecting a DUT adapted to the Multitrack interface; the DUT adapted to the Multitrack interface is connected to the motherboard through two second MCIO connectors, a second power connector, and a second sideband signal connector.

[0060] In this embodiment of the invention, the number of MCIO connectors in the uplink connector is related to the number of connectors of different interface types in the downlink connector. Since the number of MCIO connectors required for communication between connectors of different interface types in the downlink connector is inconsistent, the number of MCIO connectors in the second uplink connector can be designed to correspond to the number of MCIO connectors required for communication between connectors of different interface types in the downlink connector.

[0061] For example, if the downlink connector includes a GEN_Z connector, and the GEN_Z connector requires four MCIO connectors to transmit data when communicating with the motherboard, then the uplink connector will have four MCIO connectors corresponding to the GEN_Z connector. These four MCIO connectors communicate only with the GEN_Z connector. If the downlink connector includes a Multitrack connector, and the Multitrack connector requires two MCIO connectors to transmit data when communicating with the motherboard, then the uplink connector will have two MCIO connectors corresponding to the Multitrack connector. These two MCIO connectors communicate only with the Multitrack connector.

[0062] Therefore, if the downlink connector is equipped with both a GEN_Z connector and a Multitrack connector, then the second connector will have six MCIO connectors, four of which are used to support communication of the GEN_Z connector and the other two are used to support communication of the Multitrack connector.

[0063] Of course, if the downlink connector also includes connectors of other interface types, the number of MCIO connectors in the second connector is set according to the MCIO specifications of those other interface types, so that communication connections to the motherboard under test can be achieved through the MCIO connectors in the second connector. The arrangement of multiple MCIO connectors on the fixture board can be an array arrangement, etc., which is not limited in this embodiment.

[0064] In addition, basic hardware testing and functional verification of the board under test include, but are not limited to: hardware low-speed signal testing, VR testing, current flow testing, data communication function testing of hardware module circuits (e.g., FRU information reading, Thermal Sensor information reading, BMC and CPLD or MCU information interaction, hard disk identification, PCIe card identification, etc.), error reporting function testing (e.g., fan board not in place or fan failure), control function testing (e.g., fan speed control, hard disk power on / off, LED lighting control, etc.).

[0065] Therefore, refer to Figure 3 The testing device of this application allows for the following steps for testing the board under test: 1. Select any existing motherboard and connect the upstream connector of the fixture board to the corresponding interface on the motherboard using an adapter cable; 2. Connect the board under test to the downstream connector of the fixture board using an adapter cable or a direct plug-in method; 3. Based on the PCIe / SAS / SATA protocol SPEC boundary values, select one set of links with the motherboard for signal testing and functional verification. The board under test connected to the fixture board may include: a riser card, backplane, mounting plate, fan plate, etc., and the specific components can be tested according to actual needs. This application embodiment does not limit the specific components.

[0066] This application separates the testing of the server's board under test, enabling decoupled development of the server motherboard and the board under test. For boards under test in different projects / configurations, the same motherboard can be used for testing and verification, thereby reducing the complexity of setting up the test environment during R&D self-testing, improving testing efficiency, and reducing the time investment of R&D personnel in hardware development.

[0067] In summary, this application discloses a testing device comprising: a motherboard, the motherboard having a first baseboard management controller, the first baseboard management controller being connected to a first IPMB connector and a field-replaceable unit via I2C, the first baseboard management controller being used to provide information stored in the field-replaceable unit to a fixture board via the first IPMB connector; the motherboard further comprising a first sideband signal connector, a first MCIO connector, and a first power connector; the fixture board comprising a second baseboard management controller, the second baseboard management controller being connected to a second IPMB connector via I2C, the second IPMB connector being connected to the first IPMB connector, and being used to acquire information stored in the field-replaceable unit of the motherboard; the fixture board further comprising a second sideband signal connector, a second MCIO connector, and a second power connector; the first sideband signal connector being connected to the second sideband signal connector, and being used to provide sideband signals to the fixture board; the first MCIO connector being connected to the second MCIO connector, and being used for high-speed data transmission between the fixture board and the motherboard; the first power connector being connected to the second power connector, and being used to supply power to the fixture board; the fixture board further comprising: a downlink connector; the downlink connector comprising multiple test interfaces for connecting different boards under test. This application's solution isolates the board under test (DUT) and uses a fixture board to achieve compatible connections for DUTs with different interfaces. The high-speed bus signal from the second MCIO connector can be directly transferred to the DUT via the downlink connector, and the motherboard's sideband signals can be connected to the fixture board's BMC. The IPMB connector enables communication between the fixture board's BMC and the motherboard's BMC. The fixture board's BMC can parse and process the input sideband signals and transmit them to the DUT, thereby enabling functional verification of the hardware module circuits in the DUT. For DUTs of different projects / configurations, the same motherboard can be used for testing and verification, thereby reducing the complexity of test environment setup during R&D self-testing, improving testing efficiency, and reducing the time invested by R&D personnel in hardware development.

[0068] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more.

[0069] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A testing device, characterized in that, include: The motherboard and the fixture board are provided. The motherboard is equipped with a first baseboard management controller. The first baseboard management controller is connected to a first IPMB connector and a field replaceable unit via I2C. The first baseboard management controller is used to provide the fixture board with the information stored in the field replaceable unit through the first IPMB connector. The motherboard also includes a first sideband signal connector, a first MCIO connector, and a first power connector; The fixture board includes a second baseboard management controller, which is connected to a second IPMB connector via I2C. The second IPMB connector is connected to the first IPMB connector and is used to acquire information stored in the field replaceable unit of the mainboard. The fixture plate also includes a second sideband signal connector, a second MCIO connector, and a second power connector. The first sideband signal connector is connected to the second sideband signal connector and is used to provide a sideband signal to the fixture plate; The first MCIO connector is connected to the second MCIO connector for high-speed data transmission between the fixture board and the motherboard; The first power connector and the second power connector are connected to supply power to the fixture plate; The fixture board also includes a downlink connector; the downlink connector includes multiple test interfaces for connecting different boards under test.

2. The testing apparatus according to claim 1, characterized in that, The second baseboard management controller, the second MCIO connector, and the second power connector are respectively connected to the downlink connector.

3. The testing apparatus according to claim 1, characterized in that, The downlink connector includes: a third power connector; The second power connector is connected to the third power connector and is used to supply power to the board under test.

4. The testing apparatus according to claim 1, characterized in that, The downlink connector includes: a GEN_Z connector power supply module and a Multitrack connector power supply module; The second power connector is connected to the GEN_Z connector power supply module and the Multitrack connector power supply module respectively, and is used to supply power to the GEN_Z connector power supply module and the Multitrack connector power supply module.

5. The testing apparatus according to claim 1, characterized in that, The second baseboard management controller is connected to the downlink connector via an I2C bus and is used to perform functional verification on the board under test connected to the downlink connector.

6. The testing apparatus according to claim 1, characterized in that, The second baseboard management controller is equipped with a universal input / output interface; The general-purpose input / output interface is connected to the downlink connector.

7. The testing apparatus according to claim 1, characterized in that, The board under test is connected to the test interface of the downlink connector via a cable; and / or, the board under test is directly plugged into the test interface of the downlink connector.

8. The testing apparatus according to claim 1, characterized in that, The number of the first MCIO connectors is multiple; the number of the second MCIO connectors is multiple.

9. The testing apparatus according to claim 1, characterized in that, The downlink connector includes a third MCIO connector; the third MCIO connector is connected to the board under test.

10. The testing apparatus according to claim 1, characterized in that, The downlink connectors include: a GEN_Z connector and a Multitrack connector; The second MCIO connector is connected to the corresponding GEN_Z connector; The second MCIO connector is connected to the corresponding Multitrack connector; The number of the second MCIO connector is the sum of the first number of MCIO connectors corresponding to the GEN_Z connector and the second number of MCIO connectors corresponding to the Multitrack connector; The GEN_Z connector is provided with a first slot, which is used to connect a board under test that is compatible with the Gen_Z interface; the board under test that is compatible with the Gen_Z interface is connected to the motherboard through four second MCIO connectors, a second power connector, and a second sideband signal connector. The Multitrack connector is provided with a second slot for connecting a board under test that is compatible with the Multitrack interface; the board under test that is compatible with the Multitrack interface is connected to the motherboard through two second MCIO connectors, a second power connector, and a second sideband signal connector.

Images