Display panel

Abstract

The present application provides a display panel including a substrate, a plurality of scan lines, a plurality of data lines and a plurality of pixel structures. The scan lines and the data lines are disposed on the substrate and define a plurality of pixel regions. The pixel structures are disposed corresponding to the pixel regions respectively and each include at least one active element, a reflective electrode, a first common electrode and a capacitor electrode. The active element disposed on the substrate is electrically connected to one scan line and one data line. The reflective electrode is electrically connected to the at least one active element. The first common electrode is disposed between the reflective electrode and the substrate. The capacitor electrode is disposed between the reflective electrode and the substrate. The capacitor electrode is electrically connected to the reflective electrode and a drain of the at least one active element and overlaps the first common electrode. At least one metal pattern overlaps the reflective electrode and is located between the substrate and the reflective electrode. In the orthographic projection of the substrate, more than 70% of the area of the reflective electrode overlaps the orthographic projection of the at least one metal pattern on the substrate.

Description

Technical Field

[0001] This invention relates to a display technology, and more particularly to a display panel. Background Technology

[0002] In response to energy-saving requirements, a total internal reflection or transmissive reflection liquid crystal display panel has been proposed. These types of display panels are mostly equipped with reflective electrodes to reflect ambient light for display purposes. To increase reflection efficiency, the reflective electrodes are generally made of highly reflective metal materials, and their distribution range in the display pixel area is maximized. However, other electronic components or conductive structures that constitute the pixel structure are usually located within the display pixel area. Therefore, as the distribution range of the reflective electrodes increases, height differences arise on the surface due to the different metal stacking structures at different locations within the pixel area. This results in uneven film thickness of the display dielectric layer in the reflective electrode area, leading to a decrease in overall reflection efficiency. Summary of the Invention

[0003] The present invention relates to a display panel with reflective electrodes, which has better overall reflectivity.

[0004] According to an embodiment of the present invention, a display panel includes a substrate, multiple scan lines, multiple data lines, and multiple pixel structures. The scan lines and data lines are intersectingly disposed on the substrate and define multiple pixel regions. The pixel structures are respectively disposed corresponding to these pixel regions and each includes at least one active element, a reflective electrode, a first common electrode, and a capacitor electrode. The active element disposed on the substrate is electrically connected to one scan line and one data line. The reflective electrode is electrically connected to at least one active element. The first common electrode is disposed between the reflective electrode and the substrate. The capacitor electrode is disposed between the reflective electrode and the substrate. The capacitor electrode is electrically connected to the reflective electrode and the drain of at least one active element, and overlaps with the first common electrode. At least one metal pattern overlaps with the reflective electrode and is located between the substrate and the reflective electrode. More than 70% of the area of ​​the reflective electrode in its orthographic projection onto the substrate overlaps with the orthographic projection of the at least one metal pattern onto the substrate.

[0005] In a display panel according to an embodiment of the present invention, each of the plurality of pixel structures further includes a coating layer disposed between a reflective electrode and at least one metal pattern.

[0006] In a display panel according to an embodiment of the present invention, each of the plurality of pixel structures further includes a transparent conductive layer disposed between a reflective electrode and a capacitive electrode, and includes a first transparent conductive pattern. The reflective electrode is electrically connected to the capacitive electrode via the first transparent conductive pattern.

[0007] In a display panel according to an embodiment of the present invention, at least one metal pattern includes a first common electrode and a capacitor electrode. The first common electrode belongs to a first metal layer, and the capacitor electrode belongs to a second metal layer.

[0008] In a display panel according to an embodiment of the present invention, scan lines belong to a first metal layer and data lines belong to a second metal layer.

[0009] In a display panel according to an embodiment of the present invention, each of the plurality of pixel structures includes two active elements, and the two active elements are electrically connected to two scan lines of the plurality of scan lines respectively. Each of the plurality of pixel structures also includes a dummy electrode disposed between a reflective electrode and a substrate, and located between two scan lines. The dummy electrode belongs to a first metal layer and is electrically insulated from the two scan lines of the plurality of scan lines, wherein at least one metal pattern further includes two scan lines and the dummy electrode.

[0010] In a display panel according to an embodiment of the present invention, each of the plurality of pixel structures further includes a second common electrode disposed between a capacitor electrode and a reflective electrode. The second common electrode overlaps with the capacitor electrode and belongs to a third metal layer. At least one metal pattern further includes a second common electrode.

[0011] In a display panel according to an embodiment of the present invention, each of the plurality of pixel structures further includes an auxiliary electrode disposed between the reflective electrode and the substrate, and overlapping the first common electrode. The auxiliary electrode belongs to a second metal layer and is electrically insulated from the capacitor electrode. At least one metal pattern further includes an auxiliary electrode.

[0012] In a display panel according to an embodiment of the present invention, the distance between the auxiliary electrode and the capacitor electrode is between 0.5 micrometers and 7.0 micrometers.

[0013] In a display panel according to an embodiment of the present invention, the auxiliary electrode has a floating potential.

[0014] In a display panel according to an embodiment of the present invention, each of the plurality of pixel structures further includes a dummy electrode disposed between a reflective electrode and a substrate, and overlapping one of the plurality of scan lines. The dummy electrode belongs to a second metal layer and is electrically insulated from the auxiliary electrode. At least one metal pattern further includes scan lines and dummy electrodes.

[0015] In a display panel according to an embodiment of the present invention, the auxiliary electrodes have a common potential.

[0016] In a display panel according to an embodiment of the present invention, each of the plurality of pixel structures further includes a second common electrode and a second transparent conductive pattern. The second common electrode is disposed between the capacitor electrode and the reflective electrode and between the auxiliary electrode and the reflective electrode, and overlaps the capacitor electrode and the auxiliary electrode. The second common electrode belongs to a third metal layer. The auxiliary electrode is electrically connected to the second common electrode via the second transparent conductive pattern. At least one metal pattern further includes the second common electrode.

[0017] In a display panel according to an embodiment of the present invention, each of the plurality of pixel structures further includes a dummy electrode, which is disposed overlapping at least one active element. The dummy electrode belongs to a third metal layer and is electrically insulated from a second common electrode. At least one metal pattern also includes a dummy electrode.

[0018] Based on the above, in a display panel according to an embodiment of the present invention, at least one metal pattern is overlapped between the reflective electrode and the substrate, and more than 70% of the area of ​​the reflective electrode in the orthographic projection of the substrate overlaps with the orthographic projection of the at least one metal pattern in the orthographic projection of the substrate. Accordingly, the height difference of the metal stacking structure at different positions within the configuration area of ​​the reflective electrode can be effectively reduced, thereby improving the overall reflection efficiency of the reflective electrode. Attached Figure Description

[0019] Figure 1 is a top view of the display panel according to the first embodiment of the present invention;

[0020] Figure 2 is a cross-sectional view of the display panel in Figure 1;

[0021] Figures 3A to 3H are top views of each film layer in the display panel of Figure 1;

[0022] Figure 4 is a top view of a first variant of the first embodiment;

[0023] Figure 5 is a top view of the third metal layer in the display panel of Figure 4;

[0024] Figure 6 is a top view of the display panel of a second variation of the first embodiment of the present invention;

[0025] Figure 7 is a cross-sectional view of the display panel in Figure 6;

[0026] Figure 8 is a top view of the display panel according to the second embodiment of the present invention;

[0027] Figures 9A to 9C are top views of some of the film layers in the display panel of Figure 8;

[0028] Figure 10 is a cross-sectional view of the display panel in Figure 8;

[0029] Figure 11 is a top view of the display panel according to the third embodiment of the present invention;

[0030] Figure 12 is a top view of the second metal layer in the display panel of Figure 11;

[0031] Figure 13 is a top view of the display panel according to the fourth embodiment of the present invention;

[0032] Figures 14A to 14H are top views of each film layer in the display panel of Figure 13;

[0033] Figure 15 is a top view of the display panel according to the fifth embodiment of the present invention;

[0034] Figure 16 is a top view of the display panel according to the sixth embodiment of the present invention;

[0035] Figure 17 is a top view of the second metal layer in the display panel of Figure 16.

[0036] Explanation of reference numerals in the attached figures

[0037] 10, 10-1, 10-2, 10A, 10B, 20A, 20B, 20C: Display panels;

[0038] 100, 200: substrate;

[0039] 110, 121, 122, 121A, 122A: Insulation layer;

[0040] 130, 130A: Overburden;

[0041] AE, AE-A: Auxiliary electrode;

[0042] CE1: First common electrode;

[0043] CE2, CE2-1, CE2-A: Second common electrode;

[0044] CE3: Third common electrode;

[0045] CE2op, OP: Opening;

[0046] CPE, CPE-A: Capacitor electrodes;

[0047] Cst1: First storage capacitor;

[0048] Cst2: Second storage capacitor;

[0049] Cst3: Third storage capacitor;

[0050] d: Unit gap;

[0051] DE: Drain electrode;

[0052] DL: Data cable;

[0053] DME1, DME2, DME3, DME1a, DME1b, DME2a, DME2b, DME2c, DME3a, DME3b, DME3c, DME4: Dummy electrodes;

[0054] GE: Gate;

[0055] GP: gap;

[0056] LC: Display media layer;

[0057] ML1, ML1-A: First metal layer;

[0058] ML2, ML2-A, ML2-B, ML2-C: Second metal layer;

[0059] ML3, ML3-1, ML3-A, ML3-B, ML3-C: Third metal layer;

[0060] ML4: Fourth metal layer;

[0061] NH: Gap;

[0062] PA: Pixel area;

[0063] PX, PX-1, PX-2, PX-A, PX-B, PX-C, PX-D, PX-E: Pixel structure;

[0064] RE, RE-A: Reflective electrodes;

[0065] S1x, S1y, S2, S3, S4x, S4y, S5, S6: Spacing;

[0066] SC: Semiconductor pattern;

[0067] SE: Source pole;

[0068] SL, SL1, SL2: Scan lines;

[0069] T, T1, T2: Active components;

[0070] TCL, TCL-A: Transparent conductive layer;

[0071] TCP1: First transparent conductive pattern;

[0072] TCP2: Second transparent conductive pattern;

[0073] TH, TH1, TH2, TH”: Contact holes;

[0074] X, Y, Z: Direction;

[0075] A-A': section line. Detailed Implementation

[0076] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0077] Figure 1 is a top view of the display panel according to the first embodiment of the present invention. Figure 2 is a cross-sectional view of the display panel of Figure 1. Figure 2 corresponds to the section line A-A' in Figure 1. Figures 3A to 3H are top views of each film layer in the display panel of Figure 1. Referring to Figures 1 and 2, the display panel 10 includes a substrate 100, scan lines SL, data lines DL, and pixel structures PX. It is easy to understand that although Figure 1 only shows one scan line SL, one data line DL, and one pixel structure PX, the substrate 100 of the display panel 10 can actually be provided with multiple pixel structures PX and signal lines as shown in Figure 1. For example, multiple data lines DL can be arranged along the direction X and each data line DL extends in the direction Y, and multiple scan lines SL can be arranged along the direction Y and each scan line SL extends in the direction X. More specifically, these data lines DL intersect with these scan lines SL and define multiple pixel areas PA. Multiple pixel structures PX are respectively disposed in these pixel areas PA. Furthermore, for the sake of simplicity, FIG1 only shows a top view of the array substrate of the display panel 10, and omits the opposing substrate of the display panel and the display medium layer (e.g., liquid crystal layer) located between the array substrate and the opposing substrate, while FIG2 shows a cross-sectional view of the array substrate, the display medium layer and the opposing substrate of the display panel 10.

[0078] The pixel structure PX includes an active element T, a first common electrode CE1, a capacitor electrode CPE, and a reflective electrode RE. The first common electrode CE1 and the capacitor electrode CPE are disposed between the reflective electrode RE and the substrate 100. The capacitor electrode CPE is electrically connected to the reflective electrode RE and the active element T, and is electrically insulated from the first common electrode CE1. In this embodiment, the capacitor electrode CPE overlaps the first common electrode CE1 along the normal direction (e.g., direction Z) of the upper surface of the substrate 100, forming the storage capacitor of the pixel structure PX. For example, the storage capacitor (or the first storage capacitor) Cst1 is formed by the first common electrode CE1, the capacitor electrode CPE, and an insulating layer 110 located between the first common electrode CE1 and the capacitor electrode CPE. It should be noted that, unless otherwise specified below, when one component overlaps another component, it refers to the overlap relationship between the two components along the direction Z, which will not be elaborated further.

[0079] The active element T includes a gate GE, a source SE, a drain DE, and a semiconductor pattern SC. The gate GE and the source SE are electrically connected to a corresponding scan line SL and a data line DL, respectively. The source SE and the drain DE are electrically connected to two different regions (e.g., the source region and the drain region) of the semiconductor pattern SC. The capacitor electrode CPE is electrically connected to the drain DE of the active element T. In this embodiment, the gate GE of the active element T may be a portion extending from the scan line SL, and the source SE may be a portion extending from the data line DL, but this is not a limitation.

[0080] In some embodiments, an ohmic contact layer is further provided between the source SE and the semiconductor pattern SC, and between the drain DE and the semiconductor pattern SC. The material of the ohmic contact layer may be, for example, a doped amorphous silicon layer, but is not limited thereto. In this embodiment, an insulating layer 110 is provided between the gate GE and the semiconductor pattern SC, and the gate GE is optionally disposed below the semiconductor pattern SC to form a bottom-gate type active element. The insulating layer 110 is, for example, a gate insulating layer, and its material may include silicon oxide, silicon nitride, or other suitable dielectric materials. However, the invention is not limited thereto. In other embodiments, the gate GE may also be disposed above the semiconductor pattern SC to form a top-gate type active element. In this embodiment, the active element T is, for example, an amorphous silicon thin film transistor (a-Si TFT), but is not limited thereto. In other embodiments, the active element T may also be a polycrystalline silicon thin film transistor (poly-Si TFT) or a metal oxide semiconductor thin film transistor (metal oxide semiconductor TFT).

[0081] In this embodiment, the display panel 10 may further include a second common electrode CE2 and a first transparent conductive pattern TCP1. The second common electrode CE2 is disposed between the capacitor electrode CPE and the reflective electrode RE, and overlaps the capacitor electrode CPE and the reflective electrode RE. The first transparent conductive pattern TCP1 is disposed between the reflective electrode RE and the second common electrode CE2, and overlaps the capacitor electrode CPE and the second common electrode CE2. An insulating layer 121 is provided between the second common electrode CE2 and the capacitor electrode CPE, and an insulating layer 122 is provided between the second common electrode CE2 and the first transparent conductive pattern TCP1. The insulating layers 121 and 122 may be passivation layers, and their materials include, for example, silicon nitride, silicon oxide, silicon carbide, or aluminum oxide, but are not limited thereto. For example, the second storage capacitor Cst2 is formed by a capacitor electrode CPE, a second common electrode CE2 and an insulating layer 121 located between the capacitor electrode CPE and the second common electrode CE2, and the third storage capacitor Cst3 is formed by the second common electrode CE2, a first transparent conductive pattern TCP1 and an insulating layer 122 located between the second common electrode CE2 and the first transparent conductive pattern TCP1.

[0082] Insulating layers 121 and 122 are provided with contact holes TH (as shown in FIG. 3E), and a first transparent conductive pattern TCP1 disposed on insulating layer 122 extends into contact hole TH to electrically connect to capacitor electrode CPE. In this embodiment, in order to increase the surface flatness of reflective electrode RE, a coating layer 130 is also provided between reflective electrode RE and the first transparent conductive pattern TCP1, and between reflective electrode RE and insulating layer 122. The coating layer 130 is provided with an opening OP (as shown in FIG. 3G), and the reflective electrode RE disposed on coating layer 130 extends into opening OP to electrically connect to the first transparent conductive pattern TCP1. Specifically, the drain DE of active element T, capacitor electrode CPE, first transparent conductive pattern TCP1 and reflective electrode RE are electrically connected to each other and have the same potential. When active element T is turned on, data of data line DL is transmitted through the turned-on active element T to the drain DE of active element T, capacitor electrode CPE, first transparent conductive pattern TCP1 and reflective electrode RE. In addition, the first common electrode CE1 and the second common electrode CE2 can receive a common potential. For example, the display panel 10 has a display area and a peripheral area, a pixel structure PX located in the display area, and at least one common potential line located in the peripheral area. A first common electrode CE1 and a second common electrode CE2 are electrically connected to the common potential line to receive a common potential. The material of the coating layer 130 may include inorganic materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stack of at least two of the above materials), organic materials (e.g., polyesters, polyolefins, polyacrylonitriles, polycarbonates, polyoxyalkylene compounds, polystyrene, polyethers, polyketides, polyols, polyaldehydes, or other suitable materials, or combinations thereof), or other suitable materials, or combinations thereof.

[0083] In this embodiment, the cladding layer 130 may also be referred to as a planarization layer to reduce the unevenness of the film layer located below the cladding layer 130, that is, the flatness of the upper surface of the cladding layer 130 is greater than the flatness of the lower surface of the cladding layer 130. For example, the cladding layer 130 may be an organic material and formed on the substrate 100 by a coating method (e.g., spin coating or slit coating), but is not limited thereto. The film thickness of the cladding layer 130 in the Z direction may be greater than the film thickness of either insulating layer 121 or 122 in the Z direction, but is not limited thereto. For example, the film thickness of the cladding layer 130 may range from 1 micrometer to 5 micrometers, but is not limited thereto.

[0084] By the electrical coupling relationship between the second common electrode CE2 and the capacitor electrode CPE (i.e. forming the second storage capacitor Cst2) and the electrical coupling relationship between the second common electrode CE2 and the first transparent conductive pattern TCP1 (i.e. forming the third storage capacitor Cst3), the storage capacity of the pixel structure PX can be effectively increased (i.e. the total storage capacity of the pixel structure PX includes the first to third storage capacitors Cst1, Cst2, and Cst3 connected in parallel).

[0085] It is particularly noteworthy that, in this embodiment, the reflective electrode RE can completely cover the side of the active element T, scan line SL, data line DL, first common electrode CE1, capacitor electrode CPE, and second common electrode CE2 facing away from the substrate 100. That is, within the configuration range of the reflective electrode RE (i.e., the reflective area of ​​the pixel structure PX), multiple metal patterns are provided between the reflective electrode RE and the substrate 100. These metal patterns include patterns of the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3, such as those of the data line DL, scan line SL, first common electrode CE1, second common electrode CE2, capacitor electrode CPE, and the gate GE, source SE, and drain DE of the active element T. However, the present invention is not limited thereto. In other embodiments not shown, the configuration range of the reflective electrode RE within the pixel area PA (i.e., the range of the reflective area of ​​the pixel structure PX) can be adjusted according to actual application requirements. For example, the reflective electrode RE may not overlap at least one of the data line DL, scan line SL, and active element T. Furthermore, within the configuration range of the reflective electrodes RE, the cladding layer 130 is located in the Z direction between these metal patterns and the reflective electrodes RE.

[0086] As shown in Figure 2, the display panel 10 may further include another substrate 200, a third common electrode CE3, and a display medium layer LC. The display medium layer LC may be, for example, a liquid crystal layer, but is not limited thereto. The third common electrode CE3 is disposed on the surface of the substrate 200 facing the substrate 100, and the display medium layer LC is disposed between the reflective electrode RE and the third common electrode CE3. In some embodiments, at least one of a light-shielding layer (e.g., a black matrix layer), a color filter layer, and a planarization layer may also be disposed on the surface of the substrate 200 facing the substrate 100. The third common electrode CE3 may receive a common potential. For example, when the display medium layer LC is a liquid crystal layer, the electric field formed between the reflective electrode RE and the third common electrode CE3 can control the state of the liquid crystal layer to display the corresponding image. Because the flatness of the upper surface of the reflective electrode RE affects the cell gap d of the display panel 10, in order to reduce the variation of the cell gap d in different regions of the reflective area of ​​the pixel structure PX to avoid affecting the reflection efficiency, it is necessary to reduce the variation of the flatness of the upper surface of the reflective electrode RE in different regions of the reflective area of ​​the pixel structure PX. It should be noted that although the cladding layer 130 serves as a planarization layer to reduce the unevenness of the film layer below it, the flatness of the upper surface of the cladding layer 130 is still affected by the flatness of the film layer below it. Furthermore, when the film thickness of the cladding layer 130 decreases, the flatness of the upper surface of the cladding layer 130 is more significantly affected by the flatness of the film layer below it. Because the reflective electrode RE is located on and conformally to the cladding layer 130, the flatness of the upper surface of the reflective electrode RE is affected by the metal pattern below it (in this embodiment, the pattern of the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3). Therefore, within the reflective region of the pixel structure PX, the height difference between the metal stack structures below the reflective electrode RE should be minimized to improve the flatness of the upper surface of the reflective electrode RE, thereby making the cell gap d in the reflective region of the pixel structure PX uniform and improving the reflection efficiency.

[0087] As shown in Figures 3A, 3C, and 3D, in this embodiment, since the distribution range of the second common electrode CE2 is approximately the same as that of the first common electrode CE1, and the distribution range of the capacitor electrode CPE is significantly smaller than that of the first common electrode CE1 (or the second common electrode CE2), that is, the capacitor electrode CPE overlaps a portion of the first common electrode CE1 and a portion of the second common electrode CE2. Therefore, in order to reduce the height difference between the metal stacked structure in the setting area of ​​the capacitor electrode CPE and the metal stacked structure in the setting area of ​​the first common electrode CE1 that does not overlap with the setting area of ​​the capacitor electrode CPE, an auxiliary electrode AE ​​can also be superimposed in the setting area of ​​the first common electrode CE1 that does not overlap with the setting area of ​​the capacitor electrode CPE.

[0088] On the other hand, a dummy electrode DME1 can be superimposed within the area where the active element T is located to reduce the coupling effect between the active element T and the reflective electrode RE, thereby preventing leakage current caused by the potential of the reflective electrode RE causing the active element T to conduct. The dummy electrode DME1 can also reduce the height difference between the metal stack structure within the area where the active element T is located and the metal stack structure within the area where the first common electrode CE1 is located. Furthermore, dummy electrodes DME2 and DME3 can be superimposed within the area where the scan line SL is located, with the scan line SL and the dummy electrodes DME2 and DME3 overlapping each other to reduce the height difference between the metal stack structure within the area where the scan line SL is located and the metal stack structure within the area where the first common electrode CE1 is located.

[0089] Specifically, in this embodiment, the auxiliary electrode AE ​​overlapping the first common electrode CE1, the dummy electrode DME1 overlapping the active element T, and the dummy electrodes DME2 and DME3 overlapping the scan line SL are four metal patterns with floating potentials. These four metal patterns can be used to reduce the height difference between the metal stack structures located below the reflective electrode RE to improve the flatness of the upper surface of the reflective electrode RE. In this embodiment, the four metal patterns of the auxiliary electrode AE, dummy electrode DME1, and dummy electrodes DME2 and DME3 can also be referred to as planarization enhancement metal patterns. In this embodiment, the area of ​​the auxiliary electrode AE ​​is much larger than the area of ​​any one of the dummy electrodes DME1, DME2, and DME3; therefore, the auxiliary electrode AE ​​is the main planarization enhancement metal pattern in this embodiment. In some embodiments, the pixel structure may not include at least one of the dummy electrodes DME1, DME2, and DME3. That is, the planarization enhancement metal pattern of the pixel structure may only include the auxiliary electrode AE, or may include, in addition to the auxiliary electrode AE, the dummy electrode DME1 and any one or two of the dummy electrodes DME2 and DME3. The percentage of the positive projection area of ​​these planarization enhancement metal patterns and the aforementioned plurality of metal patterns (e.g., including the data line DL, scan line SL, first common electrode CE1, second common electrode CE2, capacitor electrode CPE, and the gate GE, source SE, and drain DE of the active element T) on the reflective electrode RE is greater than 70%. That is, from the top view (i.e., direction Z), more than 70% of the area of ​​the reflective electrode RE overlaps with the metal pattern located below the reflective electrode RE (i.e., less than or equal to 30% of the area of ​​the reflective electrode RE does not overlap with the metal pattern located below the reflective electrode RE). In other words, more than 70% of the area of ​​the reflective electrode RE in the orthographic projection of the substrate 100 overlaps with the orthographic projection of the metal pattern located below the reflective electrode RE on the substrate 100 (i.e., less than or equal to 30% of the area of ​​the reflective electrode RE in the orthographic projection of the substrate 100 does not overlap with the orthographic projection of the metal pattern located below the reflective electrode RE on the substrate 100). Specifically, in this embodiment, the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 are formed before the reflective electrode RE is formed (i.e., at least a portion of the first metal layer ML1, at least a portion of the second metal layer ML2, and at least a portion of the third metal layer ML3 are located below the reflective electrode RE). Therefore, the aforementioned metal pattern located below the reflective electrode RE includes, but is not limited to, the patterns of the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3.

[0090] Furthermore, preferably, in the region where the reflective electrode RE overlaps with the metal pattern located below the reflective electrode RE, the area of ​​the region with the most stacked metal layers is larger than the area of ​​the region with fewer stacked metal layers or a single metal layer. For example, in this embodiment, the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 are formed before the reflective electrode RE is formed. In the region where the reflective electrode RE overlaps with the metal pattern located below the reflective electrode RE, the metal pattern may include a three-layer metal layer stack (i.e., the first metal layer ML1, the second metal layer ML2, and the third metal layer ML3 stacked on top of each other) pattern, a two-layer metal layer stack (i.e., the first metal layer ML1 and the second metal layer ML2 stacked, the first metal layer ML1 and the third metal layer ML3 stacked, or the second metal layer ML2 and the third metal layer ML3 stacked) pattern, and / or a single metal layer (i.e., the first metal layer ML1, the second metal layer ML2, or the third metal layer ML3) pattern, and the area of ​​the three-layer metal layer stack pattern is larger than the area of ​​either the two-layer metal layer stack pattern or the single metal layer pattern, but is not limited thereto.

[0091] Accordingly, the height difference of the metal stacking structure at different locations within the configuration area of ​​the reflective electrode RE (i.e., the reflective area of ​​the pixel structure PX) can be effectively reduced, thereby increasing the uniformity of the cell gap d in the reflective area and improving the overall reflection efficiency of the reflective electrode RE. Furthermore, by setting these planarization-enhanced metal patterns, the surface flatness of the reflective electrode RE can be ensured even with a reduced film thickness of the cladding layer 130.

[0092] The display panel 10 in this embodiment can be a reflective liquid crystal display panel. However, the present invention is not limited thereto. In other embodiments, the invention content of this disclosure can also be applied to the pixel structure of other types of display panels, such as transflective liquid crystal display panels. For example, the pixel structure of a transflective liquid crystal display panel has a reflective area and a transmissive area, with a reflective electrode disposed in the reflective area, and the invention content of this disclosure can be applied to the reflective area in the pixel structure.

[0093] The following will provide an exemplary description of the manufacturing method of the display panel 10.

[0094] Please refer to Figures 1, 2, and 3A, where Figure 3A is a top view of the first metal layer ML1. First, the first metal layer ML1 is formed on the substrate 100. The first metal layer ML1 includes a gate GE, a scan line SL, and a first common electrode CE1. The material of the first metal layer ML1 includes, for example, molybdenum, aluminum, copper, nickel, chromium, the aforementioned alloys, or the aforementioned stacked structure. Next, an insulating layer 110 is formed on the first metal layer ML1. In this embodiment, after forming the insulating layer 110, a semiconductor pattern SC can be formed on the insulating layer 110, as shown in Figure 3B. The material of the semiconductor pattern SC includes, for example, amorphous silicon semiconductor, single-crystal silicon semiconductor, polycrystalline silicon semiconductor, or metal oxide semiconductor.

[0095] Referring to Figures 1, 2, and 3C, a second metal layer ML2 is formed on the insulating layer 110. A top view of the second metal layer ML2 is shown in Figure 3C. In this embodiment, the second metal layer ML2 includes a data line DL, a drain DE, a source SE, an auxiliary electrode AE, a capacitor electrode CPE, and a dummy electrode DME2. The capacitor electrode CPE overlaps the first common electrode CE1 and is electrically connected to the drain DE. Specifically, the source SE, drain DE, gate GE, semiconductor pattern SC, and a portion of the insulating layer 110 can form the active element T in this embodiment. The material of the second metal layer ML2 includes, for example, molybdenum, aluminum, copper, nickel, chromium, the aforementioned alloys, or the aforementioned laminated structure.

[0096] After completing the second metal layer ML2, an insulating layer 121 is formed on the second metal layer ML2, as shown in FIG2. Next, a third metal layer ML3 is formed on the insulating layer 121, and a top view of the third metal layer ML3 is shown in FIG3D. The third metal layer ML3 includes a second common electrode CE2 and dummy electrodes DME1 and DME3. The second common electrode CE2 overlaps the first common electrode CE1, the capacitor electrode CPE, and the auxiliary electrode AE. The second common electrode CE2 has a notch NH, which overlaps a portion of the capacitor electrode CPE. The material of the third metal layer ML3 includes, for example, molybdenum, aluminum, copper, nickel, chromium, the aforementioned alloys, or the aforementioned laminated structure.

[0097] After completing the third metal layer ML3, another insulating layer 122 is formed on the third metal layer ML3. Next, a contact hole TH is formed in the insulating layers 121 and 122. This contact hole TH overlaps the notch NH of the third metal layer ML3 and the capacitor electrode CPE (i.e., the contact hole TH overlaps the capacitor electrode CPE, but not the third metal layer ML3), and exposes a portion of the capacitor electrode CPE. A top view of the contact hole TH is shown in Figure 3E.

[0098] Referring to Figures 1, 2, and 3F, a transparent conductive layer TCL is formed on the insulating layer 122. A top view of the transparent conductive layer TCL is shown in Figure 3F. The transparent conductive layer TCL includes a first transparent conductive pattern TCP1. The material of the transparent conductive layer TCL may include, for example, indium tin oxide, but the present invention is not limited to the material of the transparent conductive layer TCL. The first transparent conductive pattern TCP1 overlaps the capacitor electrode CPE and is electrically connected to the capacitor electrode CPE via a contact hole TH. Next, a coating layer 130 is formed on the transparent conductive layer TCL, wherein the coating layer 130 has an opening OP that exposes a portion of the first transparent conductive pattern TCP1. A top view of the opening OP is shown in Figure 3G.

[0099] After the coating layer 130 is completed, a fourth metal layer ML4 is formed on the coating layer 130. The fourth metal layer ML4 includes a reflective electrode RE, and the reflective electrode RE is electrically connected to the first transparent conductive pattern TCP1 through the opening OP of the coating layer 130. The material of the fourth metal layer ML4 includes, for example, silver, aluminum or other metal materials with high reflectivity, the aforementioned alloys, or the aforementioned laminated structure. A top view of the reflective electrode RE is shown in Figure 3H.

[0100] It should be noted that, in order to achieve better planarization of the cladding layer 130, the distance between two adjacent electrodes in the same metal layer should not be too large. In this embodiment, the distance between two adjacent electrodes in the same metal layer is preferably between 0.5 micrometers and 7.0 micrometers, but is not limited thereto. For example, referring to FIG3C, in the second metal layer ML2, there is a gap GP between the adjacent and electrically insulated auxiliary electrode AE ​​and the capacitor electrode CPE. The distance S1x between the auxiliary electrode AE ​​and the capacitor electrode CPE in the X direction and the distance S1y in the Y direction are preferably both between 0.5 micrometers and 7.0 micrometers. The distance S2 between the adjacent and electrically insulated auxiliary electrode AE ​​and the dummy electrode DME2 in the Y direction is preferably between 0.5 micrometers and 7.0 micrometers. The distance S3 between the adjacent and electrically insulated capacitor electrode CPE and the dummy electrode DME2 in the Y direction is preferably between 0.5 micrometers and 7.0 micrometers. Referring to Figure 3D, in the third metal layer ML3, the spacings S4x and S4y of the adjacent and electrically insulated second common electrode CE2 and dummy electrode DME1 in the X and Y directions, respectively, and the spacing of the adjacent and electrically insulated second common electrode CE2 and dummy electrode DME3 in the Y direction, are preferably between 0.5 micrometers and 7.0 micrometers.

[0101] In this embodiment, the method for manufacturing the display panel 10 further includes: forming another transparent conductive layer on another substrate 200, wherein the other transparent conductive layer includes a third common electrode CE3. After the fabrication of the other transparent conductive layer is completed, the substrate 100 and the other substrate 200 are assembled such that the substrate 100 and the other substrate 200 are facing each other, and a display medium layer LC is provided between the substrate 100 and the other substrate 200. Thus, the fabrication of the display panel 10 of this embodiment is completed.

[0102] Other embodiments will be listed below to illustrate this disclosure in detail, wherein the same components will be marked with the same symbols, and the description of the same technical content will be omitted. For the omitted parts, please refer to the foregoing embodiments, and they will not be repeated below.

[0103] Figure 4 is a top view of a first variation of the first embodiment. Figure 5 is a top view of the third metal layer in the display panel of Figure 4. Referring to Figures 4 and 5, the pixel structure PX-1 of the display panel 10-1 in this variation is different from the pixel structure PX in the first embodiment in that the third metal layer ML3-1 in this variation is different from the third metal layer ML3 in the first embodiment. Specifically, the second common electrode CE2-1 in this variation is different from the second common electrode CE2 in the first embodiment. On the other hand, the top view of the first metal layer ML1, semiconductor pattern SC, second metal layer ML2, contact hole TH, transparent conductive layer TCL, opening OP of coating layer 130 and reflective electrode RE in this variation is similar to that in the first embodiment, and can be referred to Figures 3A to 3C and Figures 3E to 3H respectively, which will not be described again here.

[0104] The third metal layer ML3-1 of the display panel 10-1 in this variation embodiment includes a dummy electrode DME1 and a second common electrode CE2-1. The difference between this variation embodiment and the first embodiment is that the pixel structure PX-1 in this variation embodiment does not include the dummy electrode DME3 of the first embodiment, and the second common electrode CE2-1 extends to and covers the scan line SL (i.e., a portion of the second common electrode CE2-1 is located between the scan line SL and the reflective electrode RE in the Z direction), and the second common electrode CE2-1 extends to and covers the data line DL (i.e., another portion of the second common electrode CE2-1 is located between the data line DL and the reflective electrode RE in the Z direction), to avoid interference from the signals of the scan line SL and / or the data line DL on the potential of the reflective electrode RE, thereby improving image quality and reducing the height difference between the metal stacked structure in the area where the scan line SL and the data line DL are located and the metal stacked structure in the area where the first common electrode CE1 is located. The remaining portion of the second common electrode CE2-1 is the same as the second common electrode CE2 of the first embodiment, and will not be described again here.

[0105] Figure 6 is a top view of the display panel of the second variation of the first embodiment of the present invention. Figure 7 is a cross-sectional view of the display panel of Figure 6. Figure 7 corresponds to the section line B-B' of Figure 6. Referring to Figures 6 and 7, the difference between the display panel 10-2 of this variation and the display panel 10 of the first embodiment is that the pixel structure PX of the first embodiment has four metal layers (i.e., the first to fourth metal layers ML1-ML4), while the pixel structure PX-2 of the display panel 10-2 of this variation has three metal layers (i.e., the first, second, and fourth metal layers ML1, ML2, and ML4). Specifically, compared with the first embodiment, the display panel 10-2 of this variation does not have the third metal layer ML3 of the first embodiment (i.e., it does not have the second common electrode CE2 and the dummy electrodes DME1 and DME3) and the insulating layer 122, and the coating layer 130 is disposed between the reflective electrode RE and the transparent conductive layer TCL and between the reflective electrode RE and the insulating layer 121. Therefore, the insulating layer 121 has a contact hole TH”, which overlaps with the capacitor electrode CPE and exposes a portion of the capacitor electrode CPE, and the first transparent conductive pattern TCP1 is electrically connected to the capacitor electrode CPE via the contact hole TH”.

[0106] In this variant embodiment, the top view of the first metal layer ML1, the semiconductor pattern SC, the second metal layer ML2, the transparent conductive layer TCL, the opening OP of the cladding layer 130, and the reflective electrode RE is similar to that of the first embodiment, and can be referred to in Figures 3A to 3C and Figures 3F to 3H respectively. The top view of the contact hole "TH" is referred to in Figure 3E, and the marking TH(121 / 122) in Figure 3E is replaced with TH(121).

[0107] The steps in the manufacturing method of the display panel 10-2 in this variation embodiment, namely forming the first metal layer ML1, insulating layer 110, semiconductor pattern SC, second metal layer ML2, insulating layer 121, contact hole TH", transparent conductive layer TCL, coating layer 130 and fourth metal layer ML4, are similar to those in the first embodiment. The difference is that in this variation embodiment, the contact hole TH" is formed in the insulating layer 121. The other similar parts will not be described again here.

[0108] Similar to the first embodiment, in this variation, the auxiliary electrode AE ​​overlapping the first common electrode CE1 and the dummy electrode DME2 overlapping the scan line SL are two metal patterns with floating potentials. These two metal patterns can be used to reduce the height difference between the metal stack structures located below the reflective electrode RE to improve the flatness of the upper surface of the reflective electrode RE. That is, the auxiliary electrode AE ​​and the dummy electrode DME2 overlapping the scan line SL are planarization enhancement metal patterns. In this variation, the area of ​​the auxiliary electrode AE ​​is much larger than the area of ​​the dummy electrode DME2, therefore the auxiliary electrode AE ​​is the main planarization enhancement metal pattern in this embodiment. In some embodiments, the pixel structure may not have the dummy electrode DME2, that is, the planarization enhancement metal pattern of the pixel structure may only include the auxiliary electrode AE.

[0109] In this variant embodiment, the percentage of the orthographic projection area of ​​the patterns of the first metal layer ML1 and the second metal layer ML2 located below the reflective electrode RE (e.g., including data lines DL, scan lines SL, the first common electrode CE1, the capacitor electrode CPE, the gate GE, source SE, and drain DE of the active element T, the auxiliary electrode AE, and the dummy electrode DME2) onto the reflective electrode RE to the area of ​​the reflective electrode RE is greater than 70%. That is, from a top-view direction (i.e., direction Z), more than 70% of the area of ​​the reflective electrode RE overlaps with the metal pattern located below the reflective electrode RE (i.e., less than or equal to 30% of the area of ​​the reflective electrode RE does not overlap with the metal pattern located below the reflective electrode RE). In other words, more than 70% of the area of ​​the reflective electrode RE in the orthographic projection onto the substrate 100 overlaps with the orthographic projection of the metal pattern located below the reflective electrode RE onto the substrate 100 (i.e., less than or equal to 30% of the area of ​​the reflective electrode RE in the orthographic projection onto the substrate 100 does not overlap with the orthographic projection of the metal pattern located below the reflective electrode RE onto the substrate 100). Specifically, in this variant embodiment, the first metal layer ML1 and the second metal layer ML2 are formed before the reflective electrode RE is formed. Therefore, the metal pattern located below the reflective electrode RE includes the patterns of the first metal layer ML1 and the second metal layer ML2, but is not limited thereto.

[0110] Furthermore, in the region where the reflective electrode RE overlaps with the metal pattern located below the reflective electrode RE, the area of ​​the region with stacked double metal layers is larger than the area of ​​the region with a single metal layer. For example, in this variant embodiment, a pattern of a first metal layer ML1 and a second metal layer ML2 is provided below the reflective electrode RE. In the region where the reflective electrode RE overlaps with the metal pattern located below the reflective electrode RE, the metal pattern may include a double metal layer stack (i.e., a first metal layer ML1 and a second metal layer ML2 stack) pattern and a single metal layer (i.e., a first metal layer ML1 or a second metal layer ML2) pattern, and the area of ​​the double metal layer stack pattern is larger than the area of ​​the single metal layer pattern, but this is not a limitation.

[0111] It should be noted that although the pixel structure in the first embodiment and the second variation of the first embodiment have four metal layers and three metal layers respectively, the technical means of increasing the surface flatness of the reflective electrode by using the planarization reinforcement pattern provided between the reflective electrode RE and the substrate 100 can also be applied to display panels with different numbers of metal film layers (e.g., the pixel structure has more than four metal layers), and the present invention does not limit it.

[0112] Figure 8 is a top view of the display panel according to the second embodiment of the present invention. Figures 9A to 9C are top views of some film layers in the display panel of Figure 8. Figure 10 is a cross-sectional view of the display panel of Figure 8. Figure 10 corresponds to the section line C-C' in Figure 8. Referring to Figure 8, the main difference between the display panel 10A of this embodiment and the display panel 10 of Figure 1 is that the electrical configuration of the auxiliary electrode is different. Specifically, unlike the auxiliary electrode AE ​​of the display panel 10 which has a floating potential, in the display panel 10A of this embodiment, the auxiliary electrode AE-A of the pixel structure PX-A can be electrically connected to the second common electrode CE2-A and have a common potential.

[0113] In this embodiment, the top view of the first metal layer ML1, the semiconductor pattern SC, the opening OP of the cladding layer 130, and the reflective electrode RE is similar to that of the first embodiment, as shown in Figures 3A, 3B, 3G, and 3H, respectively. Furthermore, in this embodiment, the top view of the second metal layer ML2 is similar to that of the first embodiment, as shown in Figure 3C, except that the mark AE in Figure 3C is replaced with AE-A. That is, in the second metal layer ML2, the adjacent and electrically insulated auxiliary electrodes AE-A and the capacitor electrode CPE have a gap GP between them.

[0114] On the other hand, top views of the third metal layer ML3-A, the contact hole formed in at least one of the insulating layers 121A and 122A, and the transparent conductive layer TCL-A are shown in Figures 9A to 9C, respectively. The difference between the third metal layer ML3-A in this embodiment and Figure 3D of the first embodiment is that the third metal layer ML3-A further includes an opening CE2op. The difference between the contact hole formed in at least one of the insulating layers 121A and 122A in this embodiment and Figure 3E of the first embodiment is that this embodiment further includes contact holes TH1 and TH2. Furthermore, the difference between the transparent conductive layer TCL-A in this embodiment and Figure 3F of the first embodiment is that the transparent conductive layer TCL-A further includes a second transparent conductive pattern TCP2.

[0115] In this embodiment, the cross-sectional view of the display panel 10A corresponding to the section line A-A' in Figure 8 can be seen in Figure 2, and the markings ML3, 121, 122, and TCP1 (TCL) in Figure 2 are replaced with ML3-A, 121A, 122A, and TCP1 (TCL-A), respectively.

[0116] Please refer to Figures 9A to 10 simultaneously. To achieve the electrical connection between the auxiliary electrode AE-A and the second common electrode CE2-A, the second common electrode CE2-A of the third metal layer ML3-A may have an opening CE2op. The insulating layers 121A and 122A may also have a contact hole TH1. The opening CE2op of the second common electrode CE2-A overlaps with the contact hole TH1 and the auxiliary electrode AE-A. The insulating layer 122A may also have another contact hole TH2, which overlaps with the second common electrode CE2-A. The contact hole TH1 exposes the auxiliary electrode AE-A, and the contact hole TH2 exposes the second common electrode CE2-A.

[0117] In this embodiment, the transparent conductive layer TCL-A may include a first transparent conductive pattern TCP1 and a second transparent conductive pattern TCP2. The reflective electrode RE is electrically connected to the capacitor electrode CPE via the first transparent conductive pattern TCP1, and the auxiliary electrode AE-A is electrically connected to the second common electrode CE2-A via the second transparent conductive pattern TCP2. Specifically, one end of the second transparent conductive pattern TCP2 disposed on the insulating layer 122A may extend into a contact hole TH1 passing through the opening CE2op of the second common electrode CE2-A to electrically connect to the auxiliary electrode AE-A, while the other end of the second transparent conductive pattern TCP2 may extend into another contact hole TH2 of the insulating layer 122A to electrically connect to the second common electrode CE2-A.

[0118] The following will provide an exemplary description of the manufacturing method of the display panel 10A.

[0119] The steps of forming the first metal layer ML1, insulating layer 110, semiconductor pattern SC, second metal layer ML2, insulating layer 121A, third metal layer ML3-A and insulating layer 122A in the manufacturing method of the display panel 10A in this embodiment are similar to the steps of forming the first metal layer ML1, insulating layer 110, semiconductor pattern SC, second metal layer ML2, insulating layer 121, third metal layer ML3 and insulating layer 122 in the first embodiment, and will not be described again here.

[0120] After the insulating layer 122A is formed, contact holes TH and TH1 are formed in the insulating layers 121A and 122A, and contact hole TH2 is formed in the insulating layer 122A. In this embodiment, contact holes TH, TH1, and TH2 can be formed in the same step to save manufacturing costs, but this is not a limitation. Contact hole TH does not overlap with the third metal layer ML3-A (i.e., contact hole TH overlaps with the notch NH of the third metal layer ML3-A) and exposes a portion of the capacitor electrode CPE. Contact hole TH1 does not overlap with the third metal layer ML3-A and exposes the auxiliary electrode AE-A, while contact hole TH2 exposes the second common electrode CE2-A.

[0121] Next, a transparent conductive layer TCL-A is formed on the insulating layer 122A. The transparent conductive layer TCL-A includes a first transparent conductive pattern TCP1 and a second transparent conductive pattern TCP2. The first transparent conductive pattern TCP1 overlaps the capacitor electrode CPE and is electrically connected to the capacitor electrode CPE via contact holes TH. The second transparent conductive pattern TCP2 extends into contact holes TH1 and TH2 to couple the auxiliary electrode AE-A and the second common electrode CE2-A, respectively, so that the auxiliary electrode AE-A can be electrically connected to the second common electrode CE2-A through the second transparent conductive pattern TCP2 and have the same potential (e.g., common potential) as the second common electrode CE2-A.

[0122] The subsequent steps for forming the cladding layer 130 and the fourth metal layer ML4 are similar to those in the first embodiment, and will not be repeated here.

[0123] Similar to the first variant of the first embodiment, the pixel structure of this variant may not include the dummy electrode DME3, and the second common electrode CE2-A may extend to and cover the scan line SL, and / or the second common electrode CE2-2 may extend to and cover the data line DL, so as to avoid the interference of the signal of the scan line SL and / or the data line DL on the potential of the reflective electrode RE, thereby improving the image quality and reducing the height difference between the metal stack structure in the setting area of ​​the scan line SL and the data line DL and the metal stack structure in the setting area of ​​the first common electrode CE1.

[0124] Figure 11 is a top view of a display panel according to a third embodiment of the present invention. Figure 12 is a top view of the second metal layer in the display panel of Figure 11. Referring to Figures 11 and 12, the difference between the display panel 10B of this embodiment and the display panel 10 of Figure 1 is that the pixel structure PX-B of the display panel 10B of this embodiment does not have the auxiliary electrode AE ​​of Figure 1, and compared with the capacitor electrode CPE of Figure 1, the capacitor electrode CPE-A of this embodiment extends into the area where the auxiliary electrode AE ​​of Figure 1 is located. More specifically, in this embodiment, the distribution range of the capacitor electrode CPE-A of the second metal layer ML2-A is close to the distribution range of the first common electrode CE1 and the second common electrode CE2. Therefore, compared with the pixel structure PX of Figure 1, the storage capacity of the pixel structure PX-B of this embodiment can be further increased.

[0125] Similar to the first variant of the first embodiment, the pixel structure of this variant may not include the dummy electrode DME3, and the second common electrode CE2 may extend to and cover the scan line SL, and / or the second common electrode CE2 may extend to and cover the data line DL, so as to avoid the interference of the signal of the scan line SL and / or the data line DL on the potential of the reflective electrode RE, thereby improving the image quality and reducing the height difference between the metal stack structure in the setting area of ​​the scan line SL and the data line DL and the metal stack structure in the setting area of ​​the first common electrode CE1.

[0126] On the other hand, similar to the second variation of the first embodiment, another variation of this embodiment may have a pixel structure with three metal layers (i.e., first, second, and fourth metal layers ML1, ML2-A, and ML4). Specifically, the display panel of another variation of this embodiment does not have the third metal layer ML3 and insulating layer 122 of the third embodiment, and the cladding layer 130 is disposed between the reflective electrode RE and the transparent conductive layer TCL, and between the reflective electrode RE and the insulating layer 121. Therefore, the insulating layer 121 has the contact hole TH” of the second variation of the first embodiment, and the first transparent conductive pattern TCP1 is electrically connected to the capacitor electrode CPE through the contact hole TH”.

[0127] Figure 13 is a top view of the display panel according to the fourth embodiment of the present invention. Figures 14A to 14H are top views of each film layer in the display panel of Figure 13.

[0128] Figure 13 shows another modified embodiment of the display panel 10 of Figure 1, the main difference being the number of active elements T in the pixel structure. Specifically, in the display panel 20A of Figure 13, the pixel structure PX-C has two active elements T, namely active element T1 and active element T2, and the two gates GE of these two active elements T extend from different scan lines, such as scan line SL1 and scan line SL2, respectively. That is, active elements T1 and T2 in a pixel structure PX-C are coupled to scan line SL1 and scan line SL2, respectively. In addition, the source SE of active element T2 is coupled to the data line DL, the drain DE of active element T2 is coupled to the source SE of active element T1, and the drain DE of active element T1 is coupled to the capacitor electrode CPE. When the signal from data line DL needs to be transmitted to pixel structure PX-C, scan lines SL1 and SL2 receive enable signals (e.g., high-potential signals) to turn on active elements T1 and T2, allowing the signal from data line DL to be transmitted to pixel structure PX-B via the turned-on active elements T2 and T1. When pixel structure PX-B does not receive the signal from data line DL, one or the other of scan lines SL1 and SL2 receives enable signals (e.g., high-potential signals) and disable signals (e.g., low-potential signals), respectively, turning one or the other of active elements T1 and T2 on and off, thus preventing the signal from data line DL from being transmitted to pixel structure PX-C. Furthermore, during the period when the pixel structure PX-C does not receive the signal from the data line DL, one of the scan lines SL1 and SL2 sequentially receives the enable signal and the disable signal alternately, while the other of the scan lines SL1 and SL2 sequentially receives the disable signal and the enable signal alternately. Moreover, the signals of the scan lines SL1 and SL2 are out of phase during this period (i.e., when one of the signals is the enable signal, the other signal is the disable signal). Therefore, the critical voltage shift caused by the active elements T1 and T2 being biased by signals of the same phase for a long time can be reduced.

[0129] Similar to the display panel 10 in FIG1, the display panel 20A of this embodiment may also have dummy electrodes DME2a and DME2b of the second metal layer ML2-B and dummy electrodes DME3a and DME3b of the third metal layer ML3-B superimposed in the setting areas of scan lines SL1 and SL2, respectively. Scan lines SL1, dummy electrodes DME2a and DME3a overlap each other, scan lines SL2, dummy electrodes DME2b and DME3b overlap each other, and dummy electrodes DME1a and DME1b of the third metal layer ML3-B superimposed in the setting areas of active elements T1 and T2, respectively. In other words, compared to the second metal layer ML2 in FIG1, the second metal layer ML2-B in this embodiment further includes a dummy electrode (e.g., dummy electrode DME2b) overlapping another scan line (e.g., scan line SL2), and the third metal layer ML3-B further includes a dummy electrode (e.g., dummy electrode DME3b) overlapping another scan line (e.g., scan line SL2) and a dummy electrode (e.g., dummy electrode DME1b) overlapping another active element (e.g., active element T2).

[0130] It is particularly noteworthy that, since the spacing between the two scan lines in the Y direction is slightly large in this embodiment, in order to reduce the height difference between the cladding layer 130 and other areas in the region between these two scan lines, the pixel structure PX-C may have a stacked structure of multiple metal patterns in the region between scan lines SL1 and SL2. For example, these metal patterns are the dummy electrode DME4 of the first metal layer ML1-A, the dummy electrode DME2c of the second metal layer ML2-B, and the dummy electrode DME3c of the third metal layer ML3-B, and the dummy electrodes DME4, DME2c, and DME3c are stacked on top of each other.

[0131] Referring simultaneously to Figure 14A, in the first metal layer ML1-A, the distance (e.g., distance S5 or distance S6) between either scan line SL1 or scan line SL2 and the dummy electrode DME4 in the Y direction can be between 0.5 micrometers and 7.0 micrometers, which helps to improve the planarization effect of the cladding layer 130. Similarly, please refer to... Figure 14C As shown in Figure 14D, in the second metal layer ML2-B, the spacing between either dummy electrode DME2a or dummy electrode DME2b and dummy electrode DME2c in the Y direction can be between 0.5 micrometers and 7.0 micrometers, and in the third metal layer ML3-B, the spacing between either dummy electrode DME3a or dummy electrode DME3b and dummy electrode DME3c in the Y direction can be between 0.5 micrometers and 7.0 micrometers, which helps to improve the planarization effect of the cladding layer 130.

[0132] Furthermore, in some embodiments, the three dummy electrodes DME2a, DME2b, and DME2c in the second metal layer ML2-B that respectively cover the regions of scan lines SL1, SL2, and between scan lines SL1 and SL2 can be replaced with a single dummy electrode that simultaneously covers the regions of scan lines SL1, SL2, and between scan lines SL1 and SL2. Similarly, the three dummy electrodes DME3a, DME3b, and DME3c in the third metal layer ML3-B that respectively cover the regions of scan lines SL1, SL2, and between scan lines SL1 and SL2 can be replaced with a single dummy electrode that simultaneously covers the regions of scan lines SL1, SL2, and between scan lines SL1 and SL2. This also reduces the height difference between the metal stack structure in the regions of scan lines SL1 and SL2 and the regions between scan lines SL1 and SL2 and the metal stack structure in the area where the first common electrode CE1 is located.

[0133] The steps in the manufacturing method of the display panel 20A in this embodiment, namely forming the first metal layer ML1-A, insulating layer 110, semiconductor pattern SC, second metal layer ML2-B, insulating layer 121, third metal layer ML3-B, insulating layer 122, contact hole TH, transparent conductive layer TCL, cladding layer 130 and fourth metal layer ML4, are similar to those in the first embodiment, namely forming the first metal layer ML1, insulating layer 110, semiconductor pattern SC, second metal layer ML2, insulating layer 121, third metal layer ML3, insulating layer 122, contact hole TH, transparent conductive layer TCL, cladding layer 130 and fourth metal layer ML4, and will not be described again here.

[0134] Similar to the first variant of the first embodiment, the pixel structure of this variant may not include dummy electrodes DME3a, DME3b, and DME3c, and the second common electrode CE2 may extend to and cover the scan lines SL1 and SL2, and / or the second common electrode CE2 may extend to and cover the data line DL, so as to avoid interference of the signals of the scan lines SL1, SL2 and / or the data line DL on the potential of the reflective electrode RE, thereby improving the image quality and reducing the height difference between the metal stack structure in the setting area of ​​the scan lines SL1, SL2 and the data line DL and the metal stack structure in the setting area of ​​the first common electrode CE1.

[0135] On the other hand, similar to the second variation of the first embodiment, another variation of this embodiment may have a pixel structure with three metal layers (i.e., first, second, and fourth metal layers ML1-A, ML2-B, and ML4). Specifically, the display panel of another variation of this embodiment does not have the third metal layer ML3-B and the insulating layer 122 of the fourth embodiment, and the cladding layer 130 is disposed between the reflective electrode RE and the transparent conductive layer TCL, and between the reflective electrode RE and the insulating layer 121. Therefore, the insulating layer 121 has the contact hole TH” of the second variation of the first embodiment, and the first transparent conductive pattern TCP1 is electrically connected to the capacitor electrode CPE through the contact hole TH”.

[0136] However, the present invention is not limited thereto. The structural differences between FIG13 and FIG1 can also be applied to the display panel 10A of FIG8. FIG15 is a top view of the display panel of the fifth embodiment of the present invention. As shown in FIG15, the difference between the display panel 20B and the display panel 20A of FIG13 lies in the electrical configuration of the auxiliary electrodes. Since the electrical configuration of the auxiliary electrode AE-A of the second metal layer ML2-B of the pixel structure PX-D in FIG15 is similar to that of the display panel 10A in FIG8, that is, the auxiliary electrode AE-A of the pixel structure PX-D can be electrically connected to the second common electrode CE2-A and have a common potential, please refer to the relevant paragraphs of the aforementioned second embodiment for a detailed explanation, which will not be repeated here.

[0137] The steps in the manufacturing method of the display panel 20B of the fifth embodiment, namely forming the first metal layer ML1-A, insulating layer 110, semiconductor pattern SC, second metal layer ML2-B, insulating layer 121A, third metal layer ML3-C, insulating layer 122A, contact holes TH, TH1, TH2, transparent conductive layer TCL-A, coating layer 130 and fourth metal layer ML4, are similar to those in the second embodiment, namely forming the first metal layer ML1, insulating layer 110, semiconductor pattern SC, second metal layer ML2, insulating layer 121, third metal layer ML3-A, insulating layer 122A, contact holes TH, TH1, TH2, transparent conductive layer TCL-A, coating layer 130 and fourth metal layer ML4, and will not be described again here.

[0138] Similar to the first variant of the first embodiment, the pixel structure of this variant may not include the dummy electrodes DME3a, DME3b, and DME3c, and the second common electrode CE2-A may extend to and cover the scan lines SL1 and SL2, and / or the second common electrode CE2-A may extend to and cover the data line DL, so as to avoid interference of the signals of the scan lines SL1, SL2 and / or the data line DL on the potential of the reflective electrode RE, thereby improving the image quality and reducing the height difference between the metal stacked structure in the setting area of ​​the scan lines SL1, SL2 and the data line DL and the metal stacked structure in the setting area of ​​the first common electrode CE1.

[0139] Similarly, the present invention is not limited thereto. The structural differences between FIG13 and FIG1 can also be applied to the display panel 10B of FIG11. FIG16 is a top view of the display panel of the sixth embodiment of the present invention. FIG17 is a top view of the second metal layer in the display panel of FIG16. Referring to FIG16 and FIG17, the difference between the display panel 20C of this embodiment and the display panel 20A of FIG13 is that the pixel structure PX-E of the display panel 20C of this embodiment does not have the auxiliary electrode AE ​​of FIG13, and compared with the capacitor electrode CPE of FIG13, the capacitor electrode CPE-A of this embodiment extends into the setting area of ​​the auxiliary electrode AE ​​of FIG13. More specifically, in this embodiment, the distribution range of the capacitor electrode CPE-A of the second metal layer ML2-C is close to the distribution range of the first common electrode CE1 and the second common electrode CE2. Therefore, compared with the pixel structure PX-C of FIG13, the storage capacity of the pixel structure PX-E of this embodiment can be further increased.

[0140] Similar to the first variant of the first embodiment, the pixel structure of this variant may not include dummy electrodes DME3a, DME3b, and DME3c, and the second common electrode CE2 may extend to and cover the scan lines SL1 and SL2, and / or the second common electrode CE2 may extend to and cover the data line DL, so as to avoid interference of the signals of the scan lines SL1, SL2 and / or the data line DL on the potential of the reflective electrode RE, thereby improving the image quality and reducing the height difference between the metal stack structure in the setting area of ​​the scan lines SL1, SL2 and the data line DL and the metal stack structure in the setting area of ​​the first common electrode CE1.

[0141] On the other hand, similar to the second variation of the first embodiment, another variation of this embodiment may have a pixel structure with three metal layers (i.e., first, second, and fourth metal layers ML1-A, ML2-C, and ML4). Specifically, the display panel of another variation of this embodiment does not have the third metal layer ML3-B and the insulating layer 122 of the fourth embodiment, and the cladding layer 130 is disposed between the reflective electrode RE and the transparent conductive layer TCL, and between the reflective electrode RE and the insulating layer 121. Therefore, the insulating layer 121 has the contact hole TH” of the second variation of the first embodiment, and the first transparent conductive pattern TCP1 is electrically connected to the capacitor electrode CPE through the contact hole TH”.

[0142] It should be noted that, although not shown in the accompanying drawings, the technique of increasing the surface flatness of the reflective electrode by using a stacked structure of multiple metal patterns disposed between the reflective electrode and the substrate 100 in the foregoing embodiments can also be applied to display panels with different numbers of metal film layers (e.g., the pixel structure has more than four metal layers), and the present invention does not limit it.

[0143] In summary, in a display panel according to an embodiment of the present invention, at least one metal pattern is overlapped between the reflective electrode and the substrate, and the percentage of the orthogonal projection area of ​​the at least one metal pattern on the reflective electrode to the reflective area of ​​the reflective electrode is greater than 70%. Accordingly, the height difference of the metal stacking structure at different positions in the configuration area of ​​the reflective electrode can be effectively reduced, thereby improving the overall reflection efficiency of the reflective electrode.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: substrate; Multiple scan lines and multiple data lines are disposed on the substrate, and the multiple scan lines and multiple data lines intersect to define multiple pixel areas; as well as Multiple pixel structures are respectively configured to correspond to the multiple pixel regions, and each of the multiple pixel structures includes: At least one active element is disposed on the substrate and electrically connected to at least one of the plurality of scan lines and one of the plurality of data lines; A reflective electrode, electrically connected to the at least one active element; A first common electrode is disposed between the reflective electrode and the substrate, and the first common electrode belongs to the first metal layer; A capacitor electrode is disposed between the reflective electrode and the substrate, the capacitor electrode being electrically connected to the drain of the at least one active element and the reflective electrode, and overlapping the first common electrode; the capacitor electrode is part of the second metal layer; and An auxiliary electrode is disposed between the reflective electrode and the substrate, and overlaps the first common electrode. The auxiliary electrode belongs to the second metal layer and is electrically insulated from the capacitor electrode. At least one metal pattern overlaps with the reflective electrode and is located between the substrate and the reflective electrode. More than 70% of the area of ​​the reflective electrode in the orthographic projection of the substrate overlaps with the orthographic projection of the at least one metal pattern on the substrate. The at least one metal pattern includes the first common electrode, the capacitor electrode, and the auxiliary electrode.

2. The display panel according to claim 1, characterized in that, Each of the plurality of pixel structures further includes: A coating layer is disposed between the reflective electrode and the at least one metal pattern.

3. The display panel according to claim 1, characterized in that, Each of the plurality of pixel structures further includes: A transparent conductive layer is disposed between the reflective electrode and the capacitor electrode, and the transparent conductive layer includes a first transparent conductive pattern, wherein the reflective electrode is electrically connected to the capacitor electrode via the first transparent conductive pattern.

4. The display panel according to claim 1, characterized in that, The scan line belongs to the first metal layer, and the data line belongs to the second metal layer.

5. The display panel according to claim 4, characterized in that, Each of the plurality of pixel structures includes two active elements, and the two active elements are electrically connected to two scan lines of the plurality of scan lines, respectively. Each of the plurality of pixel structures further includes: A dummy electrode is disposed between the reflective electrode and the substrate, and located between the two scan lines. The dummy electrode belongs to the first metal layer and is electrically insulated from the two scan lines of the plurality of scan lines. The at least one metal pattern further includes the two scan lines and the dummy electrode, the dummy electrode having a floating potential.

6. The display panel according to claim 1, characterized in that, Each of the plurality of pixel structures further includes: A second common electrode is disposed between the capacitor electrode and the reflective electrode, overlapping the capacitor electrode, and belonging to the third metal layer. The at least one metal pattern further includes the second common electrode.

7. The display panel according to claim 1, characterized in that, The distance between the auxiliary electrode and the capacitor electrode is between 0.5 micrometers and 7.0 micrometers.

8. The display panel according to claim 1, characterized in that, The auxiliary electrode has a floating potential.

9. The display panel according to claim 1, characterized in that, Each of the plurality of pixel structures further includes: A dummy electrode is disposed between the reflective electrode and the substrate, and overlaps one of the plurality of scan lines. The dummy electrode belongs to the second metal layer and is electrically insulated from the auxiliary electrode. The at least one metal pattern further includes the scan line and the dummy electrode, the dummy electrode having a floating potential.

10. The display panel according to claim 1, characterized in that, The auxiliary electrode has a common potential.

11. The display panel according to claim 10, characterized in that, Each of the plurality of pixel structures further includes: A second common electrode is disposed between the capacitor electrode and the reflective electrode, and between the auxiliary electrode and the reflective electrode. The second common electrode overlaps the capacitor electrode and the auxiliary electrode, and belongs to a third metal layer. The second transparent conductive pattern is used to electrically connect the auxiliary electrode to the second common electrode. The at least one metal pattern further includes the second common electrode.

12. The display panel according to claim 6 or 11, characterized in that, Each of the plurality of pixel structures further includes: A dummy electrode is disposed overlapping the at least one active element. The dummy electrode belongs to the third metal layer and is electrically insulated from the second common electrode. The at least one of the metal patterns further includes the dummy electrode having a floating potential.

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