A control method and a controller of a TMR architecture memory

Abstract

The application provides a control method and a controller of a TMR architecture memory, wherein the control method is used for controlling the write-in operation and the write-out operation of the data of three sub-memories of the TMR architecture memory when an upper computer or a processor accesses the TMR architecture memory, and the control method comprises the following steps: when the upper computer or the processor performs data access, performing majority voting on the addresses of the three sub-memories; when the data write-in operation is performed, performing majority voting on three groups of data to be written in; and when the data write-out operation is performed, performing majority voting on the data in the three sub-memories. The control method solves the technical problems of the prior art, such as difficulty in guaranteeing data integrity and additional timing overhead caused by ECC memory, effectively improves the integrity and availability of the three-mode memory, reduces data errors caused by memory failure, various bit flips and the like, and can be applied to occasions requiring high-integrity storage and calculation.

Description

Technical Field

[0001] This invention belongs to the field of computer science and relates to memory control and fault recovery design technology, specifically to a control method and controller for a TMR architecture memory. Background Technology

[0002] In high-integrity computer architectures, memory may experience bit flips and data errors due to single-event events, necessitating a memory controller capable of real-time fault detection to prevent fault propagation. Currently, commonly used controller designs employ ECC memory (Error Correcting Code), a technology that enables error checking and correction. However, ECC memory can only correct a single-bit flip, making it difficult to guarantee data integrity. Furthermore, the need for ECC calculation and storage incurs additional timing overhead for data read and write operations, reducing availability. Summary of the Invention

[0003] To address the technical problems of data integrity and additional timing overhead caused by ECC memory in existing technologies, this invention provides a control method and controller for a TMR architecture memory. This method employs a majority voting mechanism to write correct data into the faulty sub-memory, effectively reducing data errors caused by memory failures, bit flips, etc., and ensuring the integrity and correctness of data within the memory. The controller implementing this control method can be applied to applications requiring high-integrity storage and computation, and has broad development prospects.

[0004] The technical solution to achieve the purpose of the invention is as follows:

[0005] This invention provides a control method for a TMR architecture memory. The control method is used by a host computer or processor to control the write and write operations of data in the three sub-memories of the TMR architecture memory when accessing the memory. The control method includes the following steps:

[0006] When the host computer or processor accesses data, a majority vote is held on the addresses of the three sub-memories;

[0007] When at least two of the sub-memory addresses are consistent, the data write or write address is determined;

[0008] When performing a data write operation, a majority vote is taken on the three sets of data to be written. When at least two sets of data are the same, the same data is written into the three sub-memories.

[0009] When performing a data write operation, a majority vote is taken on the data in the three sub-memories; when the data in at least two of the sub-memories is consistent, the identical data is written out.

[0010] Furthermore, the control method further includes:

[0011] When performing a data write operation, if the data in two of the sub-memories is consistent, the data in the sub-memories with different voting data is considered abnormal data. The abnormal data is then overwritten with the same data to restore the sub-memory.

[0012] Furthermore, the control method further includes:

[0013] When the host computer or processor accesses data, if the access to the three sub-memories by the host computer or processor is not synchronized, a bus wait signal is generated, and the access to the three sub-memories by the host computer or processor is synchronized according to the bus wait signal.

[0014] Furthermore, the control method further includes:

[0015] When performing a data write operation, if all three sets of data are different, a data write error signal is output.

[0016] When performing a data write operation, if the data in the three sub-memories are all different, a data write error signal is output.

[0017] This invention also provides a controller for a TMR architecture memory, including a memory voting controller, one end of which is connected to a host computer or processor, and the other end of which is connected to three sub-memories of the TMR architecture memory.

[0018] The memory voting controller includes an address voting module, a data voting module, and a sub-memory recovery module;

[0019] The address voting module performs a majority vote on the addresses of the three sub-memories during data write or write operations.

[0020] The data voting module performs a majority vote on the three sets of data during a data write operation, or performs a majority vote on the data in the three sub-memories during a data write-out operation.

[0021] The sub-memory recovery module is used to recover data in the sub-memory where the majority voting result is incorrect.

[0022] Furthermore, the memory voting controller is provided with a first interface and a second interface. The host computer or processor is connected to the controller via the first interface, and the three sub-memories of the TMR architecture memory are connected to the second interface.

[0023] Furthermore, the memory voting controller also includes a synchronization module, which is used to synchronize access to the three sub-memories when the host computer or processor accesses data.

[0024] This invention also provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the control method of any of the above-mentioned TMR architecture memory, so as to solve the technical problems of difficulty in guaranteeing data integrity and additional timing overhead caused by ECC memory in the prior art.

[0025] This invention also provides a computer-readable storage medium storing a computer program that executes any of the control methods for the TMR architecture memory described above, in order to solve the technical problems of difficulty in guaranteeing data integrity and additional timing overhead caused by ECC memory in the prior art.

[0026] Compared with the prior art, the beneficial effects that can be achieved by the above-mentioned at least one technical solution adopted in the embodiments of this specification include at least the following: the control method and apparatus of the TMR architecture memory of the present invention can ensure the correctness of data reading and writing (writing and writing out) of the TMR architecture memory (i.e., tri-mode memory), and can perform fault recovery when data errors occur. The method effectively improves the integrity and availability of the tri-mode memory, and can effectively reduce data errors caused by memory failures, various bit flips, etc., and can be applied to a wide range of occasions that require high integrity storage and computing. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a flowchart of the control method for the TMR architecture memory in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of writing data to the TMR architecture memory in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram illustrating the writing (i.e. reading) of data from the TMR architecture memory in an embodiment of the present invention.

[0031] Figure 4This is a schematic diagram illustrating fault recovery in the TMR architecture memory where voting is performed as an error sub-memory in an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of a computer device in an embodiment of the present invention;

[0033] Among them, 201 is the memory; 202 is the processor. Detailed Implementation

[0034] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0035] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features of the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0036] This invention provides a control method for a TMR architecture memory. This method controls the write and write operations of data in the three sub-memories of the TMR architecture memory when a host computer or processor accesses the memory. See [link to relevant documentation]. Figure 1 As shown, the control method includes the following steps:

[0037] S1. When the host computer or processor accesses data, a majority vote is held on the addresses of the three sub-memories.

[0038] S2. When at least two of the sub-memory addresses are consistent, determine the data write or write address.

[0039] S31. During the data write operation, a majority vote is performed on the three sets of data to be written. When at least two sets of data are identical, the identical data is written into the three sub-memories. See the schematic diagram of the data write operation. Figure 2 As shown.

[0040] S32. When performing a data write-out operation, a majority vote is conducted on the data in the three sub-memories; when the data in at least two of the sub-memories is consistent, the identical data is written out. See the schematic diagram of the data write-out operation. Figure 3 As shown.

[0041] Further, see Figure 4 As shown, the control method further includes:

[0042] In step S31 above, when performing the data write-out operation, if the data in two of the sub-memories is consistent, the data in the sub-memories with different voting data is abnormal data. The abnormal data is overwritten with the same data, and the sub-memory is restored.

[0043] Furthermore, the control method further includes:

[0044] In step S1 above, when the host computer or processor accesses data, if the access of the host computer or processor to the three sub-memories is not synchronized, a bus wait signal is generated, and the access of the host computer or processor to the three sub-memories is synchronized according to the bus wait signal.

[0045] Specifically, during write operations, it supports three host computers simultaneously writing data to the TMR memory controller. When a host computer or processor initiates a write operation to the three sub-memories, the TMR memory controller synchronizes the three write addresses with the write control signals to ensure that the three write instructions enter the write data stage simultaneously, writing the three sets of write data to the same address in the TMR memory at the same time.

[0046] During a write operation (i.e. a read operation), the host computer or processor initiates a read operation to the three sub-memories. The TMR memory controller synchronizes the three read addresses with the read control signals, and then synchronizes the read data read from the three sub-memories, simultaneously reading the data from the three sub-memories to the TMR memory controller.

[0047] Furthermore, the control method further includes:

[0048] In step S31 above, when performing the data writing operation, if all three sets of data are different, a data writing error signal is output.

[0049] In step S32 above, when performing the data write-out operation, if the data in the three sub-memories are all different, a data write-out error signal is output.

[0050] In this embodiment, a computer device is provided, such as... Figure 5 As shown, it includes a memory 201, a processor 202, and a computer program stored on the memory 201 and executable on the processor 202. When the processor executes the computer program, it implements the control method of any of the above-described TMR architecture memory.

[0051] Specifically, the computer device can be a computer terminal, a server, or a similar computing device.

[0052] In this embodiment, a computer-readable storage medium is provided, which stores a computer program that executes any of the control methods of the TMR architecture memory described above.

[0053] Specifically, computer-readable storage media, including both permanent and non-permanent, removable and non-removable media, can store information using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable storage media does not include transient media, such as modulated data signals and carrier waves.

[0054] Based on the same inventive concept, this invention also provides a controller for a TMR architecture memory, as described in the following embodiments. Since the principle by which the controller for the TMR architecture memory solves the problem is similar to the control method for the TMR architecture memory, the implementation of the control device can refer to the implementation of the control method described above, and repeated details will not be elaborated further. As used below, the terms "unit" or "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0055] The present invention illustrates the structure of the controller of the TMR architecture memory through the following example. The controller includes a memory voting controller, one end of which is connected to a host computer or processor, and the other end is connected to the three sub-memories of the TMR architecture memory.

[0056] The memory voting controller includes an address voting module, a data voting module, and a sub-memory recovery module.

[0057] Specifically, the address voting module performs a majority vote on the addresses of the three sub-memories during data write or write operations. The data voting module performs a majority vote on three sets of data during a data write operation, or on the data within the three sub-memories during a data write operation. The sub-memory recovery module is used to recover data within the sub-memories whose majority vote result is incorrect.

[0058] Furthermore, the memory voting controller is provided with a first interface and a second interface. The host computer or processor is connected to the controller via the first interface, and the three sub-memories of the TMR architecture memory are connected to the second interface.

[0059] Furthermore, the memory voting controller also includes a synchronization module, which is used to synchronize access to the three sub-memories when the host computer or processor accesses data.

[0060] The embodiments of the present invention achieve the following technical effects: The control method and apparatus of the TMR architecture memory of the present invention can ensure the correctness of data reading and writing (writing and writing out) of the TMR architecture memory (i.e., tri-mode memory), and can perform fault recovery when data errors occur. The method effectively improves the integrity and availability of the tri-mode memory, and can effectively reduce data errors caused by memory failures, various bit flips, etc., and can be applied to a wide range of occasions that require high integrity storage and computing.

[0061] Obviously, those skilled in the art should understand that the modules or steps of the above-described embodiments of the present invention can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. Optionally, they can be implemented using computer-executable program code, thereby storing them in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, the embodiments of the present invention are not limited to any particular hardware and software combination.

[0062] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, various modifications and variations can be made to the embodiments of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A control method for a TMR architecture memory, characterized in that, The control method is used to control the write and write operations of the three sub-memories of the TMR architecture memory when the host computer or processor accesses the TMR architecture memory. The control method includes the following steps: When the host computer or processor accesses data, a majority vote is held on the addresses of the three sub-memories; When at least two of the sub-memory addresses are consistent, the data write or write address is determined; When performing a data write operation, a majority vote is taken on the three sets of data to be written. When at least two sets of data are the same, the same data is written into the three sub-memories. When all three sets of data are different, a data write error signal is output. When performing a data write operation, a majority vote is taken on the data in the three sub-memories. When at least two of the sub-memories contain the same data, the same data is written out. When performing a data write operation, if two of the sub-memories contain the same data, the data in the sub-memories with different voting data is considered abnormal data. The abnormal data is overwritten with the same data, and the sub-memories are restored. When all three sub-memories contain different data, a data write error signal is output.

2. The control method for the TMR architecture memory according to claim 1, characterized in that, The control method further includes: When the host computer or processor accesses data, if the access to the three sub-memories by the host computer or processor is not synchronized, a bus wait signal is generated, and the access to the three sub-memories by the host computer or processor is synchronized according to the bus wait signal.

3. A controller for a TMR architecture memory, characterized in that, It includes a memory voting controller, one end of which is connected to a host computer or processor, and the other end is connected to three sub-memories of the TMR architecture memory; The memory voting controller includes an address voting module, a data voting module, and a sub-memory recovery module; The address voting module performs a majority vote on the addresses of the three sub-memories during data write or write operations. The data voting module performs a majority vote on the three sets of data during a data write operation, or performs a majority vote on the data in the three sub-memories during a data write-out operation. The sub-memory recovery module is used to recover data in the sub-memory where the majority voting result is incorrect.

4. The controller for the TMR architecture memory according to claim 3, characterized in that, The memory voting controller is provided with a first interface and a second interface. The host computer or processor is connected to the controller via the first interface, and the three sub-memories of the TMR architecture memory are connected to the second interface.

5. The controller for the TMR architecture memory according to claim 4, characterized in that, The memory voting controller also includes a synchronization module, which is used to synchronize access to the three sub-memories when the host computer or processor accesses data.

6. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the control method for the TMR architecture memory as described in any one of claims 1 to 2.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that performs the control method of the TMR architecture memory according to any one of claims 1 to 5.

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